summaryrefslogtreecommitdiff
path: root/lib/utils
AgeCommit message (Collapse)AuthorFilesLines
2022-08-08lib: utils/fdt: Use kconfig for enabling/disablingAnup Patel12-5/+39
We update FDT support makefile to use kconfig for enabling/disabling. To avoid compilation errors, we also enable FDT for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08lib: utils/gpio: Use kconfig for enabling/disabling driversAnup Patel4-5/+30
We update gpio drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate gpio drivers for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08lib: utils/i2c: Use kconfig for enabling/disabling driversAnup Patel3-5/+29
We update i2c drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate i2c drivers for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08lib: utils/irqchip: Use kconfig for enabling/disabling driversAnup Patel3-11/+53
We update irqchip drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate irqchip drivers for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08lib: utils/ipi: Use kconfig for enabling/disabling driversAnup Patel3-5/+29
We update ipi drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate ipi drivers for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08lib: utils/timer: Use kconfig for enabling/disabling driversAnup Patel3-5/+29
We update timer drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate timer drivers for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08lib: utils/sys: Use kconfig for enabling/disabling driversAnup Patel5-2/+20
We update system drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate system drivers for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08lib: utils/reset: Use kconfig for enabling/disabling driversAnup Patel3-14/+49
We update reset drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate reset drivers for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08lib: utils/serial: Use kconfig for enabling/disabling driversAnup Patel3-22/+99
We update serial drivers makefile to use kconfig for enabling/disabling drivers. To avoid compile errors, we also enable appropriate serial drivers for each platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-08-08Makefile: Add initial kconfig support for each platformAnup Patel1-0/+1
We extend the top-level makefile to allow kconfig based configuration for each platform where each platform has it's own set of configs with "defconfig" being the default config. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Atish Patra <atishp@rivosinc.com> Tested-by: Atish Patra <atishp@rivosinc.com>
2022-07-30lib: utils/serial: Ensure baudrate is non-zero before usingAndrew Jones4-6/+13
RISC-V doesn't generate exceptions on divide-by-zero, but the result, all bits set, is not likely what people expect either. In all cases where we divide by baudrate there's a chance it's zero (when the DT it came from is "bad"). To avoid difficult to debug situations, leave baudrate dependent registers alone when baudrate is zero, as, also in all cases, it appears we can skip initialization of those registers and still [hopefully] have a functioning UART. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-07-30lib: serial: Clean up coding style in sifive-uart.cAndrew Jones1-3/+8
Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-07-30lib: utils/serial: Initialize platform_uart_data to zeroAndrew Jones5-5/+5
While it doesn't look like there are any current cases of using uninitialized data, let's zero all the UART data members to be safe. Zero may not actually be better than a random number in some cases, so all structure members should still be validated before use, but at least zero is usually easier to debug than some random stack garbage... Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-07-30lib: utils/fdt: Factor out common uart node codeAndrew Jones1-92/+39
Factor out the common code used by the fdt UART node parsers, allowing us to drop duplicate code. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-07-20lib: utils/serial: Update Shakti UART based on latest implementationPrasanna T1-3/+3
The age old version of Shakti UART was upgraded long back, but we missed updating the driver in OpenSBI. The old version of UART is not supported anymore, hence removed the inline comment which is also outdated now. Signed-off-by: Prasanna T <ptprasanna@gmail.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com>
2022-06-22lib: utils/timer: Remove Allwinner D1 CLINT compatiblesVF2_v2.6.0VF2_v2.5.0VF2_v2.4.4Samuel Holland2-7/+0
The allwinner,sun20i-d1-clint compatible string is not documented in any official binding, so it should not be used by drivers. The MSWI in the D1 CLINT is compatible with the ACLINT specification, so it can take advantage of generic driver support. However, that is only possible if the MSWI and MTIMER are split into separate DT nodes. This means the final binding for this device is likely to be incompatible with what is implemented here. Remove this compatible string from the driver to prevent it from appearing in a stable version and causing future issues. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-06-22lib: irqchip/plic: fix typo in plic_warm_irqchip_initJan Remes1-1/+1
The second invocation of plic_context_init() incorrectly calls the function with m_cntx_id instead of s_cntx_id. This breaks systems which only have 1 external interrupt per hart. Fixes: 8c362e7 ("lib: irqchip/plic: Factor out a context init function") Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-06-21lib: utils/timer: Add a separate compatible for the D1 CLINTSamuel Holland2-14/+26
The CLINT in the Allwinner D1 SoC apparently does not support 64-bit MMIO access. A property was added to support this quirk (and that property was copied to the ACLINT MTIMER code). However, since this difference in behavior makes the D1 CLINT incompatible with the SiFive CLINT's programming interface, a better solution is to use a separate compatible string. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-06-21lib: utils: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel1-6/+45
Based on architecture review committee feedback, the [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are removed in the latest AIA draft v0.3.0 specification. (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31) These CSRs were mostly for software convenience and software can always use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt file bits. We update the IMSIC programming as-per above to match the latest AIA draft specification. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-06-13lib: utils/irqchip: Add wrapper for T-HEAD PLIC delegationSamuel Holland1-0/+7
The delegation bit is lost along with the rest of the PLIC state when the CPU power domain in the Allwinner D1 is powered down, so the PLIC needs to be re-delegated to S-mode during the hart resume path. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: utils/irqchip: Add FDT wrappers for PLIC save/restore functionsSamuel Holland1-0/+32
These functions save/restore the state of the PLIC associated with the current hart. The context save/restore functions only manipulate a single context, since most likely the M-mode context is unused and does not need to be saved. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-06-13lib: irqchip/plic: Add priority save/restore helpersSamuel Holland1-0/+19
These can be used by platform code to save the PLIC priority state, if it would otherwise be lost during non-retentive suspend. The platform is responsible for allocating all necessary storage. As a space optimization, store the saved priority values as 8-bit integers, since that is large enough to hold any priority value on the relevant platforms. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: irqchip/plic: Add context save/restore helpersSamuel Holland1-3/+48
These can be used by platform code to save the PLIC context state, if it would otherwise be lost during non-retentive suspend. The platform is responsible for allocating all necessary storage. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: irqchip/plic: Factor out a context init functionSamuel Holland1-26/+29
This simplifies both the callers and the callees by removing duplicated code and consolidating the error handling. It also fixes two bugs in the process: 1) ie_words was one too large when plic->num_src was a multiple of 32. 2) plic_set_ie takes a 32-bit mask, not a Boolean value, so the FPGA platforms previously only enabled one out of every 32 interrupts. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-06-13lib: irqchip/plic: Constify plic_data pointersSamuel Holland1-5/+6
None of the functions modify the passed-in plic_data, so mark it const. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-30lib: utils/fdt: Require match data to be constSamuel Holland3-4/+4
Match data stores hardware attributes which do not change at runtime, so it does not need to be mutable. Make it const. Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-05-14lib: utils/fdt: rename fdt_parse_max_hart_idJan Remes1-1/+1
The function returns the highest hart-id of the harts actually used in the system (enabled). Change the name to reflect this fact. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-14lib: utils: check if CPU node is enabledJan Remes3-1/+19
Ignore CPU nodes in FDT that are not enabled. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-14lib: utils/fdt: introduce fdt_node_is_enabled()Jan Remes1-0/+18
If an FDT node contains a "status" property and this property is not "ok" or "okay", this node should be ignored. Introduce a function that checks this. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-05-13lib: utils/irqchip: fix typo when checking for CPU nodeJan Remes1-1/+1
Fix typo in irqchip_imsic_update_hartid_table() when checking for CPU node. Signed-off-by: Jan Remes <jan.remes@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2022-05-13lib: utils/gpio: Generate FDT gpio driver list at compile-timeAnup Patel3-10/+15
Instead of having FDT gpio driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/i2c: Generate FDT i2c adapter driver list at compile-timeAnup Patel3-9/+12
Instead of having FDT i2c adapter driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/ipi: Generate FDT ipi driver list at compile-timeAnup Patel3-7/+12
Instead of having FDT ipi driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/irqchip: Generate FDT irqchip driver list at compile-timeAnup Patel3-11/+16
Instead of having FDT irqchip driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/timer: Generate FDT timer driver list at compile-timeAnup Patel3-7/+12
Instead of having FDT timer driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/serial: Generate FDT serial driver list at compile-timeAnup Patel3-21/+26
Instead of having FDT serial driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-13lib: utils/reset: Generate FDT reset driver list at compile-timeAnup Patel3-17/+20
Instead of having FDT reset driver list hard-coded in the C source, we generate it using carray.sh at compile-time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-05-07lib: sbi: Convert hart features into hart extensionsAnup Patel1-1/+1
Since past few years, we have been using "hart features" in OpenSBI to represent all optionalities and multi-letter extensions defined by the RISC-V specifications. The RISC-V profiles specification has taken a different approach and started assigning extension names for all optionalities which did not have any extension name previously. (Refer, https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) Inspired from the RISC-V profiles specification, we convert OpenSBI hart features into hart extensions. Going forward, we align the extension naming with RISC-V profiles specification. Currently, only "time CSR" and "AIA CSR" have not been assigned extension name but for everything else we have a name. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-04-17lib: utils/serial: support 'reg-offset' propertyZong Li3-3/+11
reg-offset property is used for offset to apply to the mapbase from the start of the registers in 8250 UART. In Linux kernel, it has been handled in 8250 UART driver. dt-bindings: <linux>/Documentation/devicetree/bindings/serial/8250.yaml Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-28lib: utils: serial: Initial commit of xlnx-uartliteAlistair Francis5-1/+125
Initial commit of the xlnx-uartlite device and FDT support. This was tested by running OpenSBI on a modified QEMU virt machine using the xlnx-uartlite for serial. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-28lib: sbi: Add a simple external interrupt handling frameworkAnup Patel1-2/+2
Currently, the external interrupt handling is scattered between sbi_init and sbi_trap. This patch moves all external interrupt handling into a simple framework called sbi_irqchip. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils: Disable appropriate APLIC DT nodes in fdt_fixups()Anup Patel1-0/+11
We should disable APLIC DT nodes in fdt_fixups() which are not accessible to the next booting stage based on currently assigned domain. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Add FDT based driver for APLICAnup Patel4-0/+218
We add simple FDT irqchip driver for APLIC so that generic platform (and other FDT based platforms) can utilize common APLIC initialization library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Add APLIC initialization libraryAnup Patel2-0/+280
We add simple APLIC initialization library which is independent of hardware description format (FDT or ACPI). This APLIC initialization library can be used by custom OpenSBI platform support to setup APLIC domains. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils: Disable appropriate IMSIC DT nodes in fdt_fixups()Anup Patel1-2/+30
We should disable IMSIC DT nodes in fdt_fixups() which are not accessible to the next booting stage based on currently assigned domain. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Add FDT based driver for IMSICAnup Patel4-0/+212
We add simple FDT irqchip driver for IMSIC so that generic platform (and other FDT based platforms) can utilize common IMIC library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Add IMSIC libraryAnup Patel2-0/+288
We add simple IMSIC library which is independent of hardware description format (FDT or ACPI). This IMSIC library can be used by custom OpenSBI platform support to setup IMSIC for external interrupts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-15lib: utils/irqchip: Allow multiple FDT irqchip driversAnup Patel1-7/+30
We can have multiple FDT irqchip drivers to be probed when a RISC-V system has different types of interrupt controller in a hierarchy. This will be certainly the case when a RISC-V system has both RISC-V AIA IMSIC and RISC-V AIA APLIC implemented. We extend simple FDT irqchip framework to allow multiple FDT irqchip drivers to be used for same RISC-V platform. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2022-02-04lib: utils/serial: Round UART8250 baud rate divisor to nearest integerVF_SDK_510_V1.2.1VF_SDK_510_V1.1.2VF_SDK_510_V1.0.2SDK_v2.3.3SDK_v2.3.0SDK_v2.1.1SDK_v2.1.0Jakub Luzny1-1/+1
Previously, it was rounded down and that gives suboptimal results when non-standard clock sources or baud rates are used. Signed-off-by: Jakub Luzny <jakub.luzny@codasip.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2022-02-04lib: fix compilation when strings.h is includedPetro Karashchenko1-1/+1
In a systems that provide strings.h and it is included together with sbi_bitops.h the compilation error appears. The ffs() and fls() are provided by strings.h Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 10:32:13 +0300