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path: root/include/sbi/riscv_encoding.h
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2020-09-09include: Rename ECALL defines to match latest RISC-V specAnup Patel1-2/+2
We rename CAUSE_HYPERVISOR_ECALL to CAUSE_SUPERVISOR_ECALL and CAUSE_SUPERVISOR_ECALL to CAUSE_VIRTUAL_SUPERVISOR_ECALL so that it matches latest RISC-V privilege spec. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01include: sbi: Few cosmetic changes in riscv_encoding.hAnup Patel1-87/+139
This patch does following cosmentic changes to riscv_encoding.h: 1. Re-organize CSR defines to match CSR listing in latest RISC-V privilege spec 2. Rename CSR_HCOUNTERNEN to CSR_HCOUNTEREN Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-09-01lib: sbi: Improve PMP CSR detection and progammingAnup Patel1-1/+66
As-per latest RISC-V privilege spec up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. This patch improves PMP CSR detection and progamming considering above facts. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-06-08lib: Add RISC-V hypervisor v0.6.1 supportAnup Patel1-3/+12
To support RISC-V hypervisor v0.6.1, we: 1. Don't need to explicitly forward WFI traps from VS/VU-mode 2. Have to delegate virtual instruction trap to HS-mode 3. Have to update trap redirection for changes in HSTATUS CSR Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-07lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementationAnup Patel1-0/+25
The HFENCE VVMA instructions flushes TLB based on the VMID present in HGATP CSR. To handle this, we get the current VMID for SBI HFENCE VVMA call and we use this current VMID to do remote TLB HFENCE VVMA on desired set of HARTs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-05-07include: sbi: Remove redundant page table related definesAnup Patel1-20/+0
We don't have page table programming in OpenSBI so let's remove redundant page table related defines from riscv_encoding.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-17lib: Support vector extensionAtish Patra1-0/+2
Enable vector context in mstatus by updating the corresponding bits in mstatus if vector extension is supported by the hart. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-12-16lib: Extend trap redirection for hypervisor v0.5 specAnup Patel1-3/+0
The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-12-16include: Add guest external interrupt related definesAnup Patel1-0/+4
With RISC-V H-extension v0.5 draft, we have special support for guest external interrupts so this patch adds related defines which were missed-out previously. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2019-11-06include: Use _UL() and _ULL() for defines in riscv_encoding.hAnup Patel1-81/+79
The riscv_encoding.h is shared with assembly sources so we use _UL() and _ULL() for register fields related defines. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-11-06include: Sync-up encoding with priv v1.12-draft and hypervisor v0.5-draftAnup Patel1-92/+45
This patch sync-up encoding header with the latest privilege specifications draft v1.12 and hypervisor specifications draft v0.5. The MSTATUS.MTL and HSTATUS.STL bits are not present anymore and will be removed by another patch series for hypervisor v0.5-draft. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-09-30lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSRAnup Patel1-1/+3
For platforms not having TIME CSR, we trap-n-emulate TIME CSR read/write in OpenSBI. Same rationale applies to HTIMEDELTA CSR as well so we trap-n-emulate HTIMEDELTA CSR for platforms not having TIME CSR. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-09-30lib: Redirect WFI trapped from VS/VU mode to HS-modeAnup Patel1-0/+3
The WFI will trap as illegal instruction trap when executed in VS/VU mode so we just forward/redirect it to HS-mode so that hypervisor can deal with it appropriately. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-09-30lib: Extend sbi_trap_redirect() for hypervisor extensionAnup Patel1-2/+30
When hypervisor extension is available, we can get traps from VS/VU modes. We should be able to force redirect some of these traps to HS-mode. In other words, we should be able forward traps from VS/VU mode to HS-mode using sbi_trap_redirect() hence this patch. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2019-09-30lib: Extend sbi_hart_switch_mode() to support hypervisor extensionAnup Patel1-0/+14
This patch extends sbi_hart_switch_mode() to support entering VS/VU modes when hypervisor extension is available. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-04-24all: Annotate some tables to have clang-format leave them aloneOlof Johansson1-0/+3
One of the shortcomings of clang-format is that it doesn't allow for aligned define tables, which is used for a number of constants. Add annotation to disable the automatic formatting where needed. Signed-off-by: Olof Johansson <olof@lixom.net>
2019-04-06lib: Fix the ecall macro definitionsAlistair Francis1-2/+2
Fix the ECALL definitions to matc the latest information in the privlidge spec table 5.5. Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2019-02-14lib: Use CSR_<FOO> instead of <foo> for csr_*()Atish Patra1-0/+8
Some older toolchains may not have all the csr's defined. Update all the csr functions to use the CSR_ #define values instead of the toolchain defined values. Suggested-by: Olof Johansson <olof@lixom.net> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2019-01-24all: Update copyright header in all filesAnup patel1-3/+3
This patch updates copyright header in all files as follows: 1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line 2. Change copyright year to 2019 for Western Digital Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-01-04include: Add hard FP access macros and definesAnup Patel1-0/+13
This patch adds hardware floating-point (hard FP) access macros and defines. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-31lib: Redirect illegal instruction trap to S-mode when not handledAnup Patel1-3/+6
Currently, we fail with error SBI_ENOTSUPP when we are not able to handle illegal instruction trap. Instead, we should just redirect illegal instruction trap to S-mode when not handled. This redirection of illegal instruction trap will help lazy save/restore of floating point registers to work correctly in Linux kernel. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-26lib: Move instruction encoding macros to riscv_encoding.hAnup Patel1-0/+117
This patch moves all instruction encoding macros to riscv_encoding.h. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-11Initial commit.Anup Patel1-0/+423
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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