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2023-06-23include: Bump-up version to 1.3v1.3Anup Patel1-1/+1
This patch updates OpenSBI version to 1.3 as part of release preparation. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2023-06-23lib: sbi: check A2 register in ecall_dbcn_handler.Gianluca Guida1-2/+5
Do not ignore register A2 (high bits of physical address) in the dbcn handler (RV64). Signed-off-by: Gianluca Guida <gianluca@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-06-21lib: reset: Move fdt_reset_init into generic_early_initGuo Ren1-3/+3
The fdt_reset_thead driver needs to modify the __reset_thead_csr_stub text region for the secondary harts booting. After that, the sbi_hart_pmp_configure may lock down the text region with M_READABLE & M_EXECUTABLE attributes in the future. Currently, the M_READABLE & M_EXECUtABLE have no effect on m-mode, the L-bit in pmpcfg csr is useless for the current opensbi scenario. See: Priv-isa-spec 3.7.1.2. Locking and Privilege Mode When the L bit is clear, any M-mode access matching the PMP entry will succeed; the R/W/X permissions apply only to S and U modes. That's why current fdt_reset_thead could still work well after commit: 230278dcf127 ("lib: sbi: Add separate entries for firmware RX and RW regions"). So this patch fixes up a fake bug for the M-mode permission setting of the future. Fixes: 230278dcf127 ("lib: sbi: Add separate entries for firmware RX and RW regions") Link: http://lists.infradead.org/pipermail/opensbi/2023-June/005176.html Reported-by: Jessica Clarke <jrtc27@jrtc27.com> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-06-21firmware: Fix find hart indexXiang W1-1/+0
After the loop to find the hartid is launched, assigning -1 to index will fail in the subsequent compare instruction bge. Fix This. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-06-15platform/lib: Set no-map attribute on all PMP regionsAlexandre Ghiti3-66/+10
This reverts commit 6966ad0abe70 ("platform/lib: Allow the OS to map the regions that are protected by PMP"). It was thought at the time of this commit that allowing the kernel to map PMP protected regions was safe but it is actually not: for example, the hibernation process will try to access any linear mapping page and then will fault on such mapped PMP regions [1]. Another issue is that the device tree specification [2] states that a !no-map region must be declared as EfiBootServicesData/Code in the EFI memory map which would make the PMP protected regions reclaimable by the kernel. And to circumvent this, RISC-V edk2 diverges from the DT specification to declare those regions as EfiReserved. The no-map attribute was removed to allow the kernel to use hugepages larger than 2MB to map the linear mapping to improve the performance but actually a recent talk from Mike Rapoport [3] stated that the performance benefit was marginal. For all those reasons, let's mark all the PMP protected regions as "no-map". [1] https://lore.kernel.org/linux-riscv/CAAYs2=gQvkhTeioMmqRDVGjdtNF_vhB+vm_1dHJxPNi75YDQ_Q@mail.gmail.com/ [2] "3.5.4 /reserved-memory and UEFI" https://github.com/devicetree-org/devicetree-specification/releases/download/v0.4-rc1/devicetree-specification-v0.4-rc1.pdf [3] https://lwn.net/Articles/931406/ Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Xiang W <wxjstz@126.com>
2023-06-14README.md: Improve project copyright informationAnup Patel1-2/+4
Over-time a lot of organizations and individuals have contributed to the OpenSBI project so let us add copyright RISC-V International to respect the contributions from all RISC-V members. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-14docs: Add OpenSBI logo and use it in the top-level README.mdAnup Patel3-0/+2
We do have an official OpenSBI logo which was designed few months ago and was also approved by RISC-V International. Lets add this logo under docs and also use it in the top-level README.md Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-06lib: utils/irqchip: Use scratch space to save per-HART IMSIC pointerAnup Patel2-17/+70
Instead of using a global array indexed by hartid, we should use scratch space to save per-HART IMSIC pointer and IMSIC file number. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/irqchip: Don't check hartid in imsic_update_hartid_table()Anup Patel1-3/+0
The imsic_map_hartid_to_data() already checks hartid before using so we don't need to check in imsic_update_hartid_table(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/irqchip: Use scratch space to save per-HART PLIC pointerAnup Patel1-22/+66
Instead of using a global array indexed by hartid, we should use scratch space to save per-HART PLIC pointer and PLIC context numbers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/timer: Use scratch space to save per-HART MTIMER pointerAnup Patel1-15/+61
Instead of using a global array indexed by hartid, we should use scratch space to save per-HART MTIMER pointer. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/ipi: Use scratch space to save per-HART MSWI pointerAnup Patel1-10/+33
Instead of using a global array indexed by hartid, we should use scratch space to save per-HART MSWI pointer. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/fdt: Use heap in FDT domain parsingAnup Patel1-42/+71
Let's use heap allocation in FDT domain parsing instead of using a fixed size global array. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/timer: Use heap in ACLINT MTIMER driverAnup Patel1-17/+30
Let's use heap allocation in ACLINT MTIMER driver instead of using a fixed size global array. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/irqchip: Use heap in PLIC, APLIC and IMSIC driversAnup Patel3-46/+42
Let's use heap allocation in PLIC, APLIC, and IMSIC irqchip drivers instead of using a fixed size global array. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/ipi: Use heap in ACLINT MSWI driverAnup Patel1-11/+10
Let's use heap allocation in ACLINT MSWI driver instead of using a fixed size global array. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/i2c: Use heap in DesignWare and SiFive I2C driversAnup Patel2-27/+20
Let's use heap allocation in DesignWare and SiFive I2C drivers instead of using a fixed size global array. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: utils/gpio: Use heap in SiFive and StartFive GPIO driversAnup Patel2-21/+20
Let's use heap allocation in SiFive and Starfive GPIO drivers instead of using a fixed size global array. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: sbi: Use scratch space to save per-HART domain pointerAnup Patel2-16/+45
Instead of using a global array indexed by hartid, we should use scratch space to save per-HART domain pointer. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: sbi: Use heap for root domain creationAnup Patel1-11/+34
Let's use heap allocation in root domain creation instead of using a fixed size global array. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: sbi_pmu: Use heap for per-HART PMU stateAnup Patel1-88/+127
Instead of using a global array for per-HART PMU state, we should use heap to on-demand allocate per-HART PMU state when the HART is initialized in cold boot or warm boot path. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: sbi: Print scratch size and usage at boot timeAnup Patel3-0/+19
The scratch space being a scarce resource so let us print it's size and usage at boot time. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05lib: sbi: Introduce simple heap allocatorAnup Patel4-0/+266
We provide simple heap allocator to manage the heap space provided by OpenSBI firmware and platform. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05platform: Allow platforms to specify heap sizeAnup Patel9-14/+58
We extend struct sbi_platform and struct sbi_scratch to allow platforms specify the heap size to the OpenSBI firmwares. The OpenSBI firmwares will use this information to determine the location of heap and provide heap base address in per-HART scratch space. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2023-06-05include: sbi_scratch: Add helper macros to access data typeAnup Patel1-0/+17
Reading and writing a data type in scratch space is a very common use-case so let us add related helper macros in sbi_scratch.h. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2023-06-04lib: sbi: Align system suspend errors with specAndrew Jones2-7/+16
The spec says sbi_system_suspend() will return SBI_ERR_INVALID_PARAM when "sleep_type is reserved or is platform-specific and unimplemented" and SBI_ERR_NOT_SUPPORTED when sleep_type "is not reserved and is implemented, but the platform does not support it due to one or more missing dependencies." Ensure SBI_ERR_INVALID_PARAM is returned for reserved sleep types and that the system suspend driver can choose which of the two error types to return itself by returning an error from its check function rather than a boolean. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-06-04lib: utils/ipi: buffer overrun aclint_mswi_cold_initHeinrich Schuchardt1-2/+2
The parameter checks in aclint_mswi_cold_init() don't guard against a buffer overrun. mswi_hartid2data is defined as an array of SBI_HARTMASK_MAX_BITS entries. The current check allows mswi->hart_count = ACLINT_MSWI_MAX_HARTS mswi->first_hartid = SBI_HARTMASK_MAX_BITS - 1. With these values mswi_hartid2data will be accessed at index SBI_HARTMASK_MAX_BITS + SBI_HARTMASK_MAX_BITS - 2. We have to check the sum of mswi->first_hartid and mswi->hart_count. Furthermore mswi->hart_count = 0 would not make much sense. Addresses-Coverity-ID: 1529705 ("Out-of-bounds write") Fixes: 5a049fe1d6a5 ("lib: utils/ipi: Add ACLINT MSWI library") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-26lib: utils: Improve fdt_timerXiang W1-20/+21
Remove dummy driver. Optimize fdt_timer_cold_init to exit the loop early. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-26lib: utils: Improve fdt_ipiXiang W1-20/+21
Remove dummy driver. Optimize fdt_ipi_cold_init to exit the loop early. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-26lib: utils: Improve fdt_serial_initXiang W1-31/+17
A final check of all DT nodes does not necessarily find a match, so SBI_ENODEV needs to be returned. Optimize removal of current_driver. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-26lib: sbi: Fix return of sbi_console_initXiang W1-1/+7
console is not a required peripheral. So it should return success when the console does not exist. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-22Makefile: Dereference symlinks on installFilip Filmar1-4/+4
Adds the `-L` flag (follow symlinks) to the `cp` commands used to install `libsbi.a` and `include/sbi/*`. This should make no difference in regular compilation. However, it does make a difference when compiling with bazel. Namely, bazel's sandboxing will turn all the source files into symlinks. After installation with `cp` the destination files will be symlinks pointing to the sandbox symlinks. As the sandbox files are removed when compilation ends, the just-copied symlinks become dangling symlinks. The resulting include files will be unusable due to the dangling symlink issues. Adding `-L` when copying ensures that the files obtained by executing the `install` targets are always dereferenced to files, rather than symlinks, eliminating this issue. Signed-off-by: Filip Filmar <fmil@google.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-21lib: sbi: Document sbi_ecall_extension membersAndrew Jones1-0/+35
With the introduction of the register_extensions callback the range members (extid_start and extid_end) may now change and it has become a bit subtle as to when a probe function should be implemented. Document all the members and their relationship to the register_extensions callback. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-21lib: sbi: Remove 0/1 probe implementationsAndrew Jones4-39/+10
When a probe implementation just returns zero for not available and one for available then we don't need it, as the extension won't be registered at all if it would return zero and the Base extension probe function will already set out_val to 1 if not probe function is implemented. Currently all probe functions only return zero or one, so remove them all. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-21lib: sbi: Optimize probe of srst/suspXiang W2-8/+12
No need to do a fully comprehensive count, just find a supported reset or suspend type Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-21lib: sbi: Only register available extensionsAndrew Jones6-22/+35
When an extension implements a probe function it means there's a chance that the extension is not available. Use this function in the register_extensions callback to determine if the extension should be registered at all. Where the probe implementation is simple, just open code the check. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-21lib: sbi: pmu: Remove unnecessary probe functionAndrew Jones1-8/+0
The absence of a probe implementation means that the extension is always available. Remove the implementation for the PMU extension, which does no checking, and indeed even has a comment saying it's always available. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-21lib: sbi: Narrow vendor extension rangeAndrew Jones1-4/+7
The vendor extension ID range is large, but at runtime at most a single ID will be available. Narrow the range in the register_extensions callback. After narrowing, we no longer need to check that the extension ID is correct in the other callbacks, as those callbacks will never be invoked with anything other than the single ID. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-21lib: sbi: Introduce register_extensions extension callbackAndrew Jones14-43/+143
Rather than registering all extensions on their behalf in sbi_ecall_init(), introduce another extension callback and invoke that instead. For now, implement each callback by simply registering the extension, which means this patch has no intended functional change. In later patches, extension callbacks will be modified to choose when to register and to possibly narrow the extension ID range prior to registering. When an extension range needs to remove IDs, leaving gaps, then multiple invocations of sbi_ecall_register_extension() may be used. In summary, later patches for current extensions and the introductions of future extensions will use the new callback to ensure that only valid extension IDs from the initial range, which are also available, will be registered. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-11lib: sbi: Simplify BITS_PER_LONG definitionXiang W1-7/+1
No need to use #elif ladder when defining BITS_PER_LONG. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-11lib: sbi: Simplify sbi_ipi_process remove gotoXiang W1-8/+5
Simplify sbi_ipi_process() by removing goto statement. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-05-11lib: sbi: Remove unnecessary semicolonXiang W15-19/+19
We have redundant semicolon at quite a few places so let's remove it. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-04-20lib: sbi: Add debug print when sbi_pmu_init failsTan En De1-1/+4
Since sbi_pmu_init is called after sbi_console_init, the sbi_printf can be called when sbi_pmu_init fails. Signed-off-by: Tan En De <ende.tan@starfivetech.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2023-04-17lib: sbi: Don't check SBI error range for legacy console getcharAnup Patel1-1/+3
The legacy console getchar SBI call returns character value in the sbiret.error field so the "SBI_SUCCESS < ret" check in sbi_ecall_handler() results in unwanted error prints for the legacy console getchar SBI call. Let's suppress these unwanted error prints. Fixes: 67b2a408924b ("lib: sbi: sbi_ecall: Check the range of SBI error") Signed-off-by: Anup Patel <apatel@ventanamicro.com>
2023-04-17lib: sbi: Fix counter index calculation for SBI_PMU_CFG_FLAG_SKIP_MATCHAlexandre Ghiti1-2/+7
As per the SBI specification, we should "unconditionally select the first counter from the set of counters specified by the counter_idx_base and counter_idx_mask", so implement this behaviour. Suggested-by: Atish Patra <atishp@atishpatra.org> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2023-04-17lib: sbi: Do not clear active_events for cycle/instret when stoppingAlexandre Ghiti1-1/+1
Those events are enabled by default and should not be reset afterwards since when using SBI_PMU_CFG_FLAG_SKIP_MATCH, it leads to unaccessible counters after the first use. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
2023-04-17firmware: Change to use positive offset to access relocation entriesBin Meng1-8/+7
The codes currently skip the very first relocation entry, but later reference the elements in the relocation entry using minus offsets. Change to use positive offsets so that there is no need to skip the first relocation entry. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Xiang W <wxjstz@126.com>
2023-04-17firmware: Optimize loading relocation typeBin Meng1-1/+0
't5' already contains relocation type so don't bother reloading it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Xiang W <wxjstz@126.com>
2023-04-14platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errataLad Prabhakar7-2/+95
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-04-14lib: sbi: Optimize sbi_tlb queue waitingXiang W3-26/+35
When tlb_fifo is full, it will wait and affect the ipi update to other harts. This patch is optimized. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org>
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