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2020-02-24include: Bump-up version to 0.6v0.6Anup Patel1-1/+1
This patch updates OpenSBI version to 0.6 as part of release preparation. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-24lib: Simplify the for-loop in sbi_ipi_send_many()Anup Patel1-9/+1
We don't need to separately call sbi_ipi_send() for current HART in sbi_ipi_send_many(). Instead, we can simplify the for-loop in sbi_ipi_send_many() and call sbi_ipi_send() for all HARTs in the for-loop itself. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-22lib: Use available hart mask for correct hbase valueAtish Patra1-13/+16
As per the latest SBI specification, all online harts should receive IPI if hbase is set to -1. Set the target mask to all available hart mask if hbase is -1. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-22lib: Fix typo in atomic exchange functionsAtish Patra1-1/+1
There is a typo in atomic operations code which prevents the usage of riscv atomic instructions even if it is supported. Fix the typo. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-19platform: qemu: virt: Correct the typo in config.mkBin Meng1-4/+4
It should be "aligned". Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-19platform: sifive: fu540: Add 32-bit specific fdt/payload addressesBin Meng2-2/+18
For testing 32-bit SiFive specific drivers with QEMU riscv32, add 32-bit specific FW_JUMP_FDT_ADDR and FW_PAYLOAD_OFFSET. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-19lib: Print interrupt and exception delegation in boot printsAnup Patel3-2/+15
We print MIDELEG and MEDELEG CSRs as part of boot prints so that boot log shows the interrupts and exceptions delegated to S-mode. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-19lib: Don't check MIDELEG and MEDELEG at end of delegate_traps()Anup Patel1-5/+0
The MIDELEG and MEDELEG CSR checks at end of delegate_traps() were added for initial bring-up on SiFive Unleashed and QEMU. These checks are not required any more and in-future these checks can cause failures because some of the MIDELEG/MEDELEG bits will be hard-wired to 0 or 1. For related discussion, refer github issue: https://github.com/riscv/opensbi/issues/157 Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-18lib: utils: htif: Fix 32-bit buildBin Meng1-3/+3
When building 32-bit OpenSBI images, we get: lib/utils/sys/htif.c: In function '__check_fromhost': lib/utils/sys/htif.c:12:31: error: left shift count >= width of type [-Werror=shift-count-overflow] #define HTIF_DATA_MASK ((1UL << HTIF_DATA_BITS) - 1) ^~ Fixes: c2f23cc6edd7 ("platform: Add Spike initial support") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-18Revert "lib: Use __builtin_ctzl() in pmp_get()"Anup Patel1-1/+13
This reverts commit 897b8fbdd92fcfad194417d348b8dad16ab0e17a. We are seeing compile errors using newlib based GCC cross-toolchain so we restore back old ctz() implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-18doc: thead-c910: Fix doc stylesBin Meng1-3/+3
- make title underline the same length as the title itself - satisfy the 80 character per line rule as much as possible Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-18doc: sifive_fu540: Fix doc stylesBin Meng1-8/+10
- make title underline the same length as the title itself - put all URLs at the end of the doc Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-18doc: qemu_virt: Fix doc stylesBin Meng1-1/+0
Remove the unnecessary blank line at the end of the doc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-18doc: ariane-fpga: Fix doc stylesBin Meng1-11/+12
Various styles fixes including: - satisfy the 80 character per line rule as much as possible - make title underline the same length as the title itself - remove the redundant FPGA (was FPGA FPGA SoC) Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-18doc: andes-ae350: Fix doc stylesBin Meng1-8/+10
Various styles fixes including: - satisfy the 80 character per line rule as much as possible - remove unnecessary spaces between words Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-18doc: payload_linux: Fix doc stylesBin Meng1-1/+0
Remove the unnecessary blank line at the end of the doc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-18doc: coreboot: Fix doc stylesBin Meng1-3/+11
- put all URLs at the end of the doc - satisfy the 80 character per line rule as much as possible Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-18ThirdPartyNotices: Fix doc stylesBin Meng1-1/+0
Remove the unnecessary blank line at the end of the doc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-17docs: platform: Add documentation for Spike platformAnup Patel2-0/+92
This patch adds documentation to build and run OpenSBI on Spike simulator and QEMU Spike machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-17scripts: Add Spike to platform list of binary archive scriptAnup Patel1-0/+1
The Spike platform support works perfectly fine on QEMU RV64 Spike machine and Spike emulator. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-17platform: Remove stale options from config.mk filesAnup Patel2-10/+0
This patch removes stale options from config.mk files of Ariane FPGA and QEMU virt platform support. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-17platform: Add Spike initial supportJames Clarke6-0/+327
This patch adds initial platform support Spike emulator. Signed-off-by: James Clarke <jrtc27@jrtc27.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-13lib: irqchip/plic: Disable all contexts and IRQsAtish Patra1-4/+4
To initialize PLIC in sane state, we should: 1. set maximum threshold value of M-mode PLIC contexts 2. set maximum threshold value of S-mode PLIC contexts 3. set irq priorities to miniumum Fix the comment and initialize the threshold/priorities correctly. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com>
2020-02-13lib: Initialize out value in SBI callsAtish Patra1-1/+1
As per the SBI specification, the return value in sbiret is undefined if not explicitly described in the function. However, supervisor may check this value by mistake and get a garbage value. Initialize it to zero to avoid nasty supervisor bugs. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-13lib: Use __builtin_ctzl() in pmp_get()Li Jinpei1-13/+1
We should should __builtin_ctzl() in pmp_get() instead of custom ctz() function. Signed-off-by: Li Jinpei <leekingp1994@163.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-13lib: sbi_scratch: use bitwise ops in sbi_scratch_alloc_offset()Li Jinpei1-2/+2
Instead of using loop to make "size" machine word aligned, we should use bitwise ops. Signed-off-by: Li Jinpei <leekingp1994@163.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-11doc: sifive: fu540: Update QEMU instruction when using U-Boot as the payloadBin Meng1-0/+10
Document that when U-Boot v2020.01 (or higher) is used as the payload, we need adjust the instructions a little bit when testing OpenSBI with QEMU 'sifive_u' machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-02-07platform: sifive: fu540: Add platform specific 'make run' cmdBin Meng1-0/+4
This adds sifive/fu540 specific QEMU run command. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-07platform: Drop qemu/sifive_u supportBin Meng8-286/+8
With QEMU v4.2 RISC-V changes to improve the emulation fidelity of 'sifive_u' machine, OpenSBI v0.4 / U-Boot v2019.10 / Linux kernel v5.3 images built for the SiFive HiFive Unleashed board can be used out of the box without any special hack. Hence there is no need for us to continue supporting such a special target in OpenSBI. Going forward, sifive/fu540 platform can be used on both real hardware and QEMU 'sifive_u' machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-06makefile: add support for building on macOSAlex Richardson1-3/+10
On macOS the readlink command does not include a -f flag. Instead default to using GNU readlink (which is often installed as greadlink). Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-02-05platform: sifive/fu540: Set tlb range flush limit to zeroAtish Patra1-0/+9
It was reported that tlb range flush is not working on fu540. Only tlb full flush seems to work on fu540 probably due to some hardware errata. Set the tlb flush limit to zero so that all tlb flush requests are converted to full flush. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-02-05platform: Add an platform ops to return platform specific tlb flush limitAtish Patra2-9/+7
If a platform requires to perform a tlb full flush, they should set the tlb_range_flush_limit value to zero. However, corresponding platform API ignore the value and continue to return the default value. Add a platform ops to retrieve platform specific tlb range flush limit. The platform variable becomes redundant in presence of the platform ops. Take this opportunity to remove the variable as well. The default is still set to smallest page size in RISC-V (4KB), as there is no way to figure out a best value for all platforms. Individual platform should set it to the optimal value for their platform. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-01-25platform: Update UART base addresses for qemu/sifve_uNikita Ermakov1-2/+2
In the QEMU [1] there was a change of the UART base addresses for sifive_u machine to match the hardware. Make corresponding changes in the opensbi for qemu/sifive_u platform. [1] https://git.qemu.org/?p=qemu.git;a=commitdiff;h=4b55bc2b5f7ff065da5d2b813ee5153c598d3764 Signed-off-by: Nikita Ermakov <coffe92@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-01-24platform: template: typo fix in system reboot/shutdown namesJiuyang Liu (Sequencer)1-2/+2
This patch does minor typo fix in system reboot/shutdown names in platform operations. Signed-off-by: Jiuyang Liu (Sequencer) <liujiuyang1994@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com>
2020-01-22lib: Factor-out SBI base extensionAnup Patel4-71/+86
This patch factor-out SBI base extension into its own source for better modularity of SBI implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Factor-out SBI vendor extensionAnup Patel4-27/+44
This patch factor-out SBI vendor extension into its own source for better modularity of SBI implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Factor-out SBI replacement extensionsAnup Patel4-133/+150
This patch factor-out SBI replacement extensions (such as RFENCE, IPI, and TIME) into its own source for better modularity of SBI implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Factor-out SBI legacy extensionAnup Patel4-102/+123
This patch factor-out SBI legacy extension into its own source for better modularity of SBI implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Add dynamic registration of SBI extensionsAnup Patel3-66/+200
This patch extends our SBI ecall implementation to allow dynamic registration of various SBI extensions. Using this dynamic registration we can break-up SBI ecall implementation into multiple files and even register experimental/custom SBI extensions from platform code. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22include: Add generic and simple list handling APIsAnup Patel2-0/+163
This patch adds generic and simple list handling APIs adapted from Xvisor sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Initialize TLB management directly from coldboot/warmboot pathAnup Patel2-6/+9
Currently, the remote TLB management is initialized via IPI init which is counter intuitive. This patch initializes remote TLB management directly from init_coldboot() and init_warmboot() after IPI init is done. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Drop _fifo from the name of various sbi_tlb_fifo_xyz() functionsAnup Patel4-56/+46
This patch drops _fifo from the name of various sbi_tlb_fifo_xyz() functions because all these functions deal with remote TLB managment and FIFO is the per-HART data structure used internally by remote TLB implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Introduce sbi_ipi_event_create/destroy() APIsAnup Patel4-48/+148
This patch introduces sbi_ipi_event_create/destroy() APIs and struct sbi_ipi_event_ops for creating/destroying IPI events at runtime based of event operations. This new APIs will help platform code and utils code to create custom IPI events which are not part of generic OpenSBI library. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Introduce sbi_tlb_fifo_request() APIAnup Patel4-36/+33
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_tlb_fifo_request() for halting a set of HARTs. This way in future we can assign any IPI event number for remote FENCE within sbi_tlb.c only. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Introduce sbi_ipi_send_halt() APIAnup Patel3-6/+12
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_ipi_send_halt() for halting a set of HARTs. This way in future we can assign any IPI event number for HART halting within sbi_ipi.c only. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Introduce sbi_ipi_send_smode() APIAnup Patel3-4/+10
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_ipi_send_smode() for injecting S-mode software interrupts. This way in future we can assign any IPI event number for S-mode IPIs within sbi_ipi.c only. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22lib: Move struct sbi_ipi_data definition to sbi_ipi.cAnup Patel2-5/+4
The struct sbi_ipi_data is only used in sbi_ipi.c so move it to sbi_ipi.c from sbi_ipi.h. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-22include: Typo fix in comment for SBI_SCRATCH_SIZE defineAnup Patel1-1/+1
This patch fixes a minor typo in comment for SBI_SCRATCH_SIZE define. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-01-20scripts: Add C910 to platform list in the binary archive scriptLiu Yibin1-0/+1
This patch adds T-HEAD C910 to RV64 platform list in the binary archive script. Signed-off-by: Liu Yibin <yibin_liu@c-sky.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2020-01-15platform: thead/c910: Don't set plic/clint address in warm bootLiu Yibin1-4/+4
Since all harts share the same plic/clint address now, setting them during cold boot is just fine. Signed-off-by: Liu Yibin <yibin_liu@c-sky.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
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