starfive-tech/opensbi.git/platform, branch rtthread_AMP

platform: starfive: add PMIC power ops in JH7110 visionfive2 board

2023-03-09T15:41:20+00:00

add reboot and poweroff support. The whole reboot and shutdown pm op includes shutdown jh7110 pmu device power domain and access on board pmic register through I2C. Signed-off-by: Minda Chen Reviewed-by: Anup Patel

gpio/starfive: add gpio driver and support gpio reset

2023-03-01T03:29:33+00:00

Add gpio driver and gpio reset function in Starfive JH7110 SOC platform. Signed-off-by: minda.chen Reviewed-by: Anup Patel

platform: generic: Add system suspend test

2023-02-27T14:20:51+00:00

When the system-suspend-test property is present in the domain config node as shown below, implement system suspend with a simple 5 second delay followed by a WFI. This allows testing system suspend when the low-level firmware doesn't support it. / { chosen { opensbi-domains { compatible = "opensbi,domain,config"; system-suspend-test; }; Signed-off-by: Andrew Jones Reviewed-by: Anup Patel

platform: generic: renesas: rzfive: Configure the PMA region

2023-02-27T06:06:06+00:00

On the Renesas RZ/Five SoC by default we want to configure 128MiB of memory ranging from 0x58000000 as a non-cacheable + bufferable region in the PMA and populate this region as PMA reserve DT node with shared DMA pool and no-map flags set so that Linux drivers requesting any DMA'able memory go through this region. PMA node passed to the above stack: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

platform: generic: renesas: rzfive: Add support to configure the PMA

2023-02-27T06:05:01+00:00

I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason IP blocks using DMA will fail. The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) block that allows dynamic adjustment of memory attributes in the runtime. It contains a configurable amount of PMA entries implemented as CSR registers to control the attributes of memory locations in interest. Below are the memory attributes supported: * Device, Non-bufferable * Device, bufferable * Memory, Non-cacheable, Non-bufferable * Memory, Non-cacheable, Bufferable * Memory, Write-back, No-allocate * Memory, Write-back, Read-allocate * Memory, Write-back, Write-allocate * Memory, Write-back, Read and Write-allocate More info about PMA (section 10.3): Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. Example PMA region passed as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; }; Signed-off-by: Lad Prabhakar Reviewed-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

include: sbi: Remove extid parameter from vendor_ext_provider() callback

2023-02-27T05:56:37+00:00

The extid parameter of vendor_ext_provider() is redundant so let us remove it. Signed-off-by: Anup Patel

lib: sbi: Align SBI vendor extension id with mvendorid CSR

2023-02-27T05:56:35+00:00

As-per the SBI specification, the lower 24bits of the SBI vendor extension id is same as lower 24bits of the mvendorid CSR. We update the SBI vendor extension id checking based on above. Signed-off-by: Anup Patel

platform: generic/andes: Fix ae350.c header dependency

2023-02-27T04:32:29+00:00

The code calls various macros from riscv_asm.h which is not directly included. Fix such dependency. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

platform: generic/allwinner: Fix sun20i-d1.c header dependency

2023-02-27T04:30:15+00:00

The code calls various macros from riscv_asm.h and sbi_scratch.h which are not directly included. Fix such dependency. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

platform: generic: allwinner: Advertise nonretentive suspend

2023-01-24T12:00:21+00:00

Add D1's nonretentive suspend state to the devicetree so S-mode software knows about it and can use it. Latency and power measurements were taken on an Allwinner Nezha board: - Entry latency was measured from the beginning of sbi_ecall_handler() to before the call to wfi() in sun20i_d1_hart_suspend(). - Exit latency was measured from the beginning of sbi_init() to before the call to sbi_hart_switch_mode() in init_warmboot(). - There was a 17.5 mW benefit from non-retentive suspend compared to WFI, with a 170 mW cost during the 107 us entry/exit period. This provides a break-even point around 1040 us. Residency includes entry latency, so round this up to 1100 us. - The hardware power sequence latency (after the WFI) is assumed to be negligible, so set the wakeup latency to the exit latency. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland