<feed xmlns='http://www.w3.org/2005/Atom'>
<title>starfive-tech/opensbi.git/lib, branch SDK_v2.1.0</title>
<subtitle>StarFive Tech OpenSBI for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/opensbi.git/atom?h=SDK_v2.1.0</id>
<link rel='self' href='https://git.radix-linux.su/starfive-tech/opensbi.git/atom?h=SDK_v2.1.0'/>
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<updated>2022-02-04T05:46:29+00:00</updated>
<entry>
<title>lib: utils/serial: Round UART8250 baud rate divisor to nearest integer</title>
<updated>2022-02-04T05:46:29+00:00</updated>
<author>
<name>Jakub Luzny</name>
<email>jakub.luzny@codasip.com</email>
</author>
<published>2022-01-21T15:06:14+00:00</published>
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<id>urn:sha1:ce4c0188d96b2c20c2e08d24646a5e517fe15a4b</id>
<content type='text'>
Previously, it was rounded down and that gives suboptimal results when
non-standard clock sources or baud rates are used.

Signed-off-by: Jakub Luzny &lt;jakub.luzny@codasip.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: fix compilation when strings.h is included</title>
<updated>2022-02-04T05:34:19+00:00</updated>
<author>
<name>Petro Karashchenko</name>
<email>petro.karashchenko@gmail.com</email>
</author>
<published>2022-01-28T07:13:23+00:00</published>
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<id>urn:sha1:6ad8917b7e27e5e80fb9268492b9111b17ed2024</id>
<content type='text'>
In a systems that provide strings.h and it is included
together with sbi_bitops.h the compilation error appears.
The ffs() and fls() are provided by strings.h

Signed-off-by: Petro Karashchenko &lt;petro.karashchenko@gmail.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Disable interrupt and inhibit counting in M-mode during init</title>
<updated>2022-02-04T04:40:28+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2022-01-07T18:54:09+00:00</published>
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<id>urn:sha1:a26dc609df04ca4704873b683ac03855f20b056e</id>
<content type='text'>
Currently, the mhpmevent CSRs are untouched during hart init during
cold/warm boot. Ideally, we should clear out all the bits except
overflow and MINH bit. That is required to disable overflow
interrupt and inhibit counting in M-mode to avoid any spurious
interrupts before perf start.

Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Disable interrupt during config matching</title>
<updated>2022-02-04T04:38:57+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2022-01-07T18:54:08+00:00</published>
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<id>urn:sha1:3b7c204dcaa58e415ad7451c2a690bb88773abbf</id>
<content type='text'>
PMU overflow interrupt should be disabled durinig initial configuration of
counters. They should be enabled while starting counters.

Fixes: 730f01bb41a6 ("lib: sbi: Support sscofpmf extension in OpenSBI")
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Map only the counters enabled in hardware</title>
<updated>2022-02-04T04:37:07+00:00</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2022-01-07T18:54:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=632f59392bbaa05176376b7d7a9f77f611816614'/>
<id>urn:sha1:632f59392bbaa05176376b7d7a9f77f611816614</id>
<content type='text'>
The counter mapping in DT may be incorrect if all the counters specified
in the mapping are actually not physically present in the hardware.
OpenSBI should only keep a mapping of counters enabled in hardware and
defined in DT. This assume that all the programmable hpmcounters are
consecutive as it doesn't make sense to build a system with sparse
hpmcounters.

Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: fix pointer of type 'void *' used in arithmetic</title>
<updated>2022-01-21T16:28:12+00:00</updated>
<author>
<name>Jukka Laitinen</name>
<email>jukka.laitinen@iki.fi</email>
</author>
<published>2022-01-19T09:20:17+00:00</published>
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<id>urn:sha1:5d025eb2353550eadbd2fa9b8083a92fe9b07bd9</id>
<content type='text'>
Using "void *" in arithmetic causes errors with strict compiler settings:
"error: pointer of type 'void *' used in arithmetic [-Werror=pointer-arith]"

Avoid these by calculating on "char *" where 1-byte data size is assumed.

Signed-off-by: Jukka Laitinen &lt;jukkax@ssrc.tii.ae&gt;
Reviewed-by: Dong Du &lt;Dd_nirvana@sjtu.edu.cn&gt;
Reviewed-by: Xiang W &lt;wxjstz@126.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: utils/sys: Extend HTIF library to allow custom base address</title>
<updated>2022-01-11T12:47:49+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-01-06T03:46:55+00:00</published>
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<id>urn:sha1:6dde43584f185f71a8dd713deb438d7c724a9ad5</id>
<content type='text'>
Some of RISC-V emulators provide HTIF at fixed base address so for
such emulators users have to hard-code HTIF base address in the
linker script.

To address this problem, we let users optionally provide fixed HTIF
base address via platform support (or device tree).

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Dong Du &lt;Dd_nirvana@sjtu.edu.cn&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: utils/ipi: Fix size check in aclint_mswi_cold_init()</title>
<updated>2022-01-11T12:47:07+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-01-06T03:32:45+00:00</published>
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<id>urn:sha1:5b9960379fae14b554c953b0d4139f4b1a57cd5e</id>
<content type='text'>
Currently, the ACLINT MSWI size check is forcing size to be at least
0x4000. This is inappropriate check because most systems will never
utilize full 16KB for a single ACLINT MSWI device so instead we should
check that ACLINT MSWI size is enough for on the associated HARTs.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Dong Du &lt;Dd_nirvana@sjtu.edu.cn&gt;
Reviewed-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
</content>
</entry>
<entry>
<title>firmware: Move memcpy/memset mapping to fw_base.S</title>
<updated>2021-12-23T12:16:09+00:00</updated>
<author>
<name>Anup Patel</name>
<email>anup.patel@wdc.com</email>
</author>
<published>2021-12-22T12:31:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=d30bde36d5b7a7ad74176ddf9ede4d7eb2bca86b'/>
<id>urn:sha1:d30bde36d5b7a7ad74176ddf9ede4d7eb2bca86b</id>
<content type='text'>
Some of the external firmwares using OpenSBI as library are facing
issues with the weak memcpy() and memset() aliases in libsbi.a so
we move these to fw_base.S. This way mapping of implicit memcpy()
or memset() calls to sbi_memcpy() or sbi_memset() will only be done
for OpenSBI firmwares.
(Refer, https://github.com/riscv-software-src/opensbi/issues/234)

In addition, we also add memmove() and memcmp() mappings in fw_base.S
because as-per the GCC documentation the freestanding environment must
provide memcpy(), memmove(), memset(), and memcmp().

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: simplify pmp_set(), pmp_get()</title>
<updated>2021-12-22T03:35:05+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2021-12-17T17:02:58+00:00</published>
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<id>urn:sha1:2082153fc90c54b98647b1fbaeb7511fd57b7d2b</id>
<content type='text'>
pmpcfg_csr and pmpcfg_shift are only negative for an unexpected value of
__riscv_xlen. We can immediately return in this case.

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Dong Du &lt;Dd_nirvana@sjtu.edu.cn&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
</content>
</entry>
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