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<title>starfive-tech/opensbi.git/lib/sbi/sbi_init.c, branch rtthread_AMP</title>
<subtitle>StarFive Tech OpenSBI for VisionFive (JH7110) boards (mirror)</subtitle>
<id>https://git.radix-linux.su/starfive-tech/opensbi.git/atom?h=rtthread_AMP</id>
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<updated>2023-03-10T08:43:40+00:00</updated>
<entry>
<title>lib: sbi: Clear IPIs before init_warm_startup in non-boot harts</title>
<updated>2023-03-10T08:43:40+00:00</updated>
<author>
<name>Evgenii Shatokhin</name>
<email>e.shatokhin@yadro.com</email>
</author>
<published>2023-03-05T21:22:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=c6a092cd80112529cb2e92e180767ff5341b22a3'/>
<id>urn:sha1:c6a092cd80112529cb2e92e180767ff5341b22a3</id>
<content type='text'>
Since commit 50d4fde1c5a4 ("lib: Remove redundant sbi_platform_ipi_clear()
calls"), the IPI sent from the boot hart in wake_coldboot_harts() is not
cleared in the secondary harts until they reach sbi_ipi_init(). However,
sbi_hsm_init() and sbi_hsm_hart_wait() are called earlier, so a secondary
hart might enter sbi_hsm_hart_wait() with an already pending IPI.

sbi_hsm_hart_wait() makes sure the hart leaves the loop only when it is
actually ready, so a pending unrelated IPI should not cause safety issues.
However, it might be inefficient on certain hardware, because it prevents
"wfi" from stalling the hart even if the hardware supports this, making the
hart needlessly spin in a "busy-wait" loop.

This behaviour can be observed, for example, in a QEMU VM (QEMU 7.2.0) with
"-machine virt" running a Linux guest. Inserting delays in
sbi_hsm_hart_start() allows reproducing the issue more reliably.

The comment in wait_for_coldboot() suggests that the initial IPI is needed
in the warm resume path, so let us clear it before init_warm_startup()
only.

To do this, sbi_ipi_raw_clear() was created similar to sbi_ipi_raw_send().

Signed-off-by: Evgenii Shatokhin &lt;e.shatokhin@yadro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Refactor the calls to sbi_hart_switch_mode()</title>
<updated>2023-03-10T08:30:36+00:00</updated>
<author>
<name>Evgenii Shatokhin</name>
<email>e.shatokhin@yadro.com</email>
</author>
<published>2023-03-05T21:22:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=d56049e299cce3bca2022903a5550acdc323d8a4'/>
<id>urn:sha1:d56049e299cce3bca2022903a5550acdc323d8a4</id>
<content type='text'>
Move them into sbi_hsm_hart_start_finish() and sbi_hsm_hart_resume_finish()
to make them easier to manage.

This will be used by subsequent patches.

Suggested-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Evgenii Shatokhin &lt;e.shatokhin@yadro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Add system suspend skeleton</title>
<updated>2023-02-27T14:13:52+00:00</updated>
<author>
<name>Andrew Jones</name>
<email>ajones@ventanamicro.com</email>
</author>
<published>2023-02-27T10:31:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=73623a0acac7f62646757cdd5a03b325eba3e0c9'/>
<id>urn:sha1:73623a0acac7f62646757cdd5a03b325eba3e0c9</id>
<content type='text'>
Add the SUSP extension probe and ecall support, but for now the
system suspend function is just a stub.

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Print the RW section offset</title>
<updated>2023-01-23T04:36:14+00:00</updated>
<author>
<name>Himanshu Chauhan</name>
<email>hchauhan@ventanamicro.com</email>
</author>
<published>2023-01-19T15:18:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=b666760bfafda75b6d31d6f9f01bcc60bc673aa4'/>
<id>urn:sha1:b666760bfafda75b6d31d6f9f01bcc60bc673aa4</id>
<content type='text'>
Print the RW section offset when firmware base and size is
being printed.

Signed-off-by: Himanshu Chauhan &lt;hchauhan@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Allow platform to influence cold boot HART selection</title>
<updated>2023-01-07T10:28:49+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-12-29T02:56:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=f14595a7cfc8de16a06335c6ecdf9ae23a0adf53'/>
<id>urn:sha1:f14595a7cfc8de16a06335c6ecdf9ae23a0adf53</id>
<content type='text'>
We add an optional cold_boot_allowed() platform callback which allows
platform support to decide which HARTs can do cold boot initialization.

If this platform callback is not available then any HART can do cold
boot initialization.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
</content>
</entry>
<entry>
<title>treewide: Replace TRUE/FALSE with true/false</title>
<updated>2023-01-06T11:56:35+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2022-12-21T11:38:06+00:00</published>
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<id>urn:sha1:440fa818fbffd0771d75890c4fcda062ceab7ebd</id>
<content type='text'>
C language standard uses true/false for the boolean type.
Let's switch to that for better language compatibility.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Samuel Holland &lt;samuel@sholland.org&gt;
Tested-by: Samuel Holland &lt;samuel@sholland.org&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Print platform PMU device at boot-time</title>
<updated>2022-09-01T11:23:25+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-08-24T09:59:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=ee69f8eeb3c16bfdb4bb3d8b5033fb8a7816f7b6'/>
<id>urn:sha1:ee69f8eeb3c16bfdb4bb3d8b5033fb8a7816f7b6</id>
<content type='text'>
Let us print the platform PMU device name at the boot-time so that users
know whether the underlying platform has custom per-HART PMU operations.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Convert hart features into hart extensions</title>
<updated>2022-05-07T04:46:30+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-04-28T15:59:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=cad6c91045331009f38d13f63956a119b0b053c8'/>
<id>urn:sha1:cad6c91045331009f38d13f63956a119b0b053c8</id>
<content type='text'>
Since past few years, we have been using "hart features" in OpenSBI
to represent all optionalities and multi-letter extensions defined
by the RISC-V specifications.

The RISC-V profiles specification has taken a different approach and
started assigning extension names for all optionalities which did not
have any extension name previously.
(Refer, https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc)

Inspired from the RISC-V profiles specification, we convert OpenSBI
hart features into hart extensions. Going forward, we align the
extension naming with RISC-V profiles specification. Currently, only
"time CSR" and "AIA CSR" have not been assigned extension name but
for everything else we have a name.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Update the name of ISA string printed at boot time</title>
<updated>2022-05-07T04:33:24+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-04-28T12:41:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=5b8b377178df56ee6bca2cf31b7580ca07cb7d70'/>
<id>urn:sha1:5b8b377178df56ee6bca2cf31b7580ca07cb7d70</id>
<content type='text'>
The ISA string printed at boot time is not the complete ISA string
representing all single letter and multi-letter extensions rather
it is base ISA string derived from misa CSR so let us update the
boot print accordingly.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>lib: sbi: Detect and print privileged spec version</title>
<updated>2022-05-07T04:19:54+00:00</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-04-28T12:00:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/starfive-tech/opensbi.git/commit/?id=1a754bb36522247e51fdb95323c5fa3e256db872'/>
<id>urn:sha1:1a754bb36522247e51fdb95323c5fa3e256db872</id>
<content type='text'>
It is possible to guess privileged spec versions based on the CSRs
that where introduced in different privileged spec versions. In
future, if we are not able guess privileged spec version then we
can have platform provide it.

We add privileged spec version as per-hart feature and try to guess
it based on presence of mcounteren, mcountinhibit, and menvcfg CSRs.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
</content>
</entry>
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