starfive-tech/opensbi.git/include, branch rtthread_AMP

sbi: add amp ipi call function support

2023-12-05T06:08:57+00:00

Add amp IPI call and set amp data address support. Signed-off-by: Minda Chen

lib: sbi: Clear IPIs before init_warm_startup in non-boot harts

2023-03-10T08:43:40+00:00

Since commit 50d4fde1c5a4 ("lib: Remove redundant sbi_platform_ipi_clear() calls"), the IPI sent from the boot hart in wake_coldboot_harts() is not cleared in the secondary harts until they reach sbi_ipi_init(). However, sbi_hsm_init() and sbi_hsm_hart_wait() are called earlier, so a secondary hart might enter sbi_hsm_hart_wait() with an already pending IPI. sbi_hsm_hart_wait() makes sure the hart leaves the loop only when it is actually ready, so a pending unrelated IPI should not cause safety issues. However, it might be inefficient on certain hardware, because it prevents "wfi" from stalling the hart even if the hardware supports this, making the hart needlessly spin in a "busy-wait" loop. This behaviour can be observed, for example, in a QEMU VM (QEMU 7.2.0) with "-machine virt" running a Linux guest. Inserting delays in sbi_hsm_hart_start() allows reproducing the issue more reliably. The comment in wait_for_coldboot() suggests that the initial IPI is needed in the warm resume path, so let us clear it before init_warm_startup() only. To do this, sbi_ipi_raw_clear() was created similar to sbi_ipi_raw_send(). Signed-off-by: Evgenii Shatokhin Reviewed-by: Anup Patel

lib: sbi: Refactor the calls to sbi_hart_switch_mode()

2023-03-10T08:30:36+00:00

Move them into sbi_hsm_hart_start_finish() and sbi_hsm_hart_resume_finish() to make them easier to manage. This will be used by subsequent patches. Suggested-by: Anup Patel Signed-off-by: Evgenii Shatokhin Reviewed-by: Anup Patel

lib: sbi_pmu: Add hartid parameter PMU device ops

2023-03-10T08:30:33+00:00

Platform specific firmware event handler may leverage the hartid to program per hart specific registers for a given counter. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: sbi_pmu: Introduce fw_counter_write_value API

2023-03-10T08:30:30+00:00

Add fw_counter_write_value API for platform specific firmware events which separates setting the counter's initial value from starting the counter. This is required so that the fw_event_data array can be reused to save the event data received. Signed-off-by: Mayuresh Chitale Reviewed-by: Anup Patel

lib: sbi_pmu: Update sbi_pmu dev ops

2023-03-10T08:30:26+00:00

Update fw_event_validate_code, fw_counter_match_code and fw_counter_start ops which used a 32 bit event code to use the 64 bit event data instead. Signed-off-by: Mayuresh Chitale Reviewed-by: Anup Patel

lib: sbi_pmu: Reserve space for implementation specific firmware events

2023-03-10T08:30:22+00:00

We reserve space for SBI implementation specific custom firmware events which can be used by M-mode firmwares and HS-mode hypervisors for their own use. This reserved space is intentionally large to ensure that SBI implementation has enough space to accommodate platform specific firmware events as well. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi

2023-03-10T08:30:07+00:00

To support 64 bit firmware counters on RV32 systems, we implement sbi_pmu_counter_fw_read_hi() which returns the upper 32 bits of the firmware counter value. On RV64 (or higher) systems, this function will always return zero. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: sbi_pmu: add callback for counter width

2023-03-10T08:16:52+00:00

This patch adds a callback to fetch the number of bits implemented for a custom firmware counter. If the callback fails or is not implemented then width defaults to 63. Signed-off-by: Mayuresh Chitale Reviewed-by: Atish Patra Reviewed-by: Anup Patel

lib: utils/i2c: Add minimal StarFive jh7110 I2C driver

2023-03-09T15:30:57+00:00

Starfive JH7110 I2C IP is synopsys designware. Minimum StarFIve I2C driver to read/send bytes over I2C bus. This allows querying information and perform operation of onboard PMIC, as well as power-off and reset. Signed-off-by: Minda Chen Reviewed-by: Anup Patel