starfive-tech/opensbi.git/include/sbi_utils, branch rtthread_AMP

lib: utils/i2c: Add minimal StarFive jh7110 I2C driver

2023-03-09T15:30:57+00:00

Starfive JH7110 I2C IP is synopsys designware. Minimum StarFIve I2C driver to read/send bytes over I2C bus. This allows querying information and perform operation of onboard PMIC, as well as power-off and reset. Signed-off-by: Minda Chen Reviewed-by: Anup Patel

include: fdt/fdt_helper: Change fdt_get_address() to return root.next_arg1

2023-02-27T04:34:03+00:00

In sbi_domain_finalize(), when locating the coldboot hart's domain, the coldboot hart's scratch->arg1 will be overwritten by the domain configuration. However scratch->arg1 holds the FDT address of the coldboot hart, and is still being accessed by fdt_get_address() in later boot process. scratch->arg1 could then contain completely garbage and lead to a crash. To fix this, we change fdt_get_address() to return root domain's next_arg1 as the FDT pointer. Resolves: https://github.com/riscv-software-src/opensbi/issues/281 Fixes: b1678af210dc ("lib: sbi: Add initial domain support") Reported-by: Marouene Boubakri Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils: Add fdt_add_cpu_idle_states() helper function

2023-01-24T12:00:21+00:00

Since the availability and latency properties of CPU idle states depend on the specific SBI HSM implementation, it is appropriate that the idle states are added to the devicetree at runtime by that implementation. This helper function adds a platform-provided array of idle states to the devicetree, following the SBI idle state binding. Reviewed-by: Anup Patel Signed-off-by: Samuel Holland

lib: utils: atcsmu: Add Andes System Management Unit support

2023-01-22T12:02:50+00:00

This patch adds atcsmu support for Andes AE350 platforms. The SMU provides system management capabilities, including clock, reset and power control based on power domain partitions. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

2022-12-17T03:33:30+00:00

Currently the context save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers

2022-12-17T03:30:29+00:00

Currently the priority save/restore helpers writes/reads the provided array using an index whose maximum value is determined by PLIC, which potentially may disagree with the caller to these helpers. Add a parameter to ask the caller to provide the size limit of the array to ensure no out-of-bound access happens. Signed-off-by: Bin Meng Reviewed-by: Anup Patel

lib: utils: serial: Add FDT driver for Renesas SCIF

2022-12-12T13:20:35+00:00

Add FDT driver for Renesas SCIF. dts example: soc: soc { .... scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, <414 IRQ_TYPE_LEVEL_HIGH>, <415 IRQ_TYPE_LEVEL_HIGH>, <413 IRQ_TYPE_LEVEL_HIGH>, <416 IRQ_TYPE_LEVEL_HIGH>, <416 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; clock-names = "fck"; power-domains = <&cpg>; resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; .... }; Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel

lib: utils: serial: Add Renesas SCIF driver

2022-12-12T13:20:26+00:00

Add Renesas SCIF driver. Based on a patch in the BSP by Takeki Hamada Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA Signed-off-by: Lad Prabhakar Reviewed-by: Anup Patel

lib: utils/ipi: Add Andes fdt ipi driver support

2022-10-23T05:01:01+00:00

Move Andes PLICSW ipi device to fdt ipi framework, this patch is based on Leo's modified IPI scheme on PLICSW. Current IPI scheme uses bit 0 of pending reigster on PLICSW to send IPI from hart 0 to hart 7, but bit 0 needs to be hardwired to 0 according to spec. After some investigation, self-IPI seems to be seldom or never used, so we re-order the IPI scheme to support 8 core platforms. dts example (Quad-core AX45MP): plicsw: interrupt-controller@e6400000 { compatible = "andestech,plicsw"; reg = <0x00000000 0xe6400000 0x00000000 0x00400000>; interrupts-extended = <&CPU0_intc 3 &CPU1_intc 3 &CPU2_intc 3 &CPU3_intc 3>; interrupt-controller; #address-cells = <2>; #interrupt-cells = <2>; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel

lib: utils/timer: Add Andes fdt timer support

2022-10-23T04:56:39+00:00

Since we can get the PLMT base address and timer frequency from device tree, move plmt timer device to fdt timer framework. dts example (Quad-core AX45MP): cpus { ... timebase-frequency = <0x3938700>; ... } soc { ... plmt0@e6000000 { compatible = "andestech,plmt0"; reg = <0x00 0xe6000000 0x00 0x100000>; interrupts-extended = <&cpu0_intc 0x07 &cpu1_intc 0x07 &cpu2_intc 0x07 &cpu3_intc 0x07>; }; ... } Signed-off-by: Yu Chien Peter Lin Reviewed-by: Anup Patel