starfive-tech/opensbi.git/include/sbi, branch starfive-dubhe

include: types: Use __builtin_offsetof when supported

2021-07-17T11:10:07+00:00

Clang provides a __builtin_offsetof which can be detected using __has_builtin(). Signed-off-by: Alex Richardson Reviewed-by: Anup Patel

firmware: use __SIZEOF_LONG__ for field offsets in fw_dynamic.h

2021-07-17T11:05:23+00:00

The fields are of type unsigned long and are not pointers. While this happens to be the same for RV32/RV64, it is not correct when compiling for a CHERI-RISC-V system where pointers are twice the size of long. Signed-off-by: Alex Richardson Reviewed-by: Bin Meng Reviewed-by: Anup Patel

firmware: Define a macro for version of struct fw_dynamic_info

2021-07-11T08:43:32+00:00

Avoid using a magic number, instead use a macro for the version of struct fw_dynamic_info. Signed-off-by: Bin Meng Reviewed-by: Xiang W Reviewed-by: Anup Patel

lib: sbi: Implement SBI PMU extension

2021-07-11T05:08:02+00:00

RISC-V SBI specfication 0.3 defines a PMU extension that allows supervisor mode to start/stop/configure pmu related events. This patch implements all of the functionality defined in the specification. Reviewed-by: Anup Patel Signed-off-by: Atish Patra

lib: sbi: Add PMU support

2021-07-11T04:53:18+00:00

RISC-V SBI v0.3 specification defined a PMU extension to configure/start/stop the hardware/firmware pmu events. Implement PMU support in OpenSBI library. The implementation is agnostic of event to counter mapping & mhpmevent value configuration. That means, it expects platform hooks will be used to set up the mapping and provide the mhpmevent value at runtime. Reviewed-by: Anup Patel Signed-off-by: Atish Patra

lib: sbi: Add PMU specific platform hooks

2021-07-11T04:51:38+00:00

A platform hook to initialize PMU allows platform vendors to provide their own mechanism to define pmu event-counter mappings in addition to the DT based approach. Another platform hook that allows platform vendors customize the final mhpmevent value configuration. Reviewed-by: Anup Patel Signed-off-by: Atish Patra

include: Add a list empty check function

2021-07-11T04:45:29+00:00

Implement a list helper function that checks for empty lists. Reviewed-by: Anup Patel Reviewed-by: Xiang W Signed-off-by: Atish Patra

lib: sbi: Detect number of bits implemented in mhpmcounter

2021-07-11T04:43:04+00:00

RISC-V privilege specification allows the implementation to have less than 64 bits. Add a function to detect the number of implemented bits in mhpmcounter dynamically at runtime. Reviewed-by: Xiang W Reviewed-by: Anup Patel Signed-off-by: Atish Patra

lib: sbi: Detect mcountinihibit support at runtime

2021-07-11T04:41:10+00:00

RISC-V ISA specification v1.11 defined mcountinhibit CSR that allows software to stop any counter from incrementing. The SBI PMU extension depends on this CSR support in hardware. Define mcountinhibit as a hart specific feature and detect it at runtime. Reviewed-by: Anup Patel Signed-off-by: Atish Patra

lib: sbi: Fix GET_F64_REG inline assembly

2021-06-12T04:23:33+00:00

Current, GET_F64_REG() macro does not generate correct inline assembly for the RV32 systems. This patch provides separate definitions of GET_F64_REG() macro for RV32 and RV64 systems. Signed-off-by: Charles Papon Signed-off-by: Anup Patel