1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
|
/**
****************************************************************************************
*
* @file ecrnx_ipc_app.h
*
* @brief IPC module register definitions
*
* Copyright (C) ESWIN 2015-2020
*
****************************************************************************************
*/
#ifndef _REG_IPC_APP_H_
#define _REG_IPC_APP_H_
#ifndef __KERNEL__
#include <stdint.h>
#include "arch.h"
#else
#include "ipc_compat.h"
#endif
#include "reg_access.h"
#define REG_IPC_APP_DECODING_MASK 0x0000007F
/**
* @brief APP2EMB_TRIGGER register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 APP2EMB_TRIGGER 0x0
* </pre>
*/
#define IPC_APP2EMB_TRIGGER_ADDR 0x12000000
#define IPC_APP2EMB_TRIGGER_OFFSET 0x00000000
#define IPC_APP2EMB_TRIGGER_INDEX 0x00000000
#define IPC_APP2EMB_TRIGGER_RESET 0x00000000
__INLINE u32 ipc_app2emb_trigger_get(void *env)
{
return REG_IPC_APP_RD(env, IPC_APP2EMB_TRIGGER_INDEX);
}
__INLINE void ipc_app2emb_trigger_set(void *env, u32 value)
{
REG_IPC_APP_WR(env, IPC_APP2EMB_TRIGGER_INDEX, value);
}
// field definitions
#define IPC_APP2EMB_TRIGGER_MASK ((u32)0xFFFFFFFF)
#define IPC_APP2EMB_TRIGGER_LSB 0
#define IPC_APP2EMB_TRIGGER_WIDTH ((u32)0x00000020)
#define IPC_APP2EMB_TRIGGER_RST 0x0
__INLINE u32 ipc_app2emb_trigger_getf(void *env)
{
u32 localVal = REG_IPC_APP_RD(env, IPC_APP2EMB_TRIGGER_INDEX);
ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
__INLINE void ipc_app2emb_trigger_setf(void *env, u32 app2embtrigger)
{
ASSERT_ERR((((u32)app2embtrigger << 0) & ~((u32)0xFFFFFFFF)) == 0);
REG_IPC_APP_WR(env, IPC_APP2EMB_TRIGGER_INDEX, (u32)app2embtrigger << 0);
}
/**
* @brief EMB2APP_RAWSTATUS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 EMB2APP_RAWSTATUS 0x0
* </pre>
*/
#define IPC_EMB2APP_RAWSTATUS_ADDR 0x12000004
#define IPC_EMB2APP_RAWSTATUS_OFFSET 0x00000004
#define IPC_EMB2APP_RAWSTATUS_INDEX 0x00000001
#define IPC_EMB2APP_RAWSTATUS_RESET 0x00000000
__INLINE u32 ipc_emb2app_rawstatus_get(void *env)
{
return REG_IPC_APP_RD(env, IPC_EMB2APP_RAWSTATUS_INDEX);
}
__INLINE void ipc_emb2app_rawstatus_set(void *env, u32 value)
{
REG_IPC_APP_WR(env, IPC_EMB2APP_RAWSTATUS_INDEX, value);
}
// field definitions
#define IPC_EMB2APP_RAWSTATUS_MASK ((u32)0xFFFFFFFF)
#define IPC_EMB2APP_RAWSTATUS_LSB 0
#define IPC_EMB2APP_RAWSTATUS_WIDTH ((u32)0x00000020)
#define IPC_EMB2APP_RAWSTATUS_RST 0x0
__INLINE u32 ipc_emb2app_rawstatus_getf(void *env)
{
u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_RAWSTATUS_INDEX);
ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief EMB2APP_ACK register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 EMB2APP_ACK 0x0
* </pre>
*/
#define IPC_EMB2APP_ACK_ADDR 0x12000008
#define IPC_EMB2APP_ACK_OFFSET 0x00000008
#define IPC_EMB2APP_ACK_INDEX 0x00000002
#define IPC_EMB2APP_ACK_RESET 0x00000000
__INLINE u32 ipc_emb2app_ack_get(void *env)
{
return REG_IPC_APP_RD(env, IPC_EMB2APP_ACK_INDEX);
}
__INLINE void ipc_emb2app_ack_clear(void *env, u32 value)
{
REG_IPC_APP_WR(env, IPC_EMB2APP_ACK_INDEX, value);
}
// field definitions
#define IPC_EMB2APP_ACK_MASK ((u32)0xFFFFFFFF)
#define IPC_EMB2APP_ACK_LSB 0
#define IPC_EMB2APP_ACK_WIDTH ((u32)0x00000020)
#define IPC_EMB2APP_ACK_RST 0x0
__INLINE u32 ipc_emb2app_ack_getf(void *env)
{
u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_ACK_INDEX);
ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
__INLINE void ipc_emb2app_ack_clearf(void *env, u32 emb2appack)
{
ASSERT_ERR((((u32)emb2appack << 0) & ~((u32)0xFFFFFFFF)) == 0);
REG_IPC_APP_WR(env, IPC_EMB2APP_ACK_INDEX, (u32)emb2appack << 0);
}
/**
* @brief EMB2APP_UNMASK_SET register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 EMB2APP_UNMASK 0x0
* </pre>
*/
#define IPC_EMB2APP_UNMASK_SET_ADDR 0x1200000C
#define IPC_EMB2APP_UNMASK_SET_OFFSET 0x0000000C
#define IPC_EMB2APP_UNMASK_SET_INDEX 0x00000003
#define IPC_EMB2APP_UNMASK_SET_RESET 0x00000000
__INLINE u32 ipc_emb2app_unmask_get(void *env)
{
return REG_IPC_APP_RD(env, IPC_EMB2APP_UNMASK_SET_INDEX);
}
__INLINE void ipc_emb2app_unmask_set(void *env, u32 value)
{
REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_SET_INDEX, value);
}
// field definitions
#define IPC_EMB2APP_UNMASK_MASK ((u32)0xFFFFFFFF)
#define IPC_EMB2APP_UNMASK_LSB 0
#define IPC_EMB2APP_UNMASK_WIDTH ((u32)0x00000020)
#define IPC_EMB2APP_UNMASK_RST 0x0
__INLINE u32 ipc_emb2app_unmask_getf(void *env)
{
u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_UNMASK_SET_INDEX);
ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
__INLINE void ipc_emb2app_unmask_setf(void *env, u32 emb2appunmask)
{
ASSERT_ERR((((u32)emb2appunmask << 0) & ~((u32)0xFFFFFFFF)) == 0);
REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_SET_INDEX, (u32)emb2appunmask << 0);
}
/**
* @brief EMB2APP_UNMASK_CLEAR register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 EMB2APP_UNMASK 0x0
* </pre>
*/
#define IPC_EMB2APP_UNMASK_CLEAR_ADDR 0x12000010
#define IPC_EMB2APP_UNMASK_CLEAR_OFFSET 0x00000010
#define IPC_EMB2APP_UNMASK_CLEAR_INDEX 0x00000004
#define IPC_EMB2APP_UNMASK_CLEAR_RESET 0x00000000
__INLINE void ipc_emb2app_unmask_clear(void *env, u32 value)
{
REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_CLEAR_INDEX, value);
}
// fields defined in symmetrical set/clear register
__INLINE void ipc_emb2app_unmask_clearf(void *env, u32 emb2appunmask)
{
ASSERT_ERR((((u32)emb2appunmask << 0) & ~((u32)0xFFFFFFFF)) == 0);
REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_CLEAR_INDEX, (u32)emb2appunmask << 0);
}
/**
* @brief EMB2APP_STATUS register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ -----------
* 31:00 EMB2APP_STATUS 0x0
* </pre>
*/
#ifdef CONFIG_ECRNX_OLD_IPC
#define IPC_EMB2APP_STATUS_ADDR 0x12000014
#define IPC_EMB2APP_STATUS_OFFSET 0x00000014
#define IPC_EMB2APP_STATUS_INDEX 0x00000005
#else
#define IPC_EMB2APP_STATUS_ADDR 0x1200001C
#define IPC_EMB2APP_STATUS_OFFSET 0x0000001C
#define IPC_EMB2APP_STATUS_INDEX 0x00000007
#endif
#define IPC_EMB2APP_STATUS_RESET 0x00000000
__INLINE u32 ipc_emb2app_status_get(void *env)
{
return REG_IPC_APP_RD(env, IPC_EMB2APP_STATUS_INDEX);
}
__INLINE void ipc_emb2app_status_set(void *env, u32 value)
{
REG_IPC_APP_WR(env, IPC_EMB2APP_STATUS_INDEX, value);
}
// field definitions
#define IPC_EMB2APP_STATUS_MASK ((u32)0xFFFFFFFF)
#define IPC_EMB2APP_STATUS_LSB 0
#define IPC_EMB2APP_STATUS_WIDTH ((u32)0x00000020)
#define IPC_EMB2APP_STATUS_RST 0x0
__INLINE u32 ipc_emb2app_status_getf(void *env)
{
u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_STATUS_INDEX);
ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
/**
* @brief APP_SIGNATURE register definition
* <pre>
* Bits Field Name Reset Value
* ----- ------------------ ----------
* 31:00 APP_SIGNATURE 0x0
* </pre>
*/
#define IPC_APP_SIGNATURE_ADDR 0x12000040
#define IPC_APP_SIGNATURE_OFFSET 0x00000040
#define IPC_APP_SIGNATURE_INDEX 0x00000010
#define IPC_APP_SIGNATURE_RESET 0x00000000
__INLINE u32 ipc_app_signature_get(void *env)
{
return REG_IPC_APP_RD(env, IPC_APP_SIGNATURE_INDEX);
}
__INLINE void ipc_app_signature_set(void *env, u32 value)
{
REG_IPC_APP_WR(env, IPC_APP_SIGNATURE_INDEX, value);
}
// field definitions
#define IPC_APP_SIGNATURE_MASK ((u32)0xFFFFFFFF)
#define IPC_APP_SIGNATURE_LSB 0
#define IPC_APP_SIGNATURE_WIDTH ((u32)0x00000020)
#define IPC_APP_SIGNATURE_RST 0x0
__INLINE u32 ipc_app_signature_getf(void *env)
{
u32 localVal = REG_IPC_APP_RD(env, IPC_APP_SIGNATURE_INDEX);
ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
return (localVal >> 0);
}
#endif // _REG_IPC_APP_H_
|
