1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
|
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for the Texas Instruments DP83TC811 PHY
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
*
*/
#include <linux/ethtool.h>
#include <linux/etherdevice.h>
#include <linux/kernel.h>
#include <linux/mii.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
#include <linux/netdevice.h>
#define DP83TC811_PHY_ID 0x2000a253
#define DP83811_DEVADDR 0x1f
#define MII_DP83811_SGMII_CTRL 0x09
#define MII_DP83811_INT_STAT1 0x12
#define MII_DP83811_INT_STAT2 0x13
#define MII_DP83811_INT_STAT3 0x18
#define MII_DP83811_RESET_CTRL 0x1f
#define DP83811_HW_RESET BIT(15)
#define DP83811_SW_RESET BIT(14)
/* INT_STAT1 bits */
#define DP83811_RX_ERR_HF_INT_EN BIT(0)
#define DP83811_MS_TRAINING_INT_EN BIT(1)
#define DP83811_ANEG_COMPLETE_INT_EN BIT(2)
#define DP83811_ESD_EVENT_INT_EN BIT(3)
#define DP83811_WOL_INT_EN BIT(4)
#define DP83811_LINK_STAT_INT_EN BIT(5)
#define DP83811_ENERGY_DET_INT_EN BIT(6)
#define DP83811_LINK_QUAL_INT_EN BIT(7)
/* INT_STAT2 bits */
#define DP83811_JABBER_DET_INT_EN BIT(0)
#define DP83811_POLARITY_INT_EN BIT(1)
#define DP83811_SLEEP_MODE_INT_EN BIT(2)
#define DP83811_OVERTEMP_INT_EN BIT(3)
#define DP83811_OVERVOLTAGE_INT_EN BIT(6)
#define DP83811_UNDERVOLTAGE_INT_EN BIT(7)
/* INT_STAT3 bits */
#define DP83811_LPS_INT_EN BIT(0)
#define DP83811_NO_FRAME_INT_EN BIT(3)
#define DP83811_POR_DONE_INT_EN BIT(4)
#define MII_DP83811_RXSOP1 0x04a5
#define MII_DP83811_RXSOP2 0x04a6
#define MII_DP83811_RXSOP3 0x04a7
/* WoL Registers */
#define MII_DP83811_WOL_CFG 0x04a0
#define MII_DP83811_WOL_STAT 0x04a1
#define MII_DP83811_WOL_DA1 0x04a2
#define MII_DP83811_WOL_DA2 0x04a3
#define MII_DP83811_WOL_DA3 0x04a4
/* WoL bits */
#define DP83811_WOL_MAGIC_EN BIT(0)
#define DP83811_WOL_SECURE_ON BIT(5)
#define DP83811_WOL_EN BIT(7)
#define DP83811_WOL_INDICATION_SEL BIT(8)
#define DP83811_WOL_CLR_INDICATION BIT(11)
/* SGMII CTRL bits */
#define DP83811_TDR_AUTO BIT(8)
#define DP83811_SGMII_EN BIT(12)
#define DP83811_SGMII_AUTO_NEG_EN BIT(13)
#define DP83811_SGMII_TX_ERR_DIS BIT(14)
#define DP83811_SGMII_SOFT_RESET BIT(15)
static int dp83811_ack_interrupt(struct phy_device *phydev)
{
int err;
err = phy_read(phydev, MII_DP83811_INT_STAT1);
if (err < 0)
return err;
err = phy_read(phydev, MII_DP83811_INT_STAT2);
if (err < 0)
return err;
err = phy_read(phydev, MII_DP83811_INT_STAT3);
if (err < 0)
return err;
return 0;
}
static int dp83811_set_wol(struct phy_device *phydev,
struct ethtool_wolinfo *wol)
{
struct net_device *ndev = phydev->attached_dev;
const u8 *mac;
u16 value;
if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
mac = (const u8 *)ndev->dev_addr;
if (!is_valid_ether_addr(mac))
return -EINVAL;
/* MAC addresses start with byte 5, but stored in mac[0].
* 811 PHYs store bytes 4|5, 2|3, 0|1
*/
phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1,
(mac[1] << 8) | mac[0]);
phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2,
(mac[3] << 8) | mac[2]);
phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3,
(mac[5] << 8) | mac[4]);
value = phy_read_mmd(phydev, DP83811_DEVADDR,
MII_DP83811_WOL_CFG);
if (wol->wolopts & WAKE_MAGIC)
value |= DP83811_WOL_MAGIC_EN;
else
value &= ~DP83811_WOL_MAGIC_EN;
if (wol->wolopts & WAKE_MAGICSECURE) {
phy_write_mmd(phydev, DP83811_DEVADDR,
MII_DP83811_RXSOP1,
(wol->sopass[1] << 8) | wol->sopass[0]);
phy_write_mmd(phydev, DP83811_DEVADDR,
MII_DP83811_RXSOP2,
(wol->sopass[3] << 8) | wol->sopass[2]);
phy_write_mmd(phydev, DP83811_DEVADDR,
MII_DP83811_RXSOP3,
(wol->sopass[5] << 8) | wol->sopass[4]);
value |= DP83811_WOL_SECURE_ON;
} else {
value &= ~DP83811_WOL_SECURE_ON;
}
value |= (DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL |
DP83811_WOL_CLR_INDICATION);
phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
value);
} else {
phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
DP83811_WOL_EN);
}
return 0;
}
static void dp83811_get_wol(struct phy_device *phydev,
struct ethtool_wolinfo *wol)
{
u16 sopass_val;
int value;
wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
wol->wolopts = 0;
value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
if (value & DP83811_WOL_MAGIC_EN)
wol->wolopts |= WAKE_MAGIC;
if (value & DP83811_WOL_SECURE_ON) {
sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
MII_DP83811_RXSOP1);
wol->sopass[0] = (sopass_val & 0xff);
wol->sopass[1] = (sopass_val >> 8);
sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
MII_DP83811_RXSOP2);
wol->sopass[2] = (sopass_val & 0xff);
wol->sopass[3] = (sopass_val >> 8);
sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
MII_DP83811_RXSOP3);
wol->sopass[4] = (sopass_val & 0xff);
wol->sopass[5] = (sopass_val >> 8);
wol->wolopts |= WAKE_MAGICSECURE;
}
/* WoL is not enabled so set wolopts to 0 */
if (!(value & DP83811_WOL_EN))
wol->wolopts = 0;
}
static int dp83811_config_intr(struct phy_device *phydev)
{
int misr_status, err;
if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
misr_status = phy_read(phydev, MII_DP83811_INT_STAT1);
if (misr_status < 0)
return misr_status;
misr_status |= (DP83811_RX_ERR_HF_INT_EN |
DP83811_MS_TRAINING_INT_EN |
DP83811_ANEG_COMPLETE_INT_EN |
DP83811_ESD_EVENT_INT_EN |
DP83811_WOL_INT_EN |
DP83811_LINK_STAT_INT_EN |
DP83811_ENERGY_DET_INT_EN |
DP83811_LINK_QUAL_INT_EN);
err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
if (err < 0)
return err;
misr_status = phy_read(phydev, MII_DP83811_INT_STAT2);
if (misr_status < 0)
return misr_status;
misr_status |= (DP83811_JABBER_DET_INT_EN |
DP83811_POLARITY_INT_EN |
DP83811_SLEEP_MODE_INT_EN |
DP83811_OVERTEMP_INT_EN |
DP83811_OVERVOLTAGE_INT_EN |
DP83811_UNDERVOLTAGE_INT_EN);
err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
if (err < 0)
return err;
misr_status = phy_read(phydev, MII_DP83811_INT_STAT3);
if (misr_status < 0)
return misr_status;
misr_status |= (DP83811_LPS_INT_EN |
DP83811_NO_FRAME_INT_EN |
DP83811_POR_DONE_INT_EN);
err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
} else {
err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
if (err < 0)
return err;
err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
if (err < 0)
return err;
err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
}
return err;
}
static int dp83811_config_aneg(struct phy_device *phydev)
{
int value, err;
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
if (phydev->autoneg == AUTONEG_ENABLE) {
err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
(DP83811_SGMII_AUTO_NEG_EN | value));
if (err < 0)
return err;
} else {
err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
(~DP83811_SGMII_AUTO_NEG_EN & value));
if (err < 0)
return err;
}
}
return genphy_config_aneg(phydev);
}
static int dp83811_config_init(struct phy_device *phydev)
{
int value, err;
err = genphy_config_init(phydev);
if (err < 0)
return err;
value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
(DP83811_SGMII_EN | value));
} else {
err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
(~DP83811_SGMII_EN & value));
}
if (err < 0)
return err;
value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN;
return phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
value);
}
static int dp83811_phy_reset(struct phy_device *phydev)
{
int err;
err = phy_write(phydev, MII_DP83811_RESET_CTRL, DP83811_HW_RESET);
if (err < 0)
return err;
return 0;
}
static int dp83811_suspend(struct phy_device *phydev)
{
int value;
value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
if (!(value & DP83811_WOL_EN))
genphy_suspend(phydev);
return 0;
}
static int dp83811_resume(struct phy_device *phydev)
{
genphy_resume(phydev);
phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
DP83811_WOL_CLR_INDICATION);
return 0;
}
static struct phy_driver dp83811_driver[] = {
{
.phy_id = DP83TC811_PHY_ID,
.phy_id_mask = 0xfffffff0,
.name = "TI DP83TC811",
.features = PHY_BASIC_FEATURES,
.config_init = dp83811_config_init,
.config_aneg = dp83811_config_aneg,
.soft_reset = dp83811_phy_reset,
.get_wol = dp83811_get_wol,
.set_wol = dp83811_set_wol,
.ack_interrupt = dp83811_ack_interrupt,
.config_intr = dp83811_config_intr,
.suspend = dp83811_suspend,
.resume = dp83811_resume,
},
};
module_phy_driver(dp83811_driver);
static struct mdio_device_id __maybe_unused dp83811_tbl[] = {
{ DP83TC811_PHY_ID, 0xfffffff0 },
{ },
};
MODULE_DEVICE_TABLE(mdio, dp83811_tbl);
MODULE_DESCRIPTION("Texas Instruments DP83TC811 PHY driver");
MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
MODULE_LICENSE("GPL");
|
