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|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
* Based on TQM8548 device tree
*
* XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the
* xMon boot loader memory map which differs from U-Boot's.
*/
/dts-v1/;
/ {
model = "xes,xpedite5200";
compatible = "xes,xpedite5200", "xes,MPC8548";
#address-cells = <1>;
#size-cells = <1>;
form-factor = "PMC/XMC";
boot-bank = <0x0>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
ethernet3 = &enet3;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8548@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
next-level-cache = <&L2>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>; // Filled in by boot loader
};
soc@ef000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0x0 0xef000000 0x100000>;
bus-frequency = <0>;
compatible = "fsl,mpc8548-immr", "simple-bus";
ecm-law@0 {
compatible = "fsl,ecm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <12>;
};
ecm@1000 {
compatible = "fsl,mpc8548-ecm", "fsl,ecm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
memory-controller@2000 {
compatible = "fsl,mpc8548-memory-controller";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
};
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes
cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
interrupts = <16 2>;
};
/* On-card I2C */
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
/*
* Board GPIO:
* 0: BRD_CFG0 (1: P14 IO present)
* 1: BRD_CFG1 (1: FP ethernet present)
* 2: BRD_CFG2 (1: XMC IO present)
* 3: XMC root complex indicator
* 4: Flash boot device indicator
* 5: Flash write protect enable
* 6: PMC monarch indicator
* 7: PMC EREADY
*/
gpio1: gpio@18 {
compatible = "nxp,pca9556";
reg = <0x18>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
/* P14 GPIO */
gpio2: gpio@19 {
compatible = "nxp,pca9556";
reg = <0x19>;
#gpio-cells = <2>;
gpio-controller;
polarity = <0x00>;
};
eeprom@50 {
compatible = "atmel,at24c16";
reg = <0x50>;
};
rtc@68 {
compatible = "st,m41t00",
"dallas,ds1338";
reg = <0x68>;
};
dtt@34 {
compatible = "maxim,max1237";
reg = <0x34>;
};
};
/* Off-card I2C */
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8548-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
/* eTSEC1: Front panel port 0 */
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 30 2 34 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x1>;
};
phy1: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x2>;
};
phy2: ethernet-phy@3 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x3>;
};
phy3: ethernet-phy@4 {
interrupt-parent = <&mpic>;
interrupts = <8 1>;
reg = <0x4>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC2: Front panel port 1 */
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 36 2 40 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC3: Rear panel port 2 */
enet2: ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 32 2 33 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
/* eTSEC4: Rear panel port 3 */
enet3: ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 38 2 39 2>;
interrupt-parent = <&mpic>;
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
current-speed = <9600>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
current-speed = <9600>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { // global utilities reg
compatible = "fsl,mpc8548-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
};
localbus@ef005000 {
compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
"simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xef005000 0x100>; // BRx, ORx, etc.
interrupt-parent = <&mpic>;
interrupts = <19 2>;
ranges = <
0 0x0 0xf8000000 0x08000000 // NOR boot flash
1 0x0 0xf0000000 0x08000000 // NOR expansion flash
2 0x0 0xe8000000 0x00010000 // NAND CE1
3 0x0 0xe8010000 0x00010000 // NAND CE2
>;
nor-boot@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0 0x0 0x4000000>;
bank-width = <2>;
partition@0 {
label = "Primary OS";
reg = <0x00000000 0x180000>;
};
partition@180000 {
label = "Secondary OS";
reg = <0x00180000 0x180000>;
};
partition@300000 {
label = "User";
reg = <0x00300000 0x3c80000>;
};
partition@3f80000 {
label = "Boot firmware";
reg = <0x03f80000 0x80000>;
};
};
nor-alternate@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <1 0x0 0x4000000>;
bank-width = <2>;
partition@0 {
label = "Filesystem";
reg = <0x00000000 0x3f80000>;
};
partition@3f80000 {
label = "Alternate boot firmware";
reg = <0x03f80000 0x80000>;
};
};
nand@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xes,address-ctl-nand";
reg = <2 0x0 0x10000>;
cle-line = <0x8>; /* CLE tied to A3 */
ale-line = <0x10>; /* ALE tied to A4 */
partition@0 {
label = "NAND Filesystem";
reg = <0 0x40000000>;
};
};
};
/* PMC interface */
pci0: pci@ef008000 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
reg = <0xef008000 0x1000>;
clock-frequency = <33333333>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL */
0xe000 0 0 1 &mpic 2 1
0xe000 0 0 2 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
bus-range = <0 0>;
ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
};
/* XMC PCIe */
pci1: pcie@ef00a000 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 */
0x00000 0 0 1 &mpic 0 1
0x00000 0 0 2 &mpic 1 1
0x00000 0 0 3 &mpic 2 1
0x00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
bus-range = <0 0xff>;
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xef00a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0 0xc0000000 0x02000000 0
0xc0000000 0 0x20000000
0x01000000 0 0x00000000 0x01000000 0
0x00000000 0 0x08000000>;
};
};
/* Needed for dtbImage boot wrapper compatibility */
chosen {
stdout-path = &serial0;
};
};
|
