blob: 905ec1d8692873a19337edbc6dfe0196cfe06d4f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Joshua Henderson <joshua.henderson@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/init.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <asm/time.h>
#include "pic32mzda.h"
static const struct of_device_id pic32_infra_match[] = {
{ .compatible = "microchip,pic32mzda-infra", },
{ },
};
#define DEFAULT_CORE_TIMER_INTERRUPT 0
static unsigned int pic32_xlate_core_timer_irq(void)
{
static struct device_node *node;
unsigned int irq;
node = of_find_matching_node(NULL, pic32_infra_match);
if (WARN_ON(!node))
goto default_map;
irq = irq_of_parse_and_map(node, 0);
if (!irq)
goto default_map;
return irq;
default_map:
return irq_create_mapping(NULL, DEFAULT_CORE_TIMER_INTERRUPT);
}
unsigned int get_c0_compare_int(void)
{
return pic32_xlate_core_timer_irq();
}
void __init plat_time_init(void)
{
unsigned long rate = pic32_get_pbclk(7);
of_clk_init(NULL);
pr_info("CPU Clock: %ldMHz\n", rate / 1000000);
mips_hpt_frequency = rate / 2;
timer_probe();
}
|
