1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
|
/*
* Copyright (C) 2004-2006 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_AVR32_BITOPS_H
#define __ASM_AVR32_BITOPS_H
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#include <asm/byteorder.h>
#include <asm/system.h>
/*
* clear_bit() doesn't provide any barrier for the compiler
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
/*
* set_bit - Atomically set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* This function is atomic and may not be reordered. See __set_bit()
* if you do not require the atomic guarantees.
*
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static inline void set_bit(int nr, volatile void * addr)
{
unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
unsigned long tmp;
if (__builtin_constant_p(nr)) {
asm volatile(
"1: ssrf 5\n"
" ld.w %0, %2\n"
" sbr %0, %3\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p)
: "m"(*p), "i"(nr)
: "cc");
} else {
unsigned long mask = 1UL << (nr % BITS_PER_LONG);
asm volatile(
"1: ssrf 5\n"
" ld.w %0, %2\n"
" or %0, %3\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p)
: "m"(*p), "r"(mask)
: "cc");
}
}
/*
* clear_bit - Clears a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* clear_bit() is atomic and may not be reordered. However, it does
* not contain a memory barrier, so if it is used for locking purposes,
* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
* in order to ensure changes are visible on other processors.
*/
static inline void clear_bit(int nr, volatile void * addr)
{
unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
unsigned long tmp;
if (__builtin_constant_p(nr)) {
asm volatile(
"1: ssrf 5\n"
" ld.w %0, %2\n"
" cbr %0, %3\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p)
: "m"(*p), "i"(nr)
: "cc");
} else {
unsigned long mask = 1UL << (nr % BITS_PER_LONG);
asm volatile(
"1: ssrf 5\n"
" ld.w %0, %2\n"
" andn %0, %3\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p)
: "m"(*p), "r"(mask)
: "cc");
}
}
/*
* change_bit - Toggle a bit in memory
* @nr: Bit to change
* @addr: Address to start counting from
*
* change_bit() is atomic and may not be reordered.
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static inline void change_bit(int nr, volatile void * addr)
{
unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
unsigned long mask = 1UL << (nr % BITS_PER_LONG);
unsigned long tmp;
asm volatile(
"1: ssrf 5\n"
" ld.w %0, %2\n"
" eor %0, %3\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p)
: "m"(*p), "r"(mask)
: "cc");
}
/*
* test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_set_bit(int nr, volatile void * addr)
{
unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
unsigned long mask = 1UL << (nr % BITS_PER_LONG);
unsigned long tmp, old;
if (__builtin_constant_p(nr)) {
asm volatile(
"1: ssrf 5\n"
" ld.w %0, %3\n"
" mov %2, %0\n"
" sbr %0, %4\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p), "=&r"(old)
: "m"(*p), "i"(nr)
: "memory", "cc");
} else {
asm volatile(
"1: ssrf 5\n"
" ld.w %2, %3\n"
" or %0, %2, %4\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p), "=&r"(old)
: "m"(*p), "r"(mask)
: "memory", "cc");
}
return (old & mask) != 0;
}
/*
* test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_clear_bit(int nr, volatile void * addr)
{
unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
unsigned long mask = 1UL << (nr % BITS_PER_LONG);
unsigned long tmp, old;
if (__builtin_constant_p(nr)) {
asm volatile(
"1: ssrf 5\n"
" ld.w %0, %3\n"
" mov %2, %0\n"
" cbr %0, %4\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p), "=&r"(old)
: "m"(*p), "i"(nr)
: "memory", "cc");
} else {
asm volatile(
"1: ssrf 5\n"
" ld.w %0, %3\n"
" mov %2, %0\n"
" andn %0, %4\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p), "=&r"(old)
: "m"(*p), "r"(mask)
: "memory", "cc");
}
return (old & mask) != 0;
}
/*
* test_and_change_bit - Change a bit and return its old value
* @nr: Bit to change
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_change_bit(int nr, volatile void * addr)
{
unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
unsigned long mask = 1UL << (nr % BITS_PER_LONG);
unsigned long tmp, old;
asm volatile(
"1: ssrf 5\n"
" ld.w %2, %3\n"
" eor %0, %2, %4\n"
" stcond %1, %0\n"
" brne 1b"
: "=&r"(tmp), "=o"(*p), "=&r"(old)
: "m"(*p), "r"(mask)
: "memory", "cc");
return (old & mask) != 0;
}
#include <asm-generic/bitops/non-atomic.h>
/* Find First bit Set */
static inline unsigned long __ffs(unsigned long word)
{
unsigned long result;
asm("brev %1\n\t"
"clz %0,%1"
: "=r"(result), "=&r"(word)
: "1"(word));
return result;
}
/* Find First Zero */
static inline unsigned long ffz(unsigned long word)
{
return __ffs(~word);
}
/* Find Last bit Set */
static inline int fls(unsigned long word)
{
unsigned long result;
asm("clz %0,%1" : "=r"(result) : "r"(word));
return 32 - result;
}
static inline int __fls(unsigned long word)
{
return fls(word) - 1;
}
unsigned long find_first_zero_bit(const unsigned long *addr,
unsigned long size);
unsigned long find_next_zero_bit(const unsigned long *addr,
unsigned long size,
unsigned long offset);
unsigned long find_first_bit(const unsigned long *addr,
unsigned long size);
unsigned long find_next_bit(const unsigned long *addr,
unsigned long size,
unsigned long offset);
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*
* The difference is that bit numbering starts at 1, and if no bit is set,
* the function returns 0.
*/
static inline int ffs(unsigned long word)
{
if(word == 0)
return 0;
return __ffs(word) + 1;
}
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#include <asm-generic/bitops/le.h>
#include <asm-generic/bitops/ext2-atomic.h>
#include <asm-generic/bitops/minix-le.h>
#endif /* __ASM_AVR32_BITOPS_H */
|
