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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2018-2023
*
* Authors:
* Chao Zeng <chao.zeng@siemens.com>
* Jan Kiszka <jan.kiszka@siemens.com>
*
* AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product
* Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
*
* Product homepage:
* https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
*/
#include "k3-am6548-iot2050-advanced-common.dtsi"
#include "k3-am65-iot2050-common-pg2.dtsi"
/ {
compatible = "siemens,iot2050-advanced-m2", "ti,am654";
model = "SIMATIC IOT2050 Advanced M2";
};
&mcu_r5fss0 {
/* lock-step mode not supported on this board */
ti,cluster-mode = <0>;
};
&main_pmx0 {
main_m2_enable_pins_default: main-m2-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
};
main_bkey_pcie_reset: main-bkey-pcie-reset {
pinctrl-single,pins = <
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
>;
};
main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */
AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */
>;
};
main_m2_pcie_mux_control: main-m2-pcie-mux-control {
pinctrl-single,pins = <
AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */
AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */
AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */
>;
};
};
&main_pmx1 {
main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */
AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */
>;
};
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 =
<&main_m2_pcie_mux_control>,
<&arduino_io_d4_to_d9_pins_default>;
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 =
<&main_m2_enable_pins_default>,
<&main_pmx0_m2_config_pins_default>,
<&main_pmx1_m2_config_pins_default>,
<&cp2102n_reset_pin_default>;
};
/*
* Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only.
* Firmware switches to other modes via device tree overlays.
*/
&serdes0 {
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
};
&pcie0_rc {
pinctrl-names = "default";
pinctrl-0 = <&main_bkey_pcie_reset>;
num-lanes = <2>;
phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy0","pcie-phy1";
reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie1_rc {
status = "disabled";
};
&dwc3_0 {
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
/delete-property/ phys;
/delete-property/ phy-names;
};
&usb0 {
maximum-speed = "high-speed";
/delete-property/ snps,dis-u1-entry-quirk;
/delete-property/ snps,dis-u2-entry-quirk;
};
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