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|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
*/
/dts-v1/;
#include "dt-bindings/usb/pd.h"
#include "imx8mq-sr-som.dtsi"
/ {
model = "SolidRun i.MX8MQ HummingBoard Pulse";
compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
};
reg_v_5v0: regulator-v-5v0 {
compatible = "regulator-fixed";
regulator-name = "v_5v0";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-always-on;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
typec_ptn5100: usb-typec@50 {
compatible = "nxp,ptn5110";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio1>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000,
PDO_FIXED_USB_COMM |
PDO_FIXED_SUSPEND |
PDO_FIXED_EXTPOWER)>;
sink-pdos = <PDO_FIXED(5000, 2000,
PDO_FIXED_USB_COMM |
PDO_FIXED_SUSPEND |
PDO_FIXED_EXTPOWER)
PDO_FIXED(9000, 2000,
PDO_FIXED_USB_COMM |
PDO_FIXED_SUSPEND |
PDO_FIXED_EXTPOWER)>;
op-sink-microwatt = <9000000>;
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clock-frequency = <100000>;
status = "okay";
rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;
abracon,tc-diode = "schottky";
abracon,tc-resistor = <3>;
};
};
&uart2 { /* J35 header */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart3 { /* Mikrobus */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
assigned-clock-rates = <200000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_usdhc2_vmmc>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
/* MikroBus Analog */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x41
/* MikroBus Reset */
MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x41
/*
* The following 2 pins need to be commented out and
* reconfigured to enable RTS/CTS on UART3
*/
/* MikroBus PWM */
MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x41
/* MikroBus INT */
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x17059
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
/*
* These pins are by default GPIO on the Mikro Bus
* Header. To use RTS/CTS on UART3 comment them out
* of the hoggrp and enable them here
*/
/* MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 */
/* MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 */
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>;
};
pinctrl_usdhc2_vmmc: usdhc2vmmcgpio {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
>;
};
};
|
