1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
|
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2021-2022 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "imx8mm-verdin.dtsi"
/ {
model = "MENLO MX8MM EMBEDDED DEVICE";
compatible = "menlo,mx8menlo",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
/delete-node/ gpio-keys;
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
led-1 {
label = "TestLed601";
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
led-2 {
label = "TestLed602";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
beeper {
compatible = "gpio-beeper";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_beeper>;
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
};
/* Fixed clock dedicated to SPI CAN on carrier board */
clk_xtal20: clk-xtal20 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
};
};
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
/* CAN controller on the baseboard */
canfd: can@0 {
compatible = "microchip,mcp2518fd";
clocks = <&clk_xtal20>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
reg = <0>;
spi-max-frequency = <2000000>;
};
};
&ecspi2 {
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
status = "okay";
spidev@0 {
compatible = "menlo,m53cpld";
reg = <0>;
spi-max-frequency = <25000000>;
};
spidev@1 {
compatible = "menlo,m53cpld";
reg = <1>;
spi-max-frequency = <25000000>;
};
};
ðphy0 {
max-speed = <100>;
};
&fec1 {
status = "okay";
};
&flexspi {
status = "okay";
flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <66000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&gpio1 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio3 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "DISP_reset", "KBD_intI",
"", "", "", "",
"", "", "", "";
};
&gpio4 {
/*
* CPLD_D[n] is ARM_CPLD[n] in schematic
* CPLD_int is SA_INTERRUPT in schematic
* CPLD_reset is RESET_SOFT in schematic
*/
gpio-line-names =
"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
"", "CPLD_D[7]", "", "",
"", "", "", "CPLD_D[5]",
"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
"CPLD_D[0]", "", "", "",
"", "", "", "",
"", "", "", "KBD_intK",
"", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio_expander_21 {
status = "okay";
};
&hwmon {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
/* None of this is present on the SoM. */
/delete-node/ bridge@2c;
/delete-node/ hdmi@48;
/delete-node/ touch@4a;
/delete-node/ sensor@4f;
/delete-node/ eeprom@50;
/delete-node/ eeprom@57;
};
&iomuxc {
pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
<&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
pinctrl_beeper: beepergrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
>;
};
pinctrl_uart4_rts: uart4rtsgrp {
fsl,pins = <
/* SODIMM 222 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
>;
};
};
&pinctrl_gpio1 {
fsl,pins = <
/* SODIMM 206 */
MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
>;
};
&pinctrl_gpio_hog1 {
fsl,pins = <
/* SODIMM 88 */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
/* CPLD_int */
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
/* CPLD_reset */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
/* SODIMM 94 */
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
/* SODIMM 96 */
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
/* CPLD_D[7] */
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
/* CPLD_D[6] */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
/* CPLD_D[5] */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
/* CPLD_D[4] */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
/* CPLD_D[3] */
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
/* CPLD_D[2] */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
/* CPLD_D[1] */
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
/* CPLD_D[0] */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
/* KBD_intK */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
/* DISP_reset */
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
/* KBD_intI */
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
/* SODIMM 46 */
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
>;
};
&pinctrl_uart1 {
fsl,pins = <
/* SODIMM 149 */
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
/* SODIMM 147 */
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
/* SODIMM 210 */
MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
/* SODIMM 212 */
MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
>;
};
®_usb_otg1_vbus {
/delete-property/ enable-active-high;
gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
};
®_usb_otg2_vbus {
/delete-property/ enable-active-high;
gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
&sai2 {
status = "disabled";
};
&uart1 {
uart-has-rtscts;
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
linux,rs485-enabled-at-boot-time;
rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
status = "okay";
};
|
