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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Bang & Olufsen
* Copyright 2022 Pengutronix
*/
/dts-v1/;
#include "imx8mm-innocomm-wb15.dtsi"
/ {
model = "InnoComm WB15-EVK";
compatible = "innocomm,wb15-evk", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
label = "debug";
gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reg_vsd_3v3: regulator-vsd-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_ethphy: regulator-eth-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy_reg>;
regulator-name = "PHY_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
phy-supply = <®_ethphy>;
};
};
};
&uart2 {
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
disable-over-current;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
disable-over-current;
status = "okay";
};
&usdhc2 {
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_vsd_3v3>;
status = "okay";
};
&iomuxc {
pinctrl_fec: fec-grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>;
};
pinctrl_fec_phy: fec-phy-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_fec_phy_reg: fec-phy-reg-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
>;
};
pinctrl_gpio_leds: led-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6
>;
};
pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
};
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