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/*
* TI Common Platform Interrupt Controller (cp_intc) driver
*
* Author: Steve Chen <schen@mvista.com>
* Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/export.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <asm/exception.h>
#include <mach/common.h>
#define DAVINCI_CP_INTC_CTRL 0x04
#define DAVINCI_CP_INTC_HOST_CTRL 0x0C
#define DAVINCI_CP_INTC_GLOBAL_ENABLE 0x10
#define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR 0x24
#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET 0x28
#define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR 0x2C
#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
#define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
#define DAVINCI_CP_INTC_PRIO_IDX 0x80
#define DAVINCI_CP_INTC_SYS_STAT_CLR(n) (0x0280 + (n << 2))
#define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n) (0x0380 + (n << 2))
#define DAVINCI_CP_INTC_CHAN_MAP(n) (0x0400 + (n << 2))
#define DAVINCI_CP_INTC_SYS_POLARITY(n) (0x0D00 + (n << 2))
#define DAVINCI_CP_INTC_SYS_TYPE(n) (0x0D80 + (n << 2))
#define DAVINCI_CP_INTC_HOST_ENABLE(n) (0x1500 + (n << 2))
#define DAVINCI_CP_INTC_PRI_INDX_MASK GENMASK(9, 0)
#define DAVINCI_CP_INTC_GPIR_NONE BIT(31)
static void __iomem *davinci_cp_intc_base;
static struct irq_domain *davinci_cp_intc_irq_domain;
static inline unsigned int davinci_cp_intc_read(unsigned int offset)
{
return __raw_readl(davinci_cp_intc_base + offset);
}
static inline void davinci_cp_intc_write(unsigned long value,
unsigned int offset)
{
__raw_writel(value, davinci_cp_intc_base + offset);
}
static void davinci_cp_intc_ack_irq(struct irq_data *d)
{
davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR);
}
/* Disable interrupt */
static void davinci_cp_intc_mask_irq(struct irq_data *d)
{
/* XXX don't know why we need to disable nIRQ here... */
davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR);
davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR);
davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
}
/* Enable interrupt */
static void davinci_cp_intc_unmask_irq(struct irq_data *d)
{
davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET);
}
static int davinci_cp_intc_set_irq_type(struct irq_data *d,
unsigned int flow_type)
{
unsigned reg = BIT_WORD(d->hwirq);
unsigned mask = BIT_MASK(d->hwirq);
unsigned polarity = davinci_cp_intc_read(
DAVINCI_CP_INTC_SYS_POLARITY(reg));
unsigned type = davinci_cp_intc_read(
DAVINCI_CP_INTC_SYS_TYPE(reg));
switch (flow_type) {
case IRQ_TYPE_EDGE_RISING:
polarity |= mask;
type |= mask;
break;
case IRQ_TYPE_EDGE_FALLING:
polarity &= ~mask;
type |= mask;
break;
case IRQ_TYPE_LEVEL_HIGH:
polarity |= mask;
type &= ~mask;
break;
case IRQ_TYPE_LEVEL_LOW:
polarity &= ~mask;
type &= ~mask;
break;
default:
return -EINVAL;
}
davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg));
davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg));
return 0;
}
static struct irq_chip davinci_cp_intc_irq_chip = {
.name = "cp_intc",
.irq_ack = davinci_cp_intc_ack_irq,
.irq_mask = davinci_cp_intc_mask_irq,
.irq_unmask = davinci_cp_intc_unmask_irq,
.irq_set_type = davinci_cp_intc_set_irq_type,
.flags = IRQCHIP_SKIP_SET_WAKE,
};
static asmlinkage void __exception_irq_entry
davinci_cp_intc_handle_irq(struct pt_regs *regs)
{
int gpir, irqnr, none;
/*
* The interrupt number is in first ten bits. The NONE field set to 1
* indicates a spurious irq.
*/
gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX);
irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK;
none = gpir & DAVINCI_CP_INTC_GPIR_NONE;
if (unlikely(none)) {
pr_err_once("%s: spurious irq!\n", __func__);
return;
}
handle_domain_irq(davinci_cp_intc_irq_domain, irqnr, regs);
}
static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &davinci_cp_intc_irq_chip);
irq_set_probe(virq);
irq_set_handler(virq, handle_edge_irq);
return 0;
}
static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
.map = davinci_cp_intc_host_map,
.xlate = irq_domain_xlate_onetwocell,
};
static int __init davinci_cp_intc_of_init(struct device_node *node,
struct device_node *parent)
{
u32 num_irq = davinci_soc_info.intc_irq_num;
u8 *irq_prio = davinci_soc_info.intc_irq_prios;
unsigned num_reg = BITS_TO_LONGS(num_irq);
int i, irq_base;
if (node) {
davinci_cp_intc_base = of_iomap(node, 0);
if (of_property_read_u32(node, "ti,intc-size", &num_irq))
pr_warn("unable to get intc-size, default to %d\n",
num_irq);
} else {
davinci_cp_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
}
if (WARN_ON(!davinci_cp_intc_base))
return -EINVAL;
davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE);
/* Disable all host interrupts */
davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
/* Disable system interrupts */
for (i = 0; i < num_reg; i++)
davinci_cp_intc_write(~0, DAVINCI_CP_INTC_SYS_ENABLE_CLR(i));
/* Set to normal mode, no nesting, no priority hold */
davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
/* Clear system interrupt status */
for (i = 0; i < num_reg; i++)
davinci_cp_intc_write(~0, DAVINCI_CP_INTC_SYS_STAT_CLR(i));
/* Enable nIRQ (what about nFIQ?) */
davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
/*
* Priority is determined by host channel: lower channel number has
* higher priority i.e. channel 0 has highest priority and channel 31
* had the lowest priority.
*/
num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
if (irq_prio) {
unsigned j, k;
u32 val;
for (k = i = 0; i < num_reg; i++) {
for (val = j = 0; j < 4; j++, k++) {
val >>= 8;
if (k < num_irq)
val |= irq_prio[k] << 24;
}
davinci_cp_intc_write(val, DAVINCI_CP_INTC_CHAN_MAP(i));
}
} else {
/*
* Default everything to channel 15 if priority not specified.
* Note that channel 0-1 are mapped to nFIQ and channels 2-31
* are mapped to nIRQ.
*/
for (i = 0; i < num_reg; i++)
davinci_cp_intc_write(0x0f0f0f0f,
DAVINCI_CP_INTC_CHAN_MAP(i));
}
irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
if (irq_base < 0) {
pr_warn("Couldn't allocate IRQ numbers\n");
irq_base = 0;
}
/* create a legacy host */
davinci_cp_intc_irq_domain = irq_domain_add_legacy(
node, num_irq, irq_base, 0,
&davinci_cp_intc_irq_domain_ops, NULL);
if (!davinci_cp_intc_irq_domain) {
pr_err("cp_intc: failed to allocate irq host!\n");
return -EINVAL;
}
set_handle_irq(davinci_cp_intc_handle_irq);
/* Enable global interrupt */
davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE);
return 0;
}
void __init davinci_cp_intc_init(void)
{
davinci_cp_intc_of_init(NULL, NULL);
}
IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);
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