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|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
*/
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Microchip SAM9X60 SoC";
compatible = "microchip,sam9x60";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
gpio0 = &pioA;
gpio1 = &pioB;
gpio2 = &pioC;
gpio3 = &pioD;
tcb0 = &tcb0;
tcb1 = &tcb1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
reg = <0>;
};
};
memory {
device_type = "memory";
reg = <0x20000000 0x10000000>;
};
clocks {
slow_xtal: slow_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
};
main_xtal: main_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
sram: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00300000 0x100000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usb1: ohci@600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
usb2: ehci@700000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
clock-names = "usb_clk", "ehci_clk";
assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
assigned-clock-rates = <480000000>;
status = "disabled";
};
ebi: ebi@10000000 {
compatible = "microchip,sam9x60-ebi";
#address-cells = <2>;
#size-cells = <1>;
atmel,smc = <&smc>;
microchip,sfr = <&sfr>;
reg = <0x10000000 0x60000000>;
ranges = <0x0 0x0 0x10000000 0x10000000
0x1 0x0 0x20000000 0x10000000
0x2 0x0 0x30000000 0x10000000
0x3 0x0 0x40000000 0x10000000
0x4 0x0 0x50000000 0x10000000
0x5 0x0 0x60000000 0x10000000>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
nand_controller: nand-controller {
compatible = "microchip,sam9x60-nand-controller";
ecc-engine = <&pmecc>;
#address-cells = <2>;
#size-cells = <1>;
ranges;
status = "disabled";
};
};
sdmmc0: sdio-host@80000000 {
compatible = "microchip,sam9x60-sdhci";
reg = <0x80000000 0x300>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
clock-names = "hclock", "multclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
sdmmc1: sdio-host@90000000 {
compatible = "microchip,sam9x60-sdhci";
reg = <0x90000000 0x300>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
clock-names = "hclock", "multclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
flx4: flexcom@f0000000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf0000000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf0000000 0x800>;
status = "disabled";
};
flx5: flexcom@f0004000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf0004000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf0004000 0x800>;
status = "disabled";
};
dma0: dma-controller@f0008000 {
compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
reg = <0xf0008000 0x1000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "dma_clk";
};
ssc: ssc@f0010000 {
compatible = "atmel,at91sam9g45-ssc";
reg = <0xf0010000 0x4000>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(38))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(39))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
clock-names = "pclk";
status = "disabled";
};
qspi: spi@f0014000 {
compatible = "microchip,sam9x60-qspi";
reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
reg-names = "qspi_base", "qspi_mmap";
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(26))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(27))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
clock-names = "pclk", "qspick";
atmel,pmc = <&pmc>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2s: i2s@f001c000 {
compatible = "microchip,sam9x60-i2smcc";
reg = <0xf001c000 0x100>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(36))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(37))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
clock-names = "pclk", "gclk";
status = "disabled";
};
flx11: flexcom@f0020000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf0020000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf0020000 0x800>;
status = "disabled";
};
flx12: flexcom@f0024000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf0024000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf0024000 0x800>;
status = "disabled";
};
pit64b: timer@f0028000 {
compatible = "microchip,sam9x60-pit64b";
reg = <0xf0028000 0x100>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
clock-names = "pclk", "gclk";
};
sha: sha@f002c000 {
compatible = "atmel,at91sam9g46-sha";
reg = <0xf002c000 0x100>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(34))>;
dma-names = "tx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "sha_clk";
status = "okay";
};
trng: trng@f0030000 {
compatible = "microchip,sam9x60-trng";
reg = <0xf0030000 0x100>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
status = "okay";
};
aes: aes@f0034000 {
compatible = "atmel,at91sam9g46-aes";
reg = <0xf0034000 0x100>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(32))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(33))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
clock-names = "aes_clk";
status = "okay";
};
tdes: tdes@f0038000 {
compatible = "atmel,at91sam9g46-tdes";
reg = <0xf0038000 0x100>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(31))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(30))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
clock-names = "tdes_clk";
status = "okay";
};
classd: classd@f003c000 {
compatible = "atmel,sama5d2-classd";
reg = <0xf003c000 0x100>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(35))>;
dma-names = "tx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
clock-names = "pclk", "gclk";
status = "disabled";
};
can0: can@f8000000 {
compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
reg = <0xf8000000 0x300>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
clock-names = "can_clk";
status = "disabled";
};
can1: can@f8004000 {
compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
reg = <0xf8004000 0x300>;
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
clock-names = "can_clk";
status = "disabled";
};
tcb0: timer@f8008000 {
compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
clock-names = "t0_clk", "slow_clk";
};
tcb1: timer@f800c000 {
compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf800c000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
clock-names = "t0_clk", "slow_clk";
};
flx6: flexcom@f8010000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8010000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8010000 0x800>;
status = "disabled";
};
flx7: flexcom@f8014000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8014000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8014000 0x800>;
status = "disabled";
};
flx8: flexcom@f8018000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8018000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8018000 0x800>;
status = "disabled";
};
flx0: flexcom@f801c000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf801c000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf801c000 0x800>;
status = "disabled";
};
flx1: flexcom@f8020000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8020000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8020000 0x800>;
status = "disabled";
};
flx2: flexcom@f8024000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8024000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8024000 0x800>;
status = "disabled";
};
flx3: flexcom@f8028000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8028000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8028000 0x800>;
status = "disabled";
};
macb0: ethernet@f802c000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf802c000 0x1000>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
clock-names = "hclk", "pclk";
status = "disabled";
};
macb1: ethernet@f8030000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf8030000 0x1000>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
clock-names = "hclk", "pclk";
status = "disabled";
};
pwm0: pwm@f8034000 {
compatible = "microchip,sam9x60-pwm";
reg = <0xf8034000 0x300>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
#pwm-cells = <3>;
status="disabled";
};
hlcdc: hlcdc@f8038000 {
compatible = "microchip,sam9x60-hlcdc";
reg = <0xf8038000 0x4000>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
clock-names = "periph_clk","sys_clk", "slow_clk";
assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
};
hlcdc_pwm: hlcdc-pwm {
compatible = "atmel,hlcdc-pwm";
#pwm-cells = <3>;
};
};
flx9: flexcom@f8040000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8040000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8040000 0x800>;
status = "disabled";
};
flx10: flexcom@f8044000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xf8044000 0x200>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf8044000 0x800>;
status = "disabled";
};
isi: isi@f8048000 {
compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
reg = <0xf8048000 0x100>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
clock-names = "isi_clk";
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
adc: adc@f804c000 {
compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
reg = <0xf804c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "adc_clk";
dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
dma-names = "rx";
atmel,min-sample-rate-hz = <200000>;
atmel,max-sample-rate-hz = <20000000>;
atmel,startup-time-ms = <4>;
atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
status = "disabled";
};
sfr: sfr@f8050000 {
compatible = "microchip,sam9x60-sfr", "syscon";
reg = <0xf8050000 0x100>;
};
matrix: matrix@ffffde00 {
compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
reg = <0xffffde00 0x200>;
};
pmecc: ecc-engine@ffffe000 {
compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
reg = <0xffffe000 0x300>,
<0xffffe600 0x100>;
};
mpddrc: mpddrc@ffffe800 {
compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
reg = <0xffffe800 0x200>;
clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
clock-names = "ddrck", "mpddr";
};
smc: smc@ffffea00 {
compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
reg = <0xffffea00 0x100>;
};
aic: interrupt-controller@fffff100 {
compatible = "microchip,sam9x60-aic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xfffff100 0x100>;
atmel,external-irqs = <31>;
};
dbgu: serial@fffff200 {
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(28))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(29))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
clock-names = "usart";
status = "disabled";
};
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
pioA: gpio@fffff400 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
pioB: gpio@fffff600 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <26>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
pioC: gpio@fffff800 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
pioD: gpio@fffffa00 {
compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
};
};
pmc: pmc@fffffc00 {
compatible = "microchip,sam9x60-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
#clock-cells = <2>;
clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
clock-names = "td_slck", "md_slck", "main_xtal";
};
reset_controller: rstc@fffffe00 {
compatible = "microchip,sam9x60-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k 0>;
};
shutdown_controller: shdwc@fffffe10 {
compatible = "microchip,sam9x60-shdwc";
reg = <0xfffffe10 0x10>;
clocks = <&clk32k 0>;
#address-cells = <1>;
#size-cells = <0>;
atmel,wakeup-rtc-timer;
atmel,wakeup-rtt-timer;
status = "disabled";
};
rtt: rtt@fffffe20 {
compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
reg = <0xfffffe20 0x20>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k 0>;
};
pit: timer@fffffe40 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
clk32k: sckc@fffffe50 {
compatible = "microchip,sam9x60-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;
#clock-cells = <1>;
};
gpbr: syscon@fffffe60 {
compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffe60 0x10>;
};
rtc: rtc@fffffea8 {
compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
reg = <0xfffffea8 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k 0>;
};
watchdog: watchdog@ffffff80 {
compatible = "microchip,sam9x60-wdt";
reg = <0xffffff80 0x24>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&clk32k 0>;
status = "disabled";
};
};
};
};
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