blob: f2a5f17f312e5840851c6083c3c9aba9184ceca3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright 2018-2022 TQ-Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
/dts-v1/;
#include "imx6ul-tqma6ul1.dtsi"
#include "mba6ulx.dtsi"
/ {
model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board";
compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
};
/*
* Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage)
* and need to be disabled here again
*/
&can2 {
status = "disabled";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed = <100>;
reg = <0>;
};
};
};
&fec2 {
/delete-property/ phy-handle;
/delete-node/ mdio;
};
&iomuxc {
pinctrl_enet1_mdc: enet1mdcgrp {
fsl,pins = <
/* mdio */
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
};
|
