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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Multi Core Timer (MCT)
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |+
The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
global timer and CPU local timers. The global timer is a 64-bit free running
up-counter and can generate 4 interrupts when the counter reaches one of the
four preset counter values. The CPU local timers are 32-bit free running
down-counters and generate an interrupt when the counter expires. There is
one CPU local timer instantiated in MCT for every CPU in the system.
properties:
compatible:
enum:
- samsung,exynos4210-mct
- samsung,exynos4412-mct
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- pattern: "^(fin_pll|mct)$"
- pattern: "^(fin_pll|mct)$"
reg:
maxItems: 1
interrupts:
description: |
Interrupts should be put in specific order. This is, the local timer
interrupts should be specified after the four global timer interrupts
have been specified:
0: Global Timer Interrupt 0
1: Global Timer Interrupt 1
2: Global Timer Interrupt 2
3: Global Timer Interrupt 3
4: Local Timer Interrupt 0
5: Local Timer Interrupt 1
6: ..
7: ..
i: Local Timer Interrupt n
For MCT block that uses a per-processor interrupt for local timers, such
as ones compatible with "samsung,exynos4412-mct", only one local timer
interrupt might be specified, meaning that all local timers use the same
per processor interrupt.
minItems: 5 # 4 Global + 1 local
maxItems: 20 # 4 Global + 16 local
required:
- compatible
- clock-names
- clocks
- interrupts
- reg
additionalProperties: false
examples:
- |
// In this example, the IP contains two local timers, using separate
// interrupts, so two local timer interrupts have been specified,
// in addition to four global timer interrupts.
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
- |
// In this example, the timer interrupts are connected to two separate
// interrupt controllers. Hence, an interrupts-extended is needed.
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&combiner 12 6>,
<&combiner 12 7>,
<&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
- |
// In this example, the IP contains four local timers, but using
// a per-processor interrupt to handle them. Only one first local
// interrupt is specified.
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@10050000 {
compatible = "samsung,exynos4412-mct";
reg = <0x10050000 0x800>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
- |
// In this example, the IP contains four local timers, but using
// a per-processor interrupt to handle them. All the local timer
// interrupts are specified.
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@10050000 {
compatible = "samsung,exynos4412-mct";
reg = <0x10050000 0x800>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
|
