1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive SPI controller
maintainers:
- Pragnesh Patel <pragnesh.patel@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@sifive.com>
allOf:
- $ref: "spi-controller.yaml#"
properties:
compatible:
items:
- const: sifive,fu540-c000-spi
- const: sifive,spi0
description:
Should be "sifive,<chip>-spi" and "sifive,spi<version>".
Supported compatible strings are -
"sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
SPI v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details
SPI RTL that corresponds to the IP block version numbers can be found here -
https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
reg:
maxItems: 1
description:
Physical base address and size of SPI registers map
A second (optional) range can indicate memory mapped flash
interrupts:
maxItems: 1
clocks:
maxItems: 1
description:
Must reference the frequency given to the controller
sifive,fifo-depth:
description:
Depth of hardware queues; defaults to 8
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- enum: [ 8 ]
- default: 8
sifive,max-bits-per-word:
description:
Maximum bits per word; defaults to 8
allOf:
- $ref: "/schemas/types.yaml#/definitions/uint32"
- enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8 ]
- default: 8
required:
- compatible
- reg
- interrupts
- clocks
examples:
- |
spi: spi@10040000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic>;
interrupts = <51>;
clocks = <&tlclk>;
#address-cells = <1>;
#size-cells = <0>;
sifive,fifo-depth = <8>;
sifive,max-bits-per-word = <8>;
};
...
|
