Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.yaml


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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra20/30 SLINK controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    enum:
      - nvidia,tegra20-slink
      - nvidia,tegra30-slink

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: module clock

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: spi

  dmas:
    items:
      - description: DMA channel used for reception
      - description: DMA channel used for transmission

  dma-names:
    items:
      - const: rx
      - const: tx

  operating-points-v2:
    $ref: /schemas/types.yaml#/definitions/phandle

  power-domains:
    items:
      - description: phandle to the core power domain

  spi-max-frequency:
    description: Maximum SPI clocking speed of the controller in Hz.
    $ref: /schemas/types.yaml#/definitions/uint32

allOf:
  - $ref: spi-controller.yaml

unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets
  - reset-names
  - dmas
  - dma-names

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    spi@7000d600 {
        compatible = "nvidia,tegra20-slink";
        reg = <0x7000d600 0x200>;
        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
        spi-max-frequency = <25000000>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&tegra_car TEGRA20_CLK_SBC2>;
        resets = <&tegra_car 44>;
        reset-names = "spi";
        dmas = <&apbdma 16>, <&apbdma 16>;
        dma-names = "rx", "tx";
    };