1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1 Pin Controller
maintainers:
- Gareth Williams <gareth.williams.jx@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
items:
- enum:
- renesas,r9a06g032-pinctrl # RZ/N1D
- renesas,r9a06g033-pinctrl # RZ/N1S
- const: renesas,rzn1-pinctrl # Generic RZ/N1
reg:
items:
- description: GPIO Multiplexing Level1 Register Block
- description: GPIO Multiplexing Level2 Register Block
clocks:
maxItems: 1
clock-names:
const: bus
description:
The bus clock, sometimes described as pclk, for register accesses.
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties:
anyOf:
- type: object
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
A pin multiplexing sub-node describes how to configure a set of (or a
single) pin in some desired alternate function mode.
A single sub-node may define several pin configurations.
properties:
pinmux:
description: |
Integer array representing pin number and pin multiplexing
configuration.
When a pin has to be configured in alternate function mode, use
this property to identify the pin by its global index, and provide
its alternate function configuration number along with it.
When multiple pins are required to be configured as part of the
same alternate function they shall be specified as members of the
same argument list of a single "pinmux" property.
Integers values in the "pinmux" argument list are assembled as:
(PIN | MUX_FUNC << 8)
where PIN directly corresponds to the pl_gpio pin number and
MUX_FUNC is one of the alternate function identifiers defined in:
<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
These identifiers collapse the IO Multiplex Configuration Level 1
and Level 2 numbers that are detailed in the hardware reference
manual into a single number. The identifiers for Level 2 are simply
offset by 10. Additional identifiers are provided to specify the
MDIO source peripheral.
phandle: true
bias-disable: true
bias-pull-up:
description: Pull up the pin with 50 kOhm
bias-pull-down:
description: Pull down the pin with 50 kOhm
bias-high-impedance: true
drive-strength:
enum: [ 4, 6, 8, 12 ]
required:
- pinmux
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
- type: object
properties:
phandle: true
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
examples:
- |
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
pinctrl: pinctrl@40067000 {
compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
reg = <0x40067000 0x1000>, <0x51000000 0x480>;
clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
clock-names = "bus";
/*
* A serial communication interface with a TX output pin and an RX
* input pin.
*/
pins_uart0: pins_uart0 {
pinmux = <
RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
>;
};
/*
* Set the pull-up on the RXD pin of the UART.
*/
pins_uart0_alt: pins_uart0_alt {
pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
pins_uart6_rx {
pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
bias-pull-up;
};
};
};
|
