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* Freescale i.MX7ULP IOMUX Controller
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
ports and IOMUXC DDR for DDR interface.
Note:
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
supports generic pin config.
Please refer to fsl,imx-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "fsl,imx7ulp-iomuxc1".
- fsl,pins: Each entry consists of 5 integers which represents the mux
and config setting for one pin. The first 4 integers
<mux_conf_reg input_reg mux_mode input_val> are specified
using a PIN_FUNC_ID macro, which can be found in
imx7ulp-pinfunc.h in the device tree source folder.
The last integer CONFIG is the pad setting value like
pull-up on this pin.
Please refer to i.MX7ULP Reference Manual for detailed
CONFIG settings.
CONFIG bits definition:
PAD_CTL_OBE (1 << 17)
PAD_CTL_IBE (1 << 16)
PAD_CTL_LK (1 << 16)
PAD_CTL_DSE_HI (1 << 6)
PAD_CTL_DSE_STD (0 << 6)
PAD_CTL_ODE (1 << 5)
PAD_CTL_PUSH_PULL (0 << 5)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_STD (0 << 2)
PAD_CTL_PE (1 << 0)
Examples:
#include "imx7ulp-pinfunc.h"
/* Pin Controller Node */
iomuxc1: pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
/* Pin Configuration Node */
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
IMX7ULP_PAD_PTC3__LPUART4_RX 0x1
IMX7ULP_PAD_PTC2__LPUART4_TX 0x1
>;
};
};
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