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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
The QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
properties:
compatible:
enum:
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
reg:
minItems: 1
maxItems: 2
clocks:
maxItems: 6
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
- const: rchng
- const: pipe
- const: pipediv2
power-domains:
maxItems: 1
resets:
maxItems: 1
reset-names:
items:
- const: phy
vdda-phy-supply: true
vdda-pll-supply: true
qcom,4ln-config-sel:
description: PCIe 4-lane configuration
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle of TCSR syscon
- description: offset of PCIe 4-lane configuration register
- description: offset of configuration bit for this PHY
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
"#phy-cells":
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
- resets
- reset-names
- vdda-phy-supply
- vdda-pll-supply
- "#clock-cells"
- clock-output-names
- "#phy-cells"
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
then:
properties:
reg:
items:
- description: port a
- description: port b
required:
- qcom,4ln-config-sel
else:
properties:
reg:
maxItems: 1
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
pcie2b_phy: phy@1c18000 {
compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
reg = <0x01c18000 0x2000>;
clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
<&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
<&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_2B_PIPE_CLK>,
<&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "rchng",
"pipe", "pipediv2";
power-domains = <&gcc PCIE_2B_GDSC>;
resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
reset-names = "phy";
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
#clock-cells = <0>;
clock-output-names = "pcie_2b_pipe_clk";
#phy-cells = <0>;
};
pcie2a_phy: phy@1c24000 {
compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>;
clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
<&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
<&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_2A_PIPE_CLK>,
<&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "rchng",
"pipe", "pipediv2";
power-domains = <&gcc PCIE_2A_GDSC>;
resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
reset-names = "phy";
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
qcom,4ln-config-sel = <&tcsr 0xa044 0>;
#clock-cells = <0>;
clock-output-names = "pcie_2a_pipe_clk";
#phy-cells = <0>;
};
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