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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MIPI Display Serial Interface (DSI) PHY binding
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
- Chunfeng Yun <chunfeng.yun@mediatek.com>
description: The MIPI DSI PHY supports up to 4-lane output.
properties:
$nodename:
pattern: "^dsi-phy@[0-9a-f]+$"
compatible:
enum:
- mediatek,mt2701-mipi-tx
- mediatek,mt7623-mipi-tx
- mediatek,mt8173-mipi-tx
- mediatek,mt8183-mipi-tx
reg:
maxItems: 1
clocks:
items:
- description: PLL reference clock
clock-output-names:
maxItems: 1
"#phy-cells":
const: 0
"#clock-cells":
const: 0
nvmem-cells:
maxItems: 1
description: A phandle to the calibration data provided by a nvmem device,
if unspecified, default values shall be used.
nvmem-cell-names:
items:
- const: calibration-data
drive-strength-microamp:
description: adjust driving current
multipleOf: 200
minimum: 2000
maximum: 6000
default: 4600
required:
- compatible
- reg
- clocks
- clock-output-names
- "#phy-cells"
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
dsi-phy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0x10215000 0x1000>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx0_pll";
drive-strength-microamp = <4000>;
nvmem-cells= <&mipi_tx_calibration>;
nvmem-cell-names = "calibration-data";
#clock-cells = <0>;
#phy-cells = <0>;
};
...
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