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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 PCIe 2.0 host controller
maintainers:
- Minda Chen <minda.chen@starfivetech.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:
compatible:
const: starfive,jh7110-pcie
reg:
maxItems: 2
reg-names:
items:
- const: reg
- const: config
msi-parent: true
interrupts:
maxItems: 1
clocks:
maxItems: 4
clock-names:
items:
- const: noc
- const: tl
- const: axi_mst0
- const: apb
resets:
items:
- description: AXI MST0 reset
- description: AXI SLAVE reset
- description: AXI SLAVE0 reset
- description: PCIE BRIDGE reset
- description: PCIE CORE reset
- description: PCIE APB reset
reset-names:
items:
- const: mst0
- const: slv0
- const: slv
- const: brg
- const: core
- const: apb
starfive,stg-syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle to System Register Controller stg_syscon node.
- description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
- description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
- description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
- description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
description:
The phandle to System Register Controller syscon node and the offset
of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset
for PCIe.
pwren-gpios:
description: Should specify the GPIO for controlling the PCI bus device power on.
maxItems: 1
reset-gpios:
maxItems: 1
phys:
maxItems: 1
interrupt-controller:
type: object
properties:
'#address-cells':
const: 0
'#interrupt-cells':
const: 1
interrupt-controller: true
required:
- '#address-cells'
- '#interrupt-cells'
- interrupt-controller
additionalProperties: false
required:
- reg
- reg-names
- "#interrupt-cells"
- interrupts
- interrupt-map-mask
- interrupt-map
- clocks
- clock-names
- resets
- msi-controller
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
pcie0: pcie@2B000000 {
compatible = "starfive,jh7110-pcie";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
reg = <0x0 0x2B000000 0x0 0x1000000>,
<0x9 0x40000000 0x0 0x10000000>;
reg-names = "reg", "config";
device_type = "pci";
starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
<0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
interrupt-parent = <&plic>;
interrupts = <56>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
msi-parent = <&pcie0>;
msi-controller;
clocks = <&syscrg 86>,
<&stgcrg 10>,
<&stgcrg 8>,
<&stgcrg 9>;
clock-names = "noc", "tl", "axi_mst0", "apb";
resets = <&stgcrg 11>,
<&stgcrg 12>,
<&stgcrg 13>,
<&stgcrg 14>,
<&stgcrg 15>,
<&stgcrg 16>;
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
|
