1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PCI express root complex
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description: |
Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
PCIe IP.
properties:
compatible:
oneOf:
- enum:
- qcom,pcie-apq8064
- qcom,pcie-apq8084
- qcom,pcie-ipq4019
- qcom,pcie-ipq6018
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064-v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
- qcom,pcie-msm8996
- qcom,pcie-qcs404
- qcom,pcie-sa8540p
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
- qcom,pcie-sc8280xp
- qcom,pcie-sdm845
- qcom,pcie-sm8150
- qcom,pcie-sm8250
- qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
- items:
- const: qcom,pcie-msm8998
- const: qcom,pcie-msm8996
reg:
minItems: 4
maxItems: 6
reg-names:
minItems: 4
maxItems: 6
interrupts:
minItems: 1
maxItems: 8
interrupt-names:
minItems: 1
maxItems: 8
# Common definitions for clocks, clock-names and reset.
# Platform constraints are described later.
clocks:
minItems: 3
maxItems: 13
clock-names:
minItems: 3
maxItems: 13
dma-coherent: true
interconnects:
maxItems: 2
interconnect-names:
items:
- const: pcie-mem
- const: cpu-pcie
resets:
minItems: 1
maxItems: 12
resets-names:
minItems: 1
maxItems: 12
vdda-supply:
description: A phandle to the core analog power supply
vdda_phy-supply:
description: A phandle to the core analog power supply for PHY
vdda_refclk-supply:
description: A phandle to the core analog power supply for IC which generates reference clock
vddpe-3v3-supply:
description: A phandle to the PCIe endpoint power supply
phys:
maxItems: 1
phy-names:
items:
- const: pciephy
power-domains:
maxItems: 1
perst-gpios:
description: GPIO controlled connection to PERST# signal
maxItems: 1
wake-gpios:
description: GPIO controlled connection to WAKE# signal
maxItems: 1
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
- clocks
- clock-names
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-apq8064
- qcom,pcie-ipq4019
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
- qcom,pcie-qcs404
then:
properties:
reg:
minItems: 4
maxItems: 4
reg-names:
items:
- const: dbi # DesignWare PCIe registers
- const: elbi # External local bus interface registers
- const: parf # Qualcomm specific registers
- const: config # PCIe configuration space
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-ipq6018
- qcom,pcie-ipq8074-gen3
then:
properties:
reg:
minItems: 5
maxItems: 5
reg-names:
items:
- const: dbi # DesignWare PCIe registers
- const: elbi # External local bus interface registers
- const: atu # ATU address space
- const: parf # Qualcomm specific registers
- const: config # PCIe configuration space
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-apq8084
- qcom,pcie-msm8996
- qcom,pcie-sdm845
then:
properties:
reg:
minItems: 4
maxItems: 5
reg-names:
minItems: 4
items:
- const: parf # Qualcomm specific registers
- const: dbi # DesignWare PCIe registers
- const: elbi # External local bus interface registers
- const: config # PCIe configuration space
- const: mhi # MHI registers
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
- qcom,pcie-sc8280xp
- qcom,pcie-sm8250
- qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
then:
properties:
reg:
minItems: 5
maxItems: 6
reg-names:
minItems: 5
items:
- const: parf # Qualcomm specific registers
- const: dbi # DesignWare PCIe registers
- const: elbi # External local bus interface registers
- const: atu # ATU address space
- const: config # PCIe configuration space
- const: mhi # MHI registers
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-apq8064
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064v2
then:
properties:
clocks:
minItems: 3
maxItems: 5
clock-names:
minItems: 3
items:
- const: core # Clocks the pcie hw block
- const: iface # Configuration AHB clock
- const: phy # Clocks the pcie PHY block
- const: aux # Clocks the pcie AUX block, not on apq8064
- const: ref # Clocks the pcie ref block, not on apq8064
resets:
minItems: 5
maxItems: 6
reset-names:
minItems: 5
items:
- const: axi # AXI reset
- const: ahb # AHB reset
- const: por # POR reset
- const: pci # PCI reset
- const: phy # PHY reset
- const: ext # EXT reset, not on apq8064
required:
- vdda-supply
- vdda_phy-supply
- vdda_refclk-supply
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-apq8084
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: iface # Configuration AHB clock
- const: master_bus # Master AXI clock
- const: slave_bus # Slave AXI clock
- const: aux # Auxiliary (AUX) clock
resets:
maxItems: 1
reset-names:
items:
- const: core # Core reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-ipq4019
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: aux # Auxiliary (AUX) clock
- const: master_bus # Master AXI clock
- const: slave_bus # Slave AXI clock
resets:
minItems: 12
maxItems: 12
reset-names:
items:
- const: axi_m # AXI master reset
- const: axi_s # AXI slave reset
- const: pipe # PIPE reset
- const: axi_m_vmid # VMID reset
- const: axi_s_xpu # XPU reset
- const: parf # PARF reset
- const: phy # PHY reset
- const: axi_m_sticky # AXI sticky reset
- const: pipe_sticky # PIPE sticky reset
- const: pwr # PWR reset
- const: ahb # AHB reset
- const: phy_ahb # PHY AHB reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-msm8996
then:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
items:
- const: pipe # Pipe Clock driving internal logic
- const: aux # Auxiliary (AUX) clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
resets: false
reset-names: false
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-ipq8074
then:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
items:
- const: iface # PCIe to SysNOC BIU clock
- const: axi_m # AXI Master clock
- const: axi_s # AXI Slave clock
- const: ahb # AHB clock
- const: aux # Auxiliary clock
resets:
minItems: 7
maxItems: 7
reset-names:
items:
- const: pipe # PIPE reset
- const: sleep # Sleep reset
- const: sticky # Core Sticky reset
- const: axi_m # AXI Master reset
- const: axi_s # AXI Slave reset
- const: ahb # AHB Reset
- const: axi_m_sticky # AXI Master Sticky reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-ipq6018
- qcom,pcie-ipq8074-gen3
then:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
items:
- const: iface # PCIe to SysNOC BIU clock
- const: axi_m # AXI Master clock
- const: axi_s # AXI Slave clock
- const: axi_bridge # AXI bridge clock
- const: rchng
resets:
minItems: 8
maxItems: 8
reset-names:
items:
- const: pipe # PIPE reset
- const: sleep # Sleep reset
- const: sticky # Core Sticky reset
- const: axi_m # AXI Master reset
- const: axi_s # AXI Slave reset
- const: ahb # AHB Reset
- const: axi_m_sticky # AXI Master Sticky reset
- const: axi_s_sticky # AXI Slave Sticky reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-qcs404
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: iface # AHB clock
- const: aux # Auxiliary clock
- const: master_bus # AXI Master clock
- const: slave_bus # AXI Slave clock
resets:
minItems: 6
maxItems: 6
reset-names:
items:
- const: axi_m # AXI Master reset
- const: axi_s # AXI Slave reset
- const: axi_m_sticky # AXI Master Sticky reset
- const: pipe_sticky # PIPE sticky reset
- const: pwr # PWR reset
- const: ahb # AHB reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sc7280
then:
properties:
clocks:
minItems: 13
maxItems: 13
clock-names:
items:
- const: pipe # PIPE clock
- const: pipe_mux # PIPE MUX
- const: phy_pipe # PIPE output clock
- const: ref # REFERENCE clock
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: tbu # PCIe TBU clock
- const: ddrss_sf_tbu # PCIe SF TBU clock
- const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
- const: aggre1 # Aggre NoC PCIe1 AXI clock
resets:
maxItems: 1
reset-names:
items:
- const: pci # PCIe core reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sdm845
then:
oneOf:
# Unfortunately the "optional" ref clock is used in the middle of the list
- properties:
clocks:
minItems: 8
maxItems: 8
clock-names:
items:
- const: pipe # PIPE clock
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: ref # REFERENCE clock
- const: tbu # PCIe TBU clock
- properties:
clocks:
minItems: 7
maxItems: 7
clock-names:
items:
- const: pipe # PIPE clock
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: tbu # PCIe TBU clock
properties:
resets:
maxItems: 1
reset-names:
items:
- const: pci # PCIe core reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sc8180x
- qcom,pcie-sm8150
- qcom,pcie-sm8250
then:
oneOf:
# Unfortunately the "optional" ref clock is used in the middle of the list
- properties:
clocks:
minItems: 9
maxItems: 9
clock-names:
items:
- const: pipe # PIPE clock
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: ref # REFERENCE clock
- const: tbu # PCIe TBU clock
- const: ddrss_sf_tbu # PCIe SF TBU clock
- properties:
clocks:
minItems: 8
maxItems: 8
clock-names:
items:
- const: pipe # PIPE clock
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: tbu # PCIe TBU clock
- const: ddrss_sf_tbu # PCIe SF TBU clock
properties:
resets:
maxItems: 1
reset-names:
items:
- const: pci # PCIe core reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sm8350
then:
properties:
clocks:
minItems: 8
maxItems: 9
clock-names:
minItems: 8
items:
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: tbu # PCIe TBU clock
- const: ddrss_sf_tbu # PCIe SF TBU clock
- const: aggre1 # Aggre NoC PCIe1 AXI clock
- const: aggre0 # Aggre NoC PCIe0 AXI clock
resets:
maxItems: 1
reset-names:
items:
- const: pci # PCIe core reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sm8450-pcie0
then:
properties:
clocks:
minItems: 12
maxItems: 12
clock-names:
items:
- const: pipe # PIPE clock
- const: pipe_mux # PIPE MUX
- const: phy_pipe # PIPE output clock
- const: ref # REFERENCE clock
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: ddrss_sf_tbu # PCIe SF TBU clock
- const: aggre0 # Aggre NoC PCIe0 AXI clock
- const: aggre1 # Aggre NoC PCIe1 AXI clock
resets:
maxItems: 1
reset-names:
items:
- const: pci # PCIe core reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sm8450-pcie1
then:
properties:
clocks:
minItems: 11
maxItems: 11
clock-names:
items:
- const: pipe # PIPE clock
- const: pipe_mux # PIPE MUX
- const: phy_pipe # PIPE output clock
- const: ref # REFERENCE clock
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: ddrss_sf_tbu # PCIe SF TBU clock
- const: aggre1 # Aggre NoC PCIe1 AXI clock
resets:
maxItems: 1
reset-names:
items:
- const: pci # PCIe core reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sa8540p
- qcom,pcie-sc8280xp
then:
properties:
clocks:
minItems: 8
maxItems: 9
clock-names:
minItems: 8
items:
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
- const: bus_master # Master AXI clock
- const: bus_slave # Slave AXI clock
- const: slave_q2a # Slave Q2A clock
- const: ddrss_sf_tbu # PCIe SF TBU clock
- const: noc_aggr_4 # NoC aggregate 4 clock
- const: noc_aggr_south_sf # NoC aggregate South SF clock
- const: cnoc_qx # Configuration NoC QX clock
resets:
maxItems: 1
reset-names:
items:
- const: pci # PCIe core reset
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sa8540p
- qcom,pcie-sc8280xp
then:
required:
- interconnects
- interconnect-names
- if:
not:
properties:
compatible:
contains:
enum:
- qcom,pcie-apq8064
- qcom,pcie-ipq4019
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
- qcom,pcie-qcs404
then:
required:
- power-domains
- if:
not:
properties:
compatible:
contains:
enum:
- qcom,pcie-msm8996
then:
required:
- resets
- reset-names
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-msm8996
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
- qcom,pcie-sdm845
- qcom,pcie-sm8150
- qcom,pcie-sm8250
- qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
then:
oneOf:
- properties:
interrupts:
maxItems: 1
interrupt-names:
items:
- const: msi
- properties:
interrupts:
minItems: 8
interrupt-names:
items:
- const: msi0
- const: msi1
- const: msi2
- const: msi3
- const: msi4
- const: msi5
- const: msi6
- const: msi7
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-sc8280xp
then:
properties:
interrupts:
minItems: 4
maxItems: 4
interrupt-names:
items:
- const: msi0
- const: msi1
- const: msi2
- const: msi3
- if:
properties:
compatible:
contains:
enum:
- qcom,pcie-apq8064
- qcom,pcie-apq8084
- qcom,pcie-ipq4019
- qcom,pcie-ipq6018
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064-v2
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
- qcom,pcie-qcs404
- qcom,pcie-sa8540p
then:
properties:
interrupts:
maxItems: 1
interrupt-names:
items:
- const: msi
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pcie@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
<0x1b600000 0x100>,
<0x0ff00000 0x100000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
<0x82000000 0 0 0x08000000 0 0x07e00000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc 41>,
<&gcc 43>,
<&gcc 44>,
<&gcc 42>,
<&gcc 248>;
clock-names = "core", "iface", "phy", "aux", "ref";
resets = <&gcc 27>,
<&gcc 26>,
<&gcc 25>,
<&gcc 24>,
<&gcc 23>,
<&gcc 22>;
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
pinctrl-0 = <&pcie_pins_default>;
pinctrl-names = "default";
vdda-supply = <&pm8921_s3>;
vdda_phy-supply = <&pm8921_lvs6>;
vdda_refclk-supply = <&ext_3p3v>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
pcie@fc520000 {
compatible = "qcom,pcie-apq8084";
reg = <0xfc520000 0x2000>,
<0xff000000 0x1000>,
<0xff001000 0x1000>,
<0xff002000 0x2000>;
reg-names = "parf", "dbi", "elbi", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc 324>,
<&gcc 325>,
<&gcc 327>,
<&gcc 323>;
clock-names = "iface", "master_bus", "slave_bus", "aux";
resets = <&gcc 81>;
reset-names = "core";
power-domains = <&gcc 1>;
vdda-supply = <&pma8084_l3>;
phys = <&pciephy0>;
phy-names = "pciephy";
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins_default>;
pinctrl-names = "default";
};
...
|