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Renesas R-Car Video Input driver (rcar_vin)
-------------------------------------------
The rcar_vin device provides video input capabilities for the Renesas R-Car
family of devices.
Each VIN instance has a single parallel input that supports RGB and YUV video,
with both external synchronization and BT.656 synchronization for the latter.
Depending on the instance the VIN input is connected to external SoC pins, or
on Gen3 platforms to a CSI-2 receiver.
- compatible: Must be one or more of the following
- "renesas,vin-r8a7743" for the R8A7743 device
- "renesas,vin-r8a7744" for the R8A7744 device
- "renesas,vin-r8a7745" for the R8A7745 device
- "renesas,vin-r8a7778" for the R8A7778 device
- "renesas,vin-r8a7779" for the R8A7779 device
- "renesas,vin-r8a7790" for the R8A7790 device
- "renesas,vin-r8a7791" for the R8A7791 device
- "renesas,vin-r8a7792" for the R8A7792 device
- "renesas,vin-r8a7793" for the R8A7793 device
- "renesas,vin-r8a7794" for the R8A7794 device
- "renesas,vin-r8a7795" for the R8A7795 device
- "renesas,vin-r8a7796" for the R8A7796 device
- "renesas,vin-r8a77965" for the R8A77965 device
- "renesas,vin-r8a77970" for the R8A77970 device
- "renesas,vin-r8a77995" for the R8A77995 device
- "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
device.
When compatible with the generic version nodes must list the
SoC-specific version corresponding to the platform first
followed by the generic version.
- reg: the register base and size for the device registers
- interrupts: the interrupt for the device
- clocks: Reference to the parent clock
Additionally, an alias named vinX will need to be created to specify
which video input device this is.
The per-board settings Gen2 platforms:
- port - sub-node describing a single endpoint connected to the VIN
from external SoC pins as described in video-interfaces.txt[1].
Only the first one will be considered as each vin interface has one
input port.
- Optional properties for endpoint nodes:
- hsync-active: see [1] for description. Default is active high.
- vsync-active: see [1] for description. Default is active high.
If both HSYNC and VSYNC polarities are not specified, embedded
synchronization is selected.
- field-active-even: see [1] for description. Default is active high.
- bus-width: see [1] for description. The selected bus width depends on
the SoC type and selected input image format.
Valid values are: 8, 10, 12, 16, 24 and 32.
- data-shift: see [1] for description. Valid values are 0 and 8.
- data-enable-active: polarity of CLKENB signal, see [1] for
description. Default is active high.
The per-board settings Gen3 platforms:
Gen3 platforms can support both a single connected parallel input source
from external SoC pins (port@0) and/or multiple parallel input sources
from local SoC CSI-2 receivers (port@1) depending on SoC.
- renesas,id - ID number of the VIN, VINx in the documentation.
- ports
- port@0 - sub-node describing a single endpoint connected to the VIN
from external SoC pins as described in video-interfaces.txt[1].
Describing more than one endpoint in port@0 is invalid. Only VIN
instances that are connected to external pins should have port@0.
Endpoint nodes of port@0 support the optional properties listed in
the Gen2 per-board settings description.
- port@1 - sub-nodes describing one or more endpoints connected to
the VIN from local SoC CSI-2 receivers. The endpoint numbers must
use the following schema.
- endpoint@0 - sub-node describing the endpoint connected to CSI20
- endpoint@1 - sub-node describing the endpoint connected to CSI21
- endpoint@2 - sub-node describing the endpoint connected to CSI40
- endpoint@3 - sub-node describing the endpoint connected to CSI41
Endpoint nodes of port@1 do not support any optional endpoint property.
Device node example for Gen2 platforms
--------------------------------------
aliases {
vin0 = &vin0;
};
vin0: vin@e6ef0000 {
compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
Board setup example for Gen2 platforms (vin1 composite video input)
-------------------------------------------------------------------
&i2c2 {
status = "okay";
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
adv7180@20 {
compatible = "adi,adv7180";
reg = <0x20>;
remote = <&vin1>;
port {
adv7180: endpoint {
bus-width = <8>;
remote-endpoint = <&vin1ep0>;
};
};
};
};
/* composite video input */
&vin1 {
pinctrl-0 = <&vin1_pins>;
pinctrl-names = "default";
status = "okay";
port {
vin1ep0: endpoint {
remote-endpoint = <&adv7180>;
bus-width = <8>;
};
};
};
Device node example for Gen3 platforms
--------------------------------------
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7795";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 811>;
renesas,id = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin0csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin0>;
};
vin0csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
};
};
};
};
csi20: csi2@fea80000 {
compatible = "renesas,r8a7795-csi2";
reg = <0 0xfea80000 0 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 714>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi20_in: endpoint {
clock-lanes = <0>;
data-lanes = <1>;
remote-endpoint = <&adv7482_txb>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi20vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi20>;
};
};
};
};
[1] video-interfaces.txt common video media interface
|
