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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX8QXP/QM JPEG decoder/encoder Device Tree Bindings
maintainers:
- Mirela Rabulea <mirela.rabulea@nxp.com>
description: |-
The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
and Extended Sequential DCT modes.
properties:
compatible:
items:
- enum:
# JPEG decoder
- nxp,imx8qxp-jpgdec
# JPEG encoder
- nxp,imx8qxp-jpgenc
reg:
maxItems: 1
interrupts:
description: |
There are 4 slots available in the IP, which the driver may use
If a certain slot is used, it should have an associated interrupt
The interrupt with index i is assumed to be for slot i
minItems: 1 # At least one slot is needed by the driver
maxItems: 4 # The IP has 4 slots available for use
power-domains:
description:
List of phandle and PM domain specifier as documented in
Documentation/devicetree/bindings/power/power_domain.txt
minItems: 2 # Wrapper and 1 slot
maxItems: 5 # Wrapper and 4 slots
required:
- compatible
- reg
- interrupts
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/firmware/imx/rsrc.h>
jpegdec: jpegdec@58400000 {
compatible = "nxp,imx8qxp-jpgdec";
reg = <0x58400000 0x00050000 >;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
<&pd IMX_SC_R_MJPEG_DEC_S0>,
<&pd IMX_SC_R_MJPEG_DEC_S1>,
<&pd IMX_SC_R_MJPEG_DEC_S2>,
<&pd IMX_SC_R_MJPEG_DEC_S3>;
};
jpegenc: jpegenc@58450000 {
compatible = "nxp,imx8qxp-jpgenc";
reg = <0x58450000 0x00050000 >;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
<&pd IMX_SC_R_MJPEG_ENC_S0>,
<&pd IMX_SC_R_MJPEG_ENC_S1>,
<&pd IMX_SC_R_MJPEG_ENC_S2>,
<&pd IMX_SC_R_MJPEG_ENC_S3>;
};
...
|
