1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Video Decode Accelerator
maintainers:
- Yunfei Dong <yunfei.dong@mediatek.com>
description: |+
Mediatek Video Decode is the video decode hardware present in Mediatek
SoCs which supports high resolution decoding functionalities.
properties:
compatible:
enum:
- mediatek,mt8173-vcodec-dec
- mediatek,mt8183-vcodec-dec
reg:
maxItems: 12
interrupts:
maxItems: 1
clocks:
maxItems: 8
clock-names:
items:
- const: vcodecpll
- const: univpll_d2
- const: clk_cci400_sel
- const: vdec_sel
- const: vdecpll
- const: vencpll
- const: venc_lt_sel
- const: vdec_bus_clk_src
assigned-clocks: true
assigned-clock-parents: true
assigned-clock-rates: true
power-domains:
maxItems: 1
iommus:
minItems: 1
maxItems: 32
description: |
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to vpu.
mediatek,scp:
$ref: /schemas/types.yaml#/definitions/phandle
maxItems: 1
description:
Describes point to scp.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- iommus
- assigned-clocks
- assigned-clock-parents
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8183-vcodec-dec
then:
required:
- mediatek,scp
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt8173-vcodec-dec
then:
required:
- mediatek,vpu
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8173-power.h>
vcodec_dec: vcodec@16000000 {
compatible = "mediatek,mt8173-vcodec-dec";
reg = <0x16000000 0x100>, /*VDEC_SYS*/
<0x16020000 0x1000>, /*VDEC_MISC*/
<0x16021000 0x800>, /*VDEC_LD*/
<0x16021800 0x800>, /*VDEC_TOP*/
<0x16022000 0x1000>, /*VDEC_CM*/
<0x16023000 0x1000>, /*VDEC_AD*/
<0x16024000 0x1000>, /*VDEC_AV*/
<0x16025000 0x1000>, /*VDEC_PP*/
<0x16026800 0x800>, /*VP8_VD*/
<0x16027000 0x800>, /*VP6_VD*/
<0x16027800 0x800>, /*VP8_VL*/
<0x16028400 0x400>; /*VP9_VD*/
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
mediatek,vpu = <&vpu>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_CCI400_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&topckgen CLK_TOP_VCODECPLL>,
<&apmixedsys CLK_APMIXED_VENCPLL>,
<&topckgen CLK_TOP_VENC_LT_SEL>,
<&topckgen CLK_TOP_VCODECPLL_370P5>;
clock-names = "vcodecpll",
"univpll_d2",
"clk_cci400_sel",
"vdec_sel",
"vdecpll",
"vencpll",
"venc_lt_sel",
"vdec_bus_clk_src";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
<&topckgen CLK_TOP_CCI400_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&apmixedsys CLK_APMIXED_VCODECPLL>,
<&apmixedsys CLK_APMIXED_VENCPLL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_VCODECPLL>;
assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
};
|
