1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcom MPM Interrupt Controller
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description:
Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
MSM Power Manager (MPM) that is in always-on domain. In addition to managing
resources during sleep, the hardware also has an interrupt controller that
monitors the interrupts when the system is asleep, wakes up the APSS when
one of these interrupts occur and replays it to GIC interrupt controller
after GIC becomes operational.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- const: qcom,mpm
reg:
maxItems: 1
description:
Specifies the base address and size of vMPM registers in RPM MSG RAM.
deprecated: true
qcom,rpm-msg-ram:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the APSS MPM slice of the RPM Message RAM
interrupts:
maxItems: 1
description:
Specify the IRQ used by RPM to wakeup APSS.
mboxes:
maxItems: 1
description:
Specify the mailbox used to notify RPM for writing vMPM registers.
interrupt-controller: true
'#interrupt-cells':
const: 2
description:
The first cell is the MPM pin number for the interrupt, and the second
is the trigger type.
qcom,mpm-pin-count:
description:
Specify the total MPM pin count that a SoC supports.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,mpm-pin-map:
description:
A set of MPM pin numbers and the corresponding GIC SPIs.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: MPM pin number
- description: GIC SPI number for the MPM pin
'#power-domain-cells':
const: 0
required:
- compatible
- interrupts
- mboxes
- interrupt-controller
- '#interrupt-cells'
- qcom,mpm-pin-count
- qcom,mpm-pin-map
- qcom,rpm-msg-ram
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
remoteproc-rpm {
compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
glink-edge {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
};
mpm: interrupt-controller {
compatible = "qcom,mpm";
qcom,rpm-msg-ram = <&apss_mpm>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 1>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
qcom,mpm-pin-count = <96>;
qcom,mpm-pin-map = <2 275>,
<5 296>,
<12 422>,
<24 79>,
<86 183>,
<91 260>;
#power-domain-cells = <0>;
};
};
|
