Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip GPIO bank

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,gpio-bank
      - rockchip,rk3188-gpio-bank0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: APB interface clock source
      - description: GPIO debounce reference clock source

  gpio-controller: true

  gpio-line-names: true

  "#gpio-cells":
    const: 2

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - gpio-controller
  - "#gpio-cells"
  - interrupt-controller
  - "#interrupt-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl: pinctrl {
      #address-cells = <1>;
      #size-cells = <1>;
      ranges;

      gpio0: gpio@2000a000 {
        compatible = "rockchip,rk3188-gpio-bank0";
        reg = <0x2000a000 0x100>;
        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk_gates8 9>;

        gpio-controller;
        #gpio-cells = <2>;

        interrupt-controller;
        #interrupt-cells = <2>;
      };

      gpio1: gpio@2003c000 {
        compatible = "rockchip,gpio-bank";
        reg = <0x2003c000 0x100>;
        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk_gates8 10>;

        gpio-controller;
        #gpio-cells = <2>;

        interrupt-controller;
        #interrupt-cells = <2>;
      };
    };