path: root/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt

Allwinner A10 Display Pipeline
==============================

The Allwinner A10 Display pipeline is composed of several components
that are going to be documented below:

For all connections between components up to the TCONs in the display
pipeline, when there are multiple components of the same type at the
same depth, the local endpoint ID must be the same as the remote
component's index. For example, if the remote endpoint is Frontend 1,
then the local endpoint ID must be 1.

    Frontend 0  [0] ------- [0]  Backend 0  [0] ------- [0]  TCON 0
		[1] --   -- [1]             [1] --   -- [1]
		      \ /                         \ /
		       X                           X
		      / \                         / \
		[0] --   -- [0]             [0] --   -- [0]
    Frontend 1  [1] ------- [1]  Backend 1  [1] ------- [1]  TCON 1

For a two pipeline system such as the one depicted above, the lines
represent the connections between the components, while the numbers
within the square brackets corresponds to the ID of the local endpoint.

The same rule also applies to DE 2.0 mixer-TCON connections:

    Mixer 0  [0] ----------- [0]  TCON 0
	     [1] ----   ---- [1]
		     \ /
		      X
		     / \
	     [0] ----   ---- [0]
    Mixer 1  [1] ----------- [1]  TCON 1

HDMI Encoder
------------

The HDMI Encoder supports the HDMI video and audio outputs, and does
CEC. It is one end of the pipeline.

Required properties:
  - compatible: value must be one of:
    * allwinner,sun4i-a10-hdmi
    * allwinner,sun5i-a10s-hdmi
    * allwinner,sun6i-a31-hdmi
  - reg: base address and size of memory-mapped region
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the HDMI encoder
    * ahb: the HDMI interface clock
    * mod: the HDMI module clock
    * ddc: the HDMI ddc clock (A31 only)
    * pll-0: the first video PLL
    * pll-1: the second video PLL
  - clock-names: the clock names mentioned above
  - resets: phandle to the reset control for the HDMI encoder (A31 only)
  - dmas: phandles to the DMA channels used by the HDMI encoder
    * ddc-tx: The channel for DDC transmission
    * ddc-rx: The channel for DDC reception
    * audio-tx: The channel used for audio transmission
  - dma-names: the channel names mentioned above

  - ports: A ports node with endpoint definitions as defined in
    Documentation/devicetree/bindings/media/video-interfaces.txt. The
    first port should be the input endpoint. The second should be the
    output, usually to an HDMI connector.

DWC HDMI TX Encoder
-------------------

The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
with Allwinner's own PHY IP. It supports audio and video outputs and CEC.

These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
following device-specific properties.

Required properties:

  - compatible: value must be one of:
    * "allwinner,sun8i-a83t-dw-hdmi"
    * "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"
    * "allwinner,sun50i-h6-dw-hdmi"
  - reg: base address and size of memory-mapped region
  - reg-io-width: See dw_hdmi.txt. Shall be 1.
  - interrupts: HDMI interrupt number
  - clocks: phandles to the clocks feeding the HDMI encoder
    * iahb: the HDMI bus clock
    * isfr: the HDMI register clock
    * tmds: TMDS clock
    * cec: HDMI CEC clock (H6 only)
    * hdcp: HDCP clock (H6 only)
    * hdcp-bus: HDCP bus clock (H6 only)
  - clock-names: the clock names mentioned above
  - resets:
    * ctrl: HDMI controller reset
    * hdcp: HDCP reset (H6 only)
  - reset-names: reset names mentioned above
  - phys: phandle to the DWC HDMI PHY
  - phy-names: must be "phy"

  - ports: A ports node with endpoint definitions as defined in
    Documentation/devicetree/bindings/media/video-interfaces.txt. The
    first port should be the input endpoint. The second should be the
    output, usually to an HDMI connector.

Optional properties:
  - hvcc-supply: the VCC power supply of the controller

DWC HDMI PHY
------------

Required properties:
  - compatible: value must be one of:
    * allwinner,sun8i-a83t-hdmi-phy
    * allwinner,sun8i-h3-hdmi-phy
    * allwinner,sun8i-r40-hdmi-phy
    * allwinner,sun50i-a64-hdmi-phy
    * allwinner,sun50i-h6-hdmi-phy
  - reg: base address and size of memory-mapped region
  - clocks: phandles to the clocks feeding the HDMI PHY
    * bus: the HDMI PHY interface clock
    * mod: the HDMI PHY module clock
  - clock-names: the clock names mentioned above
  - resets: phandle to the reset controller driving the PHY
  - reset-names: must be "phy"

H3, A64 and R40 HDMI PHY require additional clocks:
  - pll-0: parent of phy clock
  - pll-1: second possible phy clock parent (A64/R40 only)

TV Encoder
----------

The TV Encoder supports the composite and VGA output. It is one end of
the pipeline.

Required properties:
 - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
 - reg: base address and size of memory-mapped region
 - clocks: the clocks driving the TV encoder
 - resets: phandle to the reset controller driving the encoder

- ports: A ports node with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt. The
  first port should be the input endpoint.

TCON
----

The TCON acts as a timing controller for RGB, LVDS and TV interfaces.

Required properties:
 - compatible: value must be either:
   * allwinner,sun4i-a10-tcon
   * allwinner,sun5i-a13-tcon
   * allwinner,sun6i-a31-tcon
   * allwinner,sun6i-a31s-tcon
   * allwinner,sun7i-a20-tcon
   * allwinner,sun8i-a33-tcon
   * allwinner,sun8i-a83t-tcon-lcd
   * allwinner,sun8i-a83t-tcon-tv
   * allwinner,sun8i-r40-tcon-tv
   * allwinner,sun8i-v3s-tcon
   * allwinner,sun9i-a80-tcon-lcd
   * allwinner,sun9i-a80-tcon-tv
   * "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd"
   * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv"
   * allwinner,sun50i-h6-tcon-tv, allwinner,sun8i-r40-tcon-tv
 - reg: base address and size of memory-mapped region
 - interrupts: interrupt associated to this IP
 - clocks: phandles to the clocks feeding the TCON.
   - 'ahb': the interface clocks
   - 'tcon-ch0': The clock driving the TCON channel 0, if supported
 - resets: phandles to the reset controllers driving the encoder
   - "lcd": the reset line for the TCON
   - "edp": the reset line for the eDP block (A80 only)

 - clock-names: the clock names mentioned above
 - reset-names: the reset names mentioned above
 - clock-output-names: Name of the pixel clock created, if TCON supports
   channel 0.

- ports: A ports node with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt. The
  first port should be the input endpoint, the second one the output

  The output may have multiple endpoints. TCON can have 1 or 2 channels,
  usually with the first channel being used for the panels interfaces
  (RGB, LVDS, etc.), and the second being used for the outputs that
  require another controller (TV Encoder, HDMI, etc.). The endpoints
  will take an extra property, allwinner,tcon-channel, to specify the
  channel the endpoint is associated to. If that property is not
  present, the endpoint number will be used as the channel number.

For TCONs with channel 0, there is one more clock required:
   - 'tcon-ch0': The clock driving the TCON channel 0
For TCONs with channel 1, there is one more clock required:
   - 'tcon-ch1': The clock driving the TCON channel 1

When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found
in A13, H3, H5 and V3s SoCs), you need one more reset line:
   - 'lvds': The reset line driving the LVDS logic

And on the A23, A31, A31s and A33, you need one more clock line:
   - 'lvds-alt': An alternative clock source, separate from the TCON channel 0
                 clock, that can be used to drive the LVDS clock

TCON TOP
--------

TCON TOPs main purpose is to configure whole display pipeline. It determines
relationships between mixers and TCONs, selects source TCON for HDMI, muxes
LCD and TV encoder GPIO output, selects TV encoder clock source and contains
additional TV TCON and DSI gates.

It allows display pipeline to be configured in very different ways:

                                / LCD0/LVDS0
                 / [0] TCON-LCD0
                 |              \ MIPI DSI
 mixer0          |
        \        / [1] TCON-LCD1 - LCD1/LVDS1
         TCON-TOP
        /        \ [2] TCON-TV0 [0] - TVE0/RGB
 mixer1          |                  \
                 |                   TCON-TOP - HDMI
                 |                  /
                 \ [3] TCON-TV1 [1] - TVE1/RGB

Note that both TCON TOP references same physical unit. Both mixers can be
connected to any TCON. Not all TCON TOP variants support all features.

Required properties:
  - compatible: value must be one of:
    * allwinner,sun8i-r40-tcon-top
    * allwinner,sun50i-h6-tcon-top
  - reg: base address and size of the memory-mapped region.
  - clocks: phandle to the clocks feeding the TCON TOP
    * bus: TCON TOP interface clock
    * tcon-tv0: TCON TV0 clock
    * tve0: TVE0 clock (R40 only)
    * tcon-tv1: TCON TV1 clock (R40 only)
    * tve1: TVE0 clock (R40 only)
    * dsi: MIPI DSI clock (R40 only)
  - clock-names: clock name mentioned above
  - resets: phandle to the reset line driving the TCON TOP
  - #clock-cells : must contain 1
  - clock-output-names: Names of clocks created for TCON TV0 channel clock,
    TCON TV1 channel clock (R40 only) and DSI channel clock (R40 only), in
    that order.

- ports: A ports node with endpoint definitions as defined in
    Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should
    be defined:
    * port 0 is input for mixer0 mux
    * port 1 is output for mixer0 mux
    * port 2 is input for mixer1 mux
    * port 3 is output for mixer1 mux
    * port 4 is input for HDMI mux
    * port 5 is output for HDMI mux
    All output endpoints for mixer muxes and input endpoints for HDMI mux should
    have reg property with the id of the target TCON, as shown in above graph
    (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one
    endpoint connected to remote endpoint.

DRC
---

The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
(A31, A23, A33, A80), allows to dynamically adjust pixel
brightness/contrast based on histogram measurements for LCD content
adaptive backlight control.


Required properties:
  - compatible: value must be one of:
    * allwinner,sun6i-a31-drc
    * allwinner,sun6i-a31s-drc
    * allwinner,sun8i-a33-drc
    * allwinner,sun9i-a80-drc
  - reg: base address and size of the memory-mapped region.
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the DRC
    * ahb: the DRC interface clock
    * mod: the DRC module clock
    * ram: the DRC DRAM clock
  - clock-names: the clock names mentioned above
  - resets: phandles to the reset line driving the DRC

- ports: A ports node with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt. The
  first port should be the input endpoints, the second one the outputs

Display Engine Backend
----------------------

The display engine backend exposes layers and sprites to the
system.

Required properties:
  - compatible: value must be one of:
    * allwinner,sun4i-a10-display-backend
    * allwinner,sun5i-a13-display-backend
    * allwinner,sun6i-a31-display-backend
    * allwinner,sun7i-a20-display-backend
    * allwinner,sun8i-a33-display-backend
    * allwinner,sun9i-a80-display-backend
  - reg: base address and size of the memory-mapped region.
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the frontend and backend
    * ahb: the backend interface clock
    * mod: the backend module clock
    * ram: the backend DRAM clock
  - clock-names: the clock names mentioned above
  - resets: phandles to the reset controllers driving the backend

- ports: A ports node with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt. The
  first port should be the input endpoints, the second one the output

On the A33, some additional properties are required:
  - reg needs to have an additional region corresponding to the SAT
  - reg-names need to be set, with "be" and "sat"
  - clocks and clock-names need to have a phandle to the SAT bus
    clocks, whose name will be "sat"
  - resets and reset-names need to have a phandle to the SAT bus
    resets, whose name will be "sat"

DEU
---

The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
can sharpen the display content in both luma and chroma channels.

Required properties:
  - compatible: value must be one of:
    * allwinner,sun9i-a80-deu
  - reg: base address and size of the memory-mapped region.
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the DEU
    * ahb: the DEU interface clock
    * mod: the DEU module clock
    * ram: the DEU DRAM clock
  - clock-names: the clock names mentioned above
  - resets: phandles to the reset line driving the DEU

- ports: A ports node with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt. The
  first port should be the input endpoints, the second one the outputs

Display Engine Frontend
-----------------------

The display engine frontend does formats conversion, scaling,
deinterlacing and color space conversion.

Required properties:
  - compatible: value must be one of:
    * allwinner,sun4i-a10-display-frontend
    * allwinner,sun5i-a13-display-frontend
    * allwinner,sun6i-a31-display-frontend
    * allwinner,sun7i-a20-display-frontend
    * allwinner,sun8i-a33-display-frontend
    * allwinner,sun9i-a80-display-frontend
  - reg: base address and size of the memory-mapped region.
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the frontend and backend
    * ahb: the backend interface clock
    * mod: the backend module clock
    * ram: the backend DRAM clock
  - clock-names: the clock names mentioned above
  - resets: phandles to the reset controllers driving the backend

- ports: A ports node with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt. The
  first port should be the input endpoints, the second one the outputs

Display Engine 2.0 Mixer
------------------------

The DE2 mixer have many functionalities, currently only layer blending is
supported.

Required properties:
  - compatible: value must be one of:
    * allwinner,sun8i-a83t-de2-mixer-0
    * allwinner,sun8i-a83t-de2-mixer-1
    * allwinner,sun8i-h3-de2-mixer-0
    * allwinner,sun8i-r40-de2-mixer-0
    * allwinner,sun8i-r40-de2-mixer-1
    * allwinner,sun8i-v3s-de2-mixer
    * allwinner,sun50i-a64-de2-mixer-0
    * allwinner,sun50i-a64-de2-mixer-1
    * allwinner,sun50i-h6-de3-mixer-0
  - reg: base address and size of the memory-mapped region.
  - clocks: phandles to the clocks feeding the mixer
    * bus: the mixer interface clock
    * mod: the mixer module clock
  - clock-names: the clock names mentioned above
  - resets: phandles to the reset controllers driving the mixer

- ports: A ports node with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt. The
  first port should be the input endpoints, the second one the output


Display Engine Pipeline
-----------------------

The display engine pipeline (and its entry point, since it can be
either directly the backend or the frontend) is represented as an
extra node.

Required properties:
  - compatible: value must be one of:
    * allwinner,sun4i-a10-display-engine
    * allwinner,sun5i-a10s-display-engine
    * allwinner,sun5i-a13-display-engine
    * allwinner,sun6i-a31-display-engine
    * allwinner,sun6i-a31s-display-engine
    * allwinner,sun7i-a20-display-engine
    * allwinner,sun8i-a33-display-engine
    * allwinner,sun8i-a83t-display-engine
    * allwinner,sun8i-h3-display-engine
    * allwinner,sun8i-r40-display-engine
    * allwinner,sun8i-v3s-display-engine
    * allwinner,sun9i-a80-display-engine
    * allwinner,sun50i-a64-display-engine
    * allwinner,sun50i-h6-display-engine

  - allwinner,pipelines: list of phandle to the display engine
    frontends (DE 1.0) or mixers (DE 2.0/3.0) available.

Example:

panel: panel {
	compatible = "olimex,lcd-olinuxino-43-ts";
	#address-cells = <1>;
	#size-cells = <0>;

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		panel_input: endpoint {
			remote-endpoint = <&tcon0_out_panel>;
		};
	};
};

connector {
	compatible = "hdmi-connector";
	type = "a";

	port {
		hdmi_con_in: endpoint {
			remote-endpoint = <&hdmi_out_con>;
		};
	};
};

hdmi: hdmi@1c16000 {
	compatible = "allwinner,sun5i-a10s-hdmi";
	reg = <0x01c16000 0x1000>;
	interrupts = <58>;
	clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
		 <&ccu CLK_PLL_VIDEO0_2X>,
		 <&ccu CLK_PLL_VIDEO1_2X>;
	clock-names = "ahb", "mod", "pll-0", "pll-1";
	dmas = <&dma SUN4I_DMA_NORMAL 16>,
	       <&dma SUN4I_DMA_NORMAL 16>,
	       <&dma SUN4I_DMA_DEDICATED 24>;
	dma-names = "ddc-tx", "ddc-rx", "audio-tx";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			hdmi_in_tcon0: endpoint {
				remote-endpoint = <&tcon0_out_hdmi>;
			};
		};

		port@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			hdmi_out_con: endpoint {
				remote-endpoint = <&hdmi_con_in>;
			};
		};
	};
};

tve0: tv-encoder@1c0a000 {
	compatible = "allwinner,sun4i-a10-tv-encoder";
	reg = <0x01c0a000 0x1000>;
	clocks = <&ahb_gates 34>;
	resets = <&tcon_ch0_clk 0>;

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		tve0_in_tcon0: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&tcon0_out_tve0>;
		};
	};
};

tcon0: lcd-controller@1c0c000 {
	compatible = "allwinner,sun5i-a13-tcon";
	reg = <0x01c0c000 0x1000>;
	interrupts = <44>;
	resets = <&tcon_ch0_clk 1>;
	reset-names = "lcd";
	clocks = <&ahb_gates 36>,
		 <&tcon_ch0_clk>,
		 <&tcon_ch1_clk>;
	clock-names = "ahb",
		      "tcon-ch0",
		      "tcon-ch1";
	clock-output-names = "tcon-pixel-clock";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		tcon0_in: port@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			tcon0_in_be0: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&be0_out_tcon0>;
			};
		};

		tcon0_out: port@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			tcon0_out_panel: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&panel_input>;
			};

			tcon0_out_tve0: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&tve0_in_tcon0>;
			};
		};
	};
};

fe0: display-frontend@1e00000 {
	compatible = "allwinner,sun5i-a13-display-frontend";
	reg = <0x01e00000 0x20000>;
	interrupts = <47>;
	clocks = <&ahb_gates 46>, <&de_fe_clk>,
		 <&dram_gates 25>;
	clock-names = "ahb", "mod",
		      "ram";
	resets = <&de_fe_clk>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		fe0_out: port@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			fe0_out_be0: endpoint {
				remote-endpoint = <&be0_in_fe0>;
			};
		};
	};
};

be0: display-backend@1e60000 {
	compatible = "allwinner,sun5i-a13-display-backend";
	reg = <0x01e60000 0x10000>;
	interrupts = <47>;
	clocks = <&ahb_gates 44>, <&de_be_clk>,
		 <&dram_gates 26>;
	clock-names = "ahb", "mod",
		      "ram";
	resets = <&de_be_clk>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		be0_in: port@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			be0_in_fe0: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&fe0_out_be0>;
			};
		};

		be0_out: port@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			be0_out_tcon0: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&tcon0_in_be0>;
			};
		};
	};
};

display-engine {
	compatible = "allwinner,sun5i-a13-display-engine";
	allwinner,pipelines = <&fe0>;
};