blob: 9be44a682e67aaea7d3ca46f92f7fca89ae62ca0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Synopsys DesignWare HDMI TX Controller
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
description: |
This document defines device tree properties for the Synopsys DesignWare HDMI
TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
binding specification by itself but is meant to be referenced by device tree
bindings for the platform-specific integrations of the DWC HDMI TX.
When referenced from platform device tree bindings the properties defined in
this document are defined as follows. The platform device tree bindings are
responsible for defining whether each property is required or optional.
properties:
reg:
maxItems: 1
reg-io-width:
description:
Width (in bytes) of the registers specified by the reg property.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 4]
default: 1
clocks:
minItems: 2
maxItems: 5
items:
- description: The bus clock for either AHB and APB
- description: The internal register configuration clock
additionalItems: true
clock-names:
minItems: 2
maxItems: 5
items:
- const: iahb
- const: isfr
additionalItems: true
interrupts:
maxItems: 1
additionalProperties: true
...
|
