1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm PrimeCell Color LCD Controller PL110/PL111
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
a framebuffer region in system memory, and creates timed signals for
a variety of LCD panels.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,pl110
- arm,pl111
required:
- compatible
properties:
compatible:
items:
- enum:
- arm,pl110
- arm,pl111
- const: arm,primecell
reg:
maxItems: 1
interrupt-names:
oneOf:
- const: combined
description:
The IP provides four individual interrupt lines, but also one
combined line. If the integration only connects this line to the
interrupt controller, this single interrupt is noted here.
- items:
- const: mbe # CLCDMBEINTR
- const: vcomp # CLCDVCOMPINTR
- const: lnbu # CLCDLNBUINTR
- const: fuf # CLCDFUFINTR
interrupts:
minItems: 1
maxItems: 4
clock-names:
items:
- const: clcdclk
- const: apb_pclk
clocks:
items:
- description: The CLCDCLK reference clock for the controller.
- description: The HCLK AHB slave clock for the register access.
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
max-memory-bandwidth:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Maximum bandwidth in bytes per second that the cell's memory interface
can handle.
If not present, the memory interface is fast enough to handle all
possible video modes.
port:
$ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
description:
Output endpoint of the controller, connecting the LCD panel signals.
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
unevaluatedProperties: false
properties:
arm,pl11x,tft-r0g0b0-pads:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: index of CLD pad used for first red bit (R0)
- description: index of CLD pad used for first green bit (G0)
- description: index of CLD pad used for first blue bit (G0)
deprecated: true
description: |
DEPRECATED. An array of three 32-bit values, defining the way
CLD[23:0] pads are wired up.
The first value contains the index of the "CLD" external pin (pad)
used as R0 (first bit of the red component), the second value for
green, the third value for blue.
See also "LCD panel signal multiplexing details" paragraphs in the
PL110/PL111 Technical Reference Manuals.
This implicitly defines available color modes, for example:
- PL111 TFT 4:4:4 panel:
arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
- PL110 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
- PL111 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
- PL111 TFT 5:6:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
- PL110 and PL111 TFT 8:8:8 panel:
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
additionalProperties: false
required:
- compatible
- reg
- clock-names
- clocks
- port
allOf:
- if:
properties:
interrupts:
minItems: 2
required:
- interrupts
then:
required:
- interrupt-names
examples:
- |
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
interrupt-names = "combined";
interrupts = <44>;
clocks = <&oscclk1>, <&oscclk2>;
clock-names = "clcdclk", "apb_pclk";
max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
port {
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
};
};
};
panel {
compatible = "arm,rtsm-display", "panel-dpi";
power-supply = <&vcc_supply>;
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};
...
|