/* SPDX-License-Identifier: GPL-2.0 */
/*
 * TRNG driver for the StarFive JH7110 SoC
 *
 * Copyright (C) 2021 StarFive Technology Co., Ltd.
 */

/* trng register offset */
#define CCORE_CTRL		0x00
#define CCORE_STAT		0x04
#define CCORE_MODE		0x08
#define CCORE_SMODE		0x0C
#define CCORE_IE		0x10
#define CCORE_ISTAT		0x14
#define CCORE_FEATURES		0x1C
#define CCORE_RAND0		0x20
#define CCORE_RAND1		0x24
#define CCORE_RAND2		0x28
#define CCORE_RAND3		0x2C
#define CCORE_RAND4		0x30
#define CCORE_RAND5		0x34
#define CCORE_RAND6		0x38
#define CCORE_RAND7		0x3C
#define CCORE_SEED0		0x40
#define CCORE_SEED1		0x44
#define CCORE_SEED2		0x48
#define CCORE_SEED3		0x4C
#define CCORE_SEED4		0x50
#define CCORE_SEED5		0x54
#define CCORE_SEED6		0x58
#define CCORE_SEED7		0x5C
#define CCORE_AUTO_RQSTS	0x60
#define CCORE_AUTO_AGE		0x64
#define CCORE_BUILD_CONFIG	0x68

/* CTRL CMD */
#define CCORE_CTRL_EXEC_NOP		(0x0)
#define CCORE_CTRL_GENE_RANDOM		(0x1)
#define CCORE_CTRL_EXEC_RANDRESEED	(0x2)
#define CCORE_CTRL_EXEC_NONCRESEED	(0x3)

/* STAT */
#define _CCORE_STAT_NONCE_MODE		2
#define _CCORE_STAT_R256		3
#define _CCORE_STAT_MISSION_MODE	8
#define _CCORE_STAT_SEEDED		9
#define _CCORE_STAT_LAST_RESEED	16
#define _CCORE_STAT_SRVC_RQST		27
#define _CCORE_STAT_RAND_GENERATING	30
#define _CCORE_STAT_RAND_SEEDING	31

#define CCORE_STAT_NONCE_MODE		BIT(_CCORE_STAT_NONCE_MODE)
#define CCORE_STAT_R256			BIT(_CCORE_STAT_R256)
#define CCORE_STAT_MISSION_MODE		BIT(_CCORE_STAT_MISSION_MODE)
#define CCORE_STAT_SEEDED		BIT(_CCORE_STAT_SEEDED)
#define CCORE_STAT_LAST_RESEED(x)	((x) << _CCORE_STAT_LAST_RESEED)
#define CCORE_STAT_SRVC_RQST		BIT(_CCORE_STAT_SRVC_RQST)
#define CCORE_STAT_RAND_GENERATING	BIT(_CCORE_STAT_RAND_GENERATING)
#define CCORE_STAT_RAND_SEEDING		BIT(_CCORE_STAT_RAND_SEEDING)

/* MODE */
#define _CCORE_MODE_R256		3
#define CCORE_MODE_R256			BIT(_CCORE_MODE_R256)

/* SMODE */
#define _CCORE_SMODE_NONCE_MODE	2
#define _CCORE_SMODE_MISSION_MODE	8
#define _CCORE_SMODE_MAX_REJECTS	16

#define CCORE_SMODE_NONCE_MODE		BIT(_CCORE_SMODE_NONCE_MODE)
#define CCORE_SMODE_MISSION_MODE	BIT(_CCORE_SMODE_MISSION_MODE)
#define CCORE_SMODE_MAX_REJECTS(x)	((x) << _CCORE_SMODE_MAX_REJECTS)

/* IE */
#define _CCORE_IE_RAND_REY_EN		0
#define _CCORE_IE_SEED_DONE_EN		1
#define _CCORE_IE_AGE_ALARM_EN		2
#define _CCORE_IE_RQST_ALARM_EN	3
#define _CCORE_IE_LOCKUP_EN		4
#define _CCORE_IE_GLBL_EN		31

#define CCORE_IE_RAND_REY_EN		BIT(_CCORE_IE_RAND_REY_EN)
#define CCORE_IE_SEED_DONE_EN		BIT(_CCORE_IE_SEED_DONE_EN)
#define CCORE_IE_AGE_ALARM_EN		BIT(_CCORE_IE_AGE_ALARM_EN)
#define CCORE_IE_RQST_ALARM_EN		BIT(_CCORE_IE_RQST_ALARM_EN)
#define CCORE_IE_LOCKUP_EN		BIT(_CCORE_IE_LOCKUP_EN)
#define CCORE_IE_GLBL_EN		BIT(_CCORE_IE_GLBL_EN)

#define CCORE_IE_ALL			(CCORE_IE_GLBL_EN | CCORE_IE_RAND_REY_EN | \
					 CCORE_IE_SEED_DONE_EN | CCORE_IE_AGE_ALARM_EN | \
					 CCORE_IE_RQST_ALARM_EN | CCORE_IE_LOCKUP_EN)

/* ISTAT */
#define _CCORE_ISTAT_RAND_RDY		0
#define _CCORE_ISTAT_SEED_DONE		1
#define _CCORE_ISTAT_AGE_ALARM		2
#define _CCORE_ISTAT_RQST_ALARM		3
#define _CCORE_ISTAT_LFSR_LOOKUP	4

#define CCORE_ISTAT_RAND_RDY		BIT(_CCORE_ISTAT_RAND_RDY)
#define CCORE_ISTAT_SEED_DONE		BIT(_CCORE_ISTAT_SEED_DONE)
#define CCORE_ISTAT_AGE_ALARM		BIT(_CCORE_ISTAT_AGE_ALARM)
#define CCORE_ISTAT_LFSR_LOOKUP		BIT(_CCORE_ISTAT_LFSR_LOOKUP)

/* FEATURES */
#define _CCORE_FEATURES_MAX_RAND_LENGTH			0
#define _CCORE_FEATURES_RAND_SEED_AVAIL			2
#define _CCORE_FEATURES_MISSION_MODE_RESET_STATE	3

#define CCORE_FEATURES_MAX_RAND_LENGTH(x)	  ((x) << _CCORE_FEATURES_MAX_RAND_LENGTH)
#define CCORE_FEATURES_RAND_SEED_AVAIL		  BIT(_CCORE_FEATURES_RAND_SEED_AVAIL)
#define CCORE_FEATURES_MISSION_MODE_RESET_STATE	  BIT(_CCORE_FEATURES_MISSION_MODE_RESET_STATE)

#define AUTOREQ_DISABLED			(0x0)
#define AUTOAGE_DISABLED			(0x0)

/* BUILD_CONFIG */
#define _CCORE_BUILD_CONFIG_MAX_PRNG_LEN		2
#define _CCORE_BUILD_CONFIG_PRNG_LEN_AFTER_REST		3
#define _CCORE_BUILD_CONFIG_MODE_AFTER_REST		4
#define _CCORE_BUILD_CONFIG_AUTO_RESEED_LOOPBACK	5

#define CCORE_BUILD_CONFIG_MAX_PRNG_LEN		  BIT(_CCORE_BUILD_CONFIG_MAX_PRNG_LEN)
#define CCORE_BUILD_CONFIG_PRNG_LEN_AFTER_REST	  BIT(_CCORE_BUILD_CONFIG_PRNG_LEN_AFTER_REST)
#define CCORE_BUILD_CONFIG_MODE_AFTER_REST	  BIT(_CCORE_BUILD_CONFIG_MODE_AFTER_REST)
#define CCORE_BUILD_CONFIG_AUTO_RESEED_LOOPBACK	  BIT(_CCORE_BUILD_CONFIG_AUTO_RESEED_LOOPBACK)

#define CCORE_RAND_LEN	8
#define CCORE_SEED_LEN	8

enum sec_opmode {
	poll_mode,
	int_mode,
};

enum sec_trng_reseed {
	RANDOM_RESEED,
	NONCE_RESEED,
};

enum sec_trng_mode {
	PRNG_128BIT,  //PRNG set up for 128bit maximum
	PRNG_256BIT,  //PRNG set up for 256bit maximum
};