// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ #include / { soc { pinctrl: pin-controller@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-pinctrl"; ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x400>; clocks = <&rcc GPIOA>; st,bank-name = "GPIOA"; status = "disabled"; }; gpiob: gpio@50003000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x400>; clocks = <&rcc GPIOB>; st,bank-name = "GPIOB"; status = "disabled"; }; gpioc: gpio@50004000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x400>; clocks = <&rcc GPIOC>; st,bank-name = "GPIOC"; status = "disabled"; }; gpiod: gpio@50005000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x400>; clocks = <&rcc GPIOD>; st,bank-name = "GPIOD"; status = "disabled"; }; gpioe: gpio@50006000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x400>; clocks = <&rcc GPIOE>; st,bank-name = "GPIOE"; status = "disabled"; }; gpiof: gpio@50007000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x400>; clocks = <&rcc GPIOF>; st,bank-name = "GPIOF"; status = "disabled"; }; gpiog: gpio@50008000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x400>; clocks = <&rcc GPIOG>; st,bank-name = "GPIOG"; status = "disabled"; }; gpioh: gpio@50009000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x400>; clocks = <&rcc GPIOH>; st,bank-name = "GPIOH"; status = "disabled"; }; gpioi: gpio@5000a000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x400>; clocks = <&rcc GPIOI>; st,bank-name = "GPIOI"; status = "disabled"; }; gpioj: gpio@5000b000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x9000 0x400>; clocks = <&rcc GPIOJ>; st,bank-name = "GPIOJ"; status = "disabled"; }; gpiok: gpio@5000c000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0xa000 0x400>; clocks = <&rcc GPIOK>; st,bank-name = "GPIOK"; status = "disabled"; }; adc12_ain_pins_a: adc12-ain-0 { pins { pinmux = , /* ADC1 in13 */ , /* ADC1 in6 */ , /* ADC2 in2 */ ; /* ADC2 in6 */ }; }; adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { pins { pinmux = , /* ADC12 in18 */ ; /* ADC12 in19 */ }; }; cec_pins_a: cec-0 { pins { pinmux = ; bias-disable; drive-open-drain; slew-rate = <0>; }; }; cec_pins_sleep_a: cec-sleep-0 { pins { pinmux = ; /* HDMI_CEC */ }; }; cec_pins_b: cec-1 { pins { pinmux = ; bias-disable; drive-open-drain; slew-rate = <0>; }; }; cec_pins_sleep_b: cec-sleep-1 { pins { pinmux = ; /* HDMI_CEC */ }; }; dac_ch1_pins_a: dac-ch1 { pins { pinmux = ; }; }; dac_ch2_pins_a: dac-ch2 { pins { pinmux = ; }; }; dcmi_pins_a: dcmi-0 { pins { pinmux = ,/* DCMI_HSYNC */ ,/* DCMI_VSYNC */ ,/* DCMI_PIXCLK */ ,/* DCMI_D0 */ ,/* DCMI_D1 */ ,/* DCMI_D2 */ ,/* DCMI_D3 */ ,/* DCMI_D4 */ ,/* DCMI_D5 */ ,/* DCMI_D6 */ ,/* DCMI_D7 */ ,/* DCMI_D8 */ ,/* DCMI_D9 */ ,/* DCMI_D10 */ ;/* DCMI_D11 */ bias-disable; }; }; dcmi_sleep_pins_a: dcmi-sleep-0 { pins { pinmux = ,/* DCMI_HSYNC */ ,/* DCMI_VSYNC */ ,/* DCMI_PIXCLK */ ,/* DCMI_D0 */ ,/* DCMI_D1 */ ,/* DCMI_D2 */ ,/* DCMI_D3 */ ,/* DCMI_D4 */ ,/* DCMI_D5 */ ,/* DCMI_D6 */ ,/* DCMI_D7 */ ,/* DCMI_D8 */ ,/* DCMI_D9 */ ,/* DCMI_D10 */ ;/* DCMI_D11 */ }; }; ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ , /* ETH_RGMII_GTX_CLK */ , /* ETH_RGMII_TXD0 */ , /* ETH_RGMII_TXD1 */ , /* ETH_RGMII_TXD2 */ , /* ETH_RGMII_TXD3 */ , /* ETH_RGMII_TX_CTL */ , /* ETH_MDIO */ ; /* ETH_MDC */ bias-disable; drive-push-pull; slew-rate = <3>; }; pins2 { pinmux = , /* ETH_RGMII_RXD0 */ , /* ETH_RGMII_RXD1 */ , /* ETH_RGMII_RXD2 */ , /* ETH_RGMII_RXD3 */ , /* ETH_RGMII_RX_CLK */ ; /* ETH_RGMII_RX_CTL */ bias-disable; }; }; ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ , /* ETH_RGMII_GTX_CLK */ , /* ETH_RGMII_TXD0 */ , /* ETH_RGMII_TXD1 */ , /* ETH_RGMII_TXD2 */ , /* ETH_RGMII_TXD3 */ , /* ETH_RGMII_TX_CTL */ , /* ETH_MDIO */ , /* ETH_MDC */ , /* ETH_RGMII_RXD0 */ , /* ETH_RGMII_RXD1 */ , /* ETH_RGMII_RXD2 */ , /* ETH_RGMII_RXD3 */ , /* ETH_RGMII_RX_CLK */ ; /* ETH_RGMII_RX_CTL */ }; }; fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ , /* FMC_NWE */ , /* FMC_A16_FMC_CLE */ , /* FMC_A17_FMC_ALE */ , /* FMC_D0 */ , /* FMC_D1 */ , /* FMC_D2 */ , /* FMC_D3 */ , /* FMC_D4 */ , /* FMC_D5 */ , /* FMC_D6 */ , /* FMC_D7 */ ; /* FMC_NE2_FMC_NCE */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* FMC_NWAIT */ bias-pull-up; }; }; fmc_sleep_pins_a: fmc-sleep-0 { pins { pinmux = , /* FMC_NOE */ , /* FMC_NWE */ , /* FMC_A16_FMC_CLE */ , /* FMC_A17_FMC_ALE */ , /* FMC_D0 */ , /* FMC_D1 */ , /* FMC_D2 */ , /* FMC_D3 */ , /* FMC_D4 */ , /* FMC_D5 */ , /* FMC_D6 */ , /* FMC_D7 */ , /* FMC_NWAIT */ ; /* FMC_NE2_FMC_NCE */ }; }; i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; i2c1_pins_sleep_a: i2c1-1 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ }; }; i2c1_pins_b: i2c1-2 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; i2c1_pins_sleep_b: i2c1-3 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ }; }; i2c2_pins_a: i2c2-0 { pins { pinmux = , /* I2C2_SCL */ ; /* I2C2_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; i2c2_pins_sleep_a: i2c2-1 { pins { pinmux = , /* I2C2_SCL */ ; /* I2C2_SDA */ }; }; i2c2_pins_b1: i2c2-2 { pins { pinmux = ; /* I2C2_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; i2c2_pins_sleep_b1: i2c2-3 { pins { pinmux = ; /* I2C2_SDA */ }; }; i2c5_pins_a: i2c5-0 { pins { pinmux = , /* I2C5_SCL */ ; /* I2C5_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; i2c5_pins_sleep_a: i2c5-1 { pins { pinmux = , /* I2C5_SCL */ ; /* I2C5_SDA */ }; }; i2s2_pins_a: i2s2-0 { pins { pinmux = , /* I2S2_SDO */ , /* I2S2_WS */ ; /* I2S2_CK */ slew-rate = <1>; drive-push-pull; bias-disable; }; }; i2s2_pins_sleep_a: i2s2-1 { pins { pinmux = , /* I2S2_SDO */ , /* I2S2_WS */ ; /* I2S2_CK */ }; }; ltdc_pins_a: ltdc-a-0 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ , /* LCD_VSYNC */ , /* LCD_DE */ , /* LCD_R0 */ , /* LCD_R1 */ , /* LCD_R2 */ , /* LCD_R3 */ , /* LCD_R4 */ , /* LCD_R5 */ , /* LCD_R6 */ , /* LCD_R7 */ , /* LCD_G0 */ , /* LCD_G1 */ , /* LCD_G2 */ , /* LCD_G3 */ , /* LCD_G4 */ , /* LCD_G5 */ , /* LCD_G6 */ , /* LCD_G7 */ , /* LCD_B0 */ , /* LCD_B1 */ , /* LCD_B2 */ , /* LCD_B3 */ , /* LCD_B4 */ , /* LCD_B5 */ , /* LCD_B6 */ ; /* LCD_B7 */ bias-disable; drive-push-pull; slew-rate = <1>; }; }; ltdc_pins_sleep_a: ltdc-a-1 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ , /* LCD_VSYNC */ , /* LCD_DE */ , /* LCD_R0 */ , /* LCD_R1 */ , /* LCD_R2 */ , /* LCD_R3 */ , /* LCD_R4 */ , /* LCD_R5 */ , /* LCD_R6 */ , /* LCD_R7 */ , /* LCD_G0 */ , /* LCD_G1 */ , /* LCD_G2 */ , /* LCD_G3 */ , /* LCD_G4 */ , /* LCD_G5 */ , /* LCD_G6 */ , /* LCD_G7 */ , /* LCD_B0 */ , /* LCD_B1 */ , /* LCD_B2 */ , /* LCD_B3 */ , /* LCD_B4 */ , /* LCD_B5 */ , /* LCD_B6 */ ; /* LCD_B7 */ }; }; ltdc_pins_b: ltdc-b-0 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ , /* LCD_VSYNC */ , /* LCD_DE */ , /* LCD_R0 */ , /* LCD_R1 */ , /* LCD_R2 */ , /* LCD_R3 */ , /* LCD_R4 */ , /* LCD_R5 */ , /* LCD_R6 */ , /* LCD_R7 */ , /* LCD_G0 */ , /* LCD_G1 */ , /* LCD_G2 */ , /* LCD_G3 */ , /* LCD_G4 */ , /* LCD_G5 */ , /* LCD_G6 */ , /* LCD_G7 */ , /* LCD_B0 */ , /* LCD_B1 */ , /* LCD_B2 */ , /* LCD_B3 */ , /* LCD_B4 */ , /* LCD_B5 */ , /* LCD_B6 */ ; /* LCD_B7 */ bias-disable; drive-push-pull; slew-rate = <1>; }; }; ltdc_pins_sleep_b: ltdc-b-1 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ , /* LCD_VSYNC */ , /* LCD_DE */ , /* LCD_R0 */ , /* LCD_R1 */ , /* LCD_R2 */ , /* LCD_R3 */ , /* LCD_R4 */ , /* LCD_R5 */ , /* LCD_R6 */ , /* LCD_R7 */ , /* LCD_G0 */ , /* LCD_G1 */ , /* LCD_G2 */ , /* LCD_G3 */ , /* LCD_G4 */ , /* LCD_G5 */ , /* LCD_G6 */ , /* LCD_G7 */ , /* LCD_B0 */ , /* LCD_B1 */ , /* LCD_B2 */ , /* LCD_B3 */ , /* LCD_B4 */ , /* LCD_B5 */ , /* LCD_B6 */ ; /* LCD_B7 */ }; }; m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ slew-rate = <1>; drive-push-pull; bias-disable; }; pins2 { pinmux = ; /* CAN1_RX */ bias-disable; }; }; m_can1_sleep_pins_a: m_can1-sleep-0 { pins { pinmux = , /* CAN1_TX */ ; /* CAN1_RX */ }; }; pwm1_pins_a: pwm1-0 { pins { pinmux = , /* TIM1_CH1 */ , /* TIM1_CH2 */ ; /* TIM1_CH4 */ bias-pull-down; drive-push-pull; slew-rate = <0>; }; }; pwm1_sleep_pins_a: pwm1-sleep-0 { pins { pinmux = , /* TIM1_CH1 */ , /* TIM1_CH2 */ ; /* TIM1_CH4 */ }; }; pwm2_pins_a: pwm2-0 { pins { pinmux = ; /* TIM2_CH4 */ bias-pull-down; drive-push-pull; slew-rate = <0>; }; }; pwm2_sleep_pins_a: pwm2-sleep-0 { pins { pinmux = ; /* TIM2_CH4 */ }; }; pwm3_pins_a: pwm3-0 { pins { pinmux = ; /* TIM3_CH2 */ bias-pull-down; drive-push-pull; slew-rate = <0>; }; }; pwm3_sleep_pins_a: pwm3-sleep-0 { pins { pinmux = ; /* TIM3_CH2 */ }; }; pwm4_pins_a: pwm4-0 { pins { pinmux = , /* TIM4_CH3 */ ; /* TIM4_CH4 */ bias-pull-down; drive-push-pull; slew-rate = <0>; }; }; pwm4_sleep_pins_a: pwm4-sleep-0 { pins { pinmux = , /* TIM4_CH3 */ ; /* TIM4_CH4 */ }; }; pwm4_pins_b: pwm4-1 { pins { pinmux = ; /* TIM4_CH2 */ bias-pull-down; drive-push-pull; slew-rate = <0>; }; }; pwm4_sleep_pins_b: pwm4-sleep-1 { pins { pinmux = ; /* TIM4_CH2 */ }; }; pwm5_pins_a: pwm5-0 { pins { pinmux = ; /* TIM5_CH2 */ bias-pull-down; drive-push-pull; slew-rate = <0>; }; }; pwm5_sleep_pins_a: pwm5-sleep-0 { pins { pinmux = ; /* TIM5_CH2 */ }; }; pwm8_pins_a: pwm8-0 { pins { pinmux = ; /* TIM8_CH4 */ bias-pull-down; drive-push-pull; slew-rate = <0>; }; }; pwm8_sleep_pins_a: pwm8-sleep-0 { pins { pinmux = ; /* TIM8_CH4 */ }; }; pwm12_pins_a: pwm12-0 { pins { pinmux = ; /* TIM12_CH1 */ bias-pull-down; drive-push-pull; slew-rate = <0>; }; }; pwm12_sleep_pins_a: pwm12-sleep-0 { pins { pinmux = ; /* TIM12_CH1 */ }; }; qspi_clk_pins_a: qspi-clk-0 { pins { pinmux = ; /* QSPI_CLK */ bias-disable; drive-push-pull; slew-rate = <3>; }; }; qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { pins { pinmux = ; /* QSPI_CLK */ }; }; qspi_bk1_pins_a: qspi-bk1-0 { pins1 { pinmux = , /* QSPI_BK1_IO0 */ , /* QSPI_BK1_IO1 */ , /* QSPI_BK1_IO2 */ ; /* QSPI_BK1_IO3 */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* QSPI_BK1_NCS */ bias-pull-up; drive-push-pull; slew-rate = <1>; }; }; qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { pins { pinmux = , /* QSPI_BK1_IO0 */ , /* QSPI_BK1_IO1 */ , /* QSPI_BK1_IO2 */ , /* QSPI_BK1_IO3 */ ; /* QSPI_BK1_NCS */ }; }; qspi_bk2_pins_a: qspi-bk2-0 { pins1 { pinmux = , /* QSPI_BK2_IO0 */ , /* QSPI_BK2_IO1 */ , /* QSPI_BK2_IO2 */ ; /* QSPI_BK2_IO3 */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* QSPI_BK2_NCS */ bias-pull-up; drive-push-pull; slew-rate = <1>; }; }; qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { pins { pinmux = , /* QSPI_BK2_IO0 */ , /* QSPI_BK2_IO1 */ , /* QSPI_BK2_IO2 */ , /* QSPI_BK2_IO3 */ ; /* QSPI_BK2_NCS */ }; }; sai2a_pins_a: sai2a-0 { pins { pinmux = , /* SAI2_SCK_A */ , /* SAI2_SD_A */ , /* SAI2_FS_A */ ; /* SAI2_MCLK_A */ slew-rate = <0>; drive-push-pull; bias-disable; }; }; sai2a_sleep_pins_a: sai2a-1 { pins { pinmux = , /* SAI2_SCK_A */ , /* SAI2_SD_A */ , /* SAI2_FS_A */ ; /* SAI2_MCLK_A */ }; }; sai2b_pins_a: sai2b-0 { pins1 { pinmux = , /* SAI2_SCK_B */ , /* SAI2_FS_B */ ; /* SAI2_MCLK_B */ slew-rate = <0>; drive-push-pull; bias-disable; }; pins2 { pinmux = ; /* SAI2_SD_B */ bias-disable; }; }; sai2b_sleep_pins_a: sai2b-1 { pins { pinmux = , /* SAI2_SD_B */ , /* SAI2_SCK_B */ , /* SAI2_FS_B */ ; /* SAI2_MCLK_B */ }; }; sai2b_pins_b: sai2b-2 { pins { pinmux = ; /* SAI2_SD_B */ bias-disable; }; }; sai2b_sleep_pins_b: sai2b-3 { pins { pinmux = ; /* SAI2_SD_B */ }; }; sai4a_pins_a: sai4a-0 { pins { pinmux = ; /* SAI4_SD_A */ slew-rate = <0>; drive-push-pull; bias-disable; }; }; sai4a_sleep_pins_a: sai4a-1 { pins { pinmux = ; /* SAI4_SD_A */ }; }; sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = , /* SDMMC1_D0 */ , /* SDMMC1_D1 */ , /* SDMMC1_D2 */ , /* SDMMC1_D3 */ ; /* SDMMC1_CMD */ slew-rate = <1>; drive-push-pull; bias-disable; }; pins2 { pinmux = ; /* SDMMC1_CK */ slew-rate = <2>; drive-push-pull; bias-disable; }; }; sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { pinmux = , /* SDMMC1_D0 */ , /* SDMMC1_D1 */ , /* SDMMC1_D2 */ ; /* SDMMC1_D3 */ slew-rate = <1>; drive-push-pull; bias-disable; }; pins2 { pinmux = ; /* SDMMC1_CK */ slew-rate = <2>; drive-push-pull; bias-disable; }; pins3 { pinmux = ; /* SDMMC1_CMD */ slew-rate = <1>; drive-open-drain; bias-disable; }; }; sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { pinmux = , /* SDMMC1_D0 */ , /* SDMMC1_D1 */ , /* SDMMC1_D2 */ , /* SDMMC1_D3 */ , /* SDMMC1_CK */ ; /* SDMMC1_CMD */ }; }; sdmmc1_dir_pins_a: sdmmc1-dir-0 { pins1 { pinmux = , /* SDMMC1_D0DIR */ , /* SDMMC1_D123DIR */ ; /* SDMMC1_CDIR */ slew-rate = <1>; drive-push-pull; bias-pull-up; }; pins2{ pinmux = ; /* SDMMC1_CKIN */ bias-pull-up; }; }; sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { pins { pinmux = , /* SDMMC1_D0DIR */ , /* SDMMC1_D123DIR */ , /* SDMMC1_CDIR */ ; /* SDMMC1_CKIN */ }; }; sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = , /* SDMMC2_D0 */ , /* SDMMC2_D1 */ , /* SDMMC2_D2 */ , /* SDMMC2_D3 */ ; /* SDMMC2_CMD */ slew-rate = <1>; drive-push-pull; bias-pull-up; }; pins2 { pinmux = ; /* SDMMC2_CK */ slew-rate = <2>; drive-push-pull; bias-pull-up; }; }; sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { pins1 { pinmux = , /* SDMMC2_D0 */ , /* SDMMC2_D1 */ , /* SDMMC2_D2 */ ; /* SDMMC2_D3 */ slew-rate = <1>; drive-push-pull; bias-pull-up; }; pins2 { pinmux = ; /* SDMMC2_CK */ slew-rate = <2>; drive-push-pull; bias-pull-up; }; pins3 { pinmux = ; /* SDMMC2_CMD */ slew-rate = <1>; drive-open-drain; bias-pull-up; }; }; sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { pins { pinmux = , /* SDMMC2_D0 */ , /* SDMMC2_D1 */ , /* SDMMC2_D2 */ , /* SDMMC2_D3 */ , /* SDMMC2_CK */ ; /* SDMMC2_CMD */ }; }; sdmmc2_b4_pins_b: sdmmc2-b4-1 { pins1 { pinmux = , /* SDMMC2_D0 */ , /* SDMMC2_D1 */ , /* SDMMC2_D2 */ , /* SDMMC2_D3 */ ; /* SDMMC2_CMD */ slew-rate = <1>; drive-push-pull; bias-disable; }; pins2 { pinmux = ; /* SDMMC2_CK */ slew-rate = <2>; drive-push-pull; bias-disable; }; }; sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { pins1 { pinmux = , /* SDMMC2_D0 */ , /* SDMMC2_D1 */ , /* SDMMC2_D2 */ ; /* SDMMC2_D3 */ slew-rate = <1>; drive-push-pull; bias-disable; }; pins2 { pinmux = ; /* SDMMC2_CK */ slew-rate = <2>; drive-push-pull; bias-disable; }; pins3 { pinmux = ; /* SDMMC2_CMD */ slew-rate = <1>; drive-open-drain; bias-disable; }; }; sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = , /* SDMMC2_D4 */ , /* SDMMC2_D5 */ , /* SDMMC2_D6 */ ; /* SDMMC2_D7 */ slew-rate = <1>; drive-push-pull; bias-pull-up; }; }; sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { pins { pinmux = , /* SDMMC2_D4 */ , /* SDMMC2_D5 */ , /* SDMMC2_D6 */ ; /* SDMMC2_D7 */ }; }; sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ , /* SDMMC3_D1 */ , /* SDMMC3_D2 */ , /* SDMMC3_D3 */ ; /* SDMMC3_CMD */ slew-rate = <1>; drive-push-pull; bias-pull-up; }; pins2 { pinmux = ; /* SDMMC3_CK */ slew-rate = <2>; drive-push-pull; bias-pull-up; }; }; sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { pins1 { pinmux = , /* SDMMC3_D0 */ , /* SDMMC3_D1 */ , /* SDMMC3_D2 */ ; /* SDMMC3_D3 */ slew-rate = <1>; drive-push-pull; bias-pull-up; }; pins2 { pinmux = ; /* SDMMC3_CK */ slew-rate = <2>; drive-push-pull; bias-pull-up; }; pins3 { pinmux = ; /* SDMMC2_CMD */ slew-rate = <1>; drive-open-drain; bias-pull-up; }; }; sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { pins { pinmux = , /* SDMMC3_D0 */ , /* SDMMC3_D1 */ , /* SDMMC3_D2 */ , /* SDMMC3_D3 */ , /* SDMMC3_CK */ ; /* SDMMC3_CMD */ }; }; spdifrx_pins_a: spdifrx-0 { pins { pinmux = ; /* SPDIF_IN1 */ bias-disable; }; }; spdifrx_sleep_pins_a: spdifrx-1 { pins { pinmux = ; /* SPDIF_IN1 */ }; }; uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { pinmux = ; /* UART4_RX */ bias-disable; }; }; uart4_pins_b: uart4-1 { pins1 { pinmux = ; /* UART4_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { pinmux = ; /* UART4_RX */ bias-disable; }; }; uart7_pins_a: uart7-0 { pins1 { pinmux = ; /* UART4_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { pinmux = , /* UART4_RX */ , /* UART4_CTS */ ; /* UART4_RTS */ bias-disable; }; }; }; pinctrl_z: pin-controller-z@54004000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; ranges = <0 0x54004000 0x400>; pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; gpioz: gpio@54004000 { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x400>; clocks = <&rcc GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; }; i2c2_pins_b2: i2c2-0 { pins { pinmux = ; /* I2C2_SCL */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; i2c2_pins_sleep_b2: i2c2-1 { pins { pinmux = ; /* I2C2_SCL */ }; }; i2c4_pins_a: i2c4-0 { pins { pinmux = , /* I2C4_SCL */ ; /* I2C4_SDA */ bias-disable; drive-open-drain; slew-rate = <0>; }; }; i2c4_pins_sleep_a: i2c4-1 { pins { pinmux = , /* I2C4_SCL */ ; /* I2C4_SDA */ }; }; spi1_pins_a: spi1-0 { pins1 { pinmux = , /* SPI1_SCK */ ; /* SPI1_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* SPI1_MISO */ bias-disable; }; }; }; }; };