// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP * Dong Aisheng */ /dts-v1/; #include "imx7ulp.dtsi" / { model = "NXP i.MX7ULP EVK"; compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; chosen { stdout-path = &lpuart4; }; memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; }; backlight { compatible = "pwm-backlight"; pwms = <&tpm4 1 50000 0>; brightness-levels = <0 20 25 30 35 40 100>; default-brightness-level = <6>; status = "okay"; }; reg_vsd_3v3: regulator-vsd-3v3 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc0_rst>; gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; &lpuart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart4>; status = "okay"; }; &tpm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0>; status = "okay"; }; &usdhc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc0>; cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; vmmc-supply = <®_vsd_3v3>; status = "okay"; }; &iomuxc1 { pinctrl_lpuart4: lpuart4grp { fsl,pins = < IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 >; bias-pull-up; }; pinctrl_pwm0: pwm0grp { fsl,pins = < IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 >; }; pinctrl_usdhc0: usdhc0grp { fsl,pins = < IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40 IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */ >; }; pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { fsl,pins = < IMX7ULP_PAD_PTD0__PTD0 0x3 >; }; };