/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	chosen {
		stdout-path = &uart1;
	};

	memory {
		reg = <0x10000000 0x40000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usb_otg_vbus: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "usb_otg_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio3 22 0>;
			enable-active-high;
			vin-supply = <&swbst_reg>;
		};

		reg_usb_h1_vbus: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "usb_h1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio1 29 0>;
			enable-active-high;
			vin-supply = <&swbst_reg>;
		};

		reg_audio: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "wm8962-supply";
			gpio = <&gpio4 10 0>;
			enable-active-high;
		};

		reg_pcie: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_pcie_reg>;
			regulator-name = "MPCIE_3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio3 19 0>;
			enable-active-high;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		power {
			label = "Power Button";
			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
			wakeup-source;
			linux,code = <KEY_POWER>;
		};

		volume-up {
			label = "Volume Up";
			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
			wakeup-source;
			linux,code = <KEY_VOLUMEUP>;
		};

		volume-down {
			label = "Volume Down";
			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
			wakeup-source;
			linux,code = <KEY_VOLUMEDOWN>;
		};
	};

	sound {
		compatible = "fsl,imx6q-sabresd-wm8962",
			   "fsl,imx-audio-wm8962";
		model = "wm8962-audio";
		ssi-controller = <&ssi2>;
		audio-codec = <&codec>;
		audio-routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"Ext Spk", "SPKOUTL",
			"Ext Spk", "SPKOUTR",
			"AMIC", "MICBIAS",
			"IN3R", "AMIC";
		mux-int-port = <2>;
		mux-ext-port = <3>;
	};

	backlight_lvds: backlight-lvds {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <7>;
		status = "okay";
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		red {
			gpios = <&gpio1 2 0>;
			default-state = "on";
		};
	};

	panel {
		compatible = "hannstar,hsd100pxn1";
		backlight = <&backlight_lvds>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&lvds0_out>;
			};
		};
	};
};

&ipu1_csi0_from_ipu1_csi0_mux {
	bus-width = <8>;
	data-shift = <12>; /* Lines 19:12 used */
	hsync-active = <1>;
	vsync-active = <1>;
};

&ipu1_csi0_mux_from_parallel_sensor {
	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
};

&ipu1_csi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ipu1_csi0>;
};

&mipi_csi {
	status = "okay";

	port@0 {
		reg = <0>;

		mipi_csi2_in: endpoint {
			remote-endpoint = <&ov5640_to_mipi_csi2>;
			clock-lanes = <0>;
			data-lanes = <1 2>;
		};
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};

&ecspi1 {
	cs-gpios = <&gpio4 9 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	status = "okay";

	flash: m25p80@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p32", "jedec,spi-nor";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_cec>;
	ddc-i2c-bus = <&i2c2>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	codec: wm8962@1a {
		compatible = "wlf,wm8962";
		reg = <0x1a>;
		clocks = <&clks IMX6QDL_CLK_CKO>;
		DCVDD-supply = <&reg_audio>;
		DBVDD-supply = <&reg_audio>;
		AVDD-supply = <&reg_audio>;
		CPVDD-supply = <&reg_audio>;
		MICVDD-supply = <&reg_audio>;
		PLLVDD-supply = <&reg_audio>;
		SPKVDD1-supply = <&reg_audio>;
		SPKVDD2-supply = <&reg_audio>;
		gpio-cfg = <
			0x0000 /* 0:Default */
			0x0000 /* 1:Default */
			0x0013 /* 2:FN_DMICCLK */
			0x0000 /* 3:Default */
			0x8014 /* 4:FN_DMICCDAT */
			0x0000 /* 5:Default */
		>;
	};

	ov5642: camera@3c {
		compatible = "ovti,ov5642";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ov5642>;
		clocks = <&clks IMX6QDL_CLK_CKO>;
		clock-names = "xclk";
		reg = <0x3c>;
		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
						rev B board is VGEN5 */
		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
		status = "disabled";

		port {
			ov5642_to_ipu1_csi0_mux: endpoint {
				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
				bus-width = <8>;
				hsync-active = <1>;
				vsync-active = <1>;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	ov5640: camera@3c {
		compatible = "ovti,ov5640";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ov5640>;
		reg = <0x3c>;
		clocks = <&clks IMX6QDL_CLK_CKO>;
		clock-names = "xclk";
		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
						rev B board is VGEN5 */
		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;

		port {
			#address-cells = <1>;
			#size-cells = <0>;

			ov5640_to_mipi_csi2: endpoint {
				remote-endpoint = <&mipi_csi2_in>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
			};
		};
	};

	pmic: pfuze100@08 {
		compatible = "fsl,pfuze100";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw3a_reg: sw3a {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3b_reg: sw3b {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	egalax_ts@04 {
		compatible = "eeti,egalax_ts";
		reg = <0x04>;
		interrupt-parent = <&gpio6>;
		interrupts = <7 2>;
		wakeup-gpios = <&gpio6 7 0>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx6qdl-sabresd {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
			>;
		};

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
			>;
		};

		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
				MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
				MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
				MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
			>;
		};

		pinctrl_gpio_keys: gpio_keysgrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
				MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
				MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
			>;
		};

		pinctrl_hdmi_cec: hdmicecgrp {
			fsl,pins = <
				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b8b1
				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b8b1
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
			>;
		};

		pinctrl_ipu1_csi0: ipu1csi0grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
			>;
		};

		pinctrl_ov5640: ov5640grp {
			fsl,pins = <
				MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
				MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
			>;
		};

		pinctrl_ov5642: ov5642grp {
			fsl,pins = <
				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
			>;
		};

		pinctrl_pcie: pciegrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b0
			>;
		};

		pinctrl_pcie_reg: pciereggrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D19__GPIO3_IO19	0x1b0b0
			>;
		};

		pinctrl_pwm1: pwm1grp {
			fsl,pins = <
				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
			>;
		};

		pinctrl_usdhc4: usdhc4grp {
			fsl,pins = <
				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
			>;
		};

		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
			>;
		};
	};

	gpio_leds {
		pinctrl_gpio_leds: gpioledsgrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
			>;
		};
	};
};

&ldb {
	status = "okay";

	lvds-channel@1 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		status = "okay";

		port@4 {
			reg = <4>;

			lvds0_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
	vpcie-supply = <&reg_pcie>;
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&reg_arm {
       vin-supply = <&sw1a_reg>;
};

&reg_pu {
       vin-supply = <&sw1c_reg>;
};

&reg_soc {
       vin-supply = <&sw1c_reg>;
};

&snvs_poweroff {
	status = "okay";
};

&ssi2 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usbh1 {
	vbus-supply = <&reg_usb_h1_vbus>;
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <8>;
	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	bus-width = <8>;
	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	status = "okay";
};

&wdog1 {
	status = "disabled";
};

&wdog2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};