From c4df37fe186de4df8895a7a4793f5221eda6e5ae Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 30 Nov 2020 15:09:24 +0530 Subject: soc: qcom: llcc-qcom: Add support for SM8250 SoC SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN register needs to be written to enable the Write Sub Cache for each SCID. Hence, use a dedicated "write_scid_en" member with predefined values and write them for LLCC IP version 2. Reviewed-by: Sai Prakash Ranjan Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20201130093924.45057-5-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- include/linux/soc/qcom/llcc-qcom.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/soc') diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index d17a3de80510..64fc582ae415 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -29,6 +29,7 @@ #define LLCC_AUDHW 22 #define LLCC_NPU 23 #define LLCC_WLHW 24 +#define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30 #define LLCC_WRCACHE 31 -- cgit v1.2.3