From c822584e27911c5af089a366cb5eca378a1cd5ea Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Mon, 19 Oct 2020 07:31:14 +0800 Subject: drm/mediatek: Get CMDQ client register for all ddp component Only OVL, RDMA,and WDMA get CMDQ client register information, but all ddp component should work with CMDQ, so get this information for all ddp component. Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 3064eac1a750..cab53431ceec 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -506,6 +506,21 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, if (IS_ERR(comp->clk)) return PTR_ERR(comp->clk); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (of_address_to_resource(node, 0, &res) != 0) { + dev_err(dev, "Missing reg in %s node\n", node->full_name); + put_device(&larb_pdev->dev); + return -EINVAL; + } + comp->regs_pa = res.start; + + ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); + else + comp->subsys = cmdq_reg.subsys; +#endif + /* Only DMA capable components need the LARB property */ comp->larb_dev = NULL; if (type != MTK_DISP_OVL && @@ -531,20 +546,6 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, comp->larb_dev = &larb_pdev->dev; -#if IS_REACHABLE(CONFIG_MTK_CMDQ) - if (of_address_to_resource(node, 0, &res) != 0) { - dev_err(dev, "Missing reg in %s node\n", node->full_name); - put_device(&larb_pdev->dev); - return -EINVAL; - } - comp->regs_pa = res.start; - - ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0); - if (ret) - dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); - else - comp->subsys = cmdq_reg.subsys; -#endif return 0; } -- cgit v1.2.3 From 6ea6f8276725dc60cf8fe9a023b5f2c4cbb673a3 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Mon, 19 Oct 2020 08:15:22 +0800 Subject: drm/mediatek: Use correct device pointer to get CMDQ client register Some ddp component use mmsys device pointer to get CMDQ client register, this would get mmsys' CMDQ client register, so use each ddp component's device pointer to get. Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +++++++++++---- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 5 ++--- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- drivers/gpu/drm/mediatek/mtk_dsi.c | 2 +- 8 files changed, 19 insertions(+), 13 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index 6048cbc9f0ec..6ee4515dc272 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -118,7 +118,7 @@ static int mtk_disp_color_probe(struct platform_device *pdev) return comp_id; } - ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, + ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id, &mtk_disp_color_funcs); if (ret) { if (ret != -EPROBE_DEFER) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 74ef6fc0528b..f8e99d67132d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -384,7 +384,7 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) return comp_id; } - ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, + ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id, &mtk_disp_ovl_funcs); if (ret) { if (ret != -EPROBE_DEFER) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index d46b8ae1d080..a3c487ea8344 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -292,7 +292,7 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return comp_id; } - ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, + ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id, &mtk_disp_rdma_funcs); if (ret) { if (ret != -EPROBE_DEFER) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 52f11a63a330..81b43b640d45 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -775,7 +775,7 @@ static int mtk_dpi_probe(struct platform_device *pdev) return comp_id; } - ret = mtk_ddp_comp_init(dev, dev->of_node, &dpi->ddp_comp, comp_id, + ret = mtk_ddp_comp_init(dev->of_node, &dpi->ddp_comp, comp_id, &mtk_dpi_funcs); if (ret) { dev_err(dev, "Failed to initialize component: %d\n", ret); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index cab53431ceec..1730b3ddef70 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -465,10 +465,11 @@ unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, return ret; } -int mtk_ddp_comp_init(struct device *dev, struct device_node *node, - struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, - const struct mtk_ddp_comp_funcs *funcs) +int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, + enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs) { + struct platform_device *comp_pdev; + struct device *dev; enum mtk_ddp_comp_type type; struct device_node *larb_node; struct platform_device *larb_pdev; @@ -506,10 +507,16 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, if (IS_ERR(comp->clk)) return PTR_ERR(comp->clk); + comp_pdev = of_find_device_by_node(node); + if (!comp_pdev) { + DRM_INFO("Waiting for device %s\n", node->full_name); + return -EPROBE_DEFER; + } + dev = &comp_pdev->dev; + #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (of_address_to_resource(node, 0, &res) != 0) { dev_err(dev, "Missing reg in %s node\n", node->full_name); - put_device(&larb_pdev->dev); return -EINVAL; } comp->regs_pa = res.start; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 5aa52b7afeec..6353f050fdf5 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -172,9 +172,8 @@ int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type); unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, struct mtk_ddp_comp ddp_comp); -int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, - struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, - const struct mtk_ddp_comp_funcs *funcs); +int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp, + enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs); int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp); void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp); void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 2f717df28a77..221aac9d1f66 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -512,7 +512,7 @@ static int mtk_drm_probe(struct platform_device *pdev) goto err_node; } - ret = mtk_ddp_comp_init(dev->parent, node, comp, + ret = mtk_ddp_comp_init(node, comp, comp_id, NULL); if (ret) { of_node_put(node); diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 65fd99c528af..a71cf1f52f8b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1097,7 +1097,7 @@ static int mtk_dsi_probe(struct platform_device *pdev) goto err_unregister_host; } - ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id, + ret = mtk_ddp_comp_init(dev->of_node, &dsi->ddp_comp, comp_id, &mtk_dsi_funcs); if (ret) { dev_err(dev, "Failed to initialize component: %d\n", ret); -- cgit v1.2.3 From 926df14ec571f6cdbf6d941a0f1be112bf7a7535 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Tue, 17 Nov 2020 15:55:26 +0800 Subject: drm/mediatek: Separate getting larb device to a function To make the code cleaner, separate getting larb device to a function. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 ++++++++++++++++------------- 1 file changed, 32 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 1730b3ddef70..a11b4f8bf959 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -465,19 +465,41 @@ unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, return ret; } +static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *comp, + struct device *dev) +{ + struct device_node *larb_node; + struct platform_device *larb_pdev; + + larb_node = of_parse_phandle(node, "mediatek,larb", 0); + if (!larb_node) { + dev_err(dev, "Missing mediadek,larb phandle in %pOF node\n", node); + return -EINVAL; + } + + larb_pdev = of_find_device_by_node(larb_node); + if (!larb_pdev) { + dev_warn(dev, "Waiting for larb device %pOF\n", larb_node); + of_node_put(larb_node); + return -EPROBE_DEFER; + } + of_node_put(larb_node); + comp->larb_dev = &larb_pdev->dev; + + return 0; +} + int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs) { struct platform_device *comp_pdev; struct device *dev; enum mtk_ddp_comp_type type; - struct device_node *larb_node; - struct platform_device *larb_pdev; #if IS_REACHABLE(CONFIG_MTK_CMDQ) struct resource res; struct cmdq_client_reg cmdq_reg; - int ret; #endif + int ret; if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) return -EINVAL; @@ -529,30 +551,15 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, #endif /* Only DMA capable components need the LARB property */ - comp->larb_dev = NULL; - if (type != MTK_DISP_OVL && - type != MTK_DISP_OVL_2L && - type != MTK_DISP_RDMA && - type != MTK_DISP_WDMA) - return 0; - - larb_node = of_parse_phandle(node, "mediatek,larb", 0); - if (!larb_node) { - dev_err(dev, - "Missing mediadek,larb phandle in %pOF node\n", node); - return -EINVAL; + if (type == MTK_DISP_OVL || + type == MTK_DISP_OVL_2L || + type == MTK_DISP_RDMA || + type == MTK_DISP_WDMA) { + ret = mtk_ddp_get_larb_dev(node, comp, dev); + if (ret) + return ret; } - larb_pdev = of_find_device_by_node(larb_node); - if (!larb_pdev) { - dev_warn(dev, "Waiting for larb device %pOF\n", larb_node); - of_node_put(larb_node); - return -EPROBE_DEFER; - } - of_node_put(larb_node); - - comp->larb_dev = &larb_pdev->dev; - return 0; } -- cgit v1.2.3 From c0d36de868a6834f0124d248ac5c313d3c4d90bf Mon Sep 17 00:00:00 2001 From: CK Hu Date: Fri, 28 Aug 2020 13:37:06 +0800 Subject: drm/mediatek: Move clk info from struct mtk_ddp_comp to sub driver private data Some ddp component exist in both display path and other path, so data belonged to sub driver should be moved into sub driver private data so it could be used for multiple path. clk info is one of sub driver data, so move it. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 23 +++++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23 +++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 23 +++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 6 +-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 63 ++++++++++++++++++++++++----- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 18 ++++++++- 6 files changed, 141 insertions(+), 15 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index 6ee4515dc272..7556976cd461 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -38,6 +38,7 @@ struct mtk_disp_color_data { struct mtk_disp_color { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; + struct clk *clk; const struct mtk_disp_color_data *data; }; @@ -46,6 +47,20 @@ static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp) return container_of(comp, struct mtk_disp_color, ddp_comp); } +static int mtk_color_clk_enable(struct device *dev) +{ + struct mtk_disp_color *color = dev_get_drvdata(dev); + + return clk_prepare_enable(color->clk); +} + +static void mtk_color_clk_disable(struct device *dev) +{ + struct mtk_disp_color *color = dev_get_drvdata(dev); + + clk_disable_unprepare(color->clk); +} + static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -66,6 +81,8 @@ static void mtk_color_start(struct mtk_ddp_comp *comp) } static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = { + .clk_enable = mtk_color_clk_enable, + .clk_disable = mtk_color_clk_disable, .config = mtk_color_config, .start = mtk_color_start, }; @@ -112,6 +129,12 @@ static int mtk_disp_color_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get color clk\n"); + return PTR_ERR(priv->clk); + } + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_COLOR); if (comp_id < 0) { dev_err(dev, "Failed to identify by alias: %d\n", comp_id); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index f8e99d67132d..589c33937793 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -72,6 +72,7 @@ struct mtk_disp_ovl_data { struct mtk_disp_ovl { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; + struct clk *clk; const struct mtk_disp_ovl_data *data; }; @@ -114,6 +115,20 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN); } +static int mtk_ovl_clk_enable(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return clk_prepare_enable(ovl->clk); +} + +static void mtk_ovl_clk_disable(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + clk_disable_unprepare(ovl->clk); +} + static void mtk_ovl_start(struct mtk_ddp_comp *comp) { writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN); @@ -313,6 +328,8 @@ static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp) } static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { + .clk_enable = mtk_ovl_clk_enable, + .clk_disable = mtk_ovl_clk_disable, .config = mtk_ovl_config, .start = mtk_ovl_start, .stop = mtk_ovl_stop, @@ -373,6 +390,12 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) if (irq < 0) return irq; + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get ovl clk\n"); + return PTR_ERR(priv->clk); + } + priv->data = of_device_get_match_data(dev); comp_id = mtk_ddp_comp_get_id(dev->of_node, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index a3c487ea8344..95feacda49b1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -63,6 +63,7 @@ struct mtk_disp_rdma_data { struct mtk_disp_rdma { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; + struct clk *clk; const struct mtk_disp_rdma_data *data; }; @@ -114,6 +115,20 @@ static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp) rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); } +static int mtk_rdma_clk_enable(struct device *dev) +{ + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); + + return clk_prepare_enable(rdma->clk); +} + +static void mtk_rdma_clk_disable(struct device *dev) +{ + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); + + clk_disable_unprepare(rdma->clk); +} + static void mtk_rdma_start(struct mtk_ddp_comp *comp) { rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, @@ -229,6 +244,8 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, } static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { + .clk_enable = mtk_rdma_clk_enable, + .clk_disable = mtk_rdma_clk_disable, .config = mtk_rdma_config, .start = mtk_rdma_start, .stop = mtk_rdma_stop, @@ -286,6 +303,12 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) if (irq < 0) return irq; + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get rdma clk\n"); + return PTR_ERR(priv->clk); + } + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA); if (comp_id < 0) { dev_err(dev, "Failed to identify by alias: %d\n", comp_id); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index bdd37eadecd5..c08ebfc5fb24 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -193,7 +193,7 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) int i; for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { - ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); + ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]); if (ret) { DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); goto err; @@ -203,7 +203,7 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) return 0; err: while (--i >= 0) - clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); + mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); return ret; } @@ -212,7 +212,7 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) int i; for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) - clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); + mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); } static diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index a11b4f8bf959..9ed0d38830df 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -86,6 +86,10 @@ #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0) +struct mtk_ddp_comp_dev { + struct clk *clk; +}; + void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, struct mtk_ddp_comp *comp, unsigned int offset) { @@ -132,6 +136,20 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, #endif } +static int mtk_ddp_clk_enable(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + return clk_prepare_enable(priv->clk); +} + +static void mtk_ddp_clk_disable(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); +} + void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int CFG, struct cmdq_pkt *cmdq_pkt) { @@ -322,6 +340,8 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp, } static const struct mtk_ddp_comp_funcs ddp_aal = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, .gamma_set = mtk_gamma_set, .config = mtk_aal_config, .start = mtk_aal_start, @@ -329,6 +349,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { }; static const struct mtk_ddp_comp_funcs ddp_ccorr = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, .config = mtk_ccorr_config, .start = mtk_ccorr_start, .stop = mtk_ccorr_stop, @@ -336,12 +358,16 @@ static const struct mtk_ddp_comp_funcs ddp_ccorr = { }; static const struct mtk_ddp_comp_funcs ddp_dither = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, .config = mtk_dither_config, .start = mtk_dither_start, .stop = mtk_dither_stop, }; static const struct mtk_ddp_comp_funcs ddp_gamma = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, .gamma_set = mtk_gamma_set, .config = mtk_gamma_config, .start = mtk_gamma_start, @@ -349,11 +375,15 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = { }; static const struct mtk_ddp_comp_funcs ddp_od = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, .config = mtk_od_config, .start = mtk_od_start, }; static const struct mtk_ddp_comp_funcs ddp_ufoe = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, .start = mtk_ufoe_start, }; @@ -493,8 +523,8 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs) { struct platform_device *comp_pdev; - struct device *dev; enum mtk_ddp_comp_type type; + struct mtk_ddp_comp_dev *priv; #if IS_REACHABLE(CONFIG_MTK_CMDQ) struct resource res; struct cmdq_client_reg cmdq_reg; @@ -518,34 +548,29 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, comp_id == DDP_COMPONENT_DSI3 || comp_id == DDP_COMPONENT_PWM0) { comp->regs = NULL; - comp->clk = NULL; comp->irq = 0; return 0; } comp->regs = of_iomap(node, 0); comp->irq = of_irq_get(node, 0); - comp->clk = of_clk_get(node, 0); - if (IS_ERR(comp->clk)) - return PTR_ERR(comp->clk); - comp_pdev = of_find_device_by_node(node); if (!comp_pdev) { DRM_INFO("Waiting for device %s\n", node->full_name); return -EPROBE_DEFER; } - dev = &comp_pdev->dev; + comp->dev = &comp_pdev->dev; #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (of_address_to_resource(node, 0, &res) != 0) { - dev_err(dev, "Missing reg in %s node\n", node->full_name); + dev_err(comp->dev, "Missing reg in %s node\n", node->full_name); return -EINVAL; } comp->regs_pa = res.start; - ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0); + ret = cmdq_dev_get_client_reg(comp->dev, &cmdq_reg, 0); if (ret) - dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); + dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n"); else comp->subsys = cmdq_reg.subsys; #endif @@ -555,11 +580,27 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, type == MTK_DISP_OVL_2L || type == MTK_DISP_RDMA || type == MTK_DISP_WDMA) { - ret = mtk_ddp_get_larb_dev(node, comp, dev); + ret = mtk_ddp_get_larb_dev(node, comp, comp->dev); if (ret) return ret; } + if (type == MTK_DISP_COLOR || + type == MTK_DISP_OVL || + type == MTK_DISP_OVL_2L || + type == MTK_DISP_RDMA) + return 0; + + priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = of_clk_get(node, 0); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + platform_set_drvdata(comp_pdev, priv); + return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 6353f050fdf5..89308192a384 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -39,6 +39,8 @@ enum mtk_ddp_comp_type { struct mtk_ddp_comp; struct cmdq_pkt; struct mtk_ddp_comp_funcs { + int (*clk_enable)(struct device *dev); + void (*clk_disable)(struct device *dev); void (*config)(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); @@ -63,7 +65,7 @@ struct mtk_ddp_comp_funcs { }; struct mtk_ddp_comp { - struct clk *clk; + struct device *dev; void __iomem *regs; int irq; struct device *larb_dev; @@ -73,6 +75,20 @@ struct mtk_ddp_comp { u8 subsys; }; +static inline int mtk_ddp_comp_clk_enable(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->clk_enable) + return comp->funcs->clk_enable(comp->dev); + + return 0; +} + +static inline void mtk_ddp_comp_clk_disable(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->clk_disable) + comp->funcs->clk_disable(comp->dev); +} + static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, -- cgit v1.2.3 From 3c87daefc5c3637bed36f1f29dc9bbf3506cba55 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Fri, 28 Aug 2020 16:13:13 +0800 Subject: drm/mediatek: Move regs info from struct mtk_ddp_comp to sub driver private data Some ddp component exist in both display path and other path, so data belonged to sub driver should be moved into sub driver private data so it could be used for multiple path. regs info is one of sub driver data, so move it. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 17 +++- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 67 +++++++++------ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 42 ++++++---- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 121 ++++++++++++++++++---------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 11 +-- 5 files changed, 165 insertions(+), 93 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index 7556976cd461..93863dbfb761 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -39,6 +39,7 @@ struct mtk_disp_color { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; struct clk *clk; + void __iomem *regs; const struct mtk_disp_color_data *data; }; @@ -67,8 +68,8 @@ static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, { struct mtk_disp_color *color = comp_to_color(comp); - mtk_ddp_write(cmdq_pkt, w, comp, DISP_COLOR_WIDTH(color)); - mtk_ddp_write(cmdq_pkt, h, comp, DISP_COLOR_HEIGHT(color)); + mtk_ddp_write(cmdq_pkt, w, comp, color->regs, DISP_COLOR_WIDTH(color)); + mtk_ddp_write(cmdq_pkt, h, comp, color->regs, DISP_COLOR_HEIGHT(color)); } static void mtk_color_start(struct mtk_ddp_comp *comp) @@ -76,8 +77,8 @@ static void mtk_color_start(struct mtk_ddp_comp *comp) struct mtk_disp_color *color = comp_to_color(comp); writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL, - comp->regs + DISP_COLOR_CFG_MAIN); - writel(0x1, comp->regs + DISP_COLOR_START(color)); + color->regs + DISP_COLOR_CFG_MAIN); + writel(0x1, color->regs + DISP_COLOR_START(color)); } static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = { @@ -122,6 +123,7 @@ static int mtk_disp_color_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_disp_color *priv; + struct resource *res; int comp_id; int ret; @@ -135,6 +137,13 @@ static int mtk_disp_color_probe(struct platform_device *pdev) return PTR_ERR(priv->clk); } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap color\n"); + return PTR_ERR(priv->regs); + } + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_COLOR); if (comp_id < 0) { dev_err(dev, "Failed to identify by alias: %d\n", comp_id); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 589c33937793..90a78db0e96b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -73,6 +73,7 @@ struct mtk_disp_ovl { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; struct clk *clk; + void __iomem *regs; const struct mtk_disp_ovl_data *data; }; @@ -87,7 +88,7 @@ static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) struct mtk_ddp_comp *ovl = &priv->ddp_comp; /* Clear frame completion interrupt */ - writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); + writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); if (!priv->crtc) return IRQ_NONE; @@ -103,8 +104,8 @@ static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, struct mtk_disp_ovl *ovl = comp_to_ovl(comp); ovl->crtc = crtc; - writel(0x0, comp->regs + DISP_REG_OVL_INTSTA); - writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN); + writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); + writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); } static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) @@ -112,7 +113,7 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) struct mtk_disp_ovl *ovl = comp_to_ovl(comp); ovl->crtc = NULL; - writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN); + writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } static int mtk_ovl_clk_enable(struct device *dev) @@ -131,25 +132,31 @@ static void mtk_ovl_clk_disable(struct device *dev) static void mtk_ovl_start(struct mtk_ddp_comp *comp) { - writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN); + struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); + + writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); } static void mtk_ovl_stop(struct mtk_ddp_comp *comp) { - writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN); + struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); + + writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); } static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { + struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); + if (w != 0 && h != 0) - mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp, + mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp, ovl->regs, DISP_REG_OVL_ROI_SIZE); - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR); + mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, ovl->regs, DISP_REG_OVL_ROI_BGCLR); - mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST); - mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST); + mtk_ddp_write(cmdq_pkt, 0x1, comp, ovl->regs, DISP_REG_OVL_RST); + mtk_ddp_write(cmdq_pkt, 0x0, comp, ovl->regs, DISP_REG_OVL_RST); } static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) @@ -201,7 +208,7 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int gmc_value; struct mtk_disp_ovl *ovl = comp_to_ovl(comp); - mtk_ddp_write(cmdq_pkt, 0x1, comp, + mtk_ddp_write(cmdq_pkt, 0x1, comp, ovl->regs, DISP_REG_OVL_RDMA_CTRL(idx)); gmc_thrshd_l = GMC_THRESHOLD_LOW >> (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); @@ -213,17 +220,19 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx, gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | gmc_thrshd_h << 16 | gmc_thrshd_h << 24; mtk_ddp_write(cmdq_pkt, gmc_value, - comp, DISP_REG_OVL_RDMA_GMC(idx)); - mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp, + comp, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp, ovl->regs, DISP_REG_OVL_SRC_CON, BIT(idx)); } static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx, struct cmdq_pkt *cmdq_pkt) { - mtk_ddp_write_mask(cmdq_pkt, 0, comp, + struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); + + mtk_ddp_write_mask(cmdq_pkt, 0, comp, ovl->regs, DISP_REG_OVL_SRC_CON, BIT(idx)); - mtk_ddp_write(cmdq_pkt, 0, comp, + mtk_ddp_write(cmdq_pkt, 0, comp, ovl->regs, DISP_REG_OVL_RDMA_CTRL(idx)); } @@ -295,15 +304,15 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, addr += pending->pitch - 1; } - mtk_ddp_write_relaxed(cmdq_pkt, con, comp, + mtk_ddp_write_relaxed(cmdq_pkt, con, comp, ovl->regs, DISP_REG_OVL_CON(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, ovl->regs, DISP_REG_OVL_PITCH(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp, + mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, offset, comp, + mtk_ddp_write_relaxed(cmdq_pkt, offset, comp, ovl->regs, DISP_REG_OVL_OFFSET(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, ovl->regs, DISP_REG_OVL_ADDR(ovl, idx)); mtk_ovl_layer_on(comp, idx, cmdq_pkt); @@ -311,20 +320,22 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp) { + struct mtk_disp_ovl *ovl = comp_to_ovl(comp); unsigned int reg; - reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON); + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); reg = reg | OVL_BGCLR_SEL_IN; - writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON); + writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); } static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp) { + struct mtk_disp_ovl *ovl = comp_to_ovl(comp); unsigned int reg; - reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON); + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); reg = reg & ~OVL_BGCLR_SEL_IN; - writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON); + writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); } static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { @@ -378,6 +389,7 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_disp_ovl *priv; + struct resource *res; int comp_id; int irq; int ret; @@ -396,6 +408,13 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) return PTR_ERR(priv->clk); } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap ovl\n"); + return PTR_ERR(priv->regs); + } + priv->data = of_device_get_match_data(dev); comp_id = mtk_ddp_comp_get_id(dev->of_node, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 95feacda49b1..1057c7a42ff2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -64,6 +64,7 @@ struct mtk_disp_rdma { struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; struct clk *clk; + void __iomem *regs; const struct mtk_disp_rdma_data *data; }; @@ -78,7 +79,7 @@ static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) struct mtk_ddp_comp *rdma = &priv->ddp_comp; /* Clear frame completion interrupt */ - writel(0x0, rdma->regs + DISP_REG_RDMA_INT_STATUS); + writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); if (!priv->crtc) return IRQ_NONE; @@ -91,10 +92,11 @@ static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg, unsigned int mask, unsigned int val) { - unsigned int tmp = readl(comp->regs + reg); + struct mtk_disp_rdma *rdma = dev_get_drvdata(comp->dev); + unsigned int tmp = readl(rdma->regs + reg); tmp = (tmp & ~mask) | (val & mask); - writel(tmp, comp->regs + reg); + writel(tmp, rdma->regs + reg); } static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp, @@ -148,9 +150,9 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); - mtk_ddp_write_mask(cmdq_pkt, width, comp, + mtk_ddp_write_mask(cmdq_pkt, width, comp, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, 0xfff); - mtk_ddp_write_mask(cmdq_pkt, height, comp, + mtk_ddp_write_mask(cmdq_pkt, height, comp, rdma->regs, DISP_REG_RDMA_SIZE_CON_1, 0xfffff); /* @@ -163,7 +165,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); - mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); + mtk_ddp_write(cmdq_pkt, reg, comp, rdma->regs, DISP_REG_RDMA_FIFO_CON); } static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, @@ -220,25 +222,25 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int con; con = rdma_fmt_convert(rdma, fmt); - mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON); + mtk_ddp_write_relaxed(cmdq_pkt, con, comp, rdma->regs, DISP_RDMA_MEM_CON); if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { - mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp, + mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, RDMA_MATRIX_ENABLE); mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, - comp, DISP_REG_RDMA_SIZE_CON_0, + comp, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, RDMA_MATRIX_INT_MTX_SEL); } else { - mtk_ddp_write_mask(cmdq_pkt, 0, comp, + mtk_ddp_write_mask(cmdq_pkt, 0, comp, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, RDMA_MATRIX_ENABLE); } - mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR); - mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH); - mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp, + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, rdma->regs, DISP_RDMA_MEM_START_ADDR); + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, rdma->regs, DISP_RDMA_MEM_SRC_PITCH); + mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp, rdma->regs, DISP_RDMA_MEM_GMC_SETTING_0); - mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp, + mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp, rdma->regs, DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY); } @@ -291,6 +293,7 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_disp_rdma *priv; + struct resource *res; int comp_id; int irq; int ret; @@ -309,6 +312,13 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return PTR_ERR(priv->clk); } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap rdma\n"); + return PTR_ERR(priv->regs); + } + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA); if (comp_id < 0) { dev_err(dev, "Failed to identify by alias: %d\n", comp_id); @@ -326,8 +336,8 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) } /* Disable and clear pending interrupts */ - writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_ENABLE); - writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_STATUS); + writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE); + writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler, IRQF_TRIGGER_NONE, dev_name(dev), priv); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 9ed0d38830df..eaca3b930c5b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -88,10 +88,12 @@ struct mtk_ddp_comp_dev { struct clk *clk; + void __iomem *regs; }; void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, unsigned int offset) + struct mtk_ddp_comp *comp, void __iomem *regs, + unsigned int offset) { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) @@ -99,11 +101,11 @@ void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, comp->regs_pa + offset, value); else #endif - writel(value, comp->regs + offset); + writel(value, regs + offset); } void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, + struct mtk_ddp_comp *comp, void __iomem *regs, unsigned int offset) { #if IS_REACHABLE(CONFIG_MTK_CMDQ) @@ -112,14 +114,12 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, comp->regs_pa + offset, value); else #endif - writel_relaxed(value, comp->regs + offset); + writel_relaxed(value, regs + offset); } -void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, - unsigned int value, - struct mtk_ddp_comp *comp, - unsigned int offset, - unsigned int mask) +void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, void __iomem *regs, + unsigned int offset, unsigned int mask) { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) { @@ -127,10 +127,10 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, comp->regs_pa + offset, value, mask); } else { #endif - u32 tmp = readl(comp->regs + offset); + u32 tmp = readl(regs + offset); tmp = (tmp & ~mask) | (value & mask); - writel(tmp, comp->regs + offset); + writel(tmp, regs + offset); #if IS_REACHABLE(CONFIG_MTK_CMDQ) } #endif @@ -153,25 +153,27 @@ static void mtk_ddp_clk_disable(struct device *dev) void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int CFG, struct cmdq_pkt *cmdq_pkt) { + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + /* If bpc equal to 0, the dithering function didn't be enabled */ if (bpc == 0) return; if (bpc >= MTK_MIN_BPC) { - mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); - mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); + mtk_ddp_write(cmdq_pkt, 0, comp, priv->regs, DISP_DITHER_5); + mtk_ddp_write(cmdq_pkt, 0, comp, priv->regs, DISP_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | DITHER_NEW_BIT_MODE, - comp, DISP_DITHER_15); + comp, priv->regs, DISP_DITHER_15); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), - comp, DISP_DITHER_16); - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); + comp, priv->regs, DISP_DITHER_16); + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, priv->regs, CFG); } } @@ -179,54 +181,72 @@ static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE); - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, priv->regs, DISP_OD_SIZE); + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, priv->regs, DISP_OD_CFG); mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt); } static void mtk_od_start(struct mtk_ddp_comp *comp) { - writel(1, comp->regs + DISP_OD_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel(1, priv->regs + DISP_OD_EN); } static void mtk_ufoe_start(struct mtk_ddp_comp *comp) { - writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); } static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_AAL_SIZE); } static void mtk_aal_start(struct mtk_ddp_comp *comp) { - writel(AAL_EN, comp->regs + DISP_AAL_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel(AAL_EN, priv->regs + DISP_AAL_EN); } static void mtk_aal_stop(struct mtk_ddp_comp *comp) { - writel_relaxed(0x0, comp->regs + DISP_AAL_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel_relaxed(0x0, priv->regs + DISP_AAL_EN); } static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE); - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, priv->regs, DISP_CCORR_CFG); } static void mtk_ccorr_start(struct mtk_ddp_comp *comp) { - writel(CCORR_EN, comp->regs + DISP_CCORR_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel(CCORR_EN, priv->regs + DISP_CCORR_EN); } static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) { - writel_relaxed(0x0, comp->regs + DISP_CCORR_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); } /* Converts a DRM S31.32 value to the HW S1.10 format. */ @@ -252,6 +272,7 @@ static u16 mtk_ctm_s31_32_to_s1_10(u64 in) static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); struct drm_property_blob *blob = state->ctm; struct drm_color_ctm *ctm; const u64 *input; @@ -269,66 +290,79 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], - comp, DISP_CCORR_COEF_0); + comp, priv->regs, DISP_CCORR_COEF_0); mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], - comp, DISP_CCORR_COEF_1); + comp, priv->regs, DISP_CCORR_COEF_1); mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], - comp, DISP_CCORR_COEF_2); + comp, priv->regs, DISP_CCORR_COEF_2); mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], - comp, DISP_CCORR_COEF_3); + comp, priv->regs, DISP_CCORR_COEF_3); mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, - comp, DISP_CCORR_COEF_4); + comp, priv->regs, DISP_CCORR_COEF_4); } static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE); - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_DITHER_SIZE); + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, priv->regs, DISP_DITHER_CFG); } static void mtk_dither_start(struct mtk_ddp_comp *comp) { - writel(DITHER_EN, comp->regs + DISP_DITHER_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel(DITHER_EN, priv->regs + DISP_DITHER_EN); } static void mtk_dither_stop(struct mtk_ddp_comp *comp) { - writel_relaxed(0x0, comp->regs + DISP_DITHER_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel_relaxed(0x0, priv->regs + DISP_DITHER_EN); } static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_GAMMA_SIZE); mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt); } static void mtk_gamma_start(struct mtk_ddp_comp *comp) { - writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel(GAMMA_EN, priv->regs + DISP_GAMMA_EN); } static void mtk_gamma_stop(struct mtk_ddp_comp *comp) { - writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + + writel_relaxed(0x0, priv->regs + DISP_GAMMA_EN); } static void mtk_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; u32 word; if (state->gamma_lut) { - reg = readl(comp->regs + DISP_GAMMA_CFG); + reg = readl(priv->regs + DISP_GAMMA_CFG); reg = reg | GAMMA_LUT_EN; - writel(reg, comp->regs + DISP_GAMMA_CFG); - lut_base = comp->regs + DISP_GAMMA_LUT; + writel(reg, priv->regs + DISP_GAMMA_CFG); + lut_base = priv->regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; for (i = 0; i < MTK_LUT_SIZE; i++) { word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + @@ -547,12 +581,10 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, comp_id == DDP_COMPONENT_DSI2 || comp_id == DDP_COMPONENT_DSI3 || comp_id == DDP_COMPONENT_PWM0) { - comp->regs = NULL; comp->irq = 0; return 0; } - comp->regs = of_iomap(node, 0); comp->irq = of_irq_get(node, 0); comp_pdev = of_find_device_by_node(node); if (!comp_pdev) { @@ -595,6 +627,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (!priv) return -ENOMEM; + priv->regs = of_iomap(node, 0); priv->clk = of_clk_get(node, 0); if (IS_ERR(priv->clk)) return PTR_ERR(priv->clk); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 89308192a384..2b201cc5cbc3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -66,7 +66,6 @@ struct mtk_ddp_comp_funcs { struct mtk_ddp_comp { struct device *dev; - void __iomem *regs; int irq; struct device *larb_dev; enum mtk_ddp_comp_id id; @@ -196,10 +195,12 @@ void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int CFG, struct cmdq_pkt *cmdq_pkt); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, unsigned int offset); + struct mtk_ddp_comp *comp, void __iomem *regs, + unsigned int offset); void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, unsigned int offset); + struct mtk_ddp_comp *comp, void __iomem *regs, + unsigned int offset); void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, unsigned int offset, - unsigned int mask); + struct mtk_ddp_comp *comp, void __iomem *regs, + unsigned int offset, unsigned int mask); #endif /* MTK_DRM_DDP_COMP_H */ -- cgit v1.2.3 From 993fd584942a75edda5e9cdec24c590c7a766b2d Mon Sep 17 00:00:00 2001 From: CK Hu Date: Fri, 28 Aug 2020 16:21:13 +0800 Subject: drm/mediatek: Remove irq in struct mtk_ddp_comp irq in struct mtk_ddp_comp is useless, so remove it. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index eaca3b930c5b..775bc37c4045 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -581,11 +580,9 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, comp_id == DDP_COMPONENT_DSI2 || comp_id == DDP_COMPONENT_DSI3 || comp_id == DDP_COMPONENT_PWM0) { - comp->irq = 0; return 0; } - comp->irq = of_irq_get(node, 0); comp_pdev = of_find_device_by_node(node); if (!comp_pdev) { DRM_INFO("Waiting for device %s\n", node->full_name); -- cgit v1.2.3 From f22a565d10e756f1a6141ecd8762c58aa1788db8 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Fri, 28 Aug 2020 17:05:11 +0800 Subject: drm/mediatek: Use struct cmdq_client_reg to gather cmdq variable struct cmdq_client_reg include subsys and offset, so use it to replace these two variable. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 26 +++++++------------------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 4 ++-- 2 files changed, 9 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 775bc37c4045..14371d5863ae 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -96,8 +96,8 @@ void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, comp->subsys, - comp->regs_pa + offset, value); + cmdq_pkt_write(cmdq_pkt, comp->cmdq_reg.subsys, + comp->cmdq_reg.offset + offset, value); else #endif writel(value, regs + offset); @@ -109,8 +109,8 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, comp->subsys, - comp->regs_pa + offset, value); + cmdq_pkt_write(cmdq_pkt, comp->cmdq_reg.subsys, + comp->cmdq_reg.offset + offset, value); else #endif writel_relaxed(value, regs + offset); @@ -122,8 +122,8 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) { - cmdq_pkt_write_mask(cmdq_pkt, comp->subsys, - comp->regs_pa + offset, value, mask); + cmdq_pkt_write_mask(cmdq_pkt, comp->cmdq_reg.subsys, + comp->cmdq_reg.offset + offset, value, mask); } else { #endif u32 tmp = readl(regs + offset); @@ -558,10 +558,6 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, struct platform_device *comp_pdev; enum mtk_ddp_comp_type type; struct mtk_ddp_comp_dev *priv; -#if IS_REACHABLE(CONFIG_MTK_CMDQ) - struct resource res; - struct cmdq_client_reg cmdq_reg; -#endif int ret; if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) @@ -591,17 +587,9 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, comp->dev = &comp_pdev->dev; #if IS_REACHABLE(CONFIG_MTK_CMDQ) - if (of_address_to_resource(node, 0, &res) != 0) { - dev_err(comp->dev, "Missing reg in %s node\n", node->full_name); - return -EINVAL; - } - comp->regs_pa = res.start; - - ret = cmdq_dev_get_client_reg(comp->dev, &cmdq_reg, 0); + ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_reg, 0); if (ret) dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n"); - else - comp->subsys = cmdq_reg.subsys; #endif /* Only DMA capable components need the LARB property */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 2b201cc5cbc3..ba5fcffe6f9a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -7,6 +7,7 @@ #define MTK_DRM_DDP_COMP_H #include +#include #include struct device; @@ -70,8 +71,7 @@ struct mtk_ddp_comp { struct device *larb_dev; enum mtk_ddp_comp_id id; const struct mtk_ddp_comp_funcs *funcs; - resource_size_t regs_pa; - u8 subsys; + struct cmdq_client_reg cmdq_reg; }; static inline int mtk_ddp_comp_clk_enable(struct mtk_ddp_comp *comp) -- cgit v1.2.3 From 616443ca577efccd3f67ac7f875ed68e70b34012 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Thu, 8 Oct 2020 13:41:10 +0800 Subject: drm/mediatek: Move cmdq_reg info from struct mtk_ddp_comp to sub driver private data Some ddp component exist in both display path and other path, so data belonged to sub driver should be moved into sub driver private data so it could be used for multiple path. cmdq_reg info is one of sub driver data, so move it. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 10 ++++- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 34 +++++++++------ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 30 ++++++++----- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 67 +++++++++++++++-------------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 ++- 5 files changed, 84 insertions(+), 64 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index 93863dbfb761..929379c9c233 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -40,6 +40,7 @@ struct mtk_disp_color { struct drm_crtc *crtc; struct clk *clk; void __iomem *regs; + struct cmdq_client_reg cmdq_reg; const struct mtk_disp_color_data *data; }; @@ -68,8 +69,8 @@ static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, { struct mtk_disp_color *color = comp_to_color(comp); - mtk_ddp_write(cmdq_pkt, w, comp, color->regs, DISP_COLOR_WIDTH(color)); - mtk_ddp_write(cmdq_pkt, h, comp, color->regs, DISP_COLOR_HEIGHT(color)); + mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color)); + mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); } static void mtk_color_start(struct mtk_ddp_comp *comp) @@ -143,6 +144,11 @@ static int mtk_disp_color_probe(struct platform_device *pdev) dev_err(dev, "failed to ioremap color\n"); return PTR_ERR(priv->regs); } +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_COLOR); if (comp_id < 0) { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 90a78db0e96b..0e59b360104a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -74,6 +74,7 @@ struct mtk_disp_ovl { struct drm_crtc *crtc; struct clk *clk; void __iomem *regs; + struct cmdq_client_reg cmdq_reg; const struct mtk_disp_ovl_data *data; }; @@ -151,12 +152,12 @@ static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); if (w != 0 && h != 0) - mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp, ovl->regs, + mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_SIZE); - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, ovl->regs, DISP_REG_OVL_ROI_BGCLR); + mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR); - mtk_ddp_write(cmdq_pkt, 0x1, comp, ovl->regs, DISP_REG_OVL_RST); - mtk_ddp_write(cmdq_pkt, 0x0, comp, ovl->regs, DISP_REG_OVL_RST); + mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); + mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); } static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) @@ -208,7 +209,7 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int gmc_value; struct mtk_disp_ovl *ovl = comp_to_ovl(comp); - mtk_ddp_write(cmdq_pkt, 0x1, comp, ovl->regs, + mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_CTRL(idx)); gmc_thrshd_l = GMC_THRESHOLD_LOW >> (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); @@ -220,8 +221,8 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx, gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | gmc_thrshd_h << 16 | gmc_thrshd_h << 24; mtk_ddp_write(cmdq_pkt, gmc_value, - comp, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); - mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp, ovl->regs, + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_CON, BIT(idx)); } @@ -230,9 +231,9 @@ static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx, { struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); - mtk_ddp_write_mask(cmdq_pkt, 0, comp, ovl->regs, + mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_CON, BIT(idx)); - mtk_ddp_write(cmdq_pkt, 0, comp, ovl->regs, + mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_CTRL(idx)); } @@ -304,15 +305,15 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, addr += pending->pitch - 1; } - mtk_ddp_write_relaxed(cmdq_pkt, con, comp, ovl->regs, + mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, ovl->regs, + mtk_ddp_write_relaxed(cmdq_pkt, pitch, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp, ovl->regs, + mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, offset, comp, ovl->regs, + mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_OFFSET(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, ovl->regs, + mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ADDR(ovl, idx)); mtk_ovl_layer_on(comp, idx, cmdq_pkt); @@ -414,6 +415,11 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) dev_err(dev, "failed to ioremap ovl\n"); return PTR_ERR(priv->regs); } +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif priv->data = of_device_get_match_data(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 1057c7a42ff2..d6d6c76526bb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -65,6 +65,7 @@ struct mtk_disp_rdma { struct drm_crtc *crtc; struct clk *clk; void __iomem *regs; + struct cmdq_client_reg cmdq_reg; const struct mtk_disp_rdma_data *data; }; @@ -150,9 +151,9 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); - mtk_ddp_write_mask(cmdq_pkt, width, comp, rdma->regs, + mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, 0xfff); - mtk_ddp_write_mask(cmdq_pkt, height, comp, rdma->regs, + mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_1, 0xfffff); /* @@ -165,7 +166,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); - mtk_ddp_write(cmdq_pkt, reg, comp, rdma->regs, DISP_REG_RDMA_FIFO_CON); + mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON); } static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, @@ -222,25 +223,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int con; con = rdma_fmt_convert(rdma, fmt); - mtk_ddp_write_relaxed(cmdq_pkt, con, comp, rdma->regs, DISP_RDMA_MEM_CON); + mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON); if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { - mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp, rdma->regs, + mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, RDMA_MATRIX_ENABLE); mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, - comp, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, + &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, RDMA_MATRIX_INT_MTX_SEL); } else { - mtk_ddp_write_mask(cmdq_pkt, 0, comp, rdma->regs, + mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, RDMA_MATRIX_ENABLE); } - mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, rdma->regs, DISP_RDMA_MEM_START_ADDR); - mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, rdma->regs, DISP_RDMA_MEM_SRC_PITCH); - mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp, rdma->regs, + mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs, + DISP_RDMA_MEM_START_ADDR); + mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs, + DISP_RDMA_MEM_SRC_PITCH); + mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_GMC_SETTING_0); - mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp, rdma->regs, + mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY); } @@ -318,6 +321,11 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) dev_err(dev, "failed to ioremap rdma\n"); return PTR_ERR(priv->regs); } +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA); if (comp_id < 0) { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 14371d5863ae..5da57ea6d06e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -88,42 +88,43 @@ struct mtk_ddp_comp_dev { struct clk *clk; void __iomem *regs; + struct cmdq_client_reg cmdq_reg; }; void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, void __iomem *regs, + struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset) { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, comp->cmdq_reg.subsys, - comp->cmdq_reg.offset + offset, value); + cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, + cmdq_reg->offset + offset, value); else #endif writel(value, regs + offset); } void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, void __iomem *regs, + struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset) { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, comp->cmdq_reg.subsys, - comp->cmdq_reg.offset + offset, value); + cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, + cmdq_reg->offset + offset, value); else #endif writel_relaxed(value, regs + offset); } void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, void __iomem *regs, + struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset, unsigned int mask) { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) { - cmdq_pkt_write_mask(cmdq_pkt, comp->cmdq_reg.subsys, - comp->cmdq_reg.offset + offset, value, mask); + cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, + cmdq_reg->offset + offset, value, mask); } else { #endif u32 tmp = readl(regs + offset); @@ -159,20 +160,20 @@ void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, return; if (bpc >= MTK_MIN_BPC) { - mtk_ddp_write(cmdq_pkt, 0, comp, priv->regs, DISP_DITHER_5); - mtk_ddp_write(cmdq_pkt, 0, comp, priv->regs, DISP_DITHER_7); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_5); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | DITHER_NEW_BIT_MODE, - comp, priv->regs, DISP_DITHER_15); + &priv->cmdq_reg, priv->regs, DISP_DITHER_15); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), - comp, priv->regs, DISP_DITHER_16); - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, priv->regs, CFG); + &priv->cmdq_reg, priv->regs, DISP_DITHER_16); + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, &priv->cmdq_reg, priv->regs, CFG); } } @@ -182,8 +183,8 @@ static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); - mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, priv->regs, DISP_OD_SIZE); - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, priv->regs, DISP_OD_CFG); + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE); + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG); mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt); } @@ -207,7 +208,7 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); } static void mtk_aal_start(struct mtk_ddp_comp *comp) @@ -230,8 +231,8 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_CCORR_SIZE); - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, priv->regs, DISP_CCORR_CFG); + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); } static void mtk_ccorr_start(struct mtk_ddp_comp *comp) @@ -289,15 +290,15 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], - comp, priv->regs, DISP_CCORR_COEF_0); + &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], - comp, priv->regs, DISP_CCORR_COEF_1); + &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], - comp, priv->regs, DISP_CCORR_COEF_2); + &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], - comp, priv->regs, DISP_CCORR_COEF_3); + &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, - comp, priv->regs, DISP_CCORR_COEF_4); + &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); } static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, @@ -306,8 +307,8 @@ static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_DITHER_SIZE); - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, priv->regs, DISP_DITHER_CFG); + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); } static void mtk_dither_start(struct mtk_ddp_comp *comp) @@ -330,7 +331,7 @@ static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, priv->regs, DISP_GAMMA_SIZE); + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_GAMMA_SIZE); mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt); } @@ -586,12 +587,6 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, } comp->dev = &comp_pdev->dev; -#if IS_REACHABLE(CONFIG_MTK_CMDQ) - ret = cmdq_dev_get_client_reg(comp->dev, &comp->cmdq_reg, 0); - if (ret) - dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n"); -#endif - /* Only DMA capable components need the LARB property */ if (type == MTK_DISP_OVL || type == MTK_DISP_OVL_2L || @@ -617,6 +612,12 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (IS_ERR(priv->clk)) return PTR_ERR(priv->clk); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n"); +#endif + platform_set_drvdata(comp_pdev, priv); return 0; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index ba5fcffe6f9a..1590f2af1665 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -71,7 +71,6 @@ struct mtk_ddp_comp { struct device *larb_dev; enum mtk_ddp_comp_id id; const struct mtk_ddp_comp_funcs *funcs; - struct cmdq_client_reg cmdq_reg; }; static inline int mtk_ddp_comp_clk_enable(struct mtk_ddp_comp *comp) @@ -195,12 +194,12 @@ void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, unsigned int CFG, struct cmdq_pkt *cmdq_pkt); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, void __iomem *regs, + struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset); void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, void __iomem *regs, + struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset); void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, - struct mtk_ddp_comp *comp, void __iomem *regs, + struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset, unsigned int mask); #endif /* MTK_DRM_DDP_COMP_H */ -- cgit v1.2.3 From 4d510659cf5d2c10f2793b41b02fe4cfdbd0bebe Mon Sep 17 00:00:00 2001 From: CK Hu Date: Mon, 12 Oct 2020 15:54:26 +0800 Subject: drm/mediatek: Change sub driver interface from mtk_ddp_comp to device Some ddp component exist in both display path and other path, so sub driver interface should get rid of display info. Using device instead of mtk_ddp_comp make interface general. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 13 ++-- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 57 ++++++++--------- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 39 ++++++------ drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 94 +++++++++++++---------------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 54 ++++++++--------- drivers/gpu/drm/mediatek/mtk_dsi.c | 8 +-- 7 files changed, 124 insertions(+), 149 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index 929379c9c233..dc2fdde1951c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -44,11 +44,6 @@ struct mtk_disp_color { const struct mtk_disp_color_data *data; }; -static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp) -{ - return container_of(comp, struct mtk_disp_color, ddp_comp); -} - static int mtk_color_clk_enable(struct device *dev) { struct mtk_disp_color *color = dev_get_drvdata(dev); @@ -63,19 +58,19 @@ static void mtk_color_clk_disable(struct device *dev) clk_disable_unprepare(color->clk); } -static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, +static void mtk_color_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - struct mtk_disp_color *color = comp_to_color(comp); + struct mtk_disp_color *color = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color)); mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); } -static void mtk_color_start(struct mtk_ddp_comp *comp) +static void mtk_color_start(struct device *dev) { - struct mtk_disp_color *color = comp_to_color(comp); + struct mtk_disp_color *color = dev_get_drvdata(dev); writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL, color->regs + DISP_COLOR_CFG_MAIN); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 0e59b360104a..172d2c9cb988 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -78,11 +78,6 @@ struct mtk_disp_ovl { const struct mtk_disp_ovl_data *data; }; -static inline struct mtk_disp_ovl *comp_to_ovl(struct mtk_ddp_comp *comp) -{ - return container_of(comp, struct mtk_disp_ovl, ddp_comp); -} - static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) { struct mtk_disp_ovl *priv = dev_id; @@ -99,19 +94,19 @@ static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp, +static void mtk_ovl_enable_vblank(struct device *dev, struct drm_crtc *crtc) { - struct mtk_disp_ovl *ovl = comp_to_ovl(comp); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); ovl->crtc = crtc; writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); } -static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp) +static void mtk_ovl_disable_vblank(struct device *dev) { - struct mtk_disp_ovl *ovl = comp_to_ovl(comp); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); ovl->crtc = NULL; writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); @@ -131,25 +126,25 @@ static void mtk_ovl_clk_disable(struct device *dev) clk_disable_unprepare(ovl->clk); } -static void mtk_ovl_start(struct mtk_ddp_comp *comp) +static void mtk_ovl_start(struct device *dev) { - struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); } -static void mtk_ovl_stop(struct mtk_ddp_comp *comp) +static void mtk_ovl_stop(struct device *dev) { - struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); } -static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, +static void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); if (w != 0 && h != 0) mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, @@ -160,20 +155,20 @@ static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); } -static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) +static unsigned int mtk_ovl_layer_nr(struct device *dev) { - struct mtk_disp_ovl *ovl = comp_to_ovl(comp); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); return ovl->data->layer_nr; } -static unsigned int mtk_ovl_supported_rotations(struct mtk_ddp_comp *comp) +static unsigned int mtk_ovl_supported_rotations(struct device *dev) { return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; } -static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx, +static int mtk_ovl_layer_check(struct device *dev, unsigned int idx, struct mtk_plane_state *mtk_state) { struct drm_plane_state *state = &mtk_state->base; @@ -201,13 +196,13 @@ static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx, return 0; } -static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx, +static void mtk_ovl_layer_on(struct device *dev, unsigned int idx, struct cmdq_pkt *cmdq_pkt) { unsigned int gmc_thrshd_l; unsigned int gmc_thrshd_h; unsigned int gmc_value; - struct mtk_disp_ovl *ovl = comp_to_ovl(comp); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_CTRL(idx)); @@ -226,10 +221,10 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx, DISP_REG_OVL_SRC_CON, BIT(idx)); } -static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx, +static void mtk_ovl_layer_off(struct device *dev, unsigned int idx, struct cmdq_pkt *cmdq_pkt) { - struct mtk_disp_ovl *ovl = dev_get_drvdata(comp->dev); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_CON, BIT(idx)); @@ -273,11 +268,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) } } -static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, +static void mtk_ovl_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt) { - struct mtk_disp_ovl *ovl = comp_to_ovl(comp); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); struct mtk_plane_pending_state *pending = &state->pending; unsigned int addr = pending->addr; unsigned int pitch = pending->pitch & 0xffff; @@ -287,7 +282,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int con; if (!pending->enable) { - mtk_ovl_layer_off(comp, idx, cmdq_pkt); + mtk_ovl_layer_off(dev, idx, cmdq_pkt); return; } @@ -316,12 +311,12 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ADDR(ovl, idx)); - mtk_ovl_layer_on(comp, idx, cmdq_pkt); + mtk_ovl_layer_on(dev, idx, cmdq_pkt); } -static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp) +static void mtk_ovl_bgclr_in_on(struct device *dev) { - struct mtk_disp_ovl *ovl = comp_to_ovl(comp); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); unsigned int reg; reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); @@ -329,9 +324,9 @@ static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp) writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); } -static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp) +static void mtk_ovl_bgclr_in_off(struct device *dev) { - struct mtk_disp_ovl *ovl = comp_to_ovl(comp); + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); unsigned int reg; reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index d6d6c76526bb..6e6cf039e1da 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -69,11 +69,6 @@ struct mtk_disp_rdma { const struct mtk_disp_rdma_data *data; }; -static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp) -{ - return container_of(comp, struct mtk_disp_rdma, ddp_comp); -} - static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) { struct mtk_disp_rdma *priv = dev_id; @@ -90,32 +85,32 @@ static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg, +static void rdma_update_bits(struct device *dev, unsigned int reg, unsigned int mask, unsigned int val) { - struct mtk_disp_rdma *rdma = dev_get_drvdata(comp->dev); + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); unsigned int tmp = readl(rdma->regs + reg); tmp = (tmp & ~mask) | (val & mask); writel(tmp, rdma->regs + reg); } -static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp, +static void mtk_rdma_enable_vblank(struct device *dev, struct drm_crtc *crtc) { - struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); rdma->crtc = crtc; - rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, + rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, RDMA_FRAME_END_INT); } -static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp) +static void mtk_rdma_disable_vblank(struct device *dev) { - struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); rdma->crtc = NULL; - rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); + rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); } static int mtk_rdma_clk_enable(struct device *dev) @@ -132,24 +127,24 @@ static void mtk_rdma_clk_disable(struct device *dev) clk_disable_unprepare(rdma->clk); } -static void mtk_rdma_start(struct mtk_ddp_comp *comp) +static void mtk_rdma_start(struct device *dev) { - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, + rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, RDMA_ENGINE_EN); } -static void mtk_rdma_stop(struct mtk_ddp_comp *comp) +static void mtk_rdma_stop(struct device *dev) { - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0); + rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0); } -static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, +static void mtk_rdma_config(struct device *dev, unsigned int width, unsigned int height, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { unsigned int threshold; unsigned int reg; - struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, 0xfff); @@ -206,16 +201,16 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, } } -static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp) +static unsigned int mtk_rdma_layer_nr(struct device *dev) { return 1; } -static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, +static void mtk_rdma_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt) { - struct mtk_disp_rdma *rdma = comp_to_rdma(comp); + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); struct mtk_plane_pending_state *pending = &state->pending; unsigned int addr = pending->addr; unsigned int pitch = pending->pitch & 0xffff; diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 81b43b640d45..c904ed2ead56 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -562,16 +562,16 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .enable = mtk_dpi_bridge_enable, }; -static void mtk_dpi_start(struct mtk_ddp_comp *comp) +static void mtk_dpi_start(struct device *dev) { - struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp); + struct mtk_dpi *dpi = dev_get_drvdata(dev); mtk_dpi_power_on(dpi); } -static void mtk_dpi_stop(struct mtk_ddp_comp *comp) +static void mtk_dpi_stop(struct device *dev) { - struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp); + struct mtk_dpi *dpi = dev_get_drvdata(dev); mtk_dpi_power_off(dpi); } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 5da57ea6d06e..7e7636fc781a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -150,10 +150,10 @@ static void mtk_ddp_clk_disable(struct device *dev) clk_disable_unprepare(priv->clk); } -void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, +static void mtk_dither_set(struct device *dev, unsigned int bpc, unsigned int CFG, struct cmdq_pkt *cmdq_pkt) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); /* If bpc equal to 0, the dithering function didn't be enabled */ if (bpc == 0) @@ -177,74 +177,74 @@ void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, } } -static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, +static void mtk_od_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE); mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG); - mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt); + mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt); } -static void mtk_od_start(struct mtk_ddp_comp *comp) +static void mtk_od_start(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel(1, priv->regs + DISP_OD_EN); } -static void mtk_ufoe_start(struct mtk_ddp_comp *comp) +static void mtk_ufoe_start(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); } -static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, +static void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); } -static void mtk_aal_start(struct mtk_ddp_comp *comp) +static void mtk_aal_start(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel(AAL_EN, priv->regs + DISP_AAL_EN); } -static void mtk_aal_stop(struct mtk_ddp_comp *comp) +static void mtk_aal_stop(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel_relaxed(0x0, priv->regs + DISP_AAL_EN); } -static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, +static void mtk_ccorr_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); } -static void mtk_ccorr_start(struct mtk_ddp_comp *comp) +static void mtk_ccorr_start(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel(CCORR_EN, priv->regs + DISP_CCORR_EN); } -static void mtk_ccorr_stop(struct mtk_ddp_comp *comp) +static void mtk_ccorr_stop(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); } @@ -269,10 +269,10 @@ static u16 mtk_ctm_s31_32_to_s1_10(u64 in) return r; } -static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, +static void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); struct drm_property_blob *blob = state->ctm; struct drm_color_ctm *ctm; const u64 *input; @@ -301,58 +301,58 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); } -static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, +static void mtk_dither_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); } -static void mtk_dither_start(struct mtk_ddp_comp *comp) +static void mtk_dither_start(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel(DITHER_EN, priv->regs + DISP_DITHER_EN); } -static void mtk_dither_stop(struct mtk_ddp_comp *comp) +static void mtk_dither_stop(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel_relaxed(0x0, priv->regs + DISP_DITHER_EN); } -static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, +static void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_GAMMA_SIZE); - mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt); + mtk_dither_set(dev, bpc, DISP_GAMMA_CFG, cmdq_pkt); } -static void mtk_gamma_start(struct mtk_ddp_comp *comp) +static void mtk_gamma_start(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel(GAMMA_EN, priv->regs + DISP_GAMMA_EN); } -static void mtk_gamma_stop(struct mtk_ddp_comp *comp) +static void mtk_gamma_stop(struct device *dev) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); writel_relaxed(0x0, priv->regs + DISP_GAMMA_EN); } -static void mtk_gamma_set(struct mtk_ddp_comp *comp, +static void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(comp->dev); + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; @@ -568,18 +568,6 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, comp->id = comp_id; comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs; - - if (comp_id == DDP_COMPONENT_BLS || - comp_id == DDP_COMPONENT_DPI0 || - comp_id == DDP_COMPONENT_DPI1 || - comp_id == DDP_COMPONENT_DSI0 || - comp_id == DDP_COMPONENT_DSI1 || - comp_id == DDP_COMPONENT_DSI2 || - comp_id == DDP_COMPONENT_DSI3 || - comp_id == DDP_COMPONENT_PWM0) { - return 0; - } - comp_pdev = of_find_device_by_node(node); if (!comp_pdev) { DRM_INFO("Waiting for device %s\n", node->full_name); @@ -597,9 +585,13 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, return ret; } - if (type == MTK_DISP_COLOR || + if (type == MTK_DISP_BLS || + type == MTK_DISP_COLOR || + type == MTK_DPI || + type == MTK_DSI || type == MTK_DISP_OVL || type == MTK_DISP_OVL_2L || + type == MTK_DISP_PWM || type == MTK_DISP_RDMA) return 0; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 1590f2af1665..6c796ba1d440 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -42,26 +42,26 @@ struct cmdq_pkt; struct mtk_ddp_comp_funcs { int (*clk_enable)(struct device *dev); void (*clk_disable)(struct device *dev); - void (*config)(struct mtk_ddp_comp *comp, unsigned int w, + void (*config)(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); - void (*start)(struct mtk_ddp_comp *comp); - void (*stop)(struct mtk_ddp_comp *comp); - void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc); - void (*disable_vblank)(struct mtk_ddp_comp *comp); - unsigned int (*supported_rotations)(struct mtk_ddp_comp *comp); - unsigned int (*layer_nr)(struct mtk_ddp_comp *comp); - int (*layer_check)(struct mtk_ddp_comp *comp, + void (*start)(struct device *dev); + void (*stop)(struct device *dev); + void (*enable_vblank)(struct device *dev, struct drm_crtc *crtc); + void (*disable_vblank)(struct device *dev); + unsigned int (*supported_rotations)(struct device *dev); + unsigned int (*layer_nr)(struct device *dev); + int (*layer_check)(struct device *dev, unsigned int idx, struct mtk_plane_state *state); - void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx, + void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); - void (*gamma_set)(struct mtk_ddp_comp *comp, + void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); - void (*bgclr_in_on)(struct mtk_ddp_comp *comp); - void (*bgclr_in_off)(struct mtk_ddp_comp *comp); - void (*ctm_set)(struct mtk_ddp_comp *comp, + void (*bgclr_in_on)(struct device *dev); + void (*bgclr_in_off)(struct device *dev); + void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); }; @@ -93,39 +93,39 @@ static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp, struct cmdq_pkt *cmdq_pkt) { if (comp->funcs && comp->funcs->config) - comp->funcs->config(comp, w, h, vrefresh, bpc, cmdq_pkt); + comp->funcs->config(comp->dev, w, h, vrefresh, bpc, cmdq_pkt); } static inline void mtk_ddp_comp_start(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->start) - comp->funcs->start(comp); + comp->funcs->start(comp->dev); } static inline void mtk_ddp_comp_stop(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->stop) - comp->funcs->stop(comp); + comp->funcs->stop(comp->dev); } static inline void mtk_ddp_comp_enable_vblank(struct mtk_ddp_comp *comp, struct drm_crtc *crtc) { if (comp->funcs && comp->funcs->enable_vblank) - comp->funcs->enable_vblank(comp, crtc); + comp->funcs->enable_vblank(comp->dev, crtc); } static inline void mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->disable_vblank) - comp->funcs->disable_vblank(comp); + comp->funcs->disable_vblank(comp->dev); } static inline unsigned int mtk_ddp_comp_supported_rotations(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->supported_rotations) - return comp->funcs->supported_rotations(comp); + return comp->funcs->supported_rotations(comp->dev); return 0; } @@ -133,7 +133,7 @@ unsigned int mtk_ddp_comp_supported_rotations(struct mtk_ddp_comp *comp) static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->layer_nr) - return comp->funcs->layer_nr(comp); + return comp->funcs->layer_nr(comp->dev); return 0; } @@ -143,7 +143,7 @@ static inline int mtk_ddp_comp_layer_check(struct mtk_ddp_comp *comp, struct mtk_plane_state *state) { if (comp->funcs && comp->funcs->layer_check) - return comp->funcs->layer_check(comp, idx, state); + return comp->funcs->layer_check(comp->dev, idx, state); return 0; } @@ -153,33 +153,33 @@ static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp, struct cmdq_pkt *cmdq_pkt) { if (comp->funcs && comp->funcs->layer_config) - comp->funcs->layer_config(comp, idx, state, cmdq_pkt); + comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); } static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { if (comp->funcs && comp->funcs->gamma_set) - comp->funcs->gamma_set(comp, state); + comp->funcs->gamma_set(comp->dev, state); } static inline void mtk_ddp_comp_bgclr_in_on(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->bgclr_in_on) - comp->funcs->bgclr_in_on(comp); + comp->funcs->bgclr_in_on(comp->dev); } static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp) { if (comp->funcs && comp->funcs->bgclr_in_off) - comp->funcs->bgclr_in_off(comp); + comp->funcs->bgclr_in_off(comp->dev); } static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { if (comp->funcs && comp->funcs->ctm_set) - comp->funcs->ctm_set(comp, state); + comp->funcs->ctm_set(comp->dev, state); } int mtk_ddp_comp_get_id(struct device_node *node, @@ -190,8 +190,6 @@ int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs); int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp); void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp); -void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, - unsigned int CFG, struct cmdq_pkt *cmdq_pkt); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, struct cmdq_client_reg *cmdq_reg, void __iomem *regs, diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a71cf1f52f8b..3407fc6cd802 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -767,16 +767,16 @@ static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = { .mode_set = mtk_dsi_bridge_mode_set, }; -static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp) +static void mtk_dsi_ddp_start(struct device *dev) { - struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); + struct mtk_dsi *dsi = dev_get_drvdata(dev); mtk_dsi_poweron(dsi); } -static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp) +static void mtk_dsi_ddp_stop(struct device *dev) { - struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp); + struct mtk_dsi *dsi = dev_get_drvdata(dev); mtk_dsi_poweroff(dsi); } -- cgit v1.2.3 From 9b0704988b151824a51133dc4c921f4273c5d839 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Mon, 12 Oct 2020 17:08:10 +0800 Subject: drm/mediatek: Register vblank callback function Some ddp component exist in both display path and other path, so sub driver should not directly call crtc function. crtc register callback function to sub driver to prevent sub driver directly call crtc function. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 16 ++++--- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 17 +++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 67 +++++++++++++++-------------- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 ++-- 5 files changed, 60 insertions(+), 50 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 172d2c9cb988..3c1c1dde6fba 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -76,30 +76,33 @@ struct mtk_disp_ovl { void __iomem *regs; struct cmdq_client_reg cmdq_reg; const struct mtk_disp_ovl_data *data; + void (*vblank_cb)(void *data); + void *vblank_cb_data; }; static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) { struct mtk_disp_ovl *priv = dev_id; - struct mtk_ddp_comp *ovl = &priv->ddp_comp; /* Clear frame completion interrupt */ writel(0x0, priv->regs + DISP_REG_OVL_INTSTA); - if (!priv->crtc) + if (!priv->vblank_cb) return IRQ_NONE; - mtk_crtc_ddp_irq(priv->crtc, ovl); + priv->vblank_cb(priv->vblank_cb_data); return IRQ_HANDLED; } static void mtk_ovl_enable_vblank(struct device *dev, - struct drm_crtc *crtc) + void (*vblank_cb)(void *), + void *vblank_cb_data) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); - ovl->crtc = crtc; + ovl->vblank_cb = vblank_cb; + ovl->vblank_cb_data = vblank_cb_data; writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA); writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); } @@ -108,7 +111,8 @@ static void mtk_ovl_disable_vblank(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); - ovl->crtc = NULL; + ovl->vblank_cb = NULL; + ovl->vblank_cb_data = NULL; writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 6e6cf039e1da..f4b3a32eb456 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -62,25 +62,25 @@ struct mtk_disp_rdma_data { */ struct mtk_disp_rdma { struct mtk_ddp_comp ddp_comp; - struct drm_crtc *crtc; struct clk *clk; void __iomem *regs; struct cmdq_client_reg cmdq_reg; const struct mtk_disp_rdma_data *data; + void (*vblank_cb)(void *data); + void *vblank_cb_data; }; static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) { struct mtk_disp_rdma *priv = dev_id; - struct mtk_ddp_comp *rdma = &priv->ddp_comp; /* Clear frame completion interrupt */ writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); - if (!priv->crtc) + if (!priv->vblank_cb) return IRQ_NONE; - mtk_crtc_ddp_irq(priv->crtc, rdma); + priv->vblank_cb(priv->vblank_cb_data); return IRQ_HANDLED; } @@ -96,11 +96,13 @@ static void rdma_update_bits(struct device *dev, unsigned int reg, } static void mtk_rdma_enable_vblank(struct device *dev, - struct drm_crtc *crtc) + void (*vblank_cb)(void *), + void *vblank_cb_data) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); - rdma->crtc = crtc; + rdma->vblank_cb = vblank_cb; + rdma->vblank_cb_data = vblank_cb_data; rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, RDMA_FRAME_END_INT); } @@ -109,7 +111,8 @@ static void mtk_rdma_disable_vblank(struct device *dev) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); - rdma->crtc = NULL; + rdma->vblank_cb = NULL; + rdma->vblank_cb_data = NULL; rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index c08ebfc5fb24..b5915a5af997 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -169,24 +169,6 @@ static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) state->pending_config = true; } -static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) -{ - struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; - - mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); - - return 0; -} - -static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) -{ - struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; - - mtk_ddp_comp_disable_vblank(comp); -} - static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) { int ret; @@ -493,6 +475,40 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) mutex_unlock(&mtk_crtc->hw_lock); } +static void mtk_crtc_ddp_irq(void *data) +{ + struct drm_crtc *crtc = data; + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); + struct mtk_drm_private *priv = crtc->dev->dev_private; + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) +#else + if (!priv->data->shadow_register) +#endif + mtk_crtc_ddp_config(crtc, NULL); + + mtk_drm_finish_page_flip(mtk_crtc); +} + +static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) +{ + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; + + mtk_ddp_comp_enable_vblank(comp, mtk_crtc_ddp_irq, &mtk_crtc->base); + + return 0; +} + +static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) +{ + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; + + mtk_ddp_comp_disable_vblank(comp); +} + int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state) { @@ -662,21 +678,6 @@ err_cleanup_crtc: return ret; } -void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) -{ - struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - struct mtk_drm_private *priv = crtc->dev->dev_private; - -#if IS_REACHABLE(CONFIG_MTK_CMDQ) - if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) -#else - if (!priv->data->shadow_register) -#endif - mtk_crtc_ddp_config(crtc, NULL); - - mtk_drm_finish_page_flip(mtk_crtc); -} - static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, int comp_idx) { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index a2b4677a451c..45cfd0a032de 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -15,7 +15,6 @@ #define MTK_MIN_BPC 3 void mtk_drm_crtc_commit(struct drm_crtc *crtc); -void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp); int mtk_drm_crtc_create(struct drm_device *drm_dev, const enum mtk_ddp_comp_id *path, unsigned int path_len); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 6c796ba1d440..ca059b19f663 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -47,7 +47,9 @@ struct mtk_ddp_comp_funcs { unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void (*start)(struct device *dev); void (*stop)(struct device *dev); - void (*enable_vblank)(struct device *dev, struct drm_crtc *crtc); + void (*enable_vblank)(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data); void (*disable_vblank)(struct device *dev); unsigned int (*supported_rotations)(struct device *dev); unsigned int (*layer_nr)(struct device *dev); @@ -109,10 +111,11 @@ static inline void mtk_ddp_comp_stop(struct mtk_ddp_comp *comp) } static inline void mtk_ddp_comp_enable_vblank(struct mtk_ddp_comp *comp, - struct drm_crtc *crtc) + void (*vblank_cb)(void *), + void *vblank_cb_data) { if (comp->funcs && comp->funcs->enable_vblank) - comp->funcs->enable_vblank(comp->dev, crtc); + comp->funcs->enable_vblank(comp->dev, vblank_cb, vblank_cb_data); } static inline void mtk_ddp_comp_disable_vblank(struct mtk_ddp_comp *comp) -- cgit v1.2.3 From 1d33f13a1be32915f25c63f13100938cb9de4c63 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Mon, 12 Oct 2020 11:50:47 +0800 Subject: drm/mediatek: DRM driver directly refer to sub driver's function Some ddp component exist in both display path and other path, so sub driver should not directly call DRM driver's function. Let DRM driver directly refer to sub driver's function so that sub driver need not register these function to DRM driver. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 23 +++------ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 69 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 68 ++++++++++-------------- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 46 ++++++----------- drivers/gpu/drm/mediatek/mtk_dpi.c | 13 ++--- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 80 +++++++++++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 +- drivers/gpu/drm/mediatek/mtk_dsi.c | 13 ++--- 9 files changed, 193 insertions(+), 124 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_drv.h (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index dc2fdde1951c..d28c06d02286 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -11,6 +11,7 @@ #include #include +#include "mtk_disp_drv.h" #include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -44,23 +45,23 @@ struct mtk_disp_color { const struct mtk_disp_color_data *data; }; -static int mtk_color_clk_enable(struct device *dev) +int mtk_color_clk_enable(struct device *dev) { struct mtk_disp_color *color = dev_get_drvdata(dev); return clk_prepare_enable(color->clk); } -static void mtk_color_clk_disable(struct device *dev) +void mtk_color_clk_disable(struct device *dev) { struct mtk_disp_color *color = dev_get_drvdata(dev); clk_disable_unprepare(color->clk); } -static void mtk_color_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +void mtk_color_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_color *color = dev_get_drvdata(dev); @@ -68,7 +69,7 @@ static void mtk_color_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); } -static void mtk_color_start(struct device *dev) +void mtk_color_start(struct device *dev) { struct mtk_disp_color *color = dev_get_drvdata(dev); @@ -77,13 +78,6 @@ static void mtk_color_start(struct device *dev) writel(0x1, color->regs + DISP_COLOR_START(color)); } -static const struct mtk_ddp_comp_funcs mtk_disp_color_funcs = { - .clk_enable = mtk_color_clk_enable, - .clk_disable = mtk_color_clk_disable, - .config = mtk_color_config, - .start = mtk_color_start, -}; - static int mtk_disp_color_bind(struct device *dev, struct device *master, void *data) { @@ -151,8 +145,7 @@ static int mtk_disp_color_probe(struct platform_device *pdev) return comp_id; } - ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id, - &mtk_disp_color_funcs); + ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "Failed to initialize component: %d\n", diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h new file mode 100644 index 000000000000..46d199b7b4a2 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef _MTK_DISP_DRV_H_ +#define _MTK_DISP_DRV_H_ + +#include +#include "mtk_drm_plane.h" + +void mtk_color_bypass_shadow(struct device *dev); +int mtk_color_clk_enable(struct device *dev); +void mtk_color_clk_disable(struct device *dev); +void mtk_color_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_color_start(struct device *dev); + +void mtk_dpi_start(struct device *dev); +void mtk_dpi_stop(struct device *dev); + +void mtk_dsi_ddp_start(struct device *dev); +void mtk_dsi_ddp_stop(struct device *dev); + +void mtk_ovl_bgclr_in_on(struct device *dev); +void mtk_ovl_bgclr_in_off(struct device *dev); +void mtk_ovl_bypass_shadow(struct device *dev); +int mtk_ovl_clk_enable(struct device *dev); +void mtk_ovl_clk_disable(struct device *dev); +void mtk_ovl_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +int mtk_ovl_layer_check(struct device *dev, unsigned int idx, + struct mtk_plane_state *mtk_state); +void mtk_ovl_layer_config(struct device *dev, unsigned int idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_ovl_layer_nr(struct device *dev); +void mtk_ovl_layer_on(struct device *dev, unsigned int idx, + struct cmdq_pkt *cmdq_pkt); +void mtk_ovl_layer_off(struct device *dev, unsigned int idx, + struct cmdq_pkt *cmdq_pkt); +void mtk_ovl_start(struct device *dev); +void mtk_ovl_stop(struct device *dev); +unsigned int mtk_ovl_supported_rotations(struct device *dev); +void mtk_ovl_enable_vblank(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data); +void mtk_ovl_disable_vblank(struct device *dev); + +void mtk_rdma_bypass_shadow(struct device *dev); +int mtk_rdma_clk_enable(struct device *dev); +void mtk_rdma_clk_disable(struct device *dev); +void mtk_rdma_config(struct device *dev, unsigned int width, + unsigned int height, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_rdma_layer_nr(struct device *dev); +void mtk_rdma_layer_config(struct device *dev, unsigned int idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt); +void mtk_rdma_start(struct device *dev); +void mtk_rdma_stop(struct device *dev); +void mtk_rdma_enable_vblank(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data); +void mtk_rdma_disable_vblank(struct device *dev); + +#endif diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 3c1c1dde6fba..a4f806355d2c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -13,6 +13,7 @@ #include #include +#include "mtk_disp_drv.h" #include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -95,9 +96,9 @@ static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static void mtk_ovl_enable_vblank(struct device *dev, - void (*vblank_cb)(void *), - void *vblank_cb_data) +void mtk_ovl_enable_vblank(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); @@ -107,7 +108,7 @@ static void mtk_ovl_enable_vblank(struct device *dev, writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN); } -static void mtk_ovl_disable_vblank(struct device *dev) +void mtk_ovl_disable_vblank(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); @@ -116,37 +117,37 @@ static void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } -static int mtk_ovl_clk_enable(struct device *dev) +int mtk_ovl_clk_enable(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); return clk_prepare_enable(ovl->clk); } -static void mtk_ovl_clk_disable(struct device *dev) +void mtk_ovl_clk_disable(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); clk_disable_unprepare(ovl->clk); } -static void mtk_ovl_start(struct device *dev) +void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); } -static void mtk_ovl_stop(struct device *dev) +void mtk_ovl_stop(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); } -static void mtk_ovl_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +void mtk_ovl_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); @@ -159,21 +160,21 @@ static void mtk_ovl_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); } -static unsigned int mtk_ovl_layer_nr(struct device *dev) +unsigned int mtk_ovl_layer_nr(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); return ovl->data->layer_nr; } -static unsigned int mtk_ovl_supported_rotations(struct device *dev) +unsigned int mtk_ovl_supported_rotations(struct device *dev) { return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; } -static int mtk_ovl_layer_check(struct device *dev, unsigned int idx, - struct mtk_plane_state *mtk_state) +int mtk_ovl_layer_check(struct device *dev, unsigned int idx, + struct mtk_plane_state *mtk_state) { struct drm_plane_state *state = &mtk_state->base; unsigned int rotation = 0; @@ -200,8 +201,8 @@ static int mtk_ovl_layer_check(struct device *dev, unsigned int idx, return 0; } -static void mtk_ovl_layer_on(struct device *dev, unsigned int idx, - struct cmdq_pkt *cmdq_pkt) +void mtk_ovl_layer_on(struct device *dev, unsigned int idx, + struct cmdq_pkt *cmdq_pkt) { unsigned int gmc_thrshd_l; unsigned int gmc_thrshd_h; @@ -225,8 +226,8 @@ static void mtk_ovl_layer_on(struct device *dev, unsigned int idx, DISP_REG_OVL_SRC_CON, BIT(idx)); } -static void mtk_ovl_layer_off(struct device *dev, unsigned int idx, - struct cmdq_pkt *cmdq_pkt) +void mtk_ovl_layer_off(struct device *dev, unsigned int idx, + struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); @@ -272,9 +273,9 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) } } -static void mtk_ovl_layer_config(struct device *dev, unsigned int idx, - struct mtk_plane_state *state, - struct cmdq_pkt *cmdq_pkt) +void mtk_ovl_layer_config(struct device *dev, unsigned int idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); struct mtk_plane_pending_state *pending = &state->pending; @@ -318,7 +319,7 @@ static void mtk_ovl_layer_config(struct device *dev, unsigned int idx, mtk_ovl_layer_on(dev, idx, cmdq_pkt); } -static void mtk_ovl_bgclr_in_on(struct device *dev) +void mtk_ovl_bgclr_in_on(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); unsigned int reg; @@ -328,7 +329,7 @@ static void mtk_ovl_bgclr_in_on(struct device *dev) writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); } -static void mtk_ovl_bgclr_in_off(struct device *dev) +void mtk_ovl_bgclr_in_off(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); unsigned int reg; @@ -338,22 +339,6 @@ static void mtk_ovl_bgclr_in_off(struct device *dev) writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); } -static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { - .clk_enable = mtk_ovl_clk_enable, - .clk_disable = mtk_ovl_clk_disable, - .config = mtk_ovl_config, - .start = mtk_ovl_start, - .stop = mtk_ovl_stop, - .enable_vblank = mtk_ovl_enable_vblank, - .disable_vblank = mtk_ovl_disable_vblank, - .supported_rotations = mtk_ovl_supported_rotations, - .layer_nr = mtk_ovl_layer_nr, - .layer_check = mtk_ovl_layer_check, - .layer_config = mtk_ovl_layer_config, - .bgclr_in_on = mtk_ovl_bgclr_in_on, - .bgclr_in_off = mtk_ovl_bgclr_in_off, -}; - static int mtk_disp_ovl_bind(struct device *dev, struct device *master, void *data) { @@ -431,8 +416,7 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) return comp_id; } - ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id, - &mtk_disp_ovl_funcs); + ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "Failed to initialize component: %d\n", diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index f4b3a32eb456..a263b7eab866 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -11,6 +11,7 @@ #include #include +#include "mtk_disp_drv.h" #include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -95,9 +96,9 @@ static void rdma_update_bits(struct device *dev, unsigned int reg, writel(tmp, rdma->regs + reg); } -static void mtk_rdma_enable_vblank(struct device *dev, - void (*vblank_cb)(void *), - void *vblank_cb_data) +void mtk_rdma_enable_vblank(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); @@ -107,7 +108,7 @@ static void mtk_rdma_enable_vblank(struct device *dev, RDMA_FRAME_END_INT); } -static void mtk_rdma_disable_vblank(struct device *dev) +void mtk_rdma_disable_vblank(struct device *dev) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); @@ -116,34 +117,34 @@ static void mtk_rdma_disable_vblank(struct device *dev) rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); } -static int mtk_rdma_clk_enable(struct device *dev) +int mtk_rdma_clk_enable(struct device *dev) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); return clk_prepare_enable(rdma->clk); } -static void mtk_rdma_clk_disable(struct device *dev) +void mtk_rdma_clk_disable(struct device *dev) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); clk_disable_unprepare(rdma->clk); } -static void mtk_rdma_start(struct device *dev) +void mtk_rdma_start(struct device *dev) { rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, RDMA_ENGINE_EN); } -static void mtk_rdma_stop(struct device *dev) +void mtk_rdma_stop(struct device *dev) { rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0); } -static void mtk_rdma_config(struct device *dev, unsigned int width, - unsigned int height, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +void mtk_rdma_config(struct device *dev, unsigned int width, + unsigned int height, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { unsigned int threshold; unsigned int reg; @@ -204,14 +205,14 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, } } -static unsigned int mtk_rdma_layer_nr(struct device *dev) +unsigned int mtk_rdma_layer_nr(struct device *dev) { return 1; } -static void mtk_rdma_layer_config(struct device *dev, unsigned int idx, - struct mtk_plane_state *state, - struct cmdq_pkt *cmdq_pkt) +void mtk_rdma_layer_config(struct device *dev, unsigned int idx, + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); struct mtk_plane_pending_state *pending = &state->pending; @@ -246,18 +247,6 @@ static void mtk_rdma_layer_config(struct device *dev, unsigned int idx, } -static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { - .clk_enable = mtk_rdma_clk_enable, - .clk_disable = mtk_rdma_clk_disable, - .config = mtk_rdma_config, - .start = mtk_rdma_start, - .stop = mtk_rdma_stop, - .enable_vblank = mtk_rdma_enable_vblank, - .disable_vblank = mtk_rdma_disable_vblank, - .layer_nr = mtk_rdma_layer_nr, - .layer_config = mtk_rdma_layer_config, -}; - static int mtk_disp_rdma_bind(struct device *dev, struct device *master, void *data) { @@ -331,8 +320,7 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) return comp_id; } - ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id, - &mtk_disp_rdma_funcs); + ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id); if (ret) { if (ret != -EPROBE_DEFER) dev_err(dev, "Failed to initialize component: %d\n", diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index c904ed2ead56..3c23d682fc57 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -24,6 +24,7 @@ #include #include +#include "mtk_disp_drv.h" #include "mtk_dpi_regs.h" #include "mtk_drm_ddp_comp.h" @@ -562,25 +563,20 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .enable = mtk_dpi_bridge_enable, }; -static void mtk_dpi_start(struct device *dev) +void mtk_dpi_start(struct device *dev) { struct mtk_dpi *dpi = dev_get_drvdata(dev); mtk_dpi_power_on(dpi); } -static void mtk_dpi_stop(struct device *dev) +void mtk_dpi_stop(struct device *dev) { struct mtk_dpi *dpi = dev_get_drvdata(dev); mtk_dpi_power_off(dpi); } -static const struct mtk_ddp_comp_funcs mtk_dpi_funcs = { - .start = mtk_dpi_start, - .stop = mtk_dpi_stop, -}; - static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) { struct mtk_dpi *dpi = dev_get_drvdata(dev); @@ -775,8 +771,7 @@ static int mtk_dpi_probe(struct platform_device *pdev) return comp_id; } - ret = mtk_ddp_comp_init(dev->of_node, &dpi->ddp_comp, comp_id, - &mtk_dpi_funcs); + ret = mtk_ddp_comp_init(dev->of_node, &dpi->ddp_comp, comp_id); if (ret) { dev_err(dev, "Failed to initialize component: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7e7636fc781a..6f60e8da0650 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -14,6 +14,7 @@ #include #include +#include "mtk_disp_drv.h" #include "mtk_drm_drv.h" #include "mtk_drm_plane.h" #include "mtk_drm_ddp_comp.h" @@ -391,6 +392,13 @@ static const struct mtk_ddp_comp_funcs ddp_ccorr = { .ctm_set = mtk_ccorr_ctm_set, }; +static const struct mtk_ddp_comp_funcs ddp_color = { + .clk_enable = mtk_color_clk_enable, + .clk_disable = mtk_color_clk_disable, + .config = mtk_color_config, + .start = mtk_color_start, +}; + static const struct mtk_ddp_comp_funcs ddp_dither = { .clk_enable = mtk_ddp_clk_enable, .clk_disable = mtk_ddp_clk_disable, @@ -399,6 +407,16 @@ static const struct mtk_ddp_comp_funcs ddp_dither = { .stop = mtk_dither_stop, }; +static const struct mtk_ddp_comp_funcs ddp_dpi = { + .start = mtk_dpi_start, + .stop = mtk_dpi_stop, +}; + +static const struct mtk_ddp_comp_funcs ddp_dsi = { + .start = mtk_dsi_ddp_start, + .stop = mtk_dsi_ddp_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_gamma = { .clk_enable = mtk_ddp_clk_enable, .clk_disable = mtk_ddp_clk_disable, @@ -415,6 +433,34 @@ static const struct mtk_ddp_comp_funcs ddp_od = { .start = mtk_od_start, }; +static const struct mtk_ddp_comp_funcs ddp_ovl = { + .clk_enable = mtk_ovl_clk_enable, + .clk_disable = mtk_ovl_clk_disable, + .config = mtk_ovl_config, + .start = mtk_ovl_start, + .stop = mtk_ovl_stop, + .enable_vblank = mtk_ovl_enable_vblank, + .disable_vblank = mtk_ovl_disable_vblank, + .supported_rotations = mtk_ovl_supported_rotations, + .layer_nr = mtk_ovl_layer_nr, + .layer_check = mtk_ovl_layer_check, + .layer_config = mtk_ovl_layer_config, + .bgclr_in_on = mtk_ovl_bgclr_in_on, + .bgclr_in_off = mtk_ovl_bgclr_in_off, +}; + +static const struct mtk_ddp_comp_funcs ddp_rdma = { + .clk_enable = mtk_rdma_clk_enable, + .clk_disable = mtk_rdma_clk_disable, + .config = mtk_rdma_config, + .start = mtk_rdma_start, + .stop = mtk_rdma_stop, + .enable_vblank = mtk_rdma_enable_vblank, + .disable_vblank = mtk_rdma_disable_vblank, + .layer_nr = mtk_rdma_layer_nr, + .layer_config = mtk_rdma_layer_config, +}; + static const struct mtk_ddp_comp_funcs ddp_ufoe = { .clk_enable = mtk_ddp_clk_enable, .clk_disable = mtk_ddp_clk_disable, @@ -451,28 +497,28 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL }, - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL }, + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL }, - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL }, + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, @@ -554,7 +600,7 @@ static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *c } int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, - enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs) + enum mtk_ddp_comp_id comp_id) { struct platform_device *comp_pdev; enum mtk_ddp_comp_type type; @@ -567,7 +613,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, type = mtk_ddp_matches[comp_id].type; comp->id = comp_id; - comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs; + comp->funcs = mtk_ddp_matches[comp_id].funcs; comp_pdev = of_find_device_by_node(node); if (!comp_pdev) { DRM_INFO("Waiting for device %s\n", node->full_name); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index ca059b19f663..0ab202f9380f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -190,7 +190,7 @@ int mtk_ddp_comp_get_id(struct device_node *node, unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, struct mtk_ddp_comp ddp_comp); int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp, - enum mtk_ddp_comp_id comp_id, const struct mtk_ddp_comp_funcs *funcs); + enum mtk_ddp_comp_id comp_id); int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp); void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 221aac9d1f66..68bc21200a46 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -512,8 +512,7 @@ static int mtk_drm_probe(struct platform_device *pdev) goto err_node; } - ret = mtk_ddp_comp_init(node, comp, - comp_id, NULL); + ret = mtk_ddp_comp_init(node, comp, comp_id); if (ret) { of_node_put(node); goto err_node; diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 3407fc6cd802..c4af04071e23 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -25,6 +25,7 @@ #include #include +#include "mtk_disp_drv.h" #include "mtk_drm_ddp_comp.h" #define DSI_START 0x00 @@ -767,25 +768,20 @@ static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = { .mode_set = mtk_dsi_bridge_mode_set, }; -static void mtk_dsi_ddp_start(struct device *dev) +void mtk_dsi_ddp_start(struct device *dev) { struct mtk_dsi *dsi = dev_get_drvdata(dev); mtk_dsi_poweron(dsi); } -static void mtk_dsi_ddp_stop(struct device *dev) +void mtk_dsi_ddp_stop(struct device *dev) { struct mtk_dsi *dsi = dev_get_drvdata(dev); mtk_dsi_poweroff(dsi); } -static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = { - .start = mtk_dsi_ddp_start, - .stop = mtk_dsi_ddp_stop, -}; - static int mtk_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *device) { @@ -1097,8 +1093,7 @@ static int mtk_dsi_probe(struct platform_device *pdev) goto err_unregister_host; } - ret = mtk_ddp_comp_init(dev->of_node, &dsi->ddp_comp, comp_id, - &mtk_dsi_funcs); + ret = mtk_ddp_comp_init(dev->of_node, &dsi->ddp_comp, comp_id); if (ret) { dev_err(dev, "Failed to initialize component: %d\n", ret); goto err_unregister_host; -- cgit v1.2.3 From ff1395609e20c1cd98b3ec65d16dc18f0471dca3 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Tue, 13 Oct 2020 14:15:10 +0800 Subject: drm/mediatek: Move mtk_ddp_comp_init() from sub driver to DRM driver Some ddp component exist in both display path and other path, so sub driver should not directly call DRM driver's function. Moving mtk_ddp_comp_init() from sub driver to DRM driver to achieve this. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 35 -------------------------- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 38 ----------------------------- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 32 ------------------------ drivers/gpu/drm/mediatek/mtk_dpi.c | 29 ++-------------------- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 38 +++++++++-------------------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 4 +-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 29 ++++++---------------- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_dsi.c | 32 +----------------------- 10 files changed, 25 insertions(+), 216 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index d28c06d02286..63f411ab393b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -37,7 +37,6 @@ struct mtk_disp_color_data { * @data: platform colour driver data */ struct mtk_disp_color { - struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; struct clk *clk; void __iomem *regs; @@ -81,27 +80,12 @@ void mtk_color_start(struct device *dev) static int mtk_disp_color_bind(struct device *dev, struct device *master, void *data) { - struct mtk_disp_color *priv = dev_get_drvdata(dev); - struct drm_device *drm_dev = data; - int ret; - - ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); - if (ret < 0) { - dev_err(dev, "Failed to register component %pOF: %d\n", - dev->of_node, ret); - return ret; - } - return 0; } static void mtk_disp_color_unbind(struct device *dev, struct device *master, void *data) { - struct mtk_disp_color *priv = dev_get_drvdata(dev); - struct drm_device *drm_dev = data; - - mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); } static const struct component_ops mtk_disp_color_component_ops = { @@ -114,7 +98,6 @@ static int mtk_disp_color_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mtk_disp_color *priv; struct resource *res; - int comp_id; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -139,23 +122,7 @@ static int mtk_disp_color_probe(struct platform_device *pdev) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); #endif - comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_COLOR); - if (comp_id < 0) { - dev_err(dev, "Failed to identify by alias: %d\n", comp_id); - return comp_id; - } - - ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to initialize component: %d\n", - ret); - - return ret; - } - priv->data = of_device_get_match_data(dev); - platform_set_drvdata(pdev, priv); ret = component_add(dev, &mtk_disp_color_component_ops); @@ -167,8 +134,6 @@ static int mtk_disp_color_probe(struct platform_device *pdev) static int mtk_disp_color_remove(struct platform_device *pdev) { - component_del(&pdev->dev, &mtk_disp_color_component_ops); - return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index a4f806355d2c..266c5c5ca280 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -71,7 +71,6 @@ struct mtk_disp_ovl_data { * @data: platform data */ struct mtk_disp_ovl { - struct mtk_ddp_comp ddp_comp; struct drm_crtc *crtc; struct clk *clk; void __iomem *regs; @@ -342,27 +341,12 @@ void mtk_ovl_bgclr_in_off(struct device *dev) static int mtk_disp_ovl_bind(struct device *dev, struct device *master, void *data) { - struct mtk_disp_ovl *priv = dev_get_drvdata(dev); - struct drm_device *drm_dev = data; - int ret; - - ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); - if (ret < 0) { - dev_err(dev, "Failed to register component %pOF: %d\n", - dev->of_node, ret); - return ret; - } - return 0; } static void mtk_disp_ovl_unbind(struct device *dev, struct device *master, void *data) { - struct mtk_disp_ovl *priv = dev_get_drvdata(dev); - struct drm_device *drm_dev = data; - - mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); } static const struct component_ops mtk_disp_ovl_component_ops = { @@ -375,7 +359,6 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mtk_disp_ovl *priv; struct resource *res; - int comp_id; int irq; int ret; @@ -406,25 +389,6 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) #endif priv->data = of_device_get_match_data(dev); - - comp_id = mtk_ddp_comp_get_id(dev->of_node, - priv->data->layer_nr == 4 ? - MTK_DISP_OVL : - MTK_DISP_OVL_2L); - if (comp_id < 0) { - dev_err(dev, "Failed to identify by alias: %d\n", comp_id); - return comp_id; - } - - ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to initialize component: %d\n", - ret); - - return ret; - } - platform_set_drvdata(pdev, priv); ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler, @@ -443,8 +407,6 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) static int mtk_disp_ovl_remove(struct platform_device *pdev) { - component_del(&pdev->dev, &mtk_disp_ovl_component_ops); - return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index a263b7eab866..7ac8f9ee082b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -62,7 +62,6 @@ struct mtk_disp_rdma_data { * @data: local driver data */ struct mtk_disp_rdma { - struct mtk_ddp_comp ddp_comp; struct clk *clk; void __iomem *regs; struct cmdq_client_reg cmdq_reg; @@ -250,17 +249,6 @@ void mtk_rdma_layer_config(struct device *dev, unsigned int idx, static int mtk_disp_rdma_bind(struct device *dev, struct device *master, void *data) { - struct mtk_disp_rdma *priv = dev_get_drvdata(dev); - struct drm_device *drm_dev = data; - int ret; - - ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp); - if (ret < 0) { - dev_err(dev, "Failed to register component %pOF: %d\n", - dev->of_node, ret); - return ret; - } - return 0; } @@ -268,10 +256,6 @@ static int mtk_disp_rdma_bind(struct device *dev, struct device *master, static void mtk_disp_rdma_unbind(struct device *dev, struct device *master, void *data) { - struct mtk_disp_rdma *priv = dev_get_drvdata(dev); - struct drm_device *drm_dev = data; - - mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp); } static const struct component_ops mtk_disp_rdma_component_ops = { @@ -284,7 +268,6 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mtk_disp_rdma *priv; struct resource *res; - int comp_id; int irq; int ret; @@ -314,21 +297,6 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); #endif - comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA); - if (comp_id < 0) { - dev_err(dev, "Failed to identify by alias: %d\n", comp_id); - return comp_id; - } - - ret = mtk_ddp_comp_init(dev->of_node, &priv->ddp_comp, comp_id); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to initialize component: %d\n", - ret); - - return ret; - } - /* Disable and clear pending interrupts */ writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE); writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 3c23d682fc57..88a6856024c2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -63,7 +63,6 @@ enum mtk_dpi_out_color_format { }; struct mtk_dpi { - struct mtk_ddp_comp ddp_comp; struct drm_encoder encoder; struct drm_bridge bridge; struct drm_bridge *next_bridge; @@ -583,21 +582,14 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; int ret; - ret = mtk_ddp_comp_register(drm_dev, &dpi->ddp_comp); - if (ret < 0) { - dev_err(dev, "Failed to register component %pOF: %d\n", - dev->of_node, ret); - return ret; - } - ret = drm_simple_encoder_init(drm_dev, &dpi->encoder, DRM_MODE_ENCODER_TMDS); if (ret) { dev_err(dev, "Failed to initialize decoder: %d\n", ret); - goto err_unregister; + return ret; } - dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->ddp_comp); + dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev); ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 0); if (ret) { @@ -614,8 +606,6 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) err_cleanup: drm_encoder_cleanup(&dpi->encoder); -err_unregister: - mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp); return ret; } @@ -623,10 +613,8 @@ static void mtk_dpi_unbind(struct device *dev, struct device *master, void *data) { struct mtk_dpi *dpi = dev_get_drvdata(dev); - struct drm_device *drm_dev = data; drm_encoder_cleanup(&dpi->encoder); - mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp); } static const struct component_ops mtk_dpi_component_ops = { @@ -687,7 +675,6 @@ static int mtk_dpi_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mtk_dpi *dpi; struct resource *mem; - int comp_id; int ret; dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL); @@ -765,18 +752,6 @@ static int mtk_dpi_probe(struct platform_device *pdev) dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node); - comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI); - if (comp_id < 0) { - dev_err(dev, "Failed to identify by alias: %d\n", comp_id); - return comp_id; - } - - ret = mtk_ddp_comp_init(dev->of_node, &dpi->ddp_comp, comp_id); - if (ret) { - dev_err(dev, "Failed to initialize component: %d\n", ret); - return ret; - } - platform_set_drvdata(pdev, dpi); dpi->bridge.funcs = &mtk_dpi_bridge_funcs; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index b5915a5af997..bf44a14ea0b6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -786,7 +786,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, struct device_node *node; node = priv->comp_node[comp_id]; - comp = priv->ddp_comp[comp_id]; + comp = &priv->ddp_comp[comp_id]; if (!comp) { dev_err(dev, "Component %pOF not initialized\n", node); ret = -ENODEV; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 6f60e8da0650..a17aee52d090 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -524,9 +524,10 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; -static bool mtk_drm_find_comp_in_ddp(struct mtk_ddp_comp ddp_comp, +static bool mtk_drm_find_comp_in_ddp(struct device *dev, const enum mtk_ddp_comp_id *path, - unsigned int path_len) + unsigned int path_len, + struct mtk_ddp_comp *ddp_comp) { unsigned int i; @@ -534,7 +535,7 @@ static bool mtk_drm_find_comp_in_ddp(struct mtk_ddp_comp ddp_comp, return false; for (i = 0U; i < path_len; i++) - if (ddp_comp.id == path[i]) + if (dev == ddp_comp[path[i]].dev) return true; return false; @@ -556,18 +557,19 @@ int mtk_ddp_comp_get_id(struct device_node *node, } unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, - struct mtk_ddp_comp ddp_comp) + struct device *dev) { struct mtk_drm_private *private = drm->dev_private; unsigned int ret = 0; - if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->main_path, private->data->main_len)) + if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len, + private->ddp_comp)) ret = BIT(0); - else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->ext_path, - private->data->ext_len)) + else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path, + private->data->ext_len, private->ddp_comp)) ret = BIT(1); - else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->third_path, - private->data->third_len)) + else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path, + private->data->third_len, private->ddp_comp)) ret = BIT(2); else DRM_INFO("Failed to find comp in ddp table\n"); @@ -660,21 +662,3 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, return 0; } - -int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp) -{ - struct mtk_drm_private *private = drm->dev_private; - - if (private->ddp_comp[comp->id]) - return -EBUSY; - - private->ddp_comp[comp->id] = comp; - return 0; -} - -void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp) -{ - struct mtk_drm_private *private = drm->dev_private; - - private->ddp_comp[comp->id] = NULL; -} diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 0ab202f9380f..bb914d976cf5 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -188,11 +188,9 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type); unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, - struct mtk_ddp_comp ddp_comp); + struct device *dev); int mtk_ddp_comp_init(struct device_node *comp_node, struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id); -int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp); -void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, struct cmdq_client_reg *cmdq_reg, void __iomem *regs, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 68bc21200a46..8514d68bde32 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -502,23 +502,12 @@ static int mtk_drm_probe(struct platform_device *pdev) node); drm_of_component_match_add(dev, &match, compare_of, node); - } else { - struct mtk_ddp_comp *comp; - - comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); - if (!comp) { - ret = -ENOMEM; - of_node_put(node); - goto err_node; - } - - ret = mtk_ddp_comp_init(node, comp, comp_id); - if (ret) { - of_node_put(node); - goto err_node; - } - - private->ddp_comp[comp_id] = comp; + } + + ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id); + if (ret) { + of_node_put(node); + goto err_node; } } @@ -544,10 +533,8 @@ err_node: of_node_put(private->mutex_node); for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) { of_node_put(private->comp_node[i]); - if (private->ddp_comp[i]) { - put_device(private->ddp_comp[i]->larb_dev); - private->ddp_comp[i] = NULL; - } + if (private->ddp_comp[i].larb_dev) + put_device(private->ddp_comp[i].larb_dev); } return ret; } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 5d771cf0bf25..690e92e9eff9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -41,7 +41,7 @@ struct mtk_drm_private { struct device *mutex_dev; struct device *mmsys_dev; struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; - struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX]; + struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_ID_MAX]; const struct mtk_mmsys_driver_data *data; struct drm_atomic_state *suspend_state; }; diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index c4af04071e23..a5247ee81632 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -179,7 +179,6 @@ struct mtk_dsi_driver_data { }; struct mtk_dsi { - struct mtk_ddp_comp ddp_comp; struct device *dev; struct mipi_dsi_host host; struct drm_encoder encoder; @@ -948,7 +947,7 @@ static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) return ret; } - dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp); + dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev); ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); @@ -976,32 +975,17 @@ static int mtk_dsi_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm = data; struct mtk_dsi *dsi = dev_get_drvdata(dev); - ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp); - if (ret < 0) { - dev_err(dev, "Failed to register component %pOF: %d\n", - dev->of_node, ret); - return ret; - } - ret = mtk_dsi_encoder_init(drm, dsi); - if (ret) - goto err_unregister; - - return 0; -err_unregister: - mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); return ret; } static void mtk_dsi_unbind(struct device *dev, struct device *master, void *data) { - struct drm_device *drm = data; struct mtk_dsi *dsi = dev_get_drvdata(dev); drm_encoder_cleanup(&dsi->encoder); - mtk_ddp_comp_unregister(drm, &dsi->ddp_comp); } static const struct component_ops mtk_dsi_component_ops = { @@ -1016,7 +1000,6 @@ static int mtk_dsi_probe(struct platform_device *pdev) struct drm_panel *panel; struct resource *regs; int irq_num; - int comp_id; int ret; dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); @@ -1086,19 +1069,6 @@ static int mtk_dsi_probe(struct platform_device *pdev) goto err_unregister_host; } - comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI); - if (comp_id < 0) { - dev_err(dev, "Failed to identify by alias: %d\n", comp_id); - ret = comp_id; - goto err_unregister_host; - } - - ret = mtk_ddp_comp_init(dev->of_node, &dsi->ddp_comp, comp_id); - if (ret) { - dev_err(dev, "Failed to initialize component: %d\n", ret); - goto err_unregister_host; - } - irq_num = platform_get_irq(pdev, 0); if (irq_num < 0) { dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num); -- cgit v1.2.3 From 435884b06bc0890615e93c55c0b4130bbf6fb0b4 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Fri, 25 Dec 2020 16:24:41 +0800 Subject: drm/mediatek: dsi: Use IRQF_TRIGGER_NONE for dsi irq trigger type The interrupt trigger is already set by OF. When do devm_request_irq() in driver, please use IRQF_TRIGGER_NONE and don't specify trigger type again. Signed-off-by: Jitao Shi Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dsi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a5247ee81632..a1ff152ef468 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -1076,9 +1076,8 @@ static int mtk_dsi_probe(struct platform_device *pdev) goto err_unregister_host; } - irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW); ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq, - IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi); + IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi); if (ret) { dev_err(&pdev->dev, "failed to request mediatek dsi irq\n"); goto err_unregister_host; -- cgit v1.2.3 From b1d685b6467ac0d98fc63989f71b4ca9186be5d4 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Mon, 11 Jan 2021 15:43:44 +0800 Subject: drm/mediatek: Check if fb is null It's possible that state->base.fb is null. Add a check before access its format. Fixes: b6b1bb980ec4 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha") Signed-off-by: Yongqiang Niu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 266c5c5ca280..1c295c58a5e8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -291,7 +291,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, } con = ovl_fmt_convert(ovl, fmt); - if (state->base.fb->format->has_alpha) + if (state->base.fb && state->base.fb->format->has_alpha) con |= OVL_CON_AEN | OVL_CON_ALPHA; if (pending->rotation & DRM_MODE_REFLECT_Y) { -- cgit v1.2.3 From f011951489678a9c679489136f5df064a86c84dd Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Thu, 3 Dec 2020 16:24:45 +0800 Subject: drm/mediatek: mtk_dpi: Create connector for bridges Similar to commit a9d9fea74be2 ("drm/mediatek: mtk_dsi: Create connector for bridges"): Use the drm_bridge_connector helper to create a connector for pipelines that use drm_bridge. This allows splitting connector operations across multiple bridges when necessary, instead of having the last bridge in the chain creating the connector and handling all connector operations internally. Signed-off-by: Hsin-Yi Wang Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 88a6856024c2..b05f900d9322 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -66,6 +67,7 @@ struct mtk_dpi { struct drm_encoder encoder; struct drm_bridge bridge; struct drm_bridge *next_bridge; + struct drm_connector *connector; void __iomem *regs; struct device *dev; struct clk *engine_clk; @@ -591,12 +593,21 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data) dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->dev); - ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 0); + ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret) { dev_err(dev, "Failed to attach bridge: %d\n", ret); goto err_cleanup; } + dpi->connector = drm_bridge_connector_init(drm_dev, &dpi->encoder); + if (IS_ERR(dpi->connector)) { + dev_err(dev, "Unable to create bridge connector\n"); + ret = PTR_ERR(dpi->connector); + goto err_cleanup; + } + drm_connector_attach_encoder(dpi->connector, &dpi->encoder); + dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; -- cgit v1.2.3 From 71dcadba34203d8dd35152e368720f977e9cdb81 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Mon, 11 Jan 2021 15:43:47 +0800 Subject: drm/mediatek: Fix aal size config The orginal setting is not correct, fix it to follow hardware data sheet. If keep this error setting, mt8173/mt8183 display ok but mt8192 display abnormal. Fixes: 0664d1392c26 ("drm/mediatek: Add AAL engine basic function") Signed-off-by: Yongqiang Niu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index a17aee52d090..7b5293429426 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -209,7 +209,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); } static void mtk_aal_start(struct device *dev) -- cgit v1.2.3 From 4d2598223da500982bc898b22834fc22bda57f46 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Thu, 7 Jan 2021 11:11:15 +0800 Subject: drm/mediatek: Add fifo_size into rdma private data Get the fifo size from device tree because each rdma in the same SoC may have different fifo size Signed-off-by: Yongqiang Niu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 7ac8f9ee082b..b84004394970 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -68,6 +68,7 @@ struct mtk_disp_rdma { const struct mtk_disp_rdma_data *data; void (*vblank_cb)(void *data); void *vblank_cb_data; + u32 fifo_size; }; static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id) @@ -148,12 +149,18 @@ void mtk_rdma_config(struct device *dev, unsigned int width, unsigned int threshold; unsigned int reg; struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); + u32 rdma_fifo_size; mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, 0xfff); mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_1, 0xfffff); + if (rdma->fifo_size) + rdma_fifo_size = rdma->fifo_size; + else + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); + /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the @@ -162,7 +169,7 @@ void mtk_rdma_config(struct device *dev, unsigned int width, */ threshold = width * height * vrefresh * 4 * 7 / 1000000; reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON); } @@ -297,6 +304,16 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev) dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); #endif + if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) { + ret = of_property_read_u32(dev->of_node, + "mediatek,rdma-fifo-size", + &priv->fifo_size); + if (ret) { + dev_err(dev, "Failed to get rdma fifo size\n"); + return ret; + } + } + /* Disable and clear pending interrupts */ writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE); writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS); -- cgit v1.2.3 From ad19ff82aaa70d42b417fe666318565ec5f98ff2 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Tue, 21 Jul 2020 09:31:19 +0800 Subject: drm/mediatek: Remove redundant file including Those file includings are useless, so remove them. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 2 -- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 -- 2 files changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h index 6b691a57be4a..a1ee21d15334 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h @@ -6,8 +6,6 @@ #ifndef MTK_DRM_DDP_H #define MTK_DRM_DDP_H -#include "mtk_drm_ddp_comp.h" - struct regmap; struct device; struct mtk_disp_mutex; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 8514d68bde32..25a24f69b986 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -26,7 +25,6 @@ #include #include "mtk_drm_crtc.h" -#include "mtk_drm_ddp.h" #include "mtk_drm_ddp_comp.h" #include "mtk_drm_drv.h" #include "mtk_drm_gem.h" -- cgit v1.2.3 From 8125bfa5bc402b0aa69fe2052a27ca75a8939cd6 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Tue, 21 Jul 2020 10:47:30 +0800 Subject: drm/mediatek: Rename file mtk_drm_ddp to mtk_mutex After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c has only mtk mutex function, so rename it to match the function in it. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/Makefile | 4 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 464 -------------------------------- drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 26 -- drivers/gpu/drm/mediatek/mtk_mutex.c | 464 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_mutex.h | 26 ++ 6 files changed, 493 insertions(+), 493 deletions(-) delete mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.c delete mode 100644 drivers/gpu/drm/mediatek/mtk_drm_ddp.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mutex.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mutex.h (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index a892edec5563..09979c4c340a 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -4,13 +4,13 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ mtk_drm_crtc.o \ - mtk_drm_ddp.o \ mtk_drm_ddp_comp.o \ mtk_drm_drv.o \ mtk_drm_gem.o \ mtk_drm_plane.o \ mtk_dsi.o \ - mtk_dpi.o + mtk_dpi.o \ + mtk_mutex.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index bf44a14ea0b6..fd97b7d195e3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -19,10 +19,10 @@ #include "mtk_drm_drv.h" #include "mtk_drm_crtc.h" -#include "mtk_drm_ddp.h" #include "mtk_drm_ddp_comp.h" #include "mtk_drm_gem.h" #include "mtk_drm_plane.h" +#include "mtk_mutex.h" /* * struct mtk_drm_crtc - MediaTek specific crtc structure. diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c deleted file mode 100644 index 1f99db6b1a42..000000000000 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ /dev/null @@ -1,464 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015 MediaTek Inc. - */ - -#include -#include -#include -#include -#include -#include - -#include "mtk_drm_ddp.h" -#include "mtk_drm_ddp_comp.h" - -#define MT2701_DISP_MUTEX0_MOD0 0x2c -#define MT2701_DISP_MUTEX0_SOF0 0x30 - -#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) -#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) -#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) -#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) -#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) -#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) - -#define INT_MUTEX BIT(1) - -#define MT8167_MUTEX_MOD_DISP_PWM 1 -#define MT8167_MUTEX_MOD_DISP_OVL0 6 -#define MT8167_MUTEX_MOD_DISP_OVL1 7 -#define MT8167_MUTEX_MOD_DISP_RDMA0 8 -#define MT8167_MUTEX_MOD_DISP_RDMA1 9 -#define MT8167_MUTEX_MOD_DISP_WDMA0 10 -#define MT8167_MUTEX_MOD_DISP_CCORR 11 -#define MT8167_MUTEX_MOD_DISP_COLOR 12 -#define MT8167_MUTEX_MOD_DISP_AAL 13 -#define MT8167_MUTEX_MOD_DISP_GAMMA 14 -#define MT8167_MUTEX_MOD_DISP_DITHER 15 -#define MT8167_MUTEX_MOD_DISP_UFOE 16 - -#define MT8173_MUTEX_MOD_DISP_OVL0 11 -#define MT8173_MUTEX_MOD_DISP_OVL1 12 -#define MT8173_MUTEX_MOD_DISP_RDMA0 13 -#define MT8173_MUTEX_MOD_DISP_RDMA1 14 -#define MT8173_MUTEX_MOD_DISP_RDMA2 15 -#define MT8173_MUTEX_MOD_DISP_WDMA0 16 -#define MT8173_MUTEX_MOD_DISP_WDMA1 17 -#define MT8173_MUTEX_MOD_DISP_COLOR0 18 -#define MT8173_MUTEX_MOD_DISP_COLOR1 19 -#define MT8173_MUTEX_MOD_DISP_AAL 20 -#define MT8173_MUTEX_MOD_DISP_GAMMA 21 -#define MT8173_MUTEX_MOD_DISP_UFOE 22 -#define MT8173_MUTEX_MOD_DISP_PWM0 23 -#define MT8173_MUTEX_MOD_DISP_PWM1 24 -#define MT8173_MUTEX_MOD_DISP_OD 25 - -#define MT2712_MUTEX_MOD_DISP_PWM2 10 -#define MT2712_MUTEX_MOD_DISP_OVL0 11 -#define MT2712_MUTEX_MOD_DISP_OVL1 12 -#define MT2712_MUTEX_MOD_DISP_RDMA0 13 -#define MT2712_MUTEX_MOD_DISP_RDMA1 14 -#define MT2712_MUTEX_MOD_DISP_RDMA2 15 -#define MT2712_MUTEX_MOD_DISP_WDMA0 16 -#define MT2712_MUTEX_MOD_DISP_WDMA1 17 -#define MT2712_MUTEX_MOD_DISP_COLOR0 18 -#define MT2712_MUTEX_MOD_DISP_COLOR1 19 -#define MT2712_MUTEX_MOD_DISP_AAL0 20 -#define MT2712_MUTEX_MOD_DISP_UFOE 22 -#define MT2712_MUTEX_MOD_DISP_PWM0 23 -#define MT2712_MUTEX_MOD_DISP_PWM1 24 -#define MT2712_MUTEX_MOD_DISP_OD0 25 -#define MT2712_MUTEX_MOD2_DISP_AAL1 33 -#define MT2712_MUTEX_MOD2_DISP_OD1 34 - -#define MT2701_MUTEX_MOD_DISP_OVL 3 -#define MT2701_MUTEX_MOD_DISP_WDMA 6 -#define MT2701_MUTEX_MOD_DISP_COLOR 7 -#define MT2701_MUTEX_MOD_DISP_BLS 9 -#define MT2701_MUTEX_MOD_DISP_RDMA0 10 -#define MT2701_MUTEX_MOD_DISP_RDMA1 12 - -#define MUTEX_SOF_SINGLE_MODE 0 -#define MUTEX_SOF_DSI0 1 -#define MUTEX_SOF_DSI1 2 -#define MUTEX_SOF_DPI0 3 -#define MUTEX_SOF_DPI1 4 -#define MUTEX_SOF_DSI2 5 -#define MUTEX_SOF_DSI3 6 -#define MT8167_MUTEX_SOF_DPI0 2 -#define MT8167_MUTEX_SOF_DPI1 3 - - -struct mtk_disp_mutex { - int id; - bool claimed; -}; - -enum mtk_ddp_mutex_sof_id { - DDP_MUTEX_SOF_SINGLE_MODE, - DDP_MUTEX_SOF_DSI0, - DDP_MUTEX_SOF_DSI1, - DDP_MUTEX_SOF_DPI0, - DDP_MUTEX_SOF_DPI1, - DDP_MUTEX_SOF_DSI2, - DDP_MUTEX_SOF_DSI3, -}; - -struct mtk_ddp_data { - const unsigned int *mutex_mod; - const unsigned int *mutex_sof; - const unsigned int mutex_mod_reg; - const unsigned int mutex_sof_reg; - const bool no_clk; -}; - -struct mtk_ddp { - struct device *dev; - struct clk *clk; - void __iomem *regs; - struct mtk_disp_mutex mutex[10]; - const struct mtk_ddp_data *data; -}; - -static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, - [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, - [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, - [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, - [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, - [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, -}; - -static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, - [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, - [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, - [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, - [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, - [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, - [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, - [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, - [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, - [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, - [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, - [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, - [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, - [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, - [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, - [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, - [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, -}; - -static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, - [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, - [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, - [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER, - [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, - [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, - [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, - [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, - [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, - [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, - [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, - [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, -}; - -static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, - [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, - [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, - [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, - [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, - [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, - [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, - [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, - [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, - [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, - [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, - [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, - [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, - [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, - [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, -}; - -static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { - [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, - [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, - [DDP_MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, - [DDP_MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, - [DDP_MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, - [DDP_MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, - [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, -}; - -static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { - [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, - [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, - [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, - [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, -}; - -static const struct mtk_ddp_data mt2701_ddp_driver_data = { - .mutex_mod = mt2701_mutex_mod, - .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, -}; - -static const struct mtk_ddp_data mt2712_ddp_driver_data = { - .mutex_mod = mt2712_mutex_mod, - .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, -}; - -static const struct mtk_ddp_data mt8167_ddp_driver_data = { - .mutex_mod = mt8167_mutex_mod, - .mutex_sof = mt8167_mutex_sof, - .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, - .no_clk = true, -}; - -static const struct mtk_ddp_data mt8173_ddp_driver_data = { - .mutex_mod = mt8173_mutex_mod, - .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, -}; - -struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) -{ - struct mtk_ddp *ddp = dev_get_drvdata(dev); - - if (id >= 10) - return ERR_PTR(-EINVAL); - if (ddp->mutex[id].claimed) - return ERR_PTR(-EBUSY); - - ddp->mutex[id].claimed = true; - - return &ddp->mutex[id]; -} - -void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - - WARN_ON(&ddp->mutex[mutex->id] != mutex); - - mutex->claimed = false; -} - -int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - return clk_prepare_enable(ddp->clk); -} - -void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - clk_disable_unprepare(ddp->clk); -} - -void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, - enum mtk_ddp_comp_id id) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - unsigned int reg; - unsigned int sof_id; - unsigned int offset; - - WARN_ON(&ddp->mutex[mutex->id] != mutex); - - switch (id) { - case DDP_COMPONENT_DSI0: - sof_id = DDP_MUTEX_SOF_DSI0; - break; - case DDP_COMPONENT_DSI1: - sof_id = DDP_MUTEX_SOF_DSI0; - break; - case DDP_COMPONENT_DSI2: - sof_id = DDP_MUTEX_SOF_DSI2; - break; - case DDP_COMPONENT_DSI3: - sof_id = DDP_MUTEX_SOF_DSI3; - break; - case DDP_COMPONENT_DPI0: - sof_id = DDP_MUTEX_SOF_DPI0; - break; - case DDP_COMPONENT_DPI1: - sof_id = DDP_MUTEX_SOF_DPI1; - break; - default: - if (ddp->data->mutex_mod[id] < 32) { - offset = DISP_REG_MUTEX_MOD(ddp->data->mutex_mod_reg, - mutex->id); - reg = readl_relaxed(ddp->regs + offset); - reg |= 1 << ddp->data->mutex_mod[id]; - writel_relaxed(reg, ddp->regs + offset); - } else { - offset = DISP_REG_MUTEX_MOD2(mutex->id); - reg = readl_relaxed(ddp->regs + offset); - reg |= 1 << (ddp->data->mutex_mod[id] - 32); - writel_relaxed(reg, ddp->regs + offset); - } - return; - } - - writel_relaxed(ddp->data->mutex_sof[sof_id], - ddp->regs + - DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id)); -} - -void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, - enum mtk_ddp_comp_id id) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - unsigned int reg; - unsigned int offset; - - WARN_ON(&ddp->mutex[mutex->id] != mutex); - - switch (id) { - case DDP_COMPONENT_DSI0: - case DDP_COMPONENT_DSI1: - case DDP_COMPONENT_DSI2: - case DDP_COMPONENT_DSI3: - case DDP_COMPONENT_DPI0: - case DDP_COMPONENT_DPI1: - writel_relaxed(MUTEX_SOF_SINGLE_MODE, - ddp->regs + - DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, - mutex->id)); - break; - default: - if (ddp->data->mutex_mod[id] < 32) { - offset = DISP_REG_MUTEX_MOD(ddp->data->mutex_mod_reg, - mutex->id); - reg = readl_relaxed(ddp->regs + offset); - reg &= ~(1 << ddp->data->mutex_mod[id]); - writel_relaxed(reg, ddp->regs + offset); - } else { - offset = DISP_REG_MUTEX_MOD2(mutex->id); - reg = readl_relaxed(ddp->regs + offset); - reg &= ~(1 << (ddp->data->mutex_mod[id] - 32)); - writel_relaxed(reg, ddp->regs + offset); - } - break; - } -} - -void mtk_disp_mutex_enable(struct mtk_disp_mutex *mutex) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - - WARN_ON(&ddp->mutex[mutex->id] != mutex); - - writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); -} - -void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - - WARN_ON(&ddp->mutex[mutex->id] != mutex); - - writel(0, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); -} - -void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - u32 tmp; - - writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); - writel(1, ddp->regs + DISP_REG_MUTEX(mutex->id)); - if (readl_poll_timeout_atomic(ddp->regs + DISP_REG_MUTEX(mutex->id), - tmp, tmp & INT_MUTEX, 1, 10000)) - pr_err("could not acquire mutex %d\n", mutex->id); -} - -void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex) -{ - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - - writel(0, ddp->regs + DISP_REG_MUTEX(mutex->id)); -} - -static int mtk_ddp_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct mtk_ddp *ddp; - struct resource *regs; - int i; - - ddp = devm_kzalloc(dev, sizeof(*ddp), GFP_KERNEL); - if (!ddp) - return -ENOMEM; - - for (i = 0; i < 10; i++) - ddp->mutex[i].id = i; - - ddp->data = of_device_get_match_data(dev); - - if (!ddp->data->no_clk) { - ddp->clk = devm_clk_get(dev, NULL); - if (IS_ERR(ddp->clk)) { - if (PTR_ERR(ddp->clk) != -EPROBE_DEFER) - dev_err(dev, "Failed to get clock\n"); - return PTR_ERR(ddp->clk); - } - } - - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ddp->regs = devm_ioremap_resource(dev, regs); - if (IS_ERR(ddp->regs)) { - dev_err(dev, "Failed to map mutex registers\n"); - return PTR_ERR(ddp->regs); - } - - platform_set_drvdata(pdev, ddp); - - return 0; -} - -static int mtk_ddp_remove(struct platform_device *pdev) -{ - return 0; -} - -static const struct of_device_id ddp_driver_dt_match[] = { - { .compatible = "mediatek,mt2701-disp-mutex", - .data = &mt2701_ddp_driver_data}, - { .compatible = "mediatek,mt2712-disp-mutex", - .data = &mt2712_ddp_driver_data}, - { .compatible = "mediatek,mt8167-disp-mutex", - .data = &mt8167_ddp_driver_data}, - { .compatible = "mediatek,mt8173-disp-mutex", - .data = &mt8173_ddp_driver_data}, - {}, -}; -MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); - -struct platform_driver mtk_ddp_driver = { - .probe = mtk_ddp_probe, - .remove = mtk_ddp_remove, - .driver = { - .name = "mediatek-ddp", - .owner = THIS_MODULE, - .of_match_table = ddp_driver_dt_match, - }, -}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h deleted file mode 100644 index a1ee21d15334..000000000000 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 MediaTek Inc. - */ - -#ifndef MTK_DRM_DDP_H -#define MTK_DRM_DDP_H - -struct regmap; -struct device; -struct mtk_disp_mutex; - -struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id); -int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, - enum mtk_ddp_comp_id id); -void mtk_disp_mutex_enable(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, - enum mtk_ddp_comp_id id); -void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex); - -#endif /* MTK_DRM_DDP_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_mutex.c b/drivers/gpu/drm/mediatek/mtk_mutex.c new file mode 100644 index 000000000000..1c8a253f4788 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mutex.c @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include "mtk_drm_ddp_comp.h" +#include "mtk_mutex.h" + +#define MT2701_DISP_MUTEX0_MOD0 0x2c +#define MT2701_DISP_MUTEX0_SOF0 0x30 + +#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) +#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) +#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) + +#define INT_MUTEX BIT(1) + +#define MT8167_MUTEX_MOD_DISP_PWM 1 +#define MT8167_MUTEX_MOD_DISP_OVL0 6 +#define MT8167_MUTEX_MOD_DISP_OVL1 7 +#define MT8167_MUTEX_MOD_DISP_RDMA0 8 +#define MT8167_MUTEX_MOD_DISP_RDMA1 9 +#define MT8167_MUTEX_MOD_DISP_WDMA0 10 +#define MT8167_MUTEX_MOD_DISP_CCORR 11 +#define MT8167_MUTEX_MOD_DISP_COLOR 12 +#define MT8167_MUTEX_MOD_DISP_AAL 13 +#define MT8167_MUTEX_MOD_DISP_GAMMA 14 +#define MT8167_MUTEX_MOD_DISP_DITHER 15 +#define MT8167_MUTEX_MOD_DISP_UFOE 16 + +#define MT8173_MUTEX_MOD_DISP_OVL0 11 +#define MT8173_MUTEX_MOD_DISP_OVL1 12 +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 +#define MT8173_MUTEX_MOD_DISP_AAL 20 +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 +#define MT8173_MUTEX_MOD_DISP_UFOE 22 +#define MT8173_MUTEX_MOD_DISP_PWM0 23 +#define MT8173_MUTEX_MOD_DISP_PWM1 24 +#define MT8173_MUTEX_MOD_DISP_OD 25 + +#define MT2712_MUTEX_MOD_DISP_PWM2 10 +#define MT2712_MUTEX_MOD_DISP_OVL0 11 +#define MT2712_MUTEX_MOD_DISP_OVL1 12 +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 +#define MT2712_MUTEX_MOD_DISP_AAL0 20 +#define MT2712_MUTEX_MOD_DISP_UFOE 22 +#define MT2712_MUTEX_MOD_DISP_PWM0 23 +#define MT2712_MUTEX_MOD_DISP_PWM1 24 +#define MT2712_MUTEX_MOD_DISP_OD0 25 +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 +#define MT2712_MUTEX_MOD2_DISP_OD1 34 + +#define MT2701_MUTEX_MOD_DISP_OVL 3 +#define MT2701_MUTEX_MOD_DISP_WDMA 6 +#define MT2701_MUTEX_MOD_DISP_COLOR 7 +#define MT2701_MUTEX_MOD_DISP_BLS 9 +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 + +#define MUTEX_SOF_SINGLE_MODE 0 +#define MUTEX_SOF_DSI0 1 +#define MUTEX_SOF_DSI1 2 +#define MUTEX_SOF_DPI0 3 +#define MUTEX_SOF_DPI1 4 +#define MUTEX_SOF_DSI2 5 +#define MUTEX_SOF_DSI3 6 +#define MT8167_MUTEX_SOF_DPI0 2 +#define MT8167_MUTEX_SOF_DPI1 3 + + +struct mtk_disp_mutex { + int id; + bool claimed; +}; + +enum mtk_ddp_mutex_sof_id { + DDP_MUTEX_SOF_SINGLE_MODE, + DDP_MUTEX_SOF_DSI0, + DDP_MUTEX_SOF_DSI1, + DDP_MUTEX_SOF_DPI0, + DDP_MUTEX_SOF_DPI1, + DDP_MUTEX_SOF_DSI2, + DDP_MUTEX_SOF_DSI3, +}; + +struct mtk_ddp_data { + const unsigned int *mutex_mod; + const unsigned int *mutex_sof; + const unsigned int mutex_mod_reg; + const unsigned int mutex_sof_reg; + const bool no_clk; +}; + +struct mtk_ddp { + struct device *dev; + struct clk *clk; + void __iomem *regs; + struct mtk_disp_mutex mutex[10]; + const struct mtk_ddp_data *data; +}; + +static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, + [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, + [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, +}; + +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, +}; + +static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, + [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER, + [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, + [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, + [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, +}; + +static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, + [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, + [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, + [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, +}; + +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, + [DDP_MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, + [DDP_MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, + [DDP_MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, + [DDP_MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, + [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, +}; + +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, + [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, + [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, +}; + +static const struct mtk_ddp_data mt2701_ddp_driver_data = { + .mutex_mod = mt2701_mutex_mod, + .mutex_sof = mt2712_mutex_sof, + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, +}; + +static const struct mtk_ddp_data mt2712_ddp_driver_data = { + .mutex_mod = mt2712_mutex_mod, + .mutex_sof = mt2712_mutex_sof, + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, +}; + +static const struct mtk_ddp_data mt8167_ddp_driver_data = { + .mutex_mod = mt8167_mutex_mod, + .mutex_sof = mt8167_mutex_sof, + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, + .no_clk = true, +}; + +static const struct mtk_ddp_data mt8173_ddp_driver_data = { + .mutex_mod = mt8173_mutex_mod, + .mutex_sof = mt2712_mutex_sof, + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, +}; + +struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) +{ + struct mtk_ddp *ddp = dev_get_drvdata(dev); + + if (id >= 10) + return ERR_PTR(-EINVAL); + if (ddp->mutex[id].claimed) + return ERR_PTR(-EBUSY); + + ddp->mutex[id].claimed = true; + + return &ddp->mutex[id]; +} + +void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + + WARN_ON(&ddp->mutex[mutex->id] != mutex); + + mutex->claimed = false; +} + +int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + return clk_prepare_enable(ddp->clk); +} + +void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + clk_disable_unprepare(ddp->clk); +} + +void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, + enum mtk_ddp_comp_id id) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + unsigned int reg; + unsigned int sof_id; + unsigned int offset; + + WARN_ON(&ddp->mutex[mutex->id] != mutex); + + switch (id) { + case DDP_COMPONENT_DSI0: + sof_id = DDP_MUTEX_SOF_DSI0; + break; + case DDP_COMPONENT_DSI1: + sof_id = DDP_MUTEX_SOF_DSI0; + break; + case DDP_COMPONENT_DSI2: + sof_id = DDP_MUTEX_SOF_DSI2; + break; + case DDP_COMPONENT_DSI3: + sof_id = DDP_MUTEX_SOF_DSI3; + break; + case DDP_COMPONENT_DPI0: + sof_id = DDP_MUTEX_SOF_DPI0; + break; + case DDP_COMPONENT_DPI1: + sof_id = DDP_MUTEX_SOF_DPI1; + break; + default: + if (ddp->data->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(ddp->data->mutex_mod_reg, + mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << ddp->data->mutex_mod[id]; + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << (ddp->data->mutex_mod[id] - 32); + writel_relaxed(reg, ddp->regs + offset); + } + return; + } + + writel_relaxed(ddp->data->mutex_sof[sof_id], + ddp->regs + + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id)); +} + +void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, + enum mtk_ddp_comp_id id) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + unsigned int reg; + unsigned int offset; + + WARN_ON(&ddp->mutex[mutex->id] != mutex); + + switch (id) { + case DDP_COMPONENT_DSI0: + case DDP_COMPONENT_DSI1: + case DDP_COMPONENT_DSI2: + case DDP_COMPONENT_DSI3: + case DDP_COMPONENT_DPI0: + case DDP_COMPONENT_DPI1: + writel_relaxed(MUTEX_SOF_SINGLE_MODE, + ddp->regs + + DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, + mutex->id)); + break; + default: + if (ddp->data->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(ddp->data->mutex_mod_reg, + mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << ddp->data->mutex_mod[id]); + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << (ddp->data->mutex_mod[id] - 32)); + writel_relaxed(reg, ddp->regs + offset); + } + break; + } +} + +void mtk_disp_mutex_enable(struct mtk_disp_mutex *mutex) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + + WARN_ON(&ddp->mutex[mutex->id] != mutex); + + writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); +} + +void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + + WARN_ON(&ddp->mutex[mutex->id] != mutex); + + writel(0, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); +} + +void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + u32 tmp; + + writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); + writel(1, ddp->regs + DISP_REG_MUTEX(mutex->id)); + if (readl_poll_timeout_atomic(ddp->regs + DISP_REG_MUTEX(mutex->id), + tmp, tmp & INT_MUTEX, 1, 10000)) + pr_err("could not acquire mutex %d\n", mutex->id); +} + +void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex) +{ + struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, + mutex[mutex->id]); + + writel(0, ddp->regs + DISP_REG_MUTEX(mutex->id)); +} + +static int mtk_ddp_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_ddp *ddp; + struct resource *regs; + int i; + + ddp = devm_kzalloc(dev, sizeof(*ddp), GFP_KERNEL); + if (!ddp) + return -ENOMEM; + + for (i = 0; i < 10; i++) + ddp->mutex[i].id = i; + + ddp->data = of_device_get_match_data(dev); + + if (!ddp->data->no_clk) { + ddp->clk = devm_clk_get(dev, NULL); + if (IS_ERR(ddp->clk)) { + if (PTR_ERR(ddp->clk) != -EPROBE_DEFER) + dev_err(dev, "Failed to get clock\n"); + return PTR_ERR(ddp->clk); + } + } + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ddp->regs = devm_ioremap_resource(dev, regs); + if (IS_ERR(ddp->regs)) { + dev_err(dev, "Failed to map mutex registers\n"); + return PTR_ERR(ddp->regs); + } + + platform_set_drvdata(pdev, ddp); + + return 0; +} + +static int mtk_ddp_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id ddp_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-mutex", + .data = &mt2701_ddp_driver_data}, + { .compatible = "mediatek,mt2712-disp-mutex", + .data = &mt2712_ddp_driver_data}, + { .compatible = "mediatek,mt8167-disp-mutex", + .data = &mt8167_ddp_driver_data}, + { .compatible = "mediatek,mt8173-disp-mutex", + .data = &mt8173_ddp_driver_data}, + {}, +}; +MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); + +struct platform_driver mtk_ddp_driver = { + .probe = mtk_ddp_probe, + .remove = mtk_ddp_remove, + .driver = { + .name = "mediatek-ddp", + .owner = THIS_MODULE, + .of_match_table = ddp_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_mutex.h b/drivers/gpu/drm/mediatek/mtk_mutex.h new file mode 100644 index 000000000000..3abcc20e88fb --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mutex.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015 MediaTek Inc. + */ + +#ifndef MTK_MUTEX_H +#define MTK_MUTEX_H + +struct regmap; +struct device; +struct mtk_disp_mutex; + +struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id); +int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex); +void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, + enum mtk_ddp_comp_id id); +void mtk_disp_mutex_enable(struct mtk_disp_mutex *mutex); +void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex); +void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, + enum mtk_ddp_comp_id id); +void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex); +void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex); +void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex); +void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex); + +#endif /* MTK_MUTEX_H */ -- cgit v1.2.3 From 4971593f8eb14fbb79f111b14c2d66db868c46e6 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Tue, 21 Jul 2020 11:24:36 +0800 Subject: drm/mediatek: Change disp/ddp term to mutex in mtk mutex driver mtk mutex is used by both drm and mdp driver, so change disp/ddp term to mutex to show that it's a common driver for drm and mdp. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 30 ++-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_mutex.c | 305 ++++++++++++++++---------------- drivers/gpu/drm/mediatek/mtk_mutex.h | 26 +-- 5 files changed, 182 insertions(+), 183 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index fd97b7d195e3..bba87a036fa8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -55,7 +55,7 @@ struct mtk_drm_crtc { #endif struct device *mmsys_dev; - struct mtk_disp_mutex *mutex; + struct mtk_mutex *mutex; unsigned int ddp_comp_nr; struct mtk_ddp_comp **ddp_comp; @@ -107,7 +107,7 @@ static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) { struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - mtk_disp_mutex_put(mtk_crtc->mutex); + mtk_mutex_put(mtk_crtc->mutex); drm_crtc_cleanup(crtc); } @@ -265,7 +265,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) return ret; } - ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); + ret = mtk_mutex_prepare(mtk_crtc->mutex); if (ret < 0) { DRM_ERROR("Failed to enable mutex clock: %d\n", ret); goto err_pm_runtime_put; @@ -281,11 +281,11 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, mtk_crtc->ddp_comp[i]->id, mtk_crtc->ddp_comp[i + 1]->id); - mtk_disp_mutex_add_comp(mtk_crtc->mutex, + mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); } - mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); - mtk_disp_mutex_enable(mtk_crtc->mutex); + mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); + mtk_mutex_enable(mtk_crtc->mutex); for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; @@ -314,7 +314,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) return 0; err_mutex_unprepare: - mtk_disp_mutex_unprepare(mtk_crtc->mutex); + mtk_mutex_unprepare(mtk_crtc->mutex); err_pm_runtime_put: pm_runtime_put(crtc->dev->dev); return ret; @@ -333,19 +333,19 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) } for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) - mtk_disp_mutex_remove_comp(mtk_crtc->mutex, + mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); - mtk_disp_mutex_disable(mtk_crtc->mutex); + mtk_mutex_disable(mtk_crtc->mutex); for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, mtk_crtc->ddp_comp[i]->id, mtk_crtc->ddp_comp[i + 1]->id); - mtk_disp_mutex_remove_comp(mtk_crtc->mutex, + mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); } - mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); + mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); mtk_crtc_ddp_clk_disable(mtk_crtc); - mtk_disp_mutex_unprepare(mtk_crtc->mutex); + mtk_mutex_unprepare(mtk_crtc->mutex); pm_runtime_put(drm->dev); @@ -457,9 +457,9 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) mtk_crtc->pending_async_planes = true; if (priv->data->shadow_register) { - mtk_disp_mutex_acquire(mtk_crtc->mutex); + mtk_mutex_acquire(mtk_crtc->mutex); mtk_crtc_ddp_config(crtc, NULL); - mtk_disp_mutex_release(mtk_crtc->mutex); + mtk_mutex_release(mtk_crtc->mutex); } #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (mtk_crtc->cmdq_client) { @@ -773,7 +773,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, if (!mtk_crtc->ddp_comp) return -ENOMEM; - mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); + mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev, pipe); if (IS_ERR(mtk_crtc->mutex)) { ret = PTR_ERR(mtk_crtc->mutex); dev_err(dev, "Failed to get mutex: %d\n", ret); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 25a24f69b986..b99a06e6834e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -588,7 +588,7 @@ static struct platform_driver mtk_drm_platform_driver = { }; static struct platform_driver * const mtk_drm_drivers[] = { - &mtk_ddp_driver, + &mtk_mutex_driver, &mtk_disp_color_driver, &mtk_disp_ovl_driver, &mtk_disp_rdma_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 690e92e9eff9..ae366868d01a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,7 +46,7 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; }; -extern struct platform_driver mtk_ddp_driver; +extern struct platform_driver mtk_mutex_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_ovl_driver; extern struct platform_driver mtk_disp_rdma_driver; diff --git a/drivers/gpu/drm/mediatek/mtk_mutex.c b/drivers/gpu/drm/mediatek/mtk_mutex.c index 1c8a253f4788..98a060bf225d 100644 --- a/drivers/gpu/drm/mediatek/mtk_mutex.c +++ b/drivers/gpu/drm/mediatek/mtk_mutex.c @@ -9,12 +9,12 @@ #include #include #include +#include -#include "mtk_drm_ddp_comp.h" #include "mtk_mutex.h" -#define MT2701_DISP_MUTEX0_MOD0 0x2c -#define MT2701_DISP_MUTEX0_SOF0 0x30 +#define MT2701_MUTEX0_MOD0 0x2c +#define MT2701_MUTEX0_SOF0 0x30 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) @@ -79,33 +79,32 @@ #define MT2701_MUTEX_MOD_DISP_RDMA0 10 #define MT2701_MUTEX_MOD_DISP_RDMA1 12 -#define MUTEX_SOF_SINGLE_MODE 0 -#define MUTEX_SOF_DSI0 1 -#define MUTEX_SOF_DSI1 2 -#define MUTEX_SOF_DPI0 3 -#define MUTEX_SOF_DPI1 4 -#define MUTEX_SOF_DSI2 5 -#define MUTEX_SOF_DSI3 6 -#define MT8167_MUTEX_SOF_DPI0 2 -#define MT8167_MUTEX_SOF_DPI1 3 - - -struct mtk_disp_mutex { +#define MT2712_MUTEX_SOF_SINGLE_MODE 0 +#define MT2712_MUTEX_SOF_DSI0 1 +#define MT2712_MUTEX_SOF_DSI1 2 +#define MT2712_MUTEX_SOF_DPI0 3 +#define MT2712_MUTEX_SOF_DPI1 4 +#define MT2712_MUTEX_SOF_DSI2 5 +#define MT2712_MUTEX_SOF_DSI3 6 +#define MT8167_MUTEX_SOF_DPI0 2 +#define MT8167_MUTEX_SOF_DPI1 3 + +struct mtk_mutex { int id; bool claimed; }; -enum mtk_ddp_mutex_sof_id { - DDP_MUTEX_SOF_SINGLE_MODE, - DDP_MUTEX_SOF_DSI0, - DDP_MUTEX_SOF_DSI1, - DDP_MUTEX_SOF_DPI0, - DDP_MUTEX_SOF_DPI1, - DDP_MUTEX_SOF_DSI2, - DDP_MUTEX_SOF_DSI3, +enum mtk_mutex_sof_id { + MUTEX_SOF_SINGLE_MODE, + MUTEX_SOF_DSI0, + MUTEX_SOF_DSI1, + MUTEX_SOF_DPI0, + MUTEX_SOF_DPI1, + MUTEX_SOF_DSI2, + MUTEX_SOF_DSI3, }; -struct mtk_ddp_data { +struct mtk_mutex_data { const unsigned int *mutex_mod; const unsigned int *mutex_sof; const unsigned int mutex_mod_reg; @@ -113,12 +112,12 @@ struct mtk_ddp_data { const bool no_clk; }; -struct mtk_ddp { +struct mtk_mutex_ctx { struct device *dev; struct clk *clk; void __iomem *regs; - struct mtk_disp_mutex mutex[10]; - const struct mtk_ddp_data *data; + struct mtk_mutex mutex[10]; + const struct mtk_mutex_data *data; }; static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { @@ -183,150 +182,150 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; -static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { - [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, - [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, - [DDP_MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, - [DDP_MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, - [DDP_MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, - [DDP_MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, - [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, +static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, + [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, + [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, + [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, + [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, + [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; -static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = { - [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, - [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, - [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, - [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, +static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, + [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, + [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, }; -static const struct mtk_ddp_data mt2701_ddp_driver_data = { +static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, }; -static const struct mtk_ddp_data mt2712_ddp_driver_data = { +static const struct mtk_mutex_data mt2712_mutex_driver_data = { .mutex_mod = mt2712_mutex_mod, .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, }; -static const struct mtk_ddp_data mt8167_ddp_driver_data = { +static const struct mtk_mutex_data mt8167_mutex_driver_data = { .mutex_mod = mt8167_mutex_mod, .mutex_sof = mt8167_mutex_sof, - .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, .no_clk = true, }; -static const struct mtk_ddp_data mt8173_ddp_driver_data = { +static const struct mtk_mutex_data mt8173_mutex_driver_data = { .mutex_mod = mt8173_mutex_mod, .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, }; -struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) +struct mtk_mutex *mtk_mutex_get(struct device *dev, unsigned int id) { - struct mtk_ddp *ddp = dev_get_drvdata(dev); + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); if (id >= 10) return ERR_PTR(-EINVAL); - if (ddp->mutex[id].claimed) + if (mtx->mutex[id].claimed) return ERR_PTR(-EBUSY); - ddp->mutex[id].claimed = true; + mtx->mutex[id].claimed = true; - return &ddp->mutex[id]; + return &mtx->mutex[id]; } -void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex) +void mtk_mutex_put(struct mtk_mutex *mutex) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); - WARN_ON(&ddp->mutex[mutex->id] != mutex); + WARN_ON(&mtx->mutex[mutex->id] != mutex); mutex->claimed = false; } -int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex) +int mtk_mutex_prepare(struct mtk_mutex *mutex) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - return clk_prepare_enable(ddp->clk); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + return clk_prepare_enable(mtx->clk); } -void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex) +void mtk_mutex_unprepare(struct mtk_mutex *mutex) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); - clk_disable_unprepare(ddp->clk); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + clk_disable_unprepare(mtx->clk); } -void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, - enum mtk_ddp_comp_id id) +void mtk_mutex_add_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); unsigned int reg; unsigned int sof_id; unsigned int offset; - WARN_ON(&ddp->mutex[mutex->id] != mutex); + WARN_ON(&mtx->mutex[mutex->id] != mutex); switch (id) { case DDP_COMPONENT_DSI0: - sof_id = DDP_MUTEX_SOF_DSI0; + sof_id = MUTEX_SOF_DSI0; break; case DDP_COMPONENT_DSI1: - sof_id = DDP_MUTEX_SOF_DSI0; + sof_id = MUTEX_SOF_DSI0; break; case DDP_COMPONENT_DSI2: - sof_id = DDP_MUTEX_SOF_DSI2; + sof_id = MUTEX_SOF_DSI2; break; case DDP_COMPONENT_DSI3: - sof_id = DDP_MUTEX_SOF_DSI3; + sof_id = MUTEX_SOF_DSI3; break; case DDP_COMPONENT_DPI0: - sof_id = DDP_MUTEX_SOF_DPI0; + sof_id = MUTEX_SOF_DPI0; break; case DDP_COMPONENT_DPI1: - sof_id = DDP_MUTEX_SOF_DPI1; + sof_id = MUTEX_SOF_DPI1; break; default: - if (ddp->data->mutex_mod[id] < 32) { - offset = DISP_REG_MUTEX_MOD(ddp->data->mutex_mod_reg, + if (mtx->data->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); - reg = readl_relaxed(ddp->regs + offset); - reg |= 1 << ddp->data->mutex_mod[id]; - writel_relaxed(reg, ddp->regs + offset); + reg = readl_relaxed(mtx->regs + offset); + reg |= 1 << mtx->data->mutex_mod[id]; + writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); - reg = readl_relaxed(ddp->regs + offset); - reg |= 1 << (ddp->data->mutex_mod[id] - 32); - writel_relaxed(reg, ddp->regs + offset); + reg = readl_relaxed(mtx->regs + offset); + reg |= 1 << (mtx->data->mutex_mod[id] - 32); + writel_relaxed(reg, mtx->regs + offset); } return; } - writel_relaxed(ddp->data->mutex_sof[sof_id], - ddp->regs + - DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, mutex->id)); + writel_relaxed(mtx->data->mutex_sof[sof_id], + mtx->regs + + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); } -void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, - enum mtk_ddp_comp_id id) +void mtk_mutex_remove_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); unsigned int reg; unsigned int offset; - WARN_ON(&ddp->mutex[mutex->id] != mutex); + WARN_ON(&mtx->mutex[mutex->id] != mutex); switch (id) { case DDP_COMPONENT_DSI0: @@ -336,129 +335,129 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, - ddp->regs + - DISP_REG_MUTEX_SOF(ddp->data->mutex_sof_reg, + mtx->regs + + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); break; default: - if (ddp->data->mutex_mod[id] < 32) { - offset = DISP_REG_MUTEX_MOD(ddp->data->mutex_mod_reg, + if (mtx->data->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); - reg = readl_relaxed(ddp->regs + offset); - reg &= ~(1 << ddp->data->mutex_mod[id]); - writel_relaxed(reg, ddp->regs + offset); + reg = readl_relaxed(mtx->regs + offset); + reg &= ~(1 << mtx->data->mutex_mod[id]); + writel_relaxed(reg, mtx->regs + offset); } else { offset = DISP_REG_MUTEX_MOD2(mutex->id); - reg = readl_relaxed(ddp->regs + offset); - reg &= ~(1 << (ddp->data->mutex_mod[id] - 32)); - writel_relaxed(reg, ddp->regs + offset); + reg = readl_relaxed(mtx->regs + offset); + reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); + writel_relaxed(reg, mtx->regs + offset); } break; } } -void mtk_disp_mutex_enable(struct mtk_disp_mutex *mutex) +void mtk_mutex_enable(struct mtk_mutex *mutex) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); - WARN_ON(&ddp->mutex[mutex->id] != mutex); + WARN_ON(&mtx->mutex[mutex->id] != mutex); - writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); + writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); } -void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex) +void mtk_mutex_disable(struct mtk_mutex *mutex) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); - WARN_ON(&ddp->mutex[mutex->id] != mutex); + WARN_ON(&mtx->mutex[mutex->id] != mutex); - writel(0, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); + writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); } -void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex) +void mtk_mutex_acquire(struct mtk_mutex *mutex) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); u32 tmp; - writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); - writel(1, ddp->regs + DISP_REG_MUTEX(mutex->id)); - if (readl_poll_timeout_atomic(ddp->regs + DISP_REG_MUTEX(mutex->id), + writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); + writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id)); + if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id), tmp, tmp & INT_MUTEX, 1, 10000)) pr_err("could not acquire mutex %d\n", mutex->id); } -void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex) +void mtk_mutex_release(struct mtk_mutex *mutex) { - struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, - mutex[mutex->id]); + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); - writel(0, ddp->regs + DISP_REG_MUTEX(mutex->id)); + writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id)); } -static int mtk_ddp_probe(struct platform_device *pdev) +static int mtk_mutex_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct mtk_ddp *ddp; + struct mtk_mutex_ctx *mtx; struct resource *regs; int i; - ddp = devm_kzalloc(dev, sizeof(*ddp), GFP_KERNEL); - if (!ddp) + mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL); + if (!mtx) return -ENOMEM; for (i = 0; i < 10; i++) - ddp->mutex[i].id = i; + mtx->mutex[i].id = i; - ddp->data = of_device_get_match_data(dev); + mtx->data = of_device_get_match_data(dev); - if (!ddp->data->no_clk) { - ddp->clk = devm_clk_get(dev, NULL); - if (IS_ERR(ddp->clk)) { - if (PTR_ERR(ddp->clk) != -EPROBE_DEFER) + if (!mtx->data->no_clk) { + mtx->clk = devm_clk_get(dev, NULL); + if (IS_ERR(mtx->clk)) { + if (PTR_ERR(mtx->clk) != -EPROBE_DEFER) dev_err(dev, "Failed to get clock\n"); - return PTR_ERR(ddp->clk); + return PTR_ERR(mtx->clk); } } regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ddp->regs = devm_ioremap_resource(dev, regs); - if (IS_ERR(ddp->regs)) { + mtx->regs = devm_ioremap_resource(dev, regs); + if (IS_ERR(mtx->regs)) { dev_err(dev, "Failed to map mutex registers\n"); - return PTR_ERR(ddp->regs); + return PTR_ERR(mtx->regs); } - platform_set_drvdata(pdev, ddp); + platform_set_drvdata(pdev, mtx); return 0; } -static int mtk_ddp_remove(struct platform_device *pdev) +static int mtk_mutex_remove(struct platform_device *pdev) { return 0; } -static const struct of_device_id ddp_driver_dt_match[] = { +static const struct of_device_id mutex_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-mutex", - .data = &mt2701_ddp_driver_data}, + .data = &mt2701_mutex_driver_data}, { .compatible = "mediatek,mt2712-disp-mutex", - .data = &mt2712_ddp_driver_data}, + .data = &mt2712_mutex_driver_data}, { .compatible = "mediatek,mt8167-disp-mutex", - .data = &mt8167_ddp_driver_data}, + .data = &mt8167_mutex_driver_data}, { .compatible = "mediatek,mt8173-disp-mutex", - .data = &mt8173_ddp_driver_data}, + .data = &mt8173_mutex_driver_data}, {}, }; -MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); +MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); -struct platform_driver mtk_ddp_driver = { - .probe = mtk_ddp_probe, - .remove = mtk_ddp_remove, +struct platform_driver mtk_mutex_driver = { + .probe = mtk_mutex_probe, + .remove = mtk_mutex_remove, .driver = { - .name = "mediatek-ddp", + .name = "mediatek-mutex", .owner = THIS_MODULE, - .of_match_table = ddp_driver_dt_match, + .of_match_table = mutex_driver_dt_match, }, }; diff --git a/drivers/gpu/drm/mediatek/mtk_mutex.h b/drivers/gpu/drm/mediatek/mtk_mutex.h index 3abcc20e88fb..b678e0988a37 100644 --- a/drivers/gpu/drm/mediatek/mtk_mutex.h +++ b/drivers/gpu/drm/mediatek/mtk_mutex.h @@ -8,19 +8,19 @@ struct regmap; struct device; -struct mtk_disp_mutex; +struct mtk_mutex; -struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id); -int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, - enum mtk_ddp_comp_id id); -void mtk_disp_mutex_enable(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, - enum mtk_ddp_comp_id id); -void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex); -void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex); +struct mtk_mutex *mtk_mutex_get(struct device *dev, unsigned int id); +int mtk_mutex_prepare(struct mtk_mutex *mutex); +void mtk_mutex_add_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id); +void mtk_mutex_enable(struct mtk_mutex *mutex); +void mtk_mutex_disable(struct mtk_mutex *mutex); +void mtk_mutex_remove_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id); +void mtk_mutex_unprepare(struct mtk_mutex *mutex); +void mtk_mutex_put(struct mtk_mutex *mutex); +void mtk_mutex_acquire(struct mtk_mutex *mutex); +void mtk_mutex_release(struct mtk_mutex *mutex); #endif /* MTK_MUTEX_H */ -- cgit v1.2.3 From 42a090b8459892efd97f79a3851928e4df452937 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Tue, 21 Jul 2020 11:30:11 +0800 Subject: drm/mediatek: Automatically search unclaimed mtk mutex in mtk_mutex_get() Moving mutex resource management from client driver to mutex driver could prevent client drivers negotiating for resource management. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +- drivers/gpu/drm/mediatek/mtk_mutex.c | 16 ++++++++-------- drivers/gpu/drm/mediatek/mtk_mutex.h | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index bba87a036fa8..1e3a9450680b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -773,7 +773,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, if (!mtk_crtc->ddp_comp) return -ENOMEM; - mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev, pipe); + mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev); if (IS_ERR(mtk_crtc->mutex)) { ret = PTR_ERR(mtk_crtc->mutex); dev_err(dev, "Failed to get mutex: %d\n", ret); diff --git a/drivers/gpu/drm/mediatek/mtk_mutex.c b/drivers/gpu/drm/mediatek/mtk_mutex.c index 98a060bf225d..66344759e622 100644 --- a/drivers/gpu/drm/mediatek/mtk_mutex.c +++ b/drivers/gpu/drm/mediatek/mtk_mutex.c @@ -228,18 +228,18 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = { .mutex_sof_reg = MT2701_MUTEX0_SOF0, }; -struct mtk_mutex *mtk_mutex_get(struct device *dev, unsigned int id) +struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); + int i; - if (id >= 10) - return ERR_PTR(-EINVAL); - if (mtx->mutex[id].claimed) - return ERR_PTR(-EBUSY); - - mtx->mutex[id].claimed = true; + for (i = 0; i < 10; i++) + if (!mtx->mutex[i].claimed) { + mtx->mutex[i].claimed = true; + return &mtx->mutex[i]; + } - return &mtx->mutex[id]; + return ERR_PTR(-EBUSY); } void mtk_mutex_put(struct mtk_mutex *mutex) diff --git a/drivers/gpu/drm/mediatek/mtk_mutex.h b/drivers/gpu/drm/mediatek/mtk_mutex.h index b678e0988a37..6fe4ffbde290 100644 --- a/drivers/gpu/drm/mediatek/mtk_mutex.h +++ b/drivers/gpu/drm/mediatek/mtk_mutex.h @@ -10,7 +10,7 @@ struct regmap; struct device; struct mtk_mutex; -struct mtk_mutex *mtk_mutex_get(struct device *dev, unsigned int id); +struct mtk_mutex *mtk_mutex_get(struct device *dev); int mtk_mutex_prepare(struct mtk_mutex *mutex); void mtk_mutex_add_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id); -- cgit v1.2.3 From e1e4f7fea37572f0ccf3887430e52c491e9accb6 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Tue, 21 Jul 2020 15:46:06 +0800 Subject: soc / drm: mediatek: Move mtk mutex driver to soc folder mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, so move it to soc folder. Signed-off-by: CK Hu Signed-off-by: Chun-Kuang Hu Acked-by: Matthias Brugger --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 2 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 - drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 - drivers/gpu/drm/mediatek/mtk_mutex.c | 463 ------------------------------- drivers/gpu/drm/mediatek/mtk_mutex.h | 26 -- drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-mutex.c | 474 ++++++++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-mutex.h | 26 ++ 9 files changed, 503 insertions(+), 494 deletions(-) delete mode 100644 drivers/gpu/drm/mediatek/mtk_mutex.c delete mode 100644 drivers/gpu/drm/mediatek/mtk_mutex.h create mode 100644 drivers/soc/mediatek/mtk-mutex.c create mode 100644 include/linux/soc/mediatek/mtk-mutex.h (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 09979c4c340a..01d06332f767 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -9,8 +9,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_drm_gem.o \ mtk_drm_plane.o \ mtk_dsi.o \ - mtk_dpi.o \ - mtk_mutex.o + mtk_dpi.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 1e3a9450680b..e9b6788d52cd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -22,7 +23,6 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_gem.h" #include "mtk_drm_plane.h" -#include "mtk_mutex.h" /* * struct mtk_drm_crtc - MediaTek specific crtc structure. diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b99a06e6834e..5d39dd54255d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -588,7 +588,6 @@ static struct platform_driver mtk_drm_platform_driver = { }; static struct platform_driver * const mtk_drm_drivers[] = { - &mtk_mutex_driver, &mtk_disp_color_driver, &mtk_disp_ovl_driver, &mtk_disp_rdma_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index ae366868d01a..e8238fa4aa2a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,7 +46,6 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; }; -extern struct platform_driver mtk_mutex_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_ovl_driver; extern struct platform_driver mtk_disp_rdma_driver; diff --git a/drivers/gpu/drm/mediatek/mtk_mutex.c b/drivers/gpu/drm/mediatek/mtk_mutex.c deleted file mode 100644 index 66344759e622..000000000000 --- a/drivers/gpu/drm/mediatek/mtk_mutex.c +++ /dev/null @@ -1,463 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015 MediaTek Inc. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "mtk_mutex.h" - -#define MT2701_MUTEX0_MOD0 0x2c -#define MT2701_MUTEX0_SOF0 0x30 - -#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) -#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) -#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) -#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) -#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) -#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) - -#define INT_MUTEX BIT(1) - -#define MT8167_MUTEX_MOD_DISP_PWM 1 -#define MT8167_MUTEX_MOD_DISP_OVL0 6 -#define MT8167_MUTEX_MOD_DISP_OVL1 7 -#define MT8167_MUTEX_MOD_DISP_RDMA0 8 -#define MT8167_MUTEX_MOD_DISP_RDMA1 9 -#define MT8167_MUTEX_MOD_DISP_WDMA0 10 -#define MT8167_MUTEX_MOD_DISP_CCORR 11 -#define MT8167_MUTEX_MOD_DISP_COLOR 12 -#define MT8167_MUTEX_MOD_DISP_AAL 13 -#define MT8167_MUTEX_MOD_DISP_GAMMA 14 -#define MT8167_MUTEX_MOD_DISP_DITHER 15 -#define MT8167_MUTEX_MOD_DISP_UFOE 16 - -#define MT8173_MUTEX_MOD_DISP_OVL0 11 -#define MT8173_MUTEX_MOD_DISP_OVL1 12 -#define MT8173_MUTEX_MOD_DISP_RDMA0 13 -#define MT8173_MUTEX_MOD_DISP_RDMA1 14 -#define MT8173_MUTEX_MOD_DISP_RDMA2 15 -#define MT8173_MUTEX_MOD_DISP_WDMA0 16 -#define MT8173_MUTEX_MOD_DISP_WDMA1 17 -#define MT8173_MUTEX_MOD_DISP_COLOR0 18 -#define MT8173_MUTEX_MOD_DISP_COLOR1 19 -#define MT8173_MUTEX_MOD_DISP_AAL 20 -#define MT8173_MUTEX_MOD_DISP_GAMMA 21 -#define MT8173_MUTEX_MOD_DISP_UFOE 22 -#define MT8173_MUTEX_MOD_DISP_PWM0 23 -#define MT8173_MUTEX_MOD_DISP_PWM1 24 -#define MT8173_MUTEX_MOD_DISP_OD 25 - -#define MT2712_MUTEX_MOD_DISP_PWM2 10 -#define MT2712_MUTEX_MOD_DISP_OVL0 11 -#define MT2712_MUTEX_MOD_DISP_OVL1 12 -#define MT2712_MUTEX_MOD_DISP_RDMA0 13 -#define MT2712_MUTEX_MOD_DISP_RDMA1 14 -#define MT2712_MUTEX_MOD_DISP_RDMA2 15 -#define MT2712_MUTEX_MOD_DISP_WDMA0 16 -#define MT2712_MUTEX_MOD_DISP_WDMA1 17 -#define MT2712_MUTEX_MOD_DISP_COLOR0 18 -#define MT2712_MUTEX_MOD_DISP_COLOR1 19 -#define MT2712_MUTEX_MOD_DISP_AAL0 20 -#define MT2712_MUTEX_MOD_DISP_UFOE 22 -#define MT2712_MUTEX_MOD_DISP_PWM0 23 -#define MT2712_MUTEX_MOD_DISP_PWM1 24 -#define MT2712_MUTEX_MOD_DISP_OD0 25 -#define MT2712_MUTEX_MOD2_DISP_AAL1 33 -#define MT2712_MUTEX_MOD2_DISP_OD1 34 - -#define MT2701_MUTEX_MOD_DISP_OVL 3 -#define MT2701_MUTEX_MOD_DISP_WDMA 6 -#define MT2701_MUTEX_MOD_DISP_COLOR 7 -#define MT2701_MUTEX_MOD_DISP_BLS 9 -#define MT2701_MUTEX_MOD_DISP_RDMA0 10 -#define MT2701_MUTEX_MOD_DISP_RDMA1 12 - -#define MT2712_MUTEX_SOF_SINGLE_MODE 0 -#define MT2712_MUTEX_SOF_DSI0 1 -#define MT2712_MUTEX_SOF_DSI1 2 -#define MT2712_MUTEX_SOF_DPI0 3 -#define MT2712_MUTEX_SOF_DPI1 4 -#define MT2712_MUTEX_SOF_DSI2 5 -#define MT2712_MUTEX_SOF_DSI3 6 -#define MT8167_MUTEX_SOF_DPI0 2 -#define MT8167_MUTEX_SOF_DPI1 3 - -struct mtk_mutex { - int id; - bool claimed; -}; - -enum mtk_mutex_sof_id { - MUTEX_SOF_SINGLE_MODE, - MUTEX_SOF_DSI0, - MUTEX_SOF_DSI1, - MUTEX_SOF_DPI0, - MUTEX_SOF_DPI1, - MUTEX_SOF_DSI2, - MUTEX_SOF_DSI3, -}; - -struct mtk_mutex_data { - const unsigned int *mutex_mod; - const unsigned int *mutex_sof; - const unsigned int mutex_mod_reg; - const unsigned int mutex_sof_reg; - const bool no_clk; -}; - -struct mtk_mutex_ctx { - struct device *dev; - struct clk *clk; - void __iomem *regs; - struct mtk_mutex mutex[10]; - const struct mtk_mutex_data *data; -}; - -static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, - [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, - [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, - [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, - [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, - [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, -}; - -static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, - [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, - [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, - [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, - [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, - [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, - [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, - [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, - [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, - [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, - [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, - [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, - [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, - [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, - [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, - [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, - [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, -}; - -static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, - [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, - [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, - [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER, - [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, - [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, - [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, - [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, - [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, - [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, - [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, - [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, -}; - -static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, - [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, - [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, - [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, - [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, - [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, - [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, - [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, - [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, - [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, - [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, - [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, - [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, - [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, - [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, -}; - -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { - [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, - [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, - [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, - [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, - [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, - [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, - [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, -}; - -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { - [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, - [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, - [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, - [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, -}; - -static const struct mtk_mutex_data mt2701_mutex_driver_data = { - .mutex_mod = mt2701_mutex_mod, - .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_MUTEX0_SOF0, -}; - -static const struct mtk_mutex_data mt2712_mutex_driver_data = { - .mutex_mod = mt2712_mutex_mod, - .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_MUTEX0_SOF0, -}; - -static const struct mtk_mutex_data mt8167_mutex_driver_data = { - .mutex_mod = mt8167_mutex_mod, - .mutex_sof = mt8167_mutex_sof, - .mutex_mod_reg = MT2701_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_MUTEX0_SOF0, - .no_clk = true, -}; - -static const struct mtk_mutex_data mt8173_mutex_driver_data = { - .mutex_mod = mt8173_mutex_mod, - .mutex_sof = mt2712_mutex_sof, - .mutex_mod_reg = MT2701_MUTEX0_MOD0, - .mutex_sof_reg = MT2701_MUTEX0_SOF0, -}; - -struct mtk_mutex *mtk_mutex_get(struct device *dev) -{ - struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); - int i; - - for (i = 0; i < 10; i++) - if (!mtx->mutex[i].claimed) { - mtx->mutex[i].claimed = true; - return &mtx->mutex[i]; - } - - return ERR_PTR(-EBUSY); -} - -void mtk_mutex_put(struct mtk_mutex *mutex) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - - WARN_ON(&mtx->mutex[mutex->id] != mutex); - - mutex->claimed = false; -} - -int mtk_mutex_prepare(struct mtk_mutex *mutex) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - return clk_prepare_enable(mtx->clk); -} - -void mtk_mutex_unprepare(struct mtk_mutex *mutex) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - clk_disable_unprepare(mtx->clk); -} - -void mtk_mutex_add_comp(struct mtk_mutex *mutex, - enum mtk_ddp_comp_id id) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - unsigned int reg; - unsigned int sof_id; - unsigned int offset; - - WARN_ON(&mtx->mutex[mutex->id] != mutex); - - switch (id) { - case DDP_COMPONENT_DSI0: - sof_id = MUTEX_SOF_DSI0; - break; - case DDP_COMPONENT_DSI1: - sof_id = MUTEX_SOF_DSI0; - break; - case DDP_COMPONENT_DSI2: - sof_id = MUTEX_SOF_DSI2; - break; - case DDP_COMPONENT_DSI3: - sof_id = MUTEX_SOF_DSI3; - break; - case DDP_COMPONENT_DPI0: - sof_id = MUTEX_SOF_DPI0; - break; - case DDP_COMPONENT_DPI1: - sof_id = MUTEX_SOF_DPI1; - break; - default: - if (mtx->data->mutex_mod[id] < 32) { - offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, - mutex->id); - reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << mtx->data->mutex_mod[id]; - writel_relaxed(reg, mtx->regs + offset); - } else { - offset = DISP_REG_MUTEX_MOD2(mutex->id); - reg = readl_relaxed(mtx->regs + offset); - reg |= 1 << (mtx->data->mutex_mod[id] - 32); - writel_relaxed(reg, mtx->regs + offset); - } - return; - } - - writel_relaxed(mtx->data->mutex_sof[sof_id], - mtx->regs + - DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); -} - -void mtk_mutex_remove_comp(struct mtk_mutex *mutex, - enum mtk_ddp_comp_id id) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - unsigned int reg; - unsigned int offset; - - WARN_ON(&mtx->mutex[mutex->id] != mutex); - - switch (id) { - case DDP_COMPONENT_DSI0: - case DDP_COMPONENT_DSI1: - case DDP_COMPONENT_DSI2: - case DDP_COMPONENT_DSI3: - case DDP_COMPONENT_DPI0: - case DDP_COMPONENT_DPI1: - writel_relaxed(MUTEX_SOF_SINGLE_MODE, - mtx->regs + - DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, - mutex->id)); - break; - default: - if (mtx->data->mutex_mod[id] < 32) { - offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, - mutex->id); - reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << mtx->data->mutex_mod[id]); - writel_relaxed(reg, mtx->regs + offset); - } else { - offset = DISP_REG_MUTEX_MOD2(mutex->id); - reg = readl_relaxed(mtx->regs + offset); - reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); - writel_relaxed(reg, mtx->regs + offset); - } - break; - } -} - -void mtk_mutex_enable(struct mtk_mutex *mutex) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - - WARN_ON(&mtx->mutex[mutex->id] != mutex); - - writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); -} - -void mtk_mutex_disable(struct mtk_mutex *mutex) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - - WARN_ON(&mtx->mutex[mutex->id] != mutex); - - writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); -} - -void mtk_mutex_acquire(struct mtk_mutex *mutex) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - u32 tmp; - - writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); - writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id)); - if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id), - tmp, tmp & INT_MUTEX, 1, 10000)) - pr_err("could not acquire mutex %d\n", mutex->id); -} - -void mtk_mutex_release(struct mtk_mutex *mutex) -{ - struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - - writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id)); -} - -static int mtk_mutex_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct mtk_mutex_ctx *mtx; - struct resource *regs; - int i; - - mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL); - if (!mtx) - return -ENOMEM; - - for (i = 0; i < 10; i++) - mtx->mutex[i].id = i; - - mtx->data = of_device_get_match_data(dev); - - if (!mtx->data->no_clk) { - mtx->clk = devm_clk_get(dev, NULL); - if (IS_ERR(mtx->clk)) { - if (PTR_ERR(mtx->clk) != -EPROBE_DEFER) - dev_err(dev, "Failed to get clock\n"); - return PTR_ERR(mtx->clk); - } - } - - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mtx->regs = devm_ioremap_resource(dev, regs); - if (IS_ERR(mtx->regs)) { - dev_err(dev, "Failed to map mutex registers\n"); - return PTR_ERR(mtx->regs); - } - - platform_set_drvdata(pdev, mtx); - - return 0; -} - -static int mtk_mutex_remove(struct platform_device *pdev) -{ - return 0; -} - -static const struct of_device_id mutex_driver_dt_match[] = { - { .compatible = "mediatek,mt2701-disp-mutex", - .data = &mt2701_mutex_driver_data}, - { .compatible = "mediatek,mt2712-disp-mutex", - .data = &mt2712_mutex_driver_data}, - { .compatible = "mediatek,mt8167-disp-mutex", - .data = &mt8167_mutex_driver_data}, - { .compatible = "mediatek,mt8173-disp-mutex", - .data = &mt8173_mutex_driver_data}, - {}, -}; -MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); - -struct platform_driver mtk_mutex_driver = { - .probe = mtk_mutex_probe, - .remove = mtk_mutex_remove, - .driver = { - .name = "mediatek-mutex", - .owner = THIS_MODULE, - .of_match_table = mutex_driver_dt_match, - }, -}; diff --git a/drivers/gpu/drm/mediatek/mtk_mutex.h b/drivers/gpu/drm/mediatek/mtk_mutex.h deleted file mode 100644 index 6fe4ffbde290..000000000000 --- a/drivers/gpu/drm/mediatek/mtk_mutex.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 MediaTek Inc. - */ - -#ifndef MTK_MUTEX_H -#define MTK_MUTEX_H - -struct regmap; -struct device; -struct mtk_mutex; - -struct mtk_mutex *mtk_mutex_get(struct device *dev); -int mtk_mutex_prepare(struct mtk_mutex *mutex); -void mtk_mutex_add_comp(struct mtk_mutex *mutex, - enum mtk_ddp_comp_id id); -void mtk_mutex_enable(struct mtk_mutex *mutex); -void mtk_mutex_disable(struct mtk_mutex *mutex); -void mtk_mutex_remove_comp(struct mtk_mutex *mutex, - enum mtk_ddp_comp_id id); -void mtk_mutex_unprepare(struct mtk_mutex *mutex); -void mtk_mutex_put(struct mtk_mutex *mutex); -void mtk_mutex_acquire(struct mtk_mutex *mutex); -void mtk_mutex_release(struct mtk_mutex *mutex); - -#endif /* MTK_MUTEX_H */ diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index b6908db534c2..90270f8114ed 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mtk-mutex.o diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c new file mode 100644 index 000000000000..f531b119da7a --- /dev/null +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -0,0 +1,474 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT2701_MUTEX0_MOD0 0x2c +#define MT2701_MUTEX0_SOF0 0x30 + +#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) +#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) +#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) +#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) + +#define INT_MUTEX BIT(1) + +#define MT8167_MUTEX_MOD_DISP_PWM 1 +#define MT8167_MUTEX_MOD_DISP_OVL0 6 +#define MT8167_MUTEX_MOD_DISP_OVL1 7 +#define MT8167_MUTEX_MOD_DISP_RDMA0 8 +#define MT8167_MUTEX_MOD_DISP_RDMA1 9 +#define MT8167_MUTEX_MOD_DISP_WDMA0 10 +#define MT8167_MUTEX_MOD_DISP_CCORR 11 +#define MT8167_MUTEX_MOD_DISP_COLOR 12 +#define MT8167_MUTEX_MOD_DISP_AAL 13 +#define MT8167_MUTEX_MOD_DISP_GAMMA 14 +#define MT8167_MUTEX_MOD_DISP_DITHER 15 +#define MT8167_MUTEX_MOD_DISP_UFOE 16 + +#define MT8173_MUTEX_MOD_DISP_OVL0 11 +#define MT8173_MUTEX_MOD_DISP_OVL1 12 +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 +#define MT8173_MUTEX_MOD_DISP_AAL 20 +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 +#define MT8173_MUTEX_MOD_DISP_UFOE 22 +#define MT8173_MUTEX_MOD_DISP_PWM0 23 +#define MT8173_MUTEX_MOD_DISP_PWM1 24 +#define MT8173_MUTEX_MOD_DISP_OD 25 + +#define MT2712_MUTEX_MOD_DISP_PWM2 10 +#define MT2712_MUTEX_MOD_DISP_OVL0 11 +#define MT2712_MUTEX_MOD_DISP_OVL1 12 +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 +#define MT2712_MUTEX_MOD_DISP_AAL0 20 +#define MT2712_MUTEX_MOD_DISP_UFOE 22 +#define MT2712_MUTEX_MOD_DISP_PWM0 23 +#define MT2712_MUTEX_MOD_DISP_PWM1 24 +#define MT2712_MUTEX_MOD_DISP_OD0 25 +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 +#define MT2712_MUTEX_MOD2_DISP_OD1 34 + +#define MT2701_MUTEX_MOD_DISP_OVL 3 +#define MT2701_MUTEX_MOD_DISP_WDMA 6 +#define MT2701_MUTEX_MOD_DISP_COLOR 7 +#define MT2701_MUTEX_MOD_DISP_BLS 9 +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 + +#define MT2712_MUTEX_SOF_SINGLE_MODE 0 +#define MT2712_MUTEX_SOF_DSI0 1 +#define MT2712_MUTEX_SOF_DSI1 2 +#define MT2712_MUTEX_SOF_DPI0 3 +#define MT2712_MUTEX_SOF_DPI1 4 +#define MT2712_MUTEX_SOF_DSI2 5 +#define MT2712_MUTEX_SOF_DSI3 6 +#define MT8167_MUTEX_SOF_DPI0 2 +#define MT8167_MUTEX_SOF_DPI1 3 + +struct mtk_mutex { + int id; + bool claimed; +}; + +enum mtk_mutex_sof_id { + MUTEX_SOF_SINGLE_MODE, + MUTEX_SOF_DSI0, + MUTEX_SOF_DSI1, + MUTEX_SOF_DPI0, + MUTEX_SOF_DPI1, + MUTEX_SOF_DSI2, + MUTEX_SOF_DSI3, +}; + +struct mtk_mutex_data { + const unsigned int *mutex_mod; + const unsigned int *mutex_sof; + const unsigned int mutex_mod_reg; + const unsigned int mutex_sof_reg; + const bool no_clk; +}; + +struct mtk_mutex_ctx { + struct device *dev; + struct clk *clk; + void __iomem *regs; + struct mtk_mutex mutex[10]; + const struct mtk_mutex_data *data; +}; + +static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, + [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, + [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, +}; + +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, +}; + +static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR, + [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR, + [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER, + [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA, + [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM, + [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0, +}; + +static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, + [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, + [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, + [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, +}; + +static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, + [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, + [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, + [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1, + [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2, + [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, +}; + +static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, + [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, + [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1, +}; + +static const struct mtk_mutex_data mt2701_mutex_driver_data = { + .mutex_mod = mt2701_mutex_mod, + .mutex_sof = mt2712_mutex_sof, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, +}; + +static const struct mtk_mutex_data mt2712_mutex_driver_data = { + .mutex_mod = mt2712_mutex_mod, + .mutex_sof = mt2712_mutex_sof, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, +}; + +static const struct mtk_mutex_data mt8167_mutex_driver_data = { + .mutex_mod = mt8167_mutex_mod, + .mutex_sof = mt8167_mutex_sof, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, + .no_clk = true, +}; + +static const struct mtk_mutex_data mt8173_mutex_driver_data = { + .mutex_mod = mt8173_mutex_mod, + .mutex_sof = mt2712_mutex_sof, + .mutex_mod_reg = MT2701_MUTEX0_MOD0, + .mutex_sof_reg = MT2701_MUTEX0_SOF0, +}; + +struct mtk_mutex *mtk_mutex_get(struct device *dev) +{ + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); + int i; + + for (i = 0; i < 10; i++) + if (!mtx->mutex[i].claimed) { + mtx->mutex[i].claimed = true; + return &mtx->mutex[i]; + } + + return ERR_PTR(-EBUSY); +} +EXPORT_SYMBOL_GPL(mtk_mutex_get); + +void mtk_mutex_put(struct mtk_mutex *mutex) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + mutex->claimed = false; +} +EXPORT_SYMBOL_GPL(mtk_mutex_put); + +int mtk_mutex_prepare(struct mtk_mutex *mutex) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + return clk_prepare_enable(mtx->clk); +} +EXPORT_SYMBOL_GPL(mtk_mutex_prepare); + +void mtk_mutex_unprepare(struct mtk_mutex *mutex) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + clk_disable_unprepare(mtx->clk); +} +EXPORT_SYMBOL_GPL(mtk_mutex_unprepare); + +void mtk_mutex_add_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + unsigned int reg; + unsigned int sof_id; + unsigned int offset; + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + switch (id) { + case DDP_COMPONENT_DSI0: + sof_id = MUTEX_SOF_DSI0; + break; + case DDP_COMPONENT_DSI1: + sof_id = MUTEX_SOF_DSI0; + break; + case DDP_COMPONENT_DSI2: + sof_id = MUTEX_SOF_DSI2; + break; + case DDP_COMPONENT_DSI3: + sof_id = MUTEX_SOF_DSI3; + break; + case DDP_COMPONENT_DPI0: + sof_id = MUTEX_SOF_DPI0; + break; + case DDP_COMPONENT_DPI1: + sof_id = MUTEX_SOF_DPI1; + break; + default: + if (mtx->data->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, + mutex->id); + reg = readl_relaxed(mtx->regs + offset); + reg |= 1 << mtx->data->mutex_mod[id]; + writel_relaxed(reg, mtx->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(mtx->regs + offset); + reg |= 1 << (mtx->data->mutex_mod[id] - 32); + writel_relaxed(reg, mtx->regs + offset); + } + return; + } + + writel_relaxed(mtx->data->mutex_sof[sof_id], + mtx->regs + + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); +} +EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); + +void mtk_mutex_remove_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + unsigned int reg; + unsigned int offset; + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + switch (id) { + case DDP_COMPONENT_DSI0: + case DDP_COMPONENT_DSI1: + case DDP_COMPONENT_DSI2: + case DDP_COMPONENT_DSI3: + case DDP_COMPONENT_DPI0: + case DDP_COMPONENT_DPI1: + writel_relaxed(MUTEX_SOF_SINGLE_MODE, + mtx->regs + + DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, + mutex->id)); + break; + default: + if (mtx->data->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, + mutex->id); + reg = readl_relaxed(mtx->regs + offset); + reg &= ~(1 << mtx->data->mutex_mod[id]); + writel_relaxed(reg, mtx->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(mtx->regs + offset); + reg &= ~(1 << (mtx->data->mutex_mod[id] - 32)); + writel_relaxed(reg, mtx->regs + offset); + } + break; + } +} +EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp); + +void mtk_mutex_enable(struct mtk_mutex *mutex) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); +} +EXPORT_SYMBOL_GPL(mtk_mutex_enable); + +void mtk_mutex_disable(struct mtk_mutex *mutex) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + + WARN_ON(&mtx->mutex[mutex->id] != mutex); + + writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); +} +EXPORT_SYMBOL_GPL(mtk_mutex_disable); + +void mtk_mutex_acquire(struct mtk_mutex *mutex) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + u32 tmp; + + writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id)); + writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id)); + if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id), + tmp, tmp & INT_MUTEX, 1, 10000)) + pr_err("could not acquire mutex %d\n", mutex->id); +} +EXPORT_SYMBOL_GPL(mtk_mutex_acquire); + +void mtk_mutex_release(struct mtk_mutex *mutex) +{ + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + + writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id)); +} +EXPORT_SYMBOL_GPL(mtk_mutex_release); + +static int mtk_mutex_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_mutex_ctx *mtx; + struct resource *regs; + int i; + + mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL); + if (!mtx) + return -ENOMEM; + + for (i = 0; i < 10; i++) + mtx->mutex[i].id = i; + + mtx->data = of_device_get_match_data(dev); + + if (!mtx->data->no_clk) { + mtx->clk = devm_clk_get(dev, NULL); + if (IS_ERR(mtx->clk)) { + if (PTR_ERR(mtx->clk) != -EPROBE_DEFER) + dev_err(dev, "Failed to get clock\n"); + return PTR_ERR(mtx->clk); + } + } + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mtx->regs = devm_ioremap_resource(dev, regs); + if (IS_ERR(mtx->regs)) { + dev_err(dev, "Failed to map mutex registers\n"); + return PTR_ERR(mtx->regs); + } + + platform_set_drvdata(pdev, mtx); + + return 0; +} + +static int mtk_mutex_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id mutex_driver_dt_match[] = { + { .compatible = "mediatek,mt2701-disp-mutex", + .data = &mt2701_mutex_driver_data}, + { .compatible = "mediatek,mt2712-disp-mutex", + .data = &mt2712_mutex_driver_data}, + { .compatible = "mediatek,mt8167-disp-mutex", + .data = &mt8167_mutex_driver_data}, + { .compatible = "mediatek,mt8173-disp-mutex", + .data = &mt8173_mutex_driver_data}, + {}, +}; +MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); + +struct platform_driver mtk_mutex_driver = { + .probe = mtk_mutex_probe, + .remove = mtk_mutex_remove, + .driver = { + .name = "mediatek-mutex", + .owner = THIS_MODULE, + .of_match_table = mutex_driver_dt_match, + }, +}; + +builtin_platform_driver(mtk_mutex_driver); diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h new file mode 100644 index 000000000000..6fe4ffbde290 --- /dev/null +++ b/include/linux/soc/mediatek/mtk-mutex.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015 MediaTek Inc. + */ + +#ifndef MTK_MUTEX_H +#define MTK_MUTEX_H + +struct regmap; +struct device; +struct mtk_mutex; + +struct mtk_mutex *mtk_mutex_get(struct device *dev); +int mtk_mutex_prepare(struct mtk_mutex *mutex); +void mtk_mutex_add_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id); +void mtk_mutex_enable(struct mtk_mutex *mutex); +void mtk_mutex_disable(struct mtk_mutex *mutex); +void mtk_mutex_remove_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id); +void mtk_mutex_unprepare(struct mtk_mutex *mutex); +void mtk_mutex_put(struct mtk_mutex *mutex); +void mtk_mutex_acquire(struct mtk_mutex *mutex); +void mtk_mutex_release(struct mtk_mutex *mutex); + +#endif /* MTK_MUTEX_H */ -- cgit v1.2.3 From a6b7c98afdcad0f149010ae028b24f2d0dc24cdb Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Fri, 29 Jan 2021 17:22:04 +0800 Subject: drm/mediatek: Add mtk_dither_set_common() function Current implementation of mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But other devices with different dev data would also call this function. Separate necessary parameters out so other device components (dither, gamma) can call this function. Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 27 ++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 46d199b7b4a2..9e5537f76b22 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_color_start(struct device *dev); +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, + unsigned int bpc, unsigned int cfg, + unsigned int dither_en, struct cmdq_pkt *cmdq_pkt); + void mtk_dpi_start(struct device *dev); void mtk_dpi_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7b5293429426..07804ab16f44 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -151,33 +151,42 @@ static void mtk_ddp_clk_disable(struct device *dev) clk_disable_unprepare(priv->clk); } -static void mtk_dither_set(struct device *dev, unsigned int bpc, - unsigned int CFG, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, + unsigned int bpc, unsigned int cfg, + unsigned int dither_en, struct cmdq_pkt *cmdq_pkt) +{ /* If bpc equal to 0, the dithering function didn't be enabled */ if (bpc == 0) return; if (bpc >= MTK_MIN_BPC) { - mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_5); - mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_7); + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | DITHER_NEW_BIT_MODE, - &priv->cmdq_reg, priv->regs, DISP_DITHER_15); + cmdq_reg, regs, DISP_DITHER_15); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), - &priv->cmdq_reg, priv->regs, DISP_DITHER_16); - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, &priv->cmdq_reg, priv->regs, CFG); + cmdq_reg, regs, DISP_DITHER_16); + mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg); } } +static void mtk_dither_set(struct device *dev, unsigned int bpc, + unsigned int cfg, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg, + DISP_DITHERING, cmdq_pkt); +} + static void mtk_od_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -- cgit v1.2.3 From 69a4237ab1d13acd7b35e9c7cb31a154fae35a34 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Fri, 29 Jan 2021 17:22:05 +0800 Subject: drm/mediatek: Separate gamma module mt8183 gamma module will different with mt8173, so separate gamma for adding private data. Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 10 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 190 ++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 71 ++--------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 216 insertions(+), 61 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 01d06332f767..b64674b94486 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 mediatek-drm-y := mtk_disp_color.o \ + mtk_disp_gamma.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ mtk_drm_crtc.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 9e5537f76b22..cdb0383f9906 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -27,6 +27,16 @@ void mtk_dpi_stop(struct device *dev); void mtk_dsi_ddp_start(struct device *dev); void mtk_dsi_ddp_stop(struct device *dev); +int mtk_gamma_clk_enable(struct device *dev); +void mtk_gamma_clk_disable(struct device *dev); +void mtk_gamma_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state); +void mtk_gamma_start(struct device *dev); +void mtk_gamma_stop(struct device *dev); + void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); void mtk_ovl_bypass_shadow(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c new file mode 100644 index 000000000000..6736dacc2c41 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_GAMMA_EN 0x0000 +#define GAMMA_EN BIT(0) +#define DISP_GAMMA_CFG 0x0020 +#define GAMMA_LUT_EN BIT(1) +#define GAMMA_DITHERING BIT(2) +#define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_LUT 0x0700 + +#define LUT_10BIT_MASK 0x03ff + +struct mtk_disp_gamma_data { + u32 reserved; +}; + +/** + * struct mtk_disp_gamma - DISP_GAMMA driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_gamma { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_gamma_data *data; +}; + +int mtk_gamma_clk_enable(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + return clk_prepare_enable(gamma->clk); +} + +void mtk_gamma_clk_disable(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + clk_disable_unprepare(gamma->clk); +} + +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state) +{ + unsigned int i, reg; + struct drm_color_lut *lut; + void __iomem *lut_base; + u32 word; + + if (state->gamma_lut) { + reg = readl(regs + DISP_GAMMA_CFG); + reg = reg | GAMMA_LUT_EN; + writel(reg, regs + DISP_GAMMA_CFG); + lut_base = regs + DISP_GAMMA_LUT; + lut = (struct drm_color_lut *)state->gamma_lut->data; + for (i = 0; i < MTK_LUT_SIZE; i++) { + word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + + ((lut[i].blue >> 6) & LUT_10BIT_MASK); + writel(word, (lut_base + i * 4)); + } + } +} + +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + mtk_gamma_set_common(gamma->regs, state); +} + +void mtk_gamma_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, + DISP_GAMMA_SIZE); + mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, + GAMMA_DITHERING, cmdq_pkt); +} + +void mtk_gamma_start(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + writel(GAMMA_EN, gamma->regs + DISP_GAMMA_EN); +} + +void mtk_gamma_stop(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + writel_relaxed(0x0, gamma->regs + DISP_GAMMA_EN); +} + +static int mtk_disp_gamma_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_gamma_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_gamma_component_ops = { + .bind = mtk_disp_gamma_bind, + .unbind = mtk_disp_gamma_unbind, +}; + +static int mtk_disp_gamma_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_gamma *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get gamma clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap gamma\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_disp_gamma_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_gamma_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_gamma_component_ops); + + return 0; +} + +static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { + { .compatible = "mediatek,mt8173-disp-gamma"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); + +struct platform_driver mtk_disp_gamma_driver = { + .probe = mtk_disp_gamma_probe, + .remove = mtk_disp_gamma_remove, + .driver = { + .name = "mediatek-disp-gamma", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_gamma_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 07804ab16f44..c730029ac8fc 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -55,11 +55,6 @@ #define DITHER_RELAY_MODE BIT(0) #define DISP_DITHER_SIZE 0x0030 -#define DISP_GAMMA_EN 0x0000 -#define DISP_GAMMA_CFG 0x0020 -#define DISP_GAMMA_SIZE 0x0030 -#define DISP_GAMMA_LUT 0x0700 - #define LUT_10BIT_MASK 0x03ff #define OD_RELAYMODE BIT(0) @@ -68,9 +63,6 @@ #define AAL_EN BIT(0) -#define GAMMA_EN BIT(0) -#define GAMMA_LUT_EN BIT(1) - #define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) @@ -151,7 +143,6 @@ static void mtk_ddp_clk_disable(struct device *dev) clk_disable_unprepare(priv->clk); } - void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, unsigned int bpc, unsigned int cfg, unsigned int dither_en, struct cmdq_pkt *cmdq_pkt) @@ -221,6 +212,13 @@ static void mtk_aal_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); } +static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_gamma_set_common(priv->regs, state); +} + static void mtk_aal_start(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); @@ -335,58 +333,10 @@ static void mtk_dither_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_DITHER_EN); } -static void mtk_gamma_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_GAMMA_SIZE); - mtk_dither_set(dev, bpc, DISP_GAMMA_CFG, cmdq_pkt); -} - -static void mtk_gamma_start(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel(GAMMA_EN, priv->regs + DISP_GAMMA_EN); -} - -static void mtk_gamma_stop(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel_relaxed(0x0, priv->regs + DISP_GAMMA_EN); -} - -static void mtk_gamma_set(struct device *dev, - struct drm_crtc_state *state) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - unsigned int i, reg; - struct drm_color_lut *lut; - void __iomem *lut_base; - u32 word; - - if (state->gamma_lut) { - reg = readl(priv->regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, priv->regs + DISP_GAMMA_CFG); - lut_base = priv->regs + DISP_GAMMA_LUT; - lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); - writel(word, (lut_base + i * 4)); - } - } -} - static const struct mtk_ddp_comp_funcs ddp_aal = { .clk_enable = mtk_ddp_clk_enable, .clk_disable = mtk_ddp_clk_disable, - .gamma_set = mtk_gamma_set, + .gamma_set = mtk_aal_gamma_set, .config = mtk_aal_config, .start = mtk_aal_start, .stop = mtk_aal_stop, @@ -427,8 +377,8 @@ static const struct mtk_ddp_comp_funcs ddp_dsi = { }; static const struct mtk_ddp_comp_funcs ddp_gamma = { - .clk_enable = mtk_ddp_clk_enable, - .clk_disable = mtk_ddp_clk_disable, + .clk_enable = mtk_gamma_clk_enable, + .clk_disable = mtk_gamma_clk_disable, .gamma_set = mtk_gamma_set, .config = mtk_gamma_config, .start = mtk_gamma_start, @@ -644,6 +594,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, if (type == MTK_DISP_BLS || type == MTK_DISP_COLOR || + type == MTK_DISP_GAMMA || type == MTK_DPI || type == MTK_DSI || type == MTK_DISP_OVL || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 5d39dd54255d..279d3e6f1156 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -486,11 +486,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node); /* - * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have + * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have * separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ if (comp_type == MTK_DISP_COLOR || + comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || comp_type == MTK_DISP_RDMA || @@ -589,6 +590,7 @@ static struct platform_driver mtk_drm_platform_driver = { static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_color_driver, + &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, &mtk_disp_rdma_driver, &mtk_dpi_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index e8238fa4aa2a..0e54e3d51014 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -47,6 +47,7 @@ struct mtk_drm_private { }; extern struct platform_driver mtk_disp_color_driver; +extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; extern struct platform_driver mtk_disp_rdma_driver; extern struct platform_driver mtk_dpi_driver; -- cgit v1.2.3 From 4a15d1ac37eaa1ecce14c76d10e5f66da600b54f Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Fri, 29 Jan 2021 17:22:06 +0800 Subject: drm/mediatek: Add has_dither private data for gamma Not all SoC has dither function in gamma module. Add private data to control this function setting. Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 6736dacc2c41..80e3918f0d0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -26,7 +26,7 @@ #define LUT_10BIT_MASK 0x03ff struct mtk_disp_gamma_data { - u32 reserved; + bool has_dither; }; /** @@ -92,8 +92,9 @@ void mtk_gamma_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE); - mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, - GAMMA_DITHERING, cmdq_pkt); + if (gamma->data && gamma->data->has_dither) + mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, + DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt); } void mtk_gamma_start(struct device *dev) @@ -173,8 +174,13 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev) return 0; } +static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { + .has_dither = true, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { - { .compatible = "mediatek,mt8173-disp-gamma"}, + { .compatible = "mediatek,mt8173-disp-gamma", + .data = &mt8173_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); -- cgit v1.2.3 From 641ef9e7be588e4262f7ed58abad12d446b41315 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Fri, 29 Jan 2021 17:22:09 +0800 Subject: drm/mediatek: Add support for SoC MT8183 1. Add ovl private data 2. Add rdma private data 3. Add gamma privte data 4. Add main and external path module for crtc create Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 1 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 45 +++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 80e3918f0d0d..3ebf91e0ab41 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -181,6 +181,7 @@ static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { { .compatible = "mediatek,mt8173-disp-gamma", .data = &mt8173_gamma_driver_data}, + { .compatible = "mediatek,mt8183-disp-gamma"}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 1c295c58a5e8..da7e38a28759 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -424,11 +424,29 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, +}; + +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, { .compatible = "mediatek,mt8173-disp-ovl", .data = &mt8173_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = &mt8183_ovl_driver_data}, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = &mt8183_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index b84004394970..728aaadfea8c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -351,11 +351,17 @@ static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .fifo_size = SZ_8K, }; +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, { .compatible = "mediatek,mt8173-disp-rdma", .data = &mt8173_rdma_driver_data}, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = &mt8183_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 279d3e6f1156..486e73e675ad 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -129,6 +129,24 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -161,6 +179,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { + .main_path = mt8183_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main), + .ext_path = mt8183_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -375,12 +400,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8183-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8183-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", @@ -389,22 +422,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-gamma", + .data = (void *)MTK_DISP_GAMMA, }, + { .compatible = "mediatek,mt8183-disp-dither", + .data = (void *)MTK_DISP_DITHER }, { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8183-dsi", + .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt2701-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8183-dpi", + .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8183-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", @@ -423,6 +466,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, + { .compatible = "mediatek,mt8183-mmsys", + .data = &mt8183_mmsys_driver_data}, { } }; -- cgit v1.2.3 From d41ff4dcf093885dcc253e3861834eea294827cb Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Fri, 29 Jan 2021 15:34:32 +0800 Subject: drm/mediatek: Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled. Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index da7e38a28759..961f87f8d4d1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -24,6 +24,7 @@ #define DISP_REG_OVL_RST 0x0014 #define DISP_REG_OVL_ROI_SIZE 0x0020 #define DISP_REG_OVL_DATAPATH_CON 0x0024 +#define OVL_LAYER_SMI_ID_EN BIT(0) #define OVL_BGCLR_SEL_IN BIT(2) #define DISP_REG_OVL_ROI_BGCLR 0x0028 #define DISP_REG_OVL_SRC_CON 0x002c @@ -62,6 +63,7 @@ struct mtk_disp_ovl_data { unsigned int gmc_bits; unsigned int layer_nr; bool fmt_rgb565_is_0; + bool smi_id_en; }; /** @@ -134,6 +136,13 @@ void mtk_ovl_start(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + if (ovl->data->smi_id_en) { + unsigned int reg; + + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); + reg = reg | OVL_LAYER_SMI_ID_EN; + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); + } writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN); } @@ -142,6 +151,14 @@ void mtk_ovl_stop(struct device *dev) struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN); + if (ovl->data->smi_id_en) { + unsigned int reg; + + reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON); + reg = reg & ~OVL_LAYER_SMI_ID_EN; + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON); + } + } void mtk_ovl_config(struct device *dev, unsigned int w, -- cgit v1.2.3 From 49629304b91fc7cdc484bb82047a8b97ae3978db Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Sun, 31 Jan 2021 13:10:58 +0800 Subject: drm/mediatek: Enable dither function Enable dither function to improve the display quality. Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index c730029ac8fc..1b1a30535462 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,6 +53,7 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 #define LUT_10BIT_MASK 0x03ff @@ -317,6 +318,8 @@ static void mtk_dither_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG, + DITHER_ENGINE_EN, cmdq_pkt); } static void mtk_dither_start(struct device *dev) -- cgit v1.2.3 From 072a4cb512e71cb82d65269319cce282237386ea Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Tue, 2 Feb 2021 16:12:33 +0800 Subject: drm/mediatek: Separate ccorr module ccorr ctm matrix bits will be different in mt8192. Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +----------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 236 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b94486..dc54a7a69005 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -mediatek-drm-y := mtk_disp_color.o \ +mediatek-drm-y := mtk_disp_ccorr.o \ + mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c new file mode 100644 index 000000000000..6ee2431e6b84 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_CCORR_EN 0x0000 +#define CCORR_EN BIT(0) +#define DISP_CCORR_CFG 0x0020 +#define CCORR_RELAY_MODE BIT(0) +#define CCORR_ENGINE_EN BIT(1) +#define CCORR_GAMMA_OFF BIT(2) +#define CCORR_WGAMUT_SRC_CLIP BIT(3) +#define DISP_CCORR_SIZE 0x0030 +#define DISP_CCORR_COEF_0 0x0080 +#define DISP_CCORR_COEF_1 0x0084 +#define DISP_CCORR_COEF_2 0x0088 +#define DISP_CCORR_COEF_3 0x008C +#define DISP_CCORR_COEF_4 0x0090 + +struct mtk_disp_ccorr_data { + u32 reserved; +}; + +/** + * struct mtk_disp_ccorr - DISP_CCORR driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_ccorr { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_ccorr_data *data; +}; + +int mtk_ccorr_clk_enable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + return clk_prepare_enable(ccorr->clk); +} + +void mtk_ccorr_clk_disable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + clk_disable_unprepare(ccorr->clk); +} + +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_CFG); +} + +void mtk_ccorr_start(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); +} + +void mtk_ccorr_stop(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); +} + +/* Converts a DRM S31.32 value to the HW S1.10 format. */ +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +{ + u16 r; + + /* Sign bit. */ + r = in & BIT_ULL(63) ? BIT(11) : 0; + + if ((in & GENMASK_ULL(62, 33)) > 0) { + /* identity value 0x100000000 -> 0x400, */ + /* if bigger this, set it to max 0x7ff. */ + r |= GENMASK(10, 0); + } else { + /* take the 11 most important bits. */ + r |= (in >> 22) & GENMASK(10, 0); + } + + return r; +} + +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + struct drm_property_blob *blob = state->ctm; + struct drm_color_ctm *ctm; + const u64 *input; + uint16_t coeffs[9] = { 0 }; + int i; + struct cmdq_pkt *cmdq_pkt = NULL; + + if (!blob) + return; + + ctm = (struct drm_color_ctm *)blob->data; + input = ctm->matrix; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); +} + +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_ccorr_component_ops = { + .bind = mtk_disp_ccorr_bind, + .unbind = mtk_disp_ccorr_unbind, +}; + +static int mtk_disp_ccorr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_ccorr *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get ccorr clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap ccorr\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_disp_ccorr_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_ccorr_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); + + return 0; +} + +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { + { .compatible = "mediatek,mt8183-disp-ccorr"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); + +struct platform_driver mtk_disp_ccorr_driver = { + .probe = mtk_disp_ccorr_probe, + .remove = mtk_disp_ccorr_remove, + .driver = { + .name = "mediatek-disp-ccorr", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_ccorr_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index cdb0383f9906..cafd9df2d63b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -9,6 +9,15 @@ #include #include "mtk_drm_plane.h" +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); +int mtk_ccorr_clk_enable(struct device *dev); +void mtk_ccorr_clk_disable(struct device *dev); +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_ccorr_start(struct device *dev); +void mtk_ccorr_stop(struct device *dev); + void mtk_color_bypass_shadow(struct device *dev); int mtk_color_clk_enable(struct device *dev); void mtk_color_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 1b1a30535462..75bc00e17fc4 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -35,20 +35,6 @@ #define DISP_AAL_EN 0x0000 #define DISP_AAL_SIZE 0x0030 -#define DISP_CCORR_EN 0x0000 -#define CCORR_EN BIT(0) -#define DISP_CCORR_CFG 0x0020 -#define CCORR_RELAY_MODE BIT(0) -#define CCORR_ENGINE_EN BIT(1) -#define CCORR_GAMMA_OFF BIT(2) -#define CCORR_WGAMUT_SRC_CLIP BIT(3) -#define DISP_CCORR_SIZE 0x0030 -#define DISP_CCORR_COEF_0 0x0080 -#define DISP_CCORR_COEF_1 0x0084 -#define DISP_CCORR_COEF_2 0x0088 -#define DISP_CCORR_COEF_3 0x008C -#define DISP_CCORR_COEF_4 0x0090 - #define DISP_DITHER_EN 0x0000 #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 @@ -234,82 +220,6 @@ static void mtk_aal_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_AAL_EN); } -static void mtk_ccorr_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); -} - -static void mtk_ccorr_start(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); -} - -static void mtk_ccorr_stop(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); -} - -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) -{ - u16 r; - - /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; - - if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ - /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); - } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); - } - - return r; -} - -static void mtk_ccorr_ctm_set(struct device *dev, - struct drm_crtc_state *state) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - struct drm_property_blob *blob = state->ctm; - struct drm_color_ctm *ctm; - const u64 *input; - uint16_t coeffs[9] = { 0 }; - int i; - struct cmdq_pkt *cmdq_pkt = NULL; - - if (!blob) - return; - - ctm = (struct drm_color_ctm *)blob->data; - input = ctm->matrix; - - for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); - - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); -} - static void mtk_dither_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -346,8 +256,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { }; static const struct mtk_ddp_comp_funcs ddp_ccorr = { - .clk_enable = mtk_ddp_clk_enable, - .clk_disable = mtk_ddp_clk_disable, + .clk_enable = mtk_ccorr_clk_enable, + .clk_disable = mtk_ccorr_clk_disable, .config = mtk_ccorr_config, .start = mtk_ccorr_start, .stop = mtk_ccorr_stop, @@ -596,6 +506,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, } if (type == MTK_DISP_BLS || + type == MTK_DISP_CCORR || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA || type == MTK_DPI || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad..b013d56d2777 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node); /* - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have - * separate component platform drivers and initialize their own + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI + * blocks have separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ - if (comp_type == MTK_DISP_COLOR || + if (comp_type == MTK_DISP_CCORR || + comp_type == MTK_DISP_COLOR || comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { }; static struct platform_driver * const mtk_drm_drivers[] = { + &mtk_disp_ccorr_driver, &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014..637f5669e895 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,7 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; }; +extern struct platform_driver mtk_disp_ccorr_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; -- cgit v1.2.3 From dff16681723d872308594875886d161a2f310d25 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Tue, 2 Feb 2021 16:12:34 +0800 Subject: drm/mediatek: Fix ccorr size config Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6ee2431e6b84..6c86673a835c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, { struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_SIZE); mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_CFG); -- cgit v1.2.3 From 738ed4156fbac6f6eb84c23b95cf25aa57707332 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Tue, 2 Feb 2021 16:12:35 +0800 Subject: drm/mediatek: Add matrix_bits private data for ccorr Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6c86673a835c..141cb36b9c07 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -30,7 +30,7 @@ #define DISP_CCORR_COEF_4 0x0090 struct mtk_disp_ccorr_data { - u32 reserved; + u32 matrix_bits; }; /** @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); } -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +/* Converts a DRM S31.32 value to the HW S1.n format. */ +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) { u16 r; /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ + /* identity value 0x100000000 -> 0x400(mt8183), */ + /* identity value 0x100000000 -> 0x800(mt8192), */ /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); + r |= GENMASK(n, 0); } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); + /* take the n+1 most important bits. */ + r |= (in >> (32 - n)) & GENMASK(n, 0); } return r; @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL; + u32 matrix_bits = ccorr->data->matrix_bits; if (!blob) return; @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) input = ctm->matrix; for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; } +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { + .matrix_bits = 10, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { - { .compatible = "mediatek,mt8183-disp-ccorr"}, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = &mt8183_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); -- cgit v1.2.3