From 3f724080a3e91d76ba6d5cacd3cf0a0cf16d121a Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 2 Nov 2011 12:53:44 +0100 Subject: MIPS: Alchemy: remove PB1000 support Noone seems to have test hardware or care anymore. Drop PB1000 support and along with it the old Alchemy PCMCIA socket driver. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: linux-pcmcia@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/2881/ Signed-off-by: Ralf Baechle --- drivers/net/irda/au1k_ir.c | 5 +- drivers/pcmcia/Kconfig | 4 - drivers/pcmcia/Makefile | 4 - drivers/pcmcia/au1000_generic.c | 545 ---------------------------------------- drivers/pcmcia/au1000_generic.h | 135 ---------- drivers/pcmcia/au1000_pb1x00.c | 294 ---------------------- 6 files changed, 1 insertion(+), 986 deletions(-) delete mode 100644 drivers/pcmcia/au1000_generic.c delete mode 100644 drivers/pcmcia/au1000_generic.h delete mode 100644 drivers/pcmcia/au1000_pb1x00.c (limited to 'drivers') diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index a3d696a9456a..d1a77ef9b9e8 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c @@ -32,10 +32,7 @@ #include #include #include -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) -#include -#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) -#include +#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) #include #else #error au1k_ir: unsupported board diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 6e318ce41136..c022b5cedcf9 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -155,10 +155,6 @@ config PCMCIA_M8XX This driver is also available as a module called m8xx_pcmcia. -config PCMCIA_AU1X00 - tristate "Au1x00 pcmcia support" - depends on MIPS_ALCHEMY && PCMCIA - config PCMCIA_ALCHEMY_DEVBOARD tristate "Alchemy Db/Pb1xxx PCMCIA socket services" depends on MIPS_ALCHEMY && PCMCIA diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 29935ea921df..ec543a4ff2e4 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_base.o sa1100_cs.o obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_base.o sa1111_cs.o obj-$(CONFIG_M32R_PCC) += m32r_pcc.o obj-$(CONFIG_M32R_CFC) += m32r_cfc.o -obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o @@ -39,9 +38,6 @@ obj-$(CONFIG_AT91_CF) += at91_cf.o obj-$(CONFIG_ELECTRA_CF) += electra_cf.o obj-$(CONFIG_PCMCIA_ALCHEMY_DEVBOARD) += db1xxx_ss.o -au1x00_ss-y += au1000_generic.o -au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o - sa1111_cs-y += sa1111_generic.o sa1111_cs-$(CONFIG_ASSABET_NEPONSET) += sa1100_neponset.o sa1111_cs-$(CONFIG_SA1100_BADGE4) += sa1100_badge4.o diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c deleted file mode 100644 index 95dd7c62741f..000000000000 --- a/drivers/pcmcia/au1000_generic.c +++ /dev/null @@ -1,545 +0,0 @@ -/* - * - * Alchemy Semi Au1000 pcmcia driver - * - * Copyright 2001-2003 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@embeddedalley.com or source@mvista.com - * - * Copyright 2004 Pete Popov, Embedded Alley Solutions, Inc. - * Updated the driver to 2.6. Followed the sa11xx API and largely - * copied many of the hardware independent functions. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include "au1000_generic.h" - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Pete Popov "); -MODULE_DESCRIPTION("Linux PCMCIA Card Services: Au1x00 Socket Controller"); - -#if 0 -#define debug(x,args...) printk(KERN_DEBUG "%s: " x, __func__ , ##args) -#else -#define debug(x,args...) -#endif - -#define MAP_SIZE 0x100000 -extern struct au1000_pcmcia_socket au1000_pcmcia_socket[]; -#define PCMCIA_SOCKET(x) (au1000_pcmcia_socket + (x)) -#define to_au1000_socket(x) container_of(x, struct au1000_pcmcia_socket, socket) - -/* Some boards like to support CF cards as IDE root devices, so they - * grab pcmcia sockets directly. - */ -u32 *pcmcia_base_vaddrs[2]; -extern const unsigned long mips_io_port_base; - -static DEFINE_MUTEX(pcmcia_sockets_lock); - -static int (*au1x00_pcmcia_hw_init[])(struct device *dev) = { - au1x_board_init, -}; - -static int -au1x00_pcmcia_skt_state(struct au1000_pcmcia_socket *skt) -{ - struct pcmcia_state state; - unsigned int stat; - - memset(&state, 0, sizeof(struct pcmcia_state)); - - skt->ops->socket_state(skt, &state); - - stat = state.detect ? SS_DETECT : 0; - stat |= state.ready ? SS_READY : 0; - stat |= state.wrprot ? SS_WRPROT : 0; - stat |= state.vs_3v ? SS_3VCARD : 0; - stat |= state.vs_Xv ? SS_XVCARD : 0; - stat |= skt->cs_state.Vcc ? SS_POWERON : 0; - - if (skt->cs_state.flags & SS_IOCARD) - stat |= state.bvd1 ? SS_STSCHG : 0; - else { - if (state.bvd1 == 0) - stat |= SS_BATDEAD; - else if (state.bvd2 == 0) - stat |= SS_BATWARN; - } - return stat; -} - -/* - * au100_pcmcia_config_skt - * - * Convert PCMCIA socket state to our socket configure structure. - */ -static int -au1x00_pcmcia_config_skt(struct au1000_pcmcia_socket *skt, socket_state_t *state) -{ - int ret; - - ret = skt->ops->configure_socket(skt, state); - if (ret == 0) { - skt->cs_state = *state; - } - - if (ret < 0) - debug("unable to configure socket %d\n", skt->nr); - - return ret; -} - -/* au1x00_pcmcia_sock_init() - * - * (Re-)Initialise the socket, turning on status interrupts - * and PCMCIA bus. This must wait for power to stabilise - * so that the card status signals report correctly. - * - * Returns: 0 - */ -static int au1x00_pcmcia_sock_init(struct pcmcia_socket *sock) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - - debug("initializing socket %u\n", skt->nr); - - skt->ops->socket_init(skt); - return 0; -} - -/* - * au1x00_pcmcia_suspend() - * - * Remove power on the socket, disable IRQs from the card. - * Turn off status interrupts, and disable the PCMCIA bus. - * - * Returns: 0 - */ -static int au1x00_pcmcia_suspend(struct pcmcia_socket *sock) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - - debug("suspending socket %u\n", skt->nr); - - skt->ops->socket_suspend(skt); - - return 0; -} - -static DEFINE_SPINLOCK(status_lock); - -/* - * au1x00_check_status() - */ -static void au1x00_check_status(struct au1000_pcmcia_socket *skt) -{ - unsigned int events; - - debug("entering PCMCIA monitoring thread\n"); - - do { - unsigned int status; - unsigned long flags; - - status = au1x00_pcmcia_skt_state(skt); - - spin_lock_irqsave(&status_lock, flags); - events = (status ^ skt->status) & skt->cs_state.csc_mask; - skt->status = status; - spin_unlock_irqrestore(&status_lock, flags); - - debug("events: %s%s%s%s%s%s\n", - events == 0 ? "" : "", - events & SS_DETECT ? "DETECT " : "", - events & SS_READY ? "READY " : "", - events & SS_BATDEAD ? "BATDEAD " : "", - events & SS_BATWARN ? "BATWARN " : "", - events & SS_STSCHG ? "STSCHG " : ""); - - if (events) - pcmcia_parse_events(&skt->socket, events); - } while (events); -} - -/* - * au1x00_pcmcia_poll_event() - * Let's poll for events in addition to IRQs since IRQ only is unreliable... - */ -static void au1x00_pcmcia_poll_event(unsigned long dummy) -{ - struct au1000_pcmcia_socket *skt = (struct au1000_pcmcia_socket *)dummy; - debug("polling for events\n"); - - mod_timer(&skt->poll_timer, jiffies + AU1000_PCMCIA_POLL_PERIOD); - - au1x00_check_status(skt); -} - -/* au1x00_pcmcia_get_status() - * - * From the sa11xx_core.c: - * Implements the get_status() operation for the in-kernel PCMCIA - * service (formerly SS_GetStatus in Card Services). Essentially just - * fills in bits in `status' according to internal driver state or - * the value of the voltage detect chipselect register. - * - * As a debugging note, during card startup, the PCMCIA core issues - * three set_socket() commands in a row the first with RESET deasserted, - * the second with RESET asserted, and the last with RESET deasserted - * again. Following the third set_socket(), a get_status() command will - * be issued. The kernel is looking for the SS_READY flag (see - * setup_socket(), reset_socket(), and unreset_socket() in cs.c). - * - * Returns: 0 - */ -static int -au1x00_pcmcia_get_status(struct pcmcia_socket *sock, unsigned int *status) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - - skt->status = au1x00_pcmcia_skt_state(skt); - *status = skt->status; - - return 0; -} - -/* au1x00_pcmcia_set_socket() - * Implements the set_socket() operation for the in-kernel PCMCIA - * service (formerly SS_SetSocket in Card Services). We more or - * less punt all of this work and let the kernel handle the details - * of power configuration, reset, &c. We also record the value of - * `state' in order to regurgitate it to the PCMCIA core later. - * - * Returns: 0 - */ -static int -au1x00_pcmcia_set_socket(struct pcmcia_socket *sock, socket_state_t *state) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - - debug("for sock %u\n", skt->nr); - - debug("\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n", - (state->csc_mask==0)?"":"", - (state->csc_mask&SS_DETECT)?"DETECT ":"", - (state->csc_mask&SS_READY)?"READY ":"", - (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"", - (state->csc_mask&SS_BATWARN)?"BATWARN ":"", - (state->csc_mask&SS_STSCHG)?"STSCHG ":"", - (state->flags==0)?"":"", - (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"", - (state->flags&SS_IOCARD)?"IOCARD ":"", - (state->flags&SS_RESET)?"RESET ":"", - (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"", - (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":""); - debug("\tVcc %d Vpp %d irq %d\n", - state->Vcc, state->Vpp, state->io_irq); - - return au1x00_pcmcia_config_skt(skt, state); -} - -int -au1x00_pcmcia_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *map) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - unsigned int speed; - - if(map->map>=MAX_IO_WIN){ - debug("map (%d) out of range\n", map->map); - return -1; - } - - if(map->flags&MAP_ACTIVE){ - speed=(map->speed>0)?map->speed:AU1000_PCMCIA_IO_SPEED; - skt->spd_io[map->map] = speed; - } - - map->start=(unsigned int)(u32)skt->virt_io; - map->stop=map->start+MAP_SIZE; - return 0; - -} /* au1x00_pcmcia_set_io_map() */ - - -static int -au1x00_pcmcia_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map) -{ - struct au1000_pcmcia_socket *skt = to_au1000_socket(sock); - unsigned short speed = map->speed; - - if(map->map>=MAX_WIN){ - debug("map (%d) out of range\n", map->map); - return -1; - } - - if (map->flags & MAP_ATTRIB) { - skt->spd_attr[map->map] = speed; - skt->spd_mem[map->map] = 0; - } else { - skt->spd_attr[map->map] = 0; - skt->spd_mem[map->map] = speed; - } - - if (map->flags & MAP_ATTRIB) { - map->static_start = skt->phys_attr + map->card_start; - } - else { - map->static_start = skt->phys_mem + map->card_start; - } - - debug("set_mem_map %d start %08lx card_start %08x\n", - map->map, map->static_start, map->card_start); - return 0; - -} /* au1x00_pcmcia_set_mem_map() */ - -static struct pccard_operations au1x00_pcmcia_operations = { - .init = au1x00_pcmcia_sock_init, - .suspend = au1x00_pcmcia_suspend, - .get_status = au1x00_pcmcia_get_status, - .set_socket = au1x00_pcmcia_set_socket, - .set_io_map = au1x00_pcmcia_set_io_map, - .set_mem_map = au1x00_pcmcia_set_mem_map, -}; - -static const char *skt_names[] = { - "PCMCIA socket 0", - "PCMCIA socket 1", -}; - -struct skt_dev_info { - int nskt; -}; - -int au1x00_pcmcia_socket_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr) -{ - struct skt_dev_info *sinfo; - struct au1000_pcmcia_socket *skt; - int ret, i; - - sinfo = kzalloc(sizeof(struct skt_dev_info), GFP_KERNEL); - if (!sinfo) { - ret = -ENOMEM; - goto out; - } - - sinfo->nskt = nr; - - /* - * Initialise the per-socket structure. - */ - for (i = 0; i < nr; i++) { - skt = PCMCIA_SOCKET(i); - memset(skt, 0, sizeof(*skt)); - - skt->socket.resource_ops = &pccard_static_ops; - skt->socket.ops = &au1x00_pcmcia_operations; - skt->socket.owner = ops->owner; - skt->socket.dev.parent = dev; - - init_timer(&skt->poll_timer); - skt->poll_timer.function = au1x00_pcmcia_poll_event; - skt->poll_timer.data = (unsigned long)skt; - skt->poll_timer.expires = jiffies + AU1000_PCMCIA_POLL_PERIOD; - - skt->nr = first + i; - skt->irq = 255; - skt->dev = dev; - skt->ops = ops; - - skt->res_skt.name = skt_names[skt->nr]; - skt->res_io.name = "io"; - skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; - skt->res_mem.name = "memory"; - skt->res_mem.flags = IORESOURCE_MEM; - skt->res_attr.name = "attribute"; - skt->res_attr.flags = IORESOURCE_MEM; - - /* - * PCMCIA client drivers use the inb/outb macros to access the - * IO registers. Since mips_io_port_base is added to the - * access address of the mips implementation of inb/outb, - * we need to subtract it here because we want to access the - * I/O or MEM address directly, without going through this - * "mips_io_port_base" mechanism. - */ - if (i == 0) { - skt->virt_io = (void *) - (ioremap((phys_t)AU1X_SOCK0_IO, 0x1000) - - (u32)mips_io_port_base); - skt->phys_attr = AU1X_SOCK0_PHYS_ATTR; - skt->phys_mem = AU1X_SOCK0_PHYS_MEM; - } - else { - skt->virt_io = (void *) - (ioremap((phys_t)AU1X_SOCK1_IO, 0x1000) - - (u32)mips_io_port_base); - skt->phys_attr = AU1X_SOCK1_PHYS_ATTR; - skt->phys_mem = AU1X_SOCK1_PHYS_MEM; - } - pcmcia_base_vaddrs[i] = (u32 *)skt->virt_io; - ret = ops->hw_init(skt); - - skt->socket.features = SS_CAP_STATIC_MAP|SS_CAP_PCCARD; - skt->socket.irq_mask = 0; - skt->socket.map_size = MAP_SIZE; - skt->socket.pci_irq = skt->irq; - skt->socket.io_offset = (unsigned long)skt->virt_io; - - skt->status = au1x00_pcmcia_skt_state(skt); - - ret = pcmcia_register_socket(&skt->socket); - if (ret) - goto out_err; - - WARN_ON(skt->socket.sock != i); - - add_timer(&skt->poll_timer); - } - - dev_set_drvdata(dev, sinfo); - return 0; - - -out_err: - ops->hw_shutdown(skt); - while (i-- > 0) { - skt = PCMCIA_SOCKET(i); - - del_timer_sync(&skt->poll_timer); - pcmcia_unregister_socket(&skt->socket); - if (i == 0) { - iounmap(skt->virt_io + (u32)mips_io_port_base); - skt->virt_io = NULL; - } -#ifndef CONFIG_MIPS_XXS1500 - else { - iounmap(skt->virt_io + (u32)mips_io_port_base); - skt->virt_io = NULL; - } -#endif - ops->hw_shutdown(skt); - - } - kfree(sinfo); -out: - return ret; -} - -int au1x00_drv_pcmcia_remove(struct platform_device *dev) -{ - struct skt_dev_info *sinfo = platform_get_drvdata(dev); - int i; - - mutex_lock(&pcmcia_sockets_lock); - platform_set_drvdata(dev, NULL); - - for (i = 0; i < sinfo->nskt; i++) { - struct au1000_pcmcia_socket *skt = PCMCIA_SOCKET(i); - - del_timer_sync(&skt->poll_timer); - pcmcia_unregister_socket(&skt->socket); - skt->ops->hw_shutdown(skt); - au1x00_pcmcia_config_skt(skt, &dead_socket); - iounmap(skt->virt_io + (u32)mips_io_port_base); - skt->virt_io = NULL; - } - - kfree(sinfo); - mutex_unlock(&pcmcia_sockets_lock); - return 0; -} - - -/* - * PCMCIA "Driver" API - */ - -static int au1x00_drv_pcmcia_probe(struct platform_device *dev) -{ - int i, ret = -ENODEV; - - mutex_lock(&pcmcia_sockets_lock); - for (i=0; i < ARRAY_SIZE(au1x00_pcmcia_hw_init); i++) { - ret = au1x00_pcmcia_hw_init[i](&dev->dev); - if (ret == 0) - break; - } - mutex_unlock(&pcmcia_sockets_lock); - return ret; -} - -static struct platform_driver au1x00_pcmcia_driver = { - .driver = { - .name = "au1x00-pcmcia", - .owner = THIS_MODULE, - }, - .probe = au1x00_drv_pcmcia_probe, - .remove = au1x00_drv_pcmcia_remove, -}; - - -/* au1x00_pcmcia_init() - * - * This routine performs low-level PCMCIA initialization and then - * registers this socket driver with Card Services. - * - * Returns: 0 on success, -ve error code on failure - */ -static int __init au1x00_pcmcia_init(void) -{ - int error = 0; - error = platform_driver_register(&au1x00_pcmcia_driver); - return error; -} - -/* au1x00_pcmcia_exit() - * Invokes the low-level kernel service to free IRQs associated with this - * socket controller and reset GPIO edge detection. - */ -static void __exit au1x00_pcmcia_exit(void) -{ - platform_driver_unregister(&au1x00_pcmcia_driver); -} - -module_init(au1x00_pcmcia_init); -module_exit(au1x00_pcmcia_exit); diff --git a/drivers/pcmcia/au1000_generic.h b/drivers/pcmcia/au1000_generic.h deleted file mode 100644 index 5c36bda2963b..000000000000 --- a/drivers/pcmcia/au1000_generic.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Alchemy Semi Au1000 pcmcia driver include file - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef __ASM_AU1000_PCMCIA_H -#define __ASM_AU1000_PCMCIA_H - -/* include the world */ - -#include -#include -#include "cs_internal.h" - -#define AU1000_PCMCIA_POLL_PERIOD (2*HZ) -#define AU1000_PCMCIA_IO_SPEED (255) -#define AU1000_PCMCIA_MEM_SPEED (300) - -#define AU1X_SOCK0_IO 0xF00000000ULL -#define AU1X_SOCK0_PHYS_ATTR 0xF40000000ULL -#define AU1X_SOCK0_PHYS_MEM 0xF80000000ULL - -/* pcmcia socket 1 needs external glue logic so the memory map - * differs from board to board. - */ -#if defined(CONFIG_MIPS_PB1000) -#define AU1X_SOCK1_IO 0xF08000000ULL -#define AU1X_SOCK1_PHYS_ATTR 0xF48000000ULL -#define AU1X_SOCK1_PHYS_MEM 0xF88000000ULL -#endif - -struct pcmcia_state { - unsigned detect: 1, - ready: 1, - wrprot: 1, - bvd1: 1, - bvd2: 1, - vs_3v: 1, - vs_Xv: 1; -}; - -struct pcmcia_configure { - unsigned sock: 8, - vcc: 8, - vpp: 8, - output: 1, - speaker: 1, - reset: 1; -}; - -struct pcmcia_irqs { - int sock; - int irq; - const char *str; -}; - - -struct au1000_pcmcia_socket { - struct pcmcia_socket socket; - - /* - * Info from low level handler - */ - struct device *dev; - unsigned int nr; - unsigned int irq; - - /* - * Core PCMCIA state - */ - struct pcmcia_low_level *ops; - - unsigned int status; - socket_state_t cs_state; - - unsigned short spd_io[MAX_IO_WIN]; - unsigned short spd_mem[MAX_WIN]; - unsigned short spd_attr[MAX_WIN]; - - struct resource res_skt; - struct resource res_io; - struct resource res_mem; - struct resource res_attr; - - void * virt_io; - unsigned int phys_io; - unsigned int phys_attr; - unsigned int phys_mem; - unsigned short speed_io, speed_attr, speed_mem; - - unsigned int irq_state; - - struct timer_list poll_timer; -}; - -struct pcmcia_low_level { - struct module *owner; - - int (*hw_init)(struct au1000_pcmcia_socket *); - void (*hw_shutdown)(struct au1000_pcmcia_socket *); - - void (*socket_state)(struct au1000_pcmcia_socket *, struct pcmcia_state *); - int (*configure_socket)(struct au1000_pcmcia_socket *, struct socket_state_t *); - - /* - * Enable card status IRQs on (re-)initialisation. This can - * be called at initialisation, power management event, or - * pcmcia event. - */ - void (*socket_init)(struct au1000_pcmcia_socket *); - - /* - * Disable card status IRQs and PCMCIA bus on suspend. - */ - void (*socket_suspend)(struct au1000_pcmcia_socket *); -}; - -extern int au1x_board_init(struct device *dev); - -#endif /* __ASM_AU1000_PCMCIA_H */ diff --git a/drivers/pcmcia/au1000_pb1x00.c b/drivers/pcmcia/au1000_pb1x00.c deleted file mode 100644 index b2396647a165..000000000000 --- a/drivers/pcmcia/au1000_pb1x00.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * - * Alchemy Semi Pb1000 boards specific pcmcia routines. - * - * Copyright 2002 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include - -#define debug(fmt, arg...) do { } while (0) - -#include -#define PCMCIA_IRQ AU1000_GPIO_15 - -static int pb1x00_pcmcia_init(struct pcmcia_init *init) -{ - u16 pcr; - pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST; - - au_writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */ - au_sync_delay(100); - au_writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */ - au_sync(); - - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0); - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1); - au_writel(pcr, PB1000_PCR); - au_sync_delay(20); - - return PCMCIA_NUM_SOCKS; -} - -static int pb1x00_pcmcia_shutdown(void) -{ - u16 pcr; - pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST; - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0); - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1); - au_writel(pcr, PB1000_PCR); - au_sync_delay(20); - return 0; -} - -static int -pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state) -{ - u32 inserted0, inserted1; - u16 vs0, vs1; - - vs0 = vs1 = (u16)au_readl(PB1000_ACR1); - inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2)); - inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2)); - vs0 = (vs0 >> 4) & 0x3; - vs1 = (vs1 >> 12) & 0x3; - - state->ready = 0; - state->vs_Xv = 0; - state->vs_3v = 0; - state->detect = 0; - - if (sock == 0) { - if (inserted0) { - switch (vs0) { - case 0: - case 2: - state->vs_3v=1; - break; - case 3: /* 5V */ - break; - default: - /* return without setting 'detect' */ - printk(KERN_ERR "pb1x00 bad VS (%d)\n", - vs0); - return 0; - } - state->detect = 1; - } - } - else { - if (inserted1) { - switch (vs1) { - case 0: - case 2: - state->vs_3v=1; - break; - case 3: /* 5V */ - break; - default: - /* return without setting 'detect' */ - printk(KERN_ERR "pb1x00 bad VS (%d)\n", - vs1); - return 0; - } - state->detect = 1; - } - } - - if (state->detect) { - state->ready = 1; - } - - state->bvd1=1; - state->bvd2=1; - state->wrprot=0; - return 1; -} - - -static int pb1x00_pcmcia_get_irq_info(struct pcmcia_irq_info *info) -{ - - if(info->sock > PCMCIA_MAX_SOCK) return -1; - - /* - * Even in the case of the Pb1000, both sockets are connected - * to the same irq line. - */ - info->irq = PCMCIA_IRQ; - - return 0; -} - - -static int -pb1x00_pcmcia_configure_socket(const struct pcmcia_configure *configure) -{ - u16 pcr; - - if(configure->sock > PCMCIA_MAX_SOCK) return -1; - - pcr = au_readl(PB1000_PCR); - - if (configure->sock == 0) { - pcr &= ~(PCR_SLOT_0_VCC0 | PCR_SLOT_0_VCC1 | - PCR_SLOT_0_VPP0 | PCR_SLOT_0_VPP1); - } - else { - pcr &= ~(PCR_SLOT_1_VCC0 | PCR_SLOT_1_VCC1 | - PCR_SLOT_1_VPP0 | PCR_SLOT_1_VPP1); - } - - pcr &= ~PCR_SLOT_0_RST; - debug("Vcc %dV Vpp %dV, pcr %x\n", - configure->vcc, configure->vpp, pcr); - switch(configure->vcc){ - case 0: /* Vcc 0 */ - switch(configure->vpp) { - case 0: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_GND, - configure->sock); - break; - case 12: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_12V, - configure->sock); - break; - case 50: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_5V, - configure->sock); - break; - case 33: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_3V, - configure->sock); - break; - default: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, - configure->sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __func__, - configure->vcc, - configure->vpp); - break; - } - break; - case 50: /* Vcc 5V */ - switch(configure->vpp) { - case 0: - pcr |= SET_VCC_VPP(VCC_5V,VPP_GND, - configure->sock); - break; - case 50: - pcr |= SET_VCC_VPP(VCC_5V,VPP_5V, - configure->sock); - break; - case 12: - pcr |= SET_VCC_VPP(VCC_5V,VPP_12V, - configure->sock); - break; - case 33: - pcr |= SET_VCC_VPP(VCC_5V,VPP_3V, - configure->sock); - break; - default: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, - configure->sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __func__, - configure->vcc, - configure->vpp); - break; - } - break; - case 33: /* Vcc 3.3V */ - switch(configure->vpp) { - case 0: - pcr |= SET_VCC_VPP(VCC_3V,VPP_GND, - configure->sock); - break; - case 50: - pcr |= SET_VCC_VPP(VCC_3V,VPP_5V, - configure->sock); - break; - case 12: - pcr |= SET_VCC_VPP(VCC_3V,VPP_12V, - configure->sock); - break; - case 33: - pcr |= SET_VCC_VPP(VCC_3V,VPP_3V, - configure->sock); - break; - default: - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ, - configure->sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __func__, - configure->vcc, - configure->vpp); - break; - } - break; - default: /* what's this ? */ - pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,configure->sock); - printk(KERN_ERR "%s: bad Vcc %d\n", - __func__, configure->vcc); - break; - } - - if (configure->sock == 0) { - pcr &= ~(PCR_SLOT_0_RST); - if (configure->reset) - pcr |= PCR_SLOT_0_RST; - } - else { - pcr &= ~(PCR_SLOT_1_RST); - if (configure->reset) - pcr |= PCR_SLOT_1_RST; - } - au_writel(pcr, PB1000_PCR); - au_sync_delay(300); - - return 0; -} - - -struct pcmcia_low_level pb1x00_pcmcia_ops = { - pb1x00_pcmcia_init, - pb1x00_pcmcia_shutdown, - pb1x00_pcmcia_socket_state, - pb1x00_pcmcia_get_irq_info, - pb1x00_pcmcia_configure_socket -}; -- cgit v1.2.3 From 809f36c6f4a0568178c909ff1096ca83eae33f7d Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Tue, 1 Nov 2011 20:03:30 +0100 Subject: MIPS: Alchemy: Au1300 SoC support Add basic support for the Au1300 variant(s): - New GPIO/Interrupt controller - DBDMA ids - USB setup - MMC support - enable various PSC drivers - detection code. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2866/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 4 + arch/mips/alchemy/common/Makefile | 3 +- arch/mips/alchemy/common/dbdma.c | 46 +++ arch/mips/alchemy/common/gpioint.c | 411 +++++++++++++++++++++++ arch/mips/alchemy/common/gpiolib.c | 42 +++ arch/mips/alchemy/common/platform.c | 31 +- arch/mips/alchemy/common/power.c | 3 + arch/mips/alchemy/common/sleeper.S | 73 ++++ arch/mips/alchemy/common/time.c | 1 + arch/mips/alchemy/common/vss.c | 84 +++++ arch/mips/include/asm/cpu.h | 1 + arch/mips/include/asm/mach-au1x00/au1000.h | 221 +++++++++++- arch/mips/include/asm/mach-au1x00/au1100_mmc.h | 2 + arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 31 ++ arch/mips/include/asm/mach-au1x00/gpio-au1300.h | 241 +++++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 3 + arch/mips/kernel/cpu-probe.c | 7 + drivers/i2c/busses/Kconfig | 4 +- drivers/mmc/host/au1xmmc.c | 45 ++- drivers/spi/Kconfig | 4 +- drivers/usb/host/alchemy-common.c | 277 +++++++++++++++ drivers/usb/host/ohci-au1xxx.c | 13 +- drivers/video/Kconfig | 8 +- sound/soc/au1x/Kconfig | 6 +- 24 files changed, 1514 insertions(+), 47 deletions(-) create mode 100644 arch/mips/alchemy/common/gpioint.c create mode 100644 arch/mips/alchemy/common/vss.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1300.h (limited to 'drivers') diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 36df5e2c8e07..766badaef3b0 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -2,6 +2,10 @@ config ALCHEMY_GPIOINT_AU1000 bool +# au1300-style GPIO/INT controller +config ALCHEMY_GPIOINT_AU1300 + bool + # select this in your board config if you don't want to use the gpio # namespace as documented in the manuals. In this case however you need # to create the necessary gpio_* functions in your board code/headers! diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 811ece7b22e3..d3f5c5137804 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -6,9 +6,10 @@ # obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o + sleeper.o dma.o dbdma.o vss.o obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o +obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpioint.o # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 0e63ee487d6d..c723ec1d3b2c 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -148,6 +148,50 @@ static dbdev_tab_t au1200_dbdev_tab[] __initdata = { { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, }; +static dbdev_tab_t au1300_dbdev_tab[] __initdata = { + { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 }, + { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 }, + { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 }, + { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, +}; + /* 32 predefined plus 32 custom */ #define DBDEV_TAB_SIZE 64 @@ -1038,6 +1082,8 @@ static int __init alchemy_dbdma_init(void) return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab); case ALCHEMY_CPU_AU1200: return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab); + case ALCHEMY_CPU_AU1300: + return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab); } return 0; } diff --git a/arch/mips/alchemy/common/gpioint.c b/arch/mips/alchemy/common/gpioint.c new file mode 100644 index 000000000000..b8cd3364ff69 --- /dev/null +++ b/arch/mips/alchemy/common/gpioint.c @@ -0,0 +1,411 @@ +/* + * gpioint.c - Au1300 GPIO+Interrupt controller (I call it "GPIC") support. + * + * Copyright (c) 2009-2011 Manuel Lauss + * + * licensed under the GPLv2. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static int au1300_gpic_settype(struct irq_data *d, unsigned int type); + +/* setup for known onchip sources */ +struct gpic_devint_data { + int irq; /* linux IRQ number */ + int type; /* IRQ_TYPE_ */ + int prio; /* irq priority, 0 highest, 3 lowest */ + int internal; /* internal source (no ext. pin)? */ +}; + +static const struct gpic_devint_data au1300_devints[] __initdata = { + /* multifunction: gpio pin or device */ + { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + /* au1300 internal */ + { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, }, + { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { -1, }, /* terminator */ +}; + + +/* + * au1300_gpic_chgcfg - change PIN configuration. + * @gpio: pin to change (0-based GPIO number from datasheet). + * @clr: clear all bits set in 'clr'. + * @set: set these bits. + * + * modifies a pins' configuration register, bits set in @clr will + * be cleared in the register, bits in @set will be set. + */ +static inline void au1300_gpic_chgcfg(unsigned int gpio, + unsigned long clr, + unsigned long set) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long l; + + r += gpio * 4; /* offset into pin config array */ + l = __raw_readl(r + AU1300_GPIC_PINCFG); + l &= ~clr; + l |= set; + __raw_writel(l, r + AU1300_GPIC_PINCFG); + wmb(); +} + +/* + * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl). + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to the GPIO controller, so its level can either + * be read or set through the generic GPIO functions. + * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1). + * REVISIT: is this function really necessary? + */ +void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio) +{ + au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio); + +/* + * au1300_pinfunc_to_dev - assign a pin to the device function. + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to its associated device function; the pin will be + * driven by the device and not through GPIO functions. + */ +void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + r += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, r + AU1300_GPIC_DEVSEL); + wmb(); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev); + +/* + * au1300_set_irq_priority - set internal priority of IRQ. + * @irq: irq to set priority (linux irq number). + * @p: priority (0 = highest, 3 = lowest). + */ +void au1300_set_irq_priority(unsigned int irq, int p) +{ + irq -= ALCHEMY_GPIC_INT_BASE; + au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p)); +} +EXPORT_SYMBOL_GPL(au1300_set_irq_priority); + +/* + * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers. + * @dchan: dbdma trigger select (0, 1). + * @gpio: pin to assign as trigger. + * + * DBDMA controller has 2 external trigger sources; this function + * assigns a GPIO to the selected trigger. + */ +void au1300_set_dbdma_gpio(int dchan, unsigned int gpio) +{ + unsigned long r; + + if ((dchan >= 0) && (dchan <= 1)) { + r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + r &= ~(0xff << (8 * dchan)); + r |= (gpio & 0x7f) << (8 * dchan); + __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + wmb(); + } +} + +/**********************************************************************/ + +static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow) +{ + au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE, + allow ? GPIC_CFG_IDLEWAKE : 0); +} + +static void au1300_gpic_mask(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IDIS); + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_unmask(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + + gpic_pin_set_idlewake(irq, 1); + + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IEN); + wmb(); +} + +static void au1300_gpic_maskack(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + __raw_writel(bit, r + AU1300_GPIC_IDIS); /* mask */ + wmb(); + + gpic_pin_set_idlewake(irq, 0); +} + +static void au1300_gpic_ack(struct irq_data *d) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit, irq = d->irq; + + irq -= ALCHEMY_GPIC_INT_BASE; + r += GPIC_GPIO_BANKOFF(irq); + bit = GPIC_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + wmb(); +} + +static struct irq_chip au1300_gpic = { + .name = "GPIOINT", + .irq_ack = au1300_gpic_ack, + .irq_mask = au1300_gpic_mask, + .irq_mask_ack = au1300_gpic_maskack, + .irq_unmask = au1300_gpic_unmask, + .irq_set_type = au1300_gpic_settype, +}; + +static int au1300_gpic_settype(struct irq_data *d, unsigned int type) +{ + unsigned long s; + unsigned char *name = NULL; + irq_flow_handler_t hdl = NULL; + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + s = GPIC_CFG_IC_LEVEL_HIGH; + name = "high"; + hdl = handle_level_irq; + break; + case IRQ_TYPE_LEVEL_LOW: + s = GPIC_CFG_IC_LEVEL_LOW; + name = "low"; + hdl = handle_level_irq; + break; + case IRQ_TYPE_EDGE_RISING: + s = GPIC_CFG_IC_EDGE_RISE; + name = "posedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_EDGE_FALLING: + s = GPIC_CFG_IC_EDGE_FALL; + name = "negedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_EDGE_BOTH: + s = GPIC_CFG_IC_EDGE_BOTH; + name = "bothedge"; + hdl = handle_edge_irq; + break; + case IRQ_TYPE_NONE: + s = GPIC_CFG_IC_OFF; + name = "disabled"; + hdl = handle_level_irq; + break; + default: + return -EINVAL; + } + + __irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name); + + au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s); + + return 0; +} + +static void __init alchemy_gpic_init_irq(const struct gpic_devint_data *dints) +{ + int i; + void __iomem *bank_base; + + mips_cpu_irq_init(); + + /* disable & ack all possible interrupt sources */ + for (i = 0; i < 4; i++) { + bank_base = AU1300_GPIC_ADDR + (i * 4); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS); + wmb(); + __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND); + wmb(); + } + + /* register an irq_chip for them, with 2nd highest priority */ + for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) { + au1300_set_irq_priority(i, 1); + au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); + } + + /* setup known on-chip sources */ + while ((i = dints->irq) != -1) { + au1300_gpic_settype(irq_get_irq_data(i), dints->type); + au1300_set_irq_priority(i, dints->prio); + + if (dints->internal) + au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE); + + dints++; + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); +} + +static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6]; + +static int alchemy_gpic_suspend(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; + + /* save 4 interrupt mask status registers */ + alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0); + alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4); + alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8); + alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc); + + /* save misc register(s) */ + alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL); + + /* molto silenzioso */ + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); + wmb(); + + /* save pin/int-type configuration */ + base += AU1300_GPIC_PINCFG; + for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++) + alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2)); + + wmb(); + + return 0; +} + +static void alchemy_gpic_resume(void) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + int i; + + /* disable all first */ + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8); + __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc); + wmb(); + + /* restore pin/int-type configurations */ + base += AU1300_GPIC_PINCFG; + for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++) + __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2)); + wmb(); + + /* restore misc register(s) */ + base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR); + __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL); + wmb(); + + /* finally restore masks */ + __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0); + __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4); + __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8); + __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc); + wmb(); +} + +static struct syscore_ops alchemy_gpic_pmops = { + .suspend = alchemy_gpic_suspend, + .resume = alchemy_gpic_resume, +}; + +/**********************************************************************/ + +void __init arch_init_irq(void) +{ + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + alchemy_gpic_init_irq(&au1300_devints[0]); + register_syscore_ops(&alchemy_gpic_pmops); + break; + } +} + +#define CAUSEF_GPIC (CAUSEF_IP2 | CAUSEF_IP3 | CAUSEF_IP4 | CAUSEF_IP5) + +void plat_irq_dispatch(void) +{ + unsigned long i, c = read_c0_cause() & read_c0_status(); + + if (c & CAUSEF_IP7) /* c0 timer */ + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (likely(c & CAUSEF_GPIC)) { + i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC); + do_IRQ(i + ALCHEMY_GPIC_INT_BASE); + } else + spurious_interrupt(); +} diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c index 91fb4d9e30fd..f1b50f0c01db 100644 --- a/arch/mips/alchemy/common/gpiolib.c +++ b/arch/mips/alchemy/common/gpiolib.c @@ -27,6 +27,7 @@ * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! * au1000 SoC have only one GPIO block : GPIO1 * Au1100, Au15x0, Au12x0 have a second one : GPIO2 + * Au1300 is totally different: 1 block with up to 128 GPIOs */ #include @@ -35,6 +36,7 @@ #include #include #include +#include static int gpio2_get(struct gpio_chip *chip, unsigned offset) { @@ -115,6 +117,43 @@ struct gpio_chip alchemy_gpio_chip[] = { }, }; +static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_get_value(off + AU1300_GPIO_BASE); +} + +static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v) +{ + au1300_gpio_set_value(off + AU1300_GPIO_BASE, v); +} + +static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_direction_input(off + AU1300_GPIO_BASE); +} + +static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off, + int v) +{ + return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v); +} + +static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_to_irq(off + AU1300_GPIO_BASE); +} + +static struct gpio_chip au1300_gpiochip = { + .label = "alchemy-gpic", + .direction_input = alchemy_gpic_dir_input, + .direction_output = alchemy_gpic_dir_output, + .get = alchemy_gpic_get, + .set = alchemy_gpic_set, + .to_irq = alchemy_gpic_gpio_to_irq, + .base = AU1300_GPIO_BASE, + .ngpio = AU1300_GPIO_NUM, +}; + static int __init alchemy_gpiochip_init(void) { int ret = 0; @@ -127,6 +166,9 @@ static int __init alchemy_gpiochip_init(void) ret = gpiochip_add(&alchemy_gpio_chip[0]); ret |= gpiochip_add(&alchemy_gpio_chip[1]); break; + case ALCHEMY_CPU_AU1300: + ret = gpiochip_add(&au1300_gpiochip); + break; } return ret; } diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index c8e5d72a5826..95cb9113b12c 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -82,6 +82,12 @@ static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = { PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), }, + [ALCHEMY_CPU_AU1300] = { + PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT), + PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT), + PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT), + PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT), + }, }; static struct platform_device au1xx0_uart_device = { @@ -122,10 +128,12 @@ static unsigned long alchemy_ohci_data[][2] __initdata = { [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT }, [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT }, [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT }, + [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT }, }; static unsigned long alchemy_ehci_data[][2] __initdata = { [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT }, + [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT }, }; static int __init _new_usbres(struct resource **r, struct platform_device **d) @@ -169,8 +177,8 @@ static void __init alchemy_setup_usb(int ctype) printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n"); - /* setup EHCI0: Au1200 */ - if (ctype == ALCHEMY_CPU_AU1200) { + /* setup EHCI0: Au1200/Au1300 */ + if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) { if (_new_usbres(&res, &pdev)) return; @@ -187,6 +195,25 @@ static void __init alchemy_setup_usb(int ctype) if (platform_device_register(pdev)) printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n"); } + + /* Au1300: OHCI1 */ + if (ctype == ALCHEMY_CPU_AU1300) { + if (_new_usbres(&res, &pdev)) + return; + + res[0].start = AU1300_USB_OHCI1_PHYS_ADDR; + res[0].end = res[0].start + 0x100 - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = AU1300_USB_INT; + res[1].end = res[1].start; + res[1].flags = IORESOURCE_IRQ; + pdev->name = "au1xxx-ohci"; + pdev->id = 1; + pdev->dev.dma_mask = &alchemy_ohci_dmamask; + + if (platform_device_register(pdev)) + printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n"); + } } /* Macro to help defining the Ethernet MAC resources */ diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index bdd6651e9a4f..0c7fce2a3c12 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -126,6 +126,9 @@ void au_sleep(void) case ALCHEMY_CPU_AU1200: alchemy_sleep_au1550(); break; + case ALCHEMY_CPU_AU1300: + alchemy_sleep_au1300(); + break; } restore_core_regs(); diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S index 77f3c743b716..c7bcc7e5c822 100644 --- a/arch/mips/alchemy/common/sleeper.S +++ b/arch/mips/alchemy/common/sleeper.S @@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550) END(alchemy_sleep_au1550) +/* sleepcode for Au1300 memory controller type */ +LEAF(alchemy_sleep_au1300) + + SETUP_SLEEP + + /* cache following instructions, as memory gets put to sleep */ + la t0, 2f + la t1, 4f + subu t2, t1, t0 + + .set mips3 + +1: cache 0x14, 0(t0) + subu t2, t2, 32 + bgez t2, 1b + addu t0, t0, 32 + + .set mips0 + +2: lui a0, 0xb400 /* mem_xxx */ + + /* disable all ports in mem_sdportcfga */ + sw zero, 0x868(a0) /* mem_sdportcfga */ + sync + + /* disable ODT */ + li t0, 0x03010000 + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sync + + /* precharge */ + li t0, 0x23000400 + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sync + + /* auto refresh */ + sw zero, 0x08c8(a0) /* mem_sdautoref */ + sync + + /* block access to the DDR */ + lw t0, 0x0848(a0) /* mem_sdconfigb */ + li t1, (1 << 7 | 0x3F) + or t0, t0, t1 + sw t0, 0x0848(a0) /* mem_sdconfigb */ + sync + + /* issue the Self Refresh command */ + li t0, 0x10000000 + sw t0, 0x08dc(a0) /* mem_sdcmd1 */ + sw t0, 0x08d8(a0) /* mem_sdcmd0 */ + sync + + /* wait for sdram to enter self-refresh mode */ + lui t0, 0x0300 +3: lw t1, 0x0850(a0) /* mem_sdstat */ + and t2, t1, t0 + bne t2, t0, 3b + nop + + /* disable SDRAM clocks */ + li t0, ~(3<<28) + lw t1, 0x0840(a0) /* mem_sdconfiga */ + and t1, t1, t0 /* clear CE[1:0] */ + sw t1, 0x0840(a0) /* mem_sdconfiga */ + sync + + DO_SLEEP +4: + +END(alchemy_sleep_au1300) + /* This is where we return upon wakeup. * Reload all of the registers and return. diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index d5da6adbf634..a594a85337d6 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -178,6 +178,7 @@ static int alchemy_m2inttab[] __initdata = { AU1100_RTC_MATCH2_INT, AU1550_RTC_MATCH2_INT, AU1200_RTC_MATCH2_INT, + AU1300_RTC_MATCH2_INT, }; void __init plat_time_init(void) diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c new file mode 100644 index 000000000000..d23b1444d365 --- /dev/null +++ b/arch/mips/alchemy/common/vss.c @@ -0,0 +1,84 @@ +/* + * Au1300 media block power gating (VSS) + * + * This is a stop-gap solution until I have the clock framework integration + * ready. This stuff here really must be handled transparently when clocks + * for various media blocks are enabled/disabled. + */ + +#include +#include +#include + +#define VSS_GATE 0x00 /* gate wait timers */ +#define VSS_CLKRST 0x04 /* clock/block control */ +#define VSS_FTR 0x08 /* footers */ + +#define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c)) + +static DEFINE_SPINLOCK(au1300_vss_lock); + +/* enable a block as outlined in the databook */ +static inline void __enable_block(int block) +{ + void __iomem *base = (void __iomem *)VSS_ADDR(block); + + __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ + wmb(); + + __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ + wmb(); + + /* enable footers in sequence */ + __raw_writel(0x01, base + VSS_FTR); + wmb(); + __raw_writel(0x03, base + VSS_FTR); + wmb(); + __raw_writel(0x07, base + VSS_FTR); + wmb(); + __raw_writel(0x0f, base + VSS_FTR); + wmb(); + + __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ + wmb(); + + __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ + wmb(); + + __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ + wmb(); +} + +/* disable a block as outlined in the databook */ +static inline void __disable_block(int block) +{ + void __iomem *base = (void __iomem *)VSS_ADDR(block); + + __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ + wmb(); + __raw_writel(0, base + VSS_GATE); /* disable FSM */ + wmb(); + __raw_writel(3, base + VSS_CLKRST); /* assert reset */ + wmb(); + __raw_writel(1, base + VSS_CLKRST); /* disable clock */ + wmb(); + __raw_writel(0, base + VSS_FTR); /* disable all footers */ + wmb(); +} + +void au1300_vss_block_control(int block, int enable) +{ + unsigned long flags; + + if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300) + return; + + /* only one block at a time */ + spin_lock_irqsave(&au1300_vss_lock, flags); + if (enable) + __enable_block(block); + else + __disable_block(block); + spin_unlock_irqrestore(&au1300_vss_lock, flags); +} +EXPORT_SYMBOL_GPL(au1300_vss_block_control); diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 2f7f41873f24..79e4a0dad0d9 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -169,6 +169,7 @@ #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 +#define PRID_IMP_NETLOGIC_AU13XX 0x8000 /* * Definitions for 7:0 on legacy processors diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index de24ec57dd2f..65f126217175 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void) #define ALCHEMY_CPU_AU1100 2 #define ALCHEMY_CPU_AU1550 3 #define ALCHEMY_CPU_AU1200 4 +#define ALCHEMY_CPU_AU1300 5 static inline int alchemy_get_cputype(void) { @@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void) case 0x05030000: return ALCHEMY_CPU_AU1200; break; + case 0x800c0000: + return ALCHEMY_CPU_AU1300; + break; } return ALCHEMY_CPU_UNKNOWN; @@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type) { switch (type) { case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1300: return 4; case ALCHEMY_CPU_AU1500: case ALCHEMY_CPU_AU1200: @@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void); /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */ void alchemy_sleep_au1000(void); void alchemy_sleep_au1550(void); +void alchemy_sleep_au1300(void); void au_sleep(void); /* USB: drivers/usb/host/alchemy-common.c */ @@ -251,6 +257,7 @@ enum alchemy_usb_block { ALCHEMY_USB_UDC0, ALCHEMY_USB_EHCI0, ALCHEMY_USB_OTG0, + ALCHEMY_USB_OHCI1, }; int alchemy_usb_control(int block, int enable); @@ -263,14 +270,92 @@ struct alchemy_pci_platdata { unsigned long pci_cfg_clr; }; -/* SOC Interrupt numbers */ +/* Multifunction pins: Each of these pins can either be assigned to the + * GPIO controller or a on-chip peripheral. + * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to + * assign one of these to either the GPIO controller or the device. + */ +enum au1300_multifunc_pins { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, + AU1300_PIN_WAKE3, + /* external clock sources for PSCs: 4-5 */ + AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* aux clk input for freqgen 3: 10 */ + AU1300_PIN_FG3AUX, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 29-31 */ + AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, +}; + +/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */ +extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio); +extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio); +extern void au1300_set_irq_priority(unsigned int irq, int p); +extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); + +/* Au1300 allows to disconnect certain blocks from internal power supply */ +enum au1300_vss_block { + AU1300_VSS_MPE = 0, + AU1300_VSS_BSA, + AU1300_VSS_GPE, + AU1300_VSS_MGP, +}; + +extern void au1300_vss_block_control(int block, int enable); + +/* SOC Interrupt numbers */ +/* Au1000-style (IC0/1): 2 controllers with 32 sources each */ #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8) #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31) #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1) #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31) #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST +/* Au1300-style (GPIC): 1 controller with up to 128 sources */ +#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8) +#define ALCHEMY_GPIC_INT_NUM 128 +#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1) + enum soc_au1000_ints { AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, AU1000_UART0_INT = AU1000_FIRST_INT, @@ -591,24 +676,77 @@ enum soc_au1200_ints { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ +/* Au1300 peripheral interrupt numbers */ +#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE) +#define AU1300_UART1_INT (AU1300_FIRST_INT + 17) +#define AU1300_UART2_INT (AU1300_FIRST_INT + 25) +#define AU1300_UART3_INT (AU1300_FIRST_INT + 27) +#define AU1300_SD1_INT (AU1300_FIRST_INT + 32) +#define AU1300_SD2_INT (AU1300_FIRST_INT + 38) +#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) +#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) +#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) +#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) +#define AU1300_NAND_INT (AU1300_FIRST_INT + 62) +#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) +#define AU1300_MMU_INT (AU1300_FIRST_INT + 76) +#define AU1300_MPU_INT (AU1300_FIRST_INT + 77) +#define AU1300_GPU_INT (AU1300_FIRST_INT + 78) +#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) +#define AU1300_TOY_INT (AU1300_FIRST_INT + 80) +#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) +#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) +#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) +#define AU1300_RTC_INT (AU1300_FIRST_INT + 84) +#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) +#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) +#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) +#define AU1300_UART0_INT (AU1300_FIRST_INT + 88) +#define AU1300_SD0_INT (AU1300_FIRST_INT + 89) +#define AU1300_USB_INT (AU1300_FIRST_INT + 90) +#define AU1300_LCD_INT (AU1300_FIRST_INT + 91) +#define AU1300_BSA_INT (AU1300_FIRST_INT + 92) +#define AU1300_MPE_INT (AU1300_FIRST_INT + 93) +#define AU1300_ITE_INT (AU1300_FIRST_INT + 94) +#define AU1300_AES_INT (AU1300_FIRST_INT + 95) +#define AU1300_CIM_INT (AU1300_FIRST_INT + 96) + +/**********************************************************************/ + /* * Physical base addresses for integrated peripherals - * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 + * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300 */ #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */ +#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */ +#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */ +#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */ +#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */ +#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */ +#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */ +#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */ #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */ #define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */ +#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */ #define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */ -#define AU1200_AES_PHYS_ADDR 0x10300000 /* 4 */ +#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */ #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */ +#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */ #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */ #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */ #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */ -#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */ +#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */ +#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */ +#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */ #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */ +#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */ #define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */ #define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */ +#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */ +#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */ +#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */ +#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */ #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */ #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */ #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */ @@ -622,38 +760,97 @@ enum soc_au1200_ints { #define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */ #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ -#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ +#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */ #define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */ #define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */ #define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */ #define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */ +#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */ #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ -#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ -#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ +#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */ +#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */ #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */ #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */ -#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 4 */ +#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */ #define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */ #define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */ #define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */ #define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */ +#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */ +#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */ #define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */ #define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */ #define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */ #define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */ #define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */ #define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */ +#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */ +#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */ +#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */ +#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */ +#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */ +#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */ #define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */ -#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 4 */ +#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */ #define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */ #define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */ #define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */ #define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */ -#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 01234 */ -#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 01234 */ -#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 01234 */ +#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */ +#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */ +#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */ + +/**********************************************************************/ +/* + * Au1300 GPIO+INT controller (GPIC) register offsets and bits + * Registers are 128bits (0x10 bytes), divided into 4 "banks". + */ +#define AU1300_GPIC_PINVAL 0x0000 +#define AU1300_GPIC_PINVALCLR 0x0010 +#define AU1300_GPIC_IPEND 0x0020 +#define AU1300_GPIC_PRIENC 0x0030 +#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */ +#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */ +#define AU1300_GPIC_DMASEL 0x0060 +#define AU1300_GPIC_DEVSEL 0x0080 +#define AU1300_GPIC_DEVCLR 0x0090 +#define AU1300_GPIC_RSTVAL 0x00a0 +/* pin configuration space. one 32bit register for up to 128 IRQs */ +#define AU1300_GPIC_PINCFG 0x1000 + +#define GPIC_GPIO_TO_BIT(gpio) \ + (1 << ((gpio) & 0x1f)) + +#define GPIC_GPIO_BANKOFF(gpio) \ + (((gpio) >> 5) * 4) + +/* Pin Control bits: who owns the pin, what does it do */ +#define GPIC_CFG_PC_GPIN 0 +#define GPIC_CFG_PC_DEV 1 +#define GPIC_CFG_PC_GPOLOW 2 +#define GPIC_CFG_PC_GPOHIGH 3 +#define GPIC_CFG_PC_MASK 3 + +/* assign pin to MIPS IRQ line */ +#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) +#define GPIC_CFG_IL_MASK (3 << 2) + +/* pin interrupt type setup */ +#define GPIC_CFG_IC_OFF (0 << 4) +#define GPIC_CFG_IC_LEVEL_LOW (1 << 4) +#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) +#define GPIC_CFG_IC_EDGE_FALL (5 << 4) +#define GPIC_CFG_IC_EDGE_RISE (6 << 4) +#define GPIC_CFG_IC_EDGE_BOTH (7 << 4) +#define GPIC_CFG_IC_MASK (7 << 4) + +/* allow interrupt to wake cpu from 'wait' */ +#define GPIC_CFG_IDLEWAKE (1 << 7) + +/***********************************************************************/ + /* Au1000 SDRAM memory controller register offsets */ #define AU1000_MEM_SDMODE0 0x0000 #define AU1000_MEM_SDMODE1 0x0004 diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h index 94000a3b6f0b..e221659f1bca 100644 --- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h +++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h @@ -130,8 +130,10 @@ struct au1xmmc_platform_data { #define SD_CONFIG2_DF (0x00000008) #define SD_CONFIG2_DC (0x00000010) #define SD_CONFIG2_xx2 (0x000000e0) +#define SD_CONFIG2_BB (0x00000080) #define SD_CONFIG2_WB (0x00000100) #define SD_CONFIG2_RW (0x00000200) +#define SD_CONFIG2_DP (0x00000400) /* diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 323ce2d145f2..217810e18361 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc { #define AU1200_DSCR_CMD0_PSC1_SYNC 25 #define AU1200_DSCR_CMD0_CIM_SYNC 26 +#define AU1300_DSCR_CMD0_UART0_TX 0 +#define AU1300_DSCR_CMD0_UART0_RX 1 +#define AU1300_DSCR_CMD0_UART1_TX 2 +#define AU1300_DSCR_CMD0_UART1_RX 3 +#define AU1300_DSCR_CMD0_UART2_TX 4 +#define AU1300_DSCR_CMD0_UART2_RX 5 +#define AU1300_DSCR_CMD0_UART3_TX 6 +#define AU1300_DSCR_CMD0_UART3_RX 7 +#define AU1300_DSCR_CMD0_SDMS_TX0 8 +#define AU1300_DSCR_CMD0_SDMS_RX0 9 +#define AU1300_DSCR_CMD0_SDMS_TX1 10 +#define AU1300_DSCR_CMD0_SDMS_RX1 11 +#define AU1300_DSCR_CMD0_AES_TX 12 +#define AU1300_DSCR_CMD0_AES_RX 13 +#define AU1300_DSCR_CMD0_PSC0_TX 14 +#define AU1300_DSCR_CMD0_PSC0_RX 15 +#define AU1300_DSCR_CMD0_PSC1_TX 16 +#define AU1300_DSCR_CMD0_PSC1_RX 17 +#define AU1300_DSCR_CMD0_PSC2_TX 18 +#define AU1300_DSCR_CMD0_PSC2_RX 19 +#define AU1300_DSCR_CMD0_PSC3_TX 20 +#define AU1300_DSCR_CMD0_PSC3_RX 21 +#define AU1300_DSCR_CMD0_LCD 22 +#define AU1300_DSCR_CMD0_NAND_FLASH 23 +#define AU1300_DSCR_CMD0_SDMS_TX2 24 +#define AU1300_DSCR_CMD0_SDMS_RX2 25 +#define AU1300_DSCR_CMD0_CIM_SYNC 26 +#define AU1300_DSCR_CMD0_UDMA 27 +#define AU1300_DSCR_CMD0_DMA_REQ0 28 +#define AU1300_DSCR_CMD0_DMA_REQ1 29 + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h new file mode 100644 index 000000000000..556e1be20bf6 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -0,0 +1,241 @@ +/* + * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles. + * + * Copyright (c) 2009-2011 Manuel Lauss + */ + +#ifndef _GPIO_AU1300_H_ +#define _GPIO_AU1300_H_ + +#include +#include +#include + +/* with the current GPIC design, up to 128 GPIOs are possible. + * The only implementation so far is in the Au1300, which has 75 externally + * available GPIOs. + */ +#define AU1300_GPIO_BASE 0 +#define AU1300_GPIO_NUM 75 +#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) + +#define AU1300_GPIC_ADDR \ + (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) + +static inline int au1300_gpio_get_value(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + int bit; + + gpio -= AU1300_GPIO_BASE; + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; +} + +static inline int au1300_gpio_direction_input(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); + wmb(); + + return 0; +} + +static inline int au1300_gpio_set_value(unsigned int gpio, int v) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long bit; + + gpio -= AU1300_GPIO_BASE; + + roff += GPIC_GPIO_BANKOFF(gpio); + bit = GPIC_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL + : AU1300_GPIC_PINVALCLR)); + wmb(); + + return 0; +} + +static inline int au1300_gpio_direction_output(unsigned int gpio, int v) +{ + /* hw switches to output automatically */ + return au1300_gpio_set_value(gpio, v); +} + +static inline int au1300_gpio_to_irq(unsigned int gpio) +{ + return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); +} + +static inline int au1300_irq_to_gpio(unsigned int irq) +{ + return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; +} + +static inline int au1300_gpio_is_valid(unsigned int gpio) +{ + int ret; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1300: + ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); + break; + default: + ret = 0; + } + return ret; +} + +static inline int au1300_gpio_cansleep(unsigned int gpio) +{ + return 0; +} + +/* hardware remembers gpio 0-63 levels on powerup */ +static inline int au1300_gpio_getinitlvl(unsigned int gpio) +{ + void __iomem *roff = AU1300_GPIC_ADDR; + unsigned long v; + + if (unlikely(gpio > 63)) + return 0; + else if (gpio > 31) { + gpio -= 32; + roff += 4; + } + + v = __raw_readl(roff + AU1300_GPIC_RSTVAL); + return (v >> gpio) & 1; +} + +/**********************************************************************/ + +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifndef CONFIG_GPIOLIB + +#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300 + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(unsigned int gpio) +{ + return au1300_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned int gpio, int v) +{ + return au1300_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(unsigned int gpio) +{ + return au1300_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned int gpio, int v) +{ + au1300_gpio_set_value(gpio, v); +} + +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + +static inline int gpio_is_valid(unsigned int gpio) +{ + return au1300_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(unsigned int gpio) +{ + return au1300_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(unsigned int gpio) +{ + return au1300_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned int irq) +{ + return au1300_irq_to_gpio(irq); +} + +static inline int gpio_request(unsigned int gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned int gpio) +{ +} + +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -ENOSYS; +} + +static inline void gpio_unexport(unsigned gpio) +{ +} + +static inline int gpio_export(unsigned gpio, bool direction_may_change) +{ + return -ENOSYS; +} + +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + +static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) +{ + return -ENOSYS; +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + +#endif /* CONFIG_ALCHEMY_GPIOINT_AU1300 */ + +#endif /* CONFIG GPIOLIB */ + +#endif /* _GPIO_AU1300_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index fcdc8c4809db..22e7ff17fc48 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -12,6 +12,7 @@ #include #include +#include /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before * SYS_PININPUTEN is written to at least once. On Au1550/Au1200/Au1300 this @@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq) switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200: return alchemy_irq_to_gpio(irq); + case ALCHEMY_CPU_AU1300: + return au1300_irq_to_gpio(irq); } return -EINVAL; } diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index c7d3cf1ce46e..98383995e6ac 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1014,6 +1014,13 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) { decode_configs(c); + if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { + c->cputype = CPU_ALCHEMY; + __cpu_name[cpu] = "Au1300"; + /* following stuff is not for Alchemy */ + return; + } + c->options = (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_COUNTER | diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index a3afac4be734..cbe7a2fb779f 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -299,11 +299,11 @@ config I2C_AT91 unless your system can cope with those limitations. config I2C_AU1550 - tristate "Au1550/Au1200 SMBus interface" + tristate "Au1550/Au1200/Au1300 SMBus interface" depends on MIPS_ALCHEMY help If you say yes to this option, support will be included for the - Au1550 and Au1200 SMBus interface. + Au1550/Au1200/Au1300 SMBus interface. This driver can also be built as a module. If so, the module will be called i2c-au1550. diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index 5d3b9ae64523..dbd0c8a4e98a 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -153,6 +153,7 @@ static inline int has_dbdma(void) { switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1200: + case ALCHEMY_CPU_AU1300: return 1; default: return 0; @@ -768,11 +769,15 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) config2 = au_readl(HOST_CONFIG2(host)); switch (ios->bus_width) { + case MMC_BUS_WIDTH_8: + config2 |= SD_CONFIG2_BB; + break; case MMC_BUS_WIDTH_4: + config2 &= ~SD_CONFIG2_BB; config2 |= SD_CONFIG2_WB; break; case MMC_BUS_WIDTH_1: - config2 &= ~SD_CONFIG2_WB; + config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB); break; } au_writel(config2, HOST_CONFIG2(host)); @@ -943,7 +948,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) struct mmc_host *mmc; struct au1xmmc_host *host; struct resource *r; - int ret; + int ret, iflag; mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev); if (!mmc) { @@ -982,37 +987,43 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "no IRQ defined\n"); goto out3; } - host->irq = r->start; - /* IRQ is shared among both SD controllers */ - ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED, - DRIVER_NAME, host); - if (ret) { - dev_err(&pdev->dev, "cannot grab IRQ\n"); - goto out3; - } mmc->ops = &au1xmmc_ops; mmc->f_min = 450000; mmc->f_max = 24000000; + mmc->max_blk_size = 2048; + mmc->max_blk_count = 512; + + mmc->ocr_avail = AU1XMMC_OCR; + mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; + mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; + + iflag = IRQF_SHARED; /* Au1100/Au1200: one int for both ctrls */ + switch (alchemy_get_cputype()) { case ALCHEMY_CPU_AU1100: mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE; - mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; break; case ALCHEMY_CPU_AU1200: mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; - mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT; + break; + case ALCHEMY_CPU_AU1300: + iflag = 0; /* nothing is shared */ + mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE; + mmc->f_max = 52000000; + if (host->ioarea->start == AU1100_SD0_PHYS_ADDR) + mmc->caps |= MMC_CAP_8_BIT_DATA; break; } - mmc->max_blk_size = 2048; - mmc->max_blk_count = 512; - - mmc->ocr_avail = AU1XMMC_OCR; - mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; + ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host); + if (ret) { + dev_err(&pdev->dev, "cannot grab IRQ\n"); + goto out3; + } host->status = HOST_S_IDLE; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1fd73df5416..369e092bf3d5 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -87,12 +87,12 @@ config SPI_BFIN_SPORT Enable support for a SPI bus via the Blackfin SPORT peripheral. config SPI_AU1550 - tristate "Au1550/Au12x0 SPI Controller" + tristate "Au1550/Au1200/Au1300 SPI Controller" depends on MIPS_ALCHEMY && EXPERIMENTAL select SPI_BITBANG help If you say yes to this option, support will be included for the - Au1550 SPI controller (may also work with Au1200,Au1210,Au1250). + PSC SPI controller found on Au1550, Au1200 and Au1300 series. config SPI_BITBANG tristate "Utilities for Bitbanging SPI masters" diff --git a/drivers/usb/host/alchemy-common.c b/drivers/usb/host/alchemy-common.c index b4192c964d0d..936af8359fb2 100644 --- a/drivers/usb/host/alchemy-common.c +++ b/drivers/usb/host/alchemy-common.c @@ -52,9 +52,263 @@ USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \ USBCFG_OME) +/* Au1300 USB config registers */ +#define USB_DWC_CTRL1 0x00 +#define USB_DWC_CTRL2 0x04 +#define USB_VBUS_TIMER 0x10 +#define USB_SBUS_CTRL 0x14 +#define USB_MSR_ERR 0x18 +#define USB_DWC_CTRL3 0x1C +#define USB_DWC_CTRL4 0x20 +#define USB_OTG_STATUS 0x28 +#define USB_DWC_CTRL5 0x2C +#define USB_DWC_CTRL6 0x30 +#define USB_DWC_CTRL7 0x34 +#define USB_PHY_STATUS 0xC0 +#define USB_INT_STATUS 0xC4 +#define USB_INT_ENABLE 0xC8 + +#define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */ +#define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */ +#define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */ + +#define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */ +#define USB_DWC_CTRL2_PHY0RS 0x02 /* set to enable PHY0 */ +#define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */ + +#define USB_DWC_CTRL3_OHCI1_CKEN (1 << 19) +#define USB_DWC_CTRL3_OHCI0_CKEN (1 << 18) +#define USB_DWC_CTRL3_EHCI0_CKEN (1 << 17) +#define USB_DWC_CTRL3_OTG0_CKEN (1 << 16) + +#define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */ + +#define USB_INTEN_FORCE 0x20 +#define USB_INTEN_PHY 0x10 +#define USB_INTEN_UDC 0x08 +#define USB_INTEN_EHCI 0x04 +#define USB_INTEN_OHCI1 0x02 +#define USB_INTEN_OHCI0 0x01 static DEFINE_SPINLOCK(alchemy_usb_lock); +static inline void __au1300_usb_phyctl(void __iomem *base, int enable) +{ + unsigned long r, s; + + r = __raw_readl(base + USB_DWC_CTRL2); + s = __raw_readl(base + USB_DWC_CTRL3); + + s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN | + USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN; + + if (enable) { + /* simply enable all PHYs */ + r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS | + USB_DWC_CTRL2_PHYRS; + __raw_writel(r, base + USB_DWC_CTRL2); + wmb(); + } else if (!s) { + /* no USB block active, do disable all PHYs */ + r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS | + USB_DWC_CTRL2_PHYRS); + __raw_writel(r, base + USB_DWC_CTRL2); + wmb(); + } +} + +static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) +{ + unsigned long r; + + if (enable) { + __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ + r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN + : USB_DWC_CTRL3_OHCI1_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + __au1300_usb_phyctl(base, enable); /* power up the PHYs */ + + r = __raw_readl(base + USB_INT_ENABLE); + r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + + /* reset the OHCI start clock bit */ + __raw_writel(0, base + USB_DWC_CTRL7); + wmb(); + } else { + r = __raw_readl(base + USB_INT_ENABLE); + r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1); + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL3); + r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN + : USB_DWC_CTRL3_OHCI1_CKEN); + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + __au1300_usb_phyctl(base, enable); + } +} + +static inline void __au1300_ehci_control(void __iomem *base, int enable) +{ + unsigned long r; + + if (enable) { + r = __raw_readl(base + USB_DWC_CTRL3); + r |= USB_DWC_CTRL3_EHCI0_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL1); + r |= USB_DWC_CTRL1_HSTRS; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + __au1300_usb_phyctl(base, enable); + + r = __raw_readl(base + USB_INT_ENABLE); + r |= USB_INTEN_EHCI; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + } else { + r = __raw_readl(base + USB_INT_ENABLE); + r &= ~USB_INTEN_EHCI; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL1); + r &= ~USB_DWC_CTRL1_HSTRS; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL3); + r &= ~USB_DWC_CTRL3_EHCI0_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + __au1300_usb_phyctl(base, enable); + } +} + +static inline void __au1300_udc_control(void __iomem *base, int enable) +{ + unsigned long r; + + if (enable) { + r = __raw_readl(base + USB_DWC_CTRL1); + r |= USB_DWC_CTRL1_DCRS; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + __au1300_usb_phyctl(base, enable); + + r = __raw_readl(base + USB_INT_ENABLE); + r |= USB_INTEN_UDC; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + } else { + r = __raw_readl(base + USB_INT_ENABLE); + r &= ~USB_INTEN_UDC; + __raw_writel(r, base + USB_INT_ENABLE); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL1); + r &= ~USB_DWC_CTRL1_DCRS; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + __au1300_usb_phyctl(base, enable); + } +} + +static inline void __au1300_otg_control(void __iomem *base, int enable) +{ + unsigned long r; + if (enable) { + r = __raw_readl(base + USB_DWC_CTRL3); + r |= USB_DWC_CTRL3_OTG0_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL1); + r &= ~USB_DWC_CTRL1_OTGD; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + __au1300_usb_phyctl(base, enable); + } else { + r = __raw_readl(base + USB_DWC_CTRL1); + r |= USB_DWC_CTRL1_OTGD; + __raw_writel(r, base + USB_DWC_CTRL1); + wmb(); + + r = __raw_readl(base + USB_DWC_CTRL3); + r &= ~USB_DWC_CTRL3_OTG0_CKEN; + __raw_writel(r, base + USB_DWC_CTRL3); + wmb(); + + __au1300_usb_phyctl(base, enable); + } +} + +static inline int au1300_usb_control(int block, int enable) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); + int ret = 0; + + switch (block) { + case ALCHEMY_USB_OHCI0: + __au1300_ohci_control(base, enable, 0); + break; + case ALCHEMY_USB_OHCI1: + __au1300_ohci_control(base, enable, 1); + break; + case ALCHEMY_USB_EHCI0: + __au1300_ehci_control(base, enable); + break; + case ALCHEMY_USB_UDC0: + __au1300_udc_control(base, enable); + break; + case ALCHEMY_USB_OTG0: + __au1300_otg_control(base, enable); + break; + default: + ret = -ENODEV; + } + return ret; +} + +static inline void au1300_usb_init(void) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); + + /* set some sane defaults. Note: we don't fiddle with DWC_CTRL4 + * here at all: Port 2 routing (EHCI or UDC) must be set either + * by boot firmware or platform init code; I can't autodetect + * a sane setting. + */ + __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */ + wmb(); + __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */ + wmb(); + __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */ + wmb(); + __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */ + wmb(); + /* set coherent access bit */ + __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL); + wmb(); +} static inline void __au1200_ohci_control(void __iomem *base, int enable) { @@ -233,6 +487,9 @@ int alchemy_usb_control(int block, int enable) case ALCHEMY_CPU_AU1200: ret = au1200_usb_control(block, enable); break; + case ALCHEMY_CPU_AU1300: + ret = au1300_usb_control(block, enable); + break; default: ret = -ENODEV; } @@ -281,6 +538,20 @@ static void au1200_usb_pm(int susp) } } +static void au1300_usb_pm(int susp) +{ + void __iomem *base = + (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); + /* remember Port2 routing */ + if (susp) { + alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4); + } else { + au1300_usb_init(); + __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4); + wmb(); + } +} + static void alchemy_usb_pm(int susp) { switch (alchemy_get_cputype()) { @@ -295,6 +566,9 @@ static void alchemy_usb_pm(int susp) case ALCHEMY_CPU_AU1200: au1200_usb_pm(susp); break; + case ALCHEMY_CPU_AU1300: + au1300_usb_pm(susp); + break; } } @@ -328,6 +602,9 @@ static int __init alchemy_usb_init(void) case ALCHEMY_CPU_AU1200: au1200_usb_init(); break; + case ALCHEMY_CPU_AU1300: + au1300_usb_init(); + break; } register_syscore_ops(&alchemy_usb_pm_ops); diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index 9b66df8278f3..95d1a71dccad 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -89,7 +89,7 @@ static const struct hc_driver ohci_au1xxx_hc_driver = { static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) { - int ret; + int ret, unit; struct usb_hcd *hcd; if (usb_disabled()) @@ -120,7 +120,9 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) goto err2; } - if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) { + unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ? + ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0; + if (alchemy_usb_control(unit, 1)) { printk(KERN_INFO "%s: controller init failed!\n", pdev->name); ret = -ENODEV; goto err3; @@ -135,7 +137,7 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev) return ret; } - alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); + alchemy_usb_control(unit, 0); err3: iounmap(hcd->regs); err2: @@ -148,9 +150,12 @@ err1: static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev) { struct usb_hcd *hcd = platform_get_drvdata(pdev); + int unit; + unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ? + ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0; usb_remove_hcd(hcd); - alchemy_usb_control(ALCHEMY_USB_OHCI0, 0); + alchemy_usb_control(unit, 0); iounmap(hcd->regs); release_mem_region(hcd->rsrc_start, hcd->rsrc_len); usb_put_hcd(hcd); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index d83e967e4e15..acd4ba555e3a 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1763,16 +1763,16 @@ config FB_AU1100 au1100fb:panel=. config FB_AU1200 - bool "Au1200 LCD Driver" + bool "Au1200/Au1300 LCD Driver" depends on (FB = y) && MIPS_ALCHEMY select FB_SYS_FILLRECT select FB_SYS_COPYAREA select FB_SYS_IMAGEBLIT select FB_SYS_FOPS help - This is the framebuffer driver for the AMD Au1200 SOC. It can drive - various panels and CRTs by passing in kernel cmd line option - au1200fb:panel=. + This is the framebuffer driver for the Au1200/Au1300 SOCs. + It can drive various panels and CRTs by passing in kernel cmd line + option au1200fb:panel=. config FB_VT8500 bool "VT8500 LCD Driver" diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index e908a8123110..93323cc0452a 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -1,13 +1,13 @@ ## -## Au1200/Au1550 PSC + DBDMA +## Au1200/Au1550/Au1300 PSC + DBDMA ## config SND_SOC_AU1XPSC - tristate "SoC Audio for Au1200/Au1250/Au1550" + tristate "SoC Audio for Au12xx/Au13xx/Au1550" depends on MIPS_ALCHEMY help This option enables support for the Programmable Serial Controllers in AC97 and I2S mode, and the Descriptor-Based DMA - Controller (DBDMA) as found on the Au1200/Au1250/Au1550 SoC. + Controller (DBDMA) as found on the Au12xx/Au13xx/Au1550 SoC. config SND_SOC_AU1XPSC_I2S tristate -- cgit v1.2.3 From 64cd04d0cffa3b3af0e81aa3112b71f135739e1a Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:03:26 +0000 Subject: MIPS: Alchemy: Basic support for the DB1300 board. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2867/ Patchwork: https://patchwork.linux-mips.org/patch/2919/ Patchwork: https://patchwork.linux-mips.org/patch/2928/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 8 + arch/mips/alchemy/Platform | 7 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300.c | 787 +++++++++++++++++++++++++++++ arch/mips/alchemy/devboards/prom.c | 4 + arch/mips/boot/compressed/uart-alchemy.c | 5 +- arch/mips/configs/db1300_defconfig | 391 ++++++++++++++ arch/mips/include/asm/mach-db1x00/bcsr.h | 34 +- arch/mips/include/asm/mach-db1x00/db1300.h | 40 ++ arch/mips/include/asm/mach-db1x00/irq.h | 23 + drivers/pcmcia/Kconfig | 4 +- drivers/pcmcia/db1xxx_ss.c | 26 +- drivers/video/au1200fb.c | 36 ++ sound/soc/au1x/Kconfig | 8 +- sound/soc/au1x/db1200.c | 43 +- 15 files changed, 1398 insertions(+), 19 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1300.c create mode 100644 arch/mips/configs/db1300_defconfig create mode 100644 arch/mips/include/asm/mach-db1x00/db1300.h create mode 100644 arch/mips/include/asm/mach-db1x00/irq.h (limited to 'drivers') diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 766badaef3b0..f9a13beada4a 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -49,6 +49,14 @@ config MIPS_DB1200 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK +config MIPS_DB1300 + bool "NetLogic DB1300 board" + select ALCHEMY_GPIOINT_AU1300 + select DMA_COHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + config MIPS_DB1500 bool "Alchemy DB1500 board" select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index 2920af9c2569..4d13e21eaf83 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -67,6 +67,13 @@ platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 +# +# NetLogic DBAu1300 development platform +# +platform-$(CONFIG_MIPS_DB1300) += alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 + # # 4G-Systems eval board # diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 5afaf944868f..2eb75c92a583 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_MIPS_PB1550) += pb1550/ obj-$(CONFIG_MIPS_DB1000) += db1x00/ obj-$(CONFIG_MIPS_DB1100) += db1x00/ obj-$(CONFIG_MIPS_DB1200) += db1200/ +obj-$(CONFIG_MIPS_DB1300) += db1300.o obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c new file mode 100644 index 000000000000..c41788c59278 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300.c @@ -0,0 +1,787 @@ +/* + * DBAu1300 init and platform device setup. + * + * (c) 2009 Manuel Lauss + */ + +#include +#include +#include +#include +#include /* KEY_* codes */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "platform.h" + +static struct i2c_board_info db1300_i2c_devs[] __initdata = { + { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */ + { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ +}; + +/* multifunction pins to assign to GPIO controller */ +static int db1300_gpio_pins[] __initdata = { + AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1, + AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX, + AU1300_PIN_EXTCLK1, + -1, /* terminator */ +}; + +/* multifunction pins to assign to device functions */ +static int db1300_dev_pins[] __initdata = { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0, + /* external clock sources for PSC0 */ + AU1300_PIN_EXTCLK0, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 30-31 */ + AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, + -1, /* terminator */ +}; + +static void __init db1300_gpio_config(void) +{ + int *i; + + i = &db1300_dev_pins[0]; + while (*i != -1) + au1300_pinfunc_to_dev(*i++); + + i = &db1300_gpio_pins[0]; + while (*i != -1) + au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */ + + au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); +} + +char *get_system_type(void) +{ + return "DB1300"; +} + +/**********************************************************************/ + +static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; + + ioaddr &= 0xffffff00; + + if (ctrl & NAND_CLE) { + ioaddr += MEM_STNAND_CMD; + } else if (ctrl & NAND_ALE) { + ioaddr += MEM_STNAND_ADDR; + } else { + /* assume we want to r/w real data by default */ + ioaddr += MEM_STNAND_DATA; + } + this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; + if (cmd != NAND_CMD_NONE) { + __raw_writeb(cmd, this->IO_ADDR_W); + wmb(); + } +} + +static int au1300_nand_device_ready(struct mtd_info *mtd) +{ + return __raw_readl((void __iomem *)MEM_STSTAT) & 1; +} + +static const char *db1300_part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition db1300_nand_parts[] = { + { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +struct platform_nand_data db1300_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(db1300_nand_parts), + .partitions = db1300_nand_parts, + .chip_delay = 20, + .part_probe_types = db1300_part_probes, + }, + .ctrl = { + .dev_ready = au1300_nand_device_ready, + .cmd_ctrl = au1300_nand_cmd_ctrl, + }, +}; + +static struct resource db1300_nand_res[] = { + [0] = { + .start = DB1300_NAND_PHYS_ADDR, + .end = DB1300_NAND_PHYS_ADDR + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1300_nand_dev = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(db1300_nand_res), + .resource = db1300_nand_res, + .id = -1, + .dev = { + .platform_data = &db1300_nand_platdata, + } +}; + +/**********************************************************************/ + +static struct resource db1300_eth_res[] = { + [0] = { + .start = DB1300_ETH_PHYS_ADDR, + .end = DB1300_ETH_PHYS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_ETH_INT, + .end = DB1300_ETH_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config db1300_eth_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device db1300_eth_dev = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(db1300_eth_res), + .resource = db1300_eth_res, + .dev = { + .platform_data = &db1300_eth_config, + }, +}; + +/**********************************************************************/ + +static struct resource au1300_psc1_res[] = { + [0] = { + .start = AU1300_PSC1_PHYS_ADDR, + .end = AU1300_PSC1_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC1_INT, + .end = AU1300_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC1_TX, + .end = AU1300_DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC1_RX, + .end = AU1300_DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_ac97_dev = { + .name = "au1xpsc_ac97", + .id = 1, /* PSC ID. match with AC97 codec ID! */ + .num_resources = ARRAY_SIZE(au1300_psc1_res), + .resource = au1300_psc1_res, +}; + +/**********************************************************************/ + +static struct resource au1300_psc2_res[] = { + [0] = { + .start = AU1300_PSC2_PHYS_ADDR, + .end = AU1300_PSC2_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC2_INT, + .end = AU1300_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC2_TX, + .end = AU1300_DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC2_RX, + .end = AU1300_DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2s_dev = { + .name = "au1xpsc_i2s", + .id = 2, /* PSC ID */ + .num_resources = ARRAY_SIZE(au1300_psc2_res), + .resource = au1300_psc2_res, +}; + +/**********************************************************************/ + +static struct resource au1300_psc3_res[] = { + [0] = { + .start = AU1300_PSC3_PHYS_ADDR, + .end = AU1300_PSC3_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC3_INT, + .end = AU1300_PSC3_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_PSC3_TX, + .end = AU1300_DSCR_CMD0_PSC3_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_PSC3_RX, + .end = AU1300_DSCR_CMD0_PSC3_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1300_psc3_res), + .resource = au1300_psc3_res, +}; + +/**********************************************************************/ + +/* proper key assignments when facing the LCD panel. For key assignments + * according to the schematics swap up with down and left with right. + * I chose to use it to emulate the arrow keys of a keyboard. + */ +static struct gpio_keys_button db1300_5waysw_arrowkeys[] = { + { + .code = KEY_DOWN, + .gpio = AU1300_PIN_LCDPWM0, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-down", + }, + { + .code = KEY_UP, + .gpio = AU1300_PIN_PSC2SYNC1, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-up", + }, + { + .code = KEY_RIGHT, + .gpio = AU1300_PIN_WAKE3, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-right", + }, + { + .code = KEY_LEFT, + .gpio = AU1300_PIN_WAKE2, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-left", + }, + { + .code = KEY_ENTER, + .gpio = AU1300_PIN_WAKE1, + .type = EV_KEY, + .debounce_interval = 1, + .active_low = 1, + .desc = "5waysw-push", + }, +}; + +static struct gpio_keys_platform_data db1300_5waysw_data = { + .buttons = db1300_5waysw_arrowkeys, + .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys), + .rep = 1, + .name = "db1300-5wayswitch", +}; + +static struct platform_device db1300_5waysw_dev = { + .name = "gpio-keys", + .dev = { + .platform_data = &db1300_5waysw_data, + }, +}; + +/**********************************************************************/ + +static struct platform_device db1300_rtc_dev = { + .name = "rtc-au1xxx", + .id = -1, +}; + +/**********************************************************************/ + +static struct pata_platform_info db1300_ide_info = { + .ioport_shift = DB1300_IDE_REG_SHIFT, +}; + +#define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT) +static struct resource db1300_ide_res[] = { + [0] = { + .start = DB1300_IDE_PHYS_ADDR, + .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START, + .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = DB1300_IDE_INT, + .end = DB1300_IDE_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device db1300_ide_dev = { + .dev = { + .platform_data = &db1300_ide_info, + }, + .name = "pata_platform", + .resource = db1300_ide_res, + .num_resources = ARRAY_SIZE(db1300_ide_res), +}; + +/**********************************************************************/ + +static irqreturn_t db1300_mmc_cd(int irq, void *ptr) +{ + void(*mmc_cd)(struct mmc_host *, unsigned long); + + /* disable the one currently screaming. No other way to shut it up */ + if (irq == DB1300_SD1_INSERT_INT) { + disable_irq_nosync(DB1300_SD1_INSERT_INT); + enable_irq(DB1300_SD1_EJECT_INT); + } else { + disable_irq_nosync(DB1300_SD1_EJECT_INT); + enable_irq(DB1300_SD1_INSERT_INT); + } + + /* link against CONFIG_MMC=m. We can only be called once MMC core has + * initialized the controller, so symbol_get() should always succeed. + */ + mmc_cd = symbol_get(mmc_detect_change); + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + + return IRQ_HANDLED; +} + +static int db1300_mmc_card_readonly(void *mmc_host) +{ + /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */ + return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP; +} + +static int db1300_mmc_card_inserted(void *mmc_host) +{ + return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */ +} + +static int db1300_mmc_cd_setup(void *mmc_host, int en) +{ + int ret; + + if (en) { + ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0, + "sd_insert", mmc_host); + if (ret) + goto out; + + ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0, + "sd_eject", mmc_host); + if (ret) { + free_irq(DB1300_SD1_INSERT_INT, mmc_host); + goto out; + } + + if (db1300_mmc_card_inserted(mmc_host)) + enable_irq(DB1300_SD1_EJECT_INT); + else + enable_irq(DB1300_SD1_INSERT_INT); + + } else { + free_irq(DB1300_SD1_INSERT_INT, mmc_host); + free_irq(DB1300_SD1_EJECT_INT, mmc_host); + } + ret = 0; +out: + return ret; +} + +static void db1300_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); +} + +static struct led_classdev db1300_mmc_led = { + .brightness_set = db1300_mmcled_set, +}; + +struct au1xmmc_platform_data db1300_sd1_platdata = { + .cd_setup = db1300_mmc_cd_setup, + .card_inserted = db1300_mmc_card_inserted, + .card_readonly = db1300_mmc_card_readonly, + .led = &db1300_mmc_led, +}; + +static struct resource au1300_sd1_res[] = { + [0] = { + .start = AU1300_SD1_PHYS_ADDR, + .end = AU1300_SD1_PHYS_ADDR, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_SD1_INT, + .end = AU1300_SD1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_SDMS_TX1, + .end = AU1300_DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_SDMS_RX1, + .end = AU1300_DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_sd1_dev = { + .dev = { + .platform_data = &db1300_sd1_platdata, + }, + .name = "au1xxx-mmc", + .id = 1, + .resource = au1300_sd1_res, + .num_resources = ARRAY_SIZE(au1300_sd1_res), +}; + +/**********************************************************************/ + +static int db1300_movinand_inserted(void *mmc_host) +{ + return 0; /* disable for now, it doesn't work yet */ +} + +static int db1300_movinand_readonly(void *mmc_host) +{ + return 0; +} + +static void db1300_movinand_led_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); +} + +static struct led_classdev db1300_movinand_led = { + .brightness_set = db1300_movinand_led_set, +}; + +struct au1xmmc_platform_data db1300_sd0_platdata = { + .card_inserted = db1300_movinand_inserted, + .card_readonly = db1300_movinand_readonly, + .led = &db1300_movinand_led, + .mask_host_caps = MMC_CAP_NEEDS_POLL, +}; + +static struct resource au1300_sd0_res[] = { + [0] = { + .start = AU1100_SD0_PHYS_ADDR, + .end = AU1100_SD0_PHYS_ADDR, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_SD0_INT, + .end = AU1300_SD0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = AU1300_DSCR_CMD0_SDMS_TX0, + .end = AU1300_DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = AU1300_DSCR_CMD0_SDMS_RX0, + .end = AU1300_DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_sd0_dev = { + .dev = { + .platform_data = &db1300_sd0_platdata, + }, + .name = "au1xxx-mmc", + .id = 0, + .resource = au1300_sd0_res, + .num_resources = ARRAY_SIZE(au1300_sd0_res), +}; + +/**********************************************************************/ + +static struct platform_device db1300_wm9715_dev = { + .name = "wm9712-codec", + .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */ +}; + +static struct platform_device db1300_ac97dma_dev = { + .name = "au1xpsc-pcm", + .id = 1, /* PSC ID */ +}; + +static struct platform_device db1300_i2sdma_dev = { + .name = "au1xpsc-pcm", + .id = 2, /* PSC ID */ +}; + +static struct platform_device db1300_sndac97_dev = { + .name = "db1300-ac97", +}; + +static struct platform_device db1300_sndi2s_dev = { + .name = "db1300-i2s", +}; + +/**********************************************************************/ + +static struct resource au1300_lcd_res[] = { + [0] = { + .start = AU1200_LCD_PHYS_ADDR, + .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_LCD_INT, + .end = AU1300_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device db1300_lcd_dev = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1300_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1300_lcd_res), + .resource = au1300_lcd_res, +}; + +/**********************************************************************/ + +static struct platform_device *db1300_dev[] __initdata = { + &db1300_eth_dev, + &db1300_i2c_dev, + &db1300_5waysw_dev, + &db1300_rtc_dev, + &db1300_nand_dev, + &db1300_ide_dev, + &db1300_sd0_dev, + &db1300_sd1_dev, + &db1300_lcd_dev, + &db1300_ac97_dev, + &db1300_i2s_dev, + &db1300_wm9715_dev, + &db1300_ac97dma_dev, + &db1300_i2sdma_dev, + &db1300_sndac97_dev, + &db1300_sndi2s_dev, +}; + +static int __init db1300_device_init(void) +{ + int swapped, cpldirq; + + /* setup CPLD IRQ muxer */ + cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); + irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH); + bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); + + /* insert/eject IRQs: one always triggers so don't enable them + * when doing request_irq() on them. DB1200 has this bug too. + */ + irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN); + irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN); + + /* + * setup board + */ + prom_get_ethernet_addr(&db1300_eth_config.mac[0]); + + i2c_register_board_info(0, db1300_i2c_devs, + ARRAY_SIZE(db1300_i2c_devs)); + + /* Audio PSC clock is supplied by codecs (PSC1, 2) */ + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + /* I2C uses internal 48MHz EXTCLK1 */ + __raw_writel(PSC_SEL_CLK_INTCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + + /* enable power to USB ports */ + bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR); + + /* although it is socket #0, it uses the CPLD bits which previous boards + * have used for socket #1. + */ + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, + DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1); + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; + db1x_register_norflash(64 << 20, 2, swapped); + + return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); +} +device_initcall(db1300_device_init); + + +void __init board_setup(void) +{ + unsigned short whoami; + + db1300_gpio_config(); + bcsr_init(DB1300_BCSR_PHYS_ADDR, + DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t" + "BoardID %d CPLD Rev %d DaughtercardID %d\n", + BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), + BCSR_WHOAMI_DCID(whoami)); + + /* enable UARTs, YAMON only enables #2 */ + alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); + alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); + alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); +} + + +/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ +int board_au1200fb_panel(void) +{ + return 9; /* DB1300_800x480 */ +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, + BCSR_BOARD_LCDBL); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, + BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); + return 0; +} diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index f734833fbdda..3a73f9663b0f 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -61,5 +61,9 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c index eb063e6dead9..3112df8f90db 100644 --- a/arch/mips/boot/compressed/uart-alchemy.c +++ b/arch/mips/boot/compressed/uart-alchemy.c @@ -2,6 +2,9 @@ void putc(char c) { - /* all current (Jan. 2010) in-kernel boards */ +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig new file mode 100644 index 000000000000..c38b190151c4 --- /dev/null +++ b/arch/mips/configs/db1300_defconfig @@ -0,0 +1,391 @@ +CONFIG_MIPS=y +CONFIG_MIPS_ALCHEMY=y +CONFIG_ALCHEMY_GPIOINT_AU1300=y +CONFIG_MIPS_DB1300=y +CONFIG_SOC_AU1300=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +CONFIG_GENERIC_GPIO=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_CPU_MIPS32_R1=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_32BIT=y +CONFIG_PAGE_SIZE_4KB=y +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HZ_100=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_HAVE_IRQ_WORK=y +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="-db1300" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_LZMA=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_FHANDLE=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_TINY_RCU=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_SLAB=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_INLINE_SPIN_UNLOCK=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_MMU=y +CONFIG_PCCARD=y +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_TRAD_SIGNALS=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_INET_TUNNEL=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_IDS=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_UB=y +CONFIG_HAVE_IDE=y +CONFIG_IDE=y +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +CONFIG_BLK_DEV_IDECS=y +CONFIG_IDE_TASK_IOCTL=y +CONFIG_IDE_PROC_FS=y +CONFIG_BLK_DEV_PLATFORM=y +CONFIG_SCSI_MOD=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_SMSC_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_SMSC911X=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_WM97XX=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_SMBUS=y +CONFIG_I2C_AU1550=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_AU1550=y +CONFIG_SPI_BITBANG=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +CONFIG_SENSORS_ADM1025=y +CONFIG_FB=y +CONFIG_FB_AU1200=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_CACHE_LZO=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_I2S=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +CONFIG_SND_SOC_DB1300=y +CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_SOC_WM8731=y +CONFIG_SND_SOC_WM9712=y +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_USB_HID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_AU1XXX=y +CONFIG_EXT2_FS=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_GENERIC_ACL=y +CONFIG_FAT_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +CONFIG_JFFS2_CMODE_PRIORITY=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_UTF8=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="video=au1200fb:panel:bs console=tty console=ttyS2,115200" +CONFIG_DEBUG_ZBOOT=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y +CONFIG_BITREVERSE=y +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 618d2de02ed3..0ef630071304 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -34,6 +34,8 @@ #define PB1200_BCSR_PHYS_ADDR 0x0D800000 #define PB1200_BCSR_HEXLED_OFS 0x00400000 +#define DB1300_BCSR_PHYS_ADDR 0x19800000 +#define DB1300_BCSR_HEXLED_OFS 0x00400000 enum bcsr_id { /* BCSR base 1 */ @@ -105,6 +107,7 @@ enum bcsr_whoami_boards { BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, BCSR_WHOAMI_PB1200_DDR2, BCSR_WHOAMI_DB1200, + BCSR_WHOAMI_DB1300, }; /* STATUS reg. Unless otherwise noted, they're valid on all boards. @@ -118,12 +121,12 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_SRAMWIDTH 0x0080 #define BCSR_STATUS_FLASHBUSY 0x0100 #define BCSR_STATUS_ROMBUSY 0x0400 -#define BCSR_STATUS_SD0WP 0x0400 /* DB1200 */ +#define BCSR_STATUS_SD0WP 0x0400 /* DB1200/DB1300:SD1 */ #define BCSR_STATUS_SD1WP 0x0800 #define BCSR_STATUS_USBOTGID 0x0800 /* PB/DB1550 */ #define BCSR_STATUS_DB1000_SWAPBOOT 0x2000 -#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200 */ -#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200 */ +#define BCSR_STATUS_DB1200_SWAPBOOT 0x0040 /* DB1200/1300 */ +#define BCSR_STATUS_IDECBLID 0x0200 /* DB1200/1300 */ #define BCSR_STATUS_DB1200_U0RXD 0x1000 /* DB1200 */ #define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */ #define BCSR_STATUS_FLASHDEN 0xC000 @@ -133,6 +136,11 @@ enum bcsr_whoami_boards { #define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */ #define BCSR_STATUS_PB1550_U3RXD 0x8000 /* PB1550 */ +#define BCSR_STATUS_CFWP 0x4000 /* DB1300 */ +#define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */ +#define BCSR_STATUS_OTGOCn 0x1000 /* DB1300 */ +#define BCSR_STATUS_DCDMARQ 0x0010 /* DB1300 */ +#define BCSR_STATUS_IDEDMARQ 0x0020 /* DB1300 */ /* DB/PB1000,1100,1500,1550 */ #define BCSR_RESETS_PHY0 0x0001 @@ -160,12 +168,12 @@ enum bcsr_whoami_boards { #define BCSR_BOARD_SD1WP 0x8000 /* DB1100 */ -/* DB/PB1200 */ +/* DB/PB1200/1300 */ #define BCSR_RESETS_ETH 0x0001 #define BCSR_RESETS_CAMERA 0x0002 #define BCSR_RESETS_DC 0x0004 #define BCSR_RESETS_IDE 0x0008 -#define BCSR_RESETS_TV 0x0010 /* DB1200 */ +#define BCSR_RESETS_TV 0x0010 /* DB1200/1300 */ /* Not resets but in the same register */ #define BCSR_RESETS_PWMR1MUX 0x0800 /* DB1200 */ #define BCSR_RESETS_PB1200_WSCFSM 0x0800 /* PB1200 */ @@ -174,13 +182,22 @@ enum bcsr_whoami_boards { #define BCSR_RESETS_SPISEL 0x4000 #define BCSR_RESETS_SD1MUX 0x8000 /* PB1200 */ +#define BCSR_RESETS_VDDQSHDN 0x0200 /* DB1300 */ +#define BCSR_RESETS_OTPPGM 0x0400 /* DB1300 */ +#define BCSR_RESETS_OTPSCLK 0x0800 /* DB1300 */ +#define BCSR_RESETS_OTPWRPROT 0x1000 /* DB1300 */ +#define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */ +#define BCSR_RESETS_OTGPWR 0x4000 /* DB1300 */ +#define BCSR_RESETS_USBHPWR 0x8000 /* DB1300 */ + #define BCSR_BOARD_LCDVEE 0x0001 #define BCSR_BOARD_LCDVDD 0x0002 #define BCSR_BOARD_LCDBL 0x0004 #define BCSR_BOARD_CAMSNAP 0x0010 #define BCSR_BOARD_CAMPWR 0x0020 #define BCSR_BOARD_SD0PWR 0x0040 - +#define BCSR_BOARD_CAMCS 0x0010 /* DB1300 */ +#define BCSR_BOARD_HDMI_DE 0x0040 /* DB1300 */ #define BCSR_SWITCHES_DIP 0x00FF #define BCSR_SWITCHES_DIP_1 0x0080 @@ -214,7 +231,10 @@ enum bcsr_whoami_boards { #define BCSR_SYSTEM_RESET 0x8000 /* clear to reset */ #define BCSR_SYSTEM_PWROFF 0x4000 /* set to power off */ #define BCSR_SYSTEM_VDDI 0x001F /* PB1xxx boards */ - +#define BCSR_SYSTEM_DEBUGCSMASK 0x003F /* DB1300 */ +#define BCSR_SYSTEM_UDMAMODE 0x0100 /* DB1300 */ +#define BCSR_SYSTEM_WAKEONIRQ 0x0200 /* DB1300 */ +#define BCSR_SYSTEM_VDDI1300 0x3C00 /* DB1300 */ diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h new file mode 100644 index 000000000000..7fe5fb3ba877 --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/db1300.h @@ -0,0 +1,40 @@ +/* + * NetLogic DB1300 board constants + */ + +#ifndef _DB1300_H_ +#define _DB1300_H_ + +/* FPGA (external mux) interrupt sources */ +#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1) +#define DB1300_IDE_INT (DB1300_FIRST_INT + 0) +#define DB1300_ETH_INT (DB1300_FIRST_INT + 1) +#define DB1300_CF_INT (DB1300_FIRST_INT + 2) +#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) +#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) +#define DB1300_DC_INT (DB1300_FIRST_INT + 6) +#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) +#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) +#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) +#define DB1300_AC97_INT (DB1300_FIRST_INT + 10) +#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) +#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) +#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) +#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) +#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) +#define DB1300_LAST_INT (DB1300_FIRST_INT + 15) + +/* SMSC9210 CS */ +#define DB1300_ETH_PHYS_ADDR 0x19000000 +#define DB1300_ETH_PHYS_END 0x197fffff + +/* ATA CS */ +#define DB1300_IDE_PHYS_ADDR 0x18800000 +#define DB1300_IDE_REG_SHIFT 5 +#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) + +/* NAND CS */ +#define DB1300_NAND_PHYS_ADDR 0x20000000 +#define DB1300_NAND_PHYS_END 0x20000fff + +#endif /* _DB1300_H_ */ diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h new file mode 100644 index 000000000000..15b26693238f --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/irq.h @@ -0,0 +1,23 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_IRQ_H +#define __ASM_MACH_GENERIC_IRQ_H + + +#ifdef NR_IRQS +#undef NR_IRQS +#endif + +#ifndef MIPS_CPU_IRQ_BASE +#define MIPS_CPU_IRQ_BASE 0 +#endif + +/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */ +#define NR_IRQS 152 + +#endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index c022b5cedcf9..f9e3fb3a285b 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -161,8 +161,8 @@ config PCMCIA_ALCHEMY_DEVBOARD select 64BIT_PHYS_ADDR help Enable this driver of you want PCMCIA support on your Alchemy - Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200 board. - NOT suitable for the PB1000! + Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200, DB1300 + board. NOT suitable for the PB1000! This driver is also available as a module called db1xxx_ss.ko diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c index 3e49df6d5e3b..5b7c22784aff 100644 --- a/drivers/pcmcia/db1xxx_ss.c +++ b/drivers/pcmcia/db1xxx_ss.c @@ -7,7 +7,7 @@ /* This is a fairly generic PCMCIA socket driver suitable for the * following Alchemy Development boards: - * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200. + * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200, Db1300 * * The Db1000 is used as a reference: Per-socket card-, carddetect- and * statuschange IRQs connected to SoC GPIOs, control and status register @@ -18,6 +18,7 @@ * - Pb1100/Pb1500: single socket only; voltage key bits VS are * at STATUS[5:4] (instead of STATUS[1:0]). * - Au1200-based: additional card-eject irqs, irqs not gpios! + * - Db1300: Db1200-like, no pwr ctrl, single socket (#1). */ #include @@ -59,11 +60,17 @@ struct db1x_pcmcia_sock { #define BOARD_TYPE_DEFAULT 0 /* most boards */ #define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */ #define BOARD_TYPE_PB1100 2 /* VS bits slightly different */ +#define BOARD_TYPE_DB1300 3 /* no power control */ int board_type; }; #define to_db1x_socket(x) container_of(x, struct db1x_pcmcia_sock, socket) +static int db1300_card_inserted(struct db1x_pcmcia_sock *sock) +{ + return bcsr_read(BCSR_SIGSTAT) & (1 << 8); +} + /* DB/PB1200: check CPLD SIGSTATUS register bit 10/12 */ static int db1200_card_inserted(struct db1x_pcmcia_sock *sock) { @@ -84,6 +91,8 @@ static int db1x_card_inserted(struct db1x_pcmcia_sock *sock) switch (sock->board_type) { case BOARD_TYPE_DB1200: return db1200_card_inserted(sock); + case BOARD_TYPE_DB1300: + return db1300_card_inserted(sock); default: return db1000_card_inserted(sock); } @@ -160,7 +169,8 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) * ejection handler have been registered and the currently * active one disabled. */ - if (sock->board_type == BOARD_TYPE_DB1200) { + if ((sock->board_type == BOARD_TYPE_DB1200) || + (sock->board_type == BOARD_TYPE_DB1300)) { ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq, IRQF_DISABLED, "pcmcia_insert", sock); if (ret) @@ -174,7 +184,7 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) } /* enable the currently silent one */ - if (db1200_card_inserted(sock)) + if (db1x_card_inserted(sock)) enable_irq(sock->eject_irq); else enable_irq(sock->insert_irq); @@ -270,7 +280,8 @@ static int db1x_pcmcia_configure(struct pcmcia_socket *skt, } /* create new voltage code */ - cr_set |= ((v << 2) | p) << (sock->nr * 8); + if (sock->board_type != BOARD_TYPE_DB1300) + cr_set |= ((v << 2) | p) << (sock->nr * 8); changed = state->flags ^ sock->old_flags; @@ -343,6 +354,10 @@ static int db1x_pcmcia_get_status(struct pcmcia_socket *skt, /* if Vcc is not zero, we have applied power to a card */ status |= GET_VCC(cr, sock->nr) ? SS_POWERON : 0; + /* DB1300: power always on, but don't tell when no card present */ + if ((sock->board_type == BOARD_TYPE_DB1300) && (status & SS_DETECT)) + status = SS_POWERON | SS_3VCARD | SS_DETECT; + /* reset de-asserted? then we're ready */ status |= (GET_RESET(cr, sock->nr)) ? SS_READY : SS_RESET; @@ -419,6 +434,9 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev) case BCSR_WHOAMI_PB1200 ... BCSR_WHOAMI_DB1200: sock->board_type = BOARD_TYPE_DB1200; break; + case BCSR_WHOAMI_DB1300: + sock->board_type = BOARD_TYPE_DB1300; + break; default: printk(KERN_INFO "db1xxx-ss: unknown board %d!\n", bid); ret = -ENODEV; diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c index 72005598040f..6c4342f1d9b4 100644 --- a/drivers/video/au1200fb.c +++ b/drivers/video/au1200fb.c @@ -639,6 +639,42 @@ static struct panel_settings known_lcd_panels[] = 856, 856, 480, 480, }, + [9] = { + .name = "DB1300_800x480", + .monspecs = { + .modedb = NULL, + .modedb_len = 0, + .hfmin = 30000, + .hfmax = 70000, + .vfmin = 60, + .vfmax = 60, + .dclkmin = 6000000, + .dclkmax = 28000000, + .input = FB_DISP_RGB, + }, + .mode_screen = LCD_SCREEN_SX_N(800) | + LCD_SCREEN_SY_N(480), + .mode_horztiming = LCD_HORZTIMING_HPW_N(5) | + LCD_HORZTIMING_HND1_N(16) | + LCD_HORZTIMING_HND2_N(8), + .mode_verttiming = LCD_VERTTIMING_VPW_N(4) | + LCD_VERTTIMING_VND1_N(8) | + LCD_VERTTIMING_VND2_N(5), + .mode_clkcontrol = LCD_CLKCONTROL_PCD_N(1) | + LCD_CLKCONTROL_IV | + LCD_CLKCONTROL_IH, + .mode_pwmdiv = 0x00000000, + .mode_pwmhi = 0x00000000, + .mode_outmask = 0x00FFFFFF, + .mode_fifoctrl = 0x2f2f2f2f, + .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ + .mode_backlight = 0x00000000, + .mode_auxpll = (48/12) * 2, + .device_init = board_au1200fb_panel_init, + .device_shutdown = board_au1200fb_panel_shutdown, + 800, 800, + 480, 480, + }, }; #define NUM_PANELS (ARRAY_SIZE(known_lcd_panels)) diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 93323cc0452a..78b664921cb3 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -51,12 +51,14 @@ config SND_SOC_DB1000 of boards (DB1000/DB1500/DB1100). config SND_SOC_DB1200 - tristate "DB1200 AC97+I2S audio support" + tristate "DB1200/DB1300 Audio support" depends on SND_SOC_AU1XPSC select SND_SOC_AU1XPSC_AC97 select SND_SOC_AC97_CODEC + select SND_SOC_WM9712 select SND_SOC_AU1XPSC_I2S select SND_SOC_WM8731 help - Select this option to enable audio (AC97 or I2S) on the - Alchemy/AMD/RMI DB1200 demoboard. + Select this option to enable audio (AC97 and I2S) on the + Alchemy/AMD/RMI/NetLogic Db1200 and Db1300 evaluation boards. + If you need Db1300 touchscreen support, you definitely want to say Y. diff --git a/sound/soc/au1x/db1200.c b/sound/soc/au1x/db1200.c index 289312c14b99..ca2335afe6b6 100644 --- a/sound/soc/au1x/db1200.c +++ b/sound/soc/au1x/db1200.c @@ -1,5 +1,5 @@ /* - * DB1200 ASoC audio fabric support code. + * DB1200/DB1300 ASoC audio fabric support code. * * (c) 2008-2011 Manuel Lauss * @@ -28,6 +28,12 @@ static struct platform_device_id db1200_pids[] = { }, { .name = "db1200-i2s", .driver_data = 1, + }, { + .name = "db1300-ac97", + .driver_data = 2, + }, { + .name = "db1300-i2s", + .driver_data = 3, }, {}, }; @@ -49,6 +55,21 @@ static struct snd_soc_card db1200_ac97_machine = { .num_links = 1, }; +static struct snd_soc_dai_link db1300_ac97_dai = { + .name = "AC97", + .stream_name = "AC97 HiFi", + .codec_dai_name = "wm9712-hifi", + .cpu_dai_name = "au1xpsc_ac97.1", + .platform_name = "au1xpsc-pcm.1", + .codec_name = "wm9712-codec.1", +}; + +static struct snd_soc_card db1300_ac97_machine = { + .name = "DB1300_AC97", + .dai_link = &db1300_ac97_dai, + .num_links = 1, +}; + /*------------------------- I2S PART ---------------------------*/ static int db1200_i2s_startup(struct snd_pcm_substream *substream) @@ -98,11 +119,29 @@ static struct snd_soc_card db1200_i2s_machine = { .num_links = 1, }; +static struct snd_soc_dai_link db1300_i2s_dai = { + .name = "WM8731", + .stream_name = "WM8731 PCM", + .codec_dai_name = "wm8731-hifi", + .cpu_dai_name = "au1xpsc_i2s.2", + .platform_name = "au1xpsc-pcm.2", + .codec_name = "wm8731.0-001b", + .ops = &db1200_i2s_wm8731_ops, +}; + +static struct snd_soc_card db1300_i2s_machine = { + .name = "DB1300_I2S", + .dai_link = &db1300_i2s_dai, + .num_links = 1, +}; + /*------------------------- COMMON PART ---------------------------*/ static struct snd_soc_card *db1200_cards[] __devinitdata = { &db1200_ac97_machine, &db1200_i2s_machine, + &db1300_ac97_machine, + &db1300_i2s_machine, }; static int __devinit db1200_audio_probe(struct platform_device *pdev) @@ -147,5 +186,5 @@ module_init(db1200_audio_load); module_exit(db1200_audio_unload); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("DB1200 ASoC audio support"); +MODULE_DESCRIPTION("DB1200/DB1300 ASoC audio support"); MODULE_AUTHOR("Manuel Lauss"); -- cgit v1.2.3 From a9b71a8f0f42efe1a21154667ca02305c950d30a Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:21 +0000 Subject: MIPS: Alchemy: move au1200fb global functions to platform data au1200fb calls 3 functions which have to be defined in board code. Fix this ugliness with the introduction of platform_data. Signed-off-by: Manuel Lauss Cc: linux-fbdev@vger.kernel.org To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2871/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/devboards/db1200.c | 51 +++--- arch/mips/alchemy/devboards/db1300.c | 52 +++--- arch/mips/alchemy/devboards/pb1200.c | 55 +++--- arch/mips/include/asm/mach-au1x00/au1200fb.h | 14 ++ drivers/video/au1200fb.c | 241 ++++++++++++--------------- 5 files changed, 213 insertions(+), 200 deletions(-) create mode 100644 arch/mips/include/asm/mach-au1x00/au1200fb.h (limited to 'drivers') diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index 43f5f1be9d68..e2cc5f921538 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -422,6 +423,33 @@ static struct platform_device db1200_mmc0_dev = { /**********************************************************************/ +static int db1200fb_panel_index(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +static int db1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +static int db1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} + +static struct au1200fb_platdata db1200fb_pd = { + .panel_index = db1200fb_panel_index, + .panel_init = db1200fb_panel_init, + .panel_shutdown = db1200fb_panel_shutdown, +}; + static struct resource au1200_lcd_res[] = { [0] = { .start = AU1200_LCD_PHYS_ADDR, @@ -443,6 +471,7 @@ static struct platform_device au1200_lcd_dev = { .dev = { .dma_mask = &au1200_lcd_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1200fb_pd, }, .num_resources = ARRAY_SIZE(au1200_lcd_res), .resource = au1200_lcd_res, @@ -681,25 +710,3 @@ static int __init db1200_dev_init(void) return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); } device_initcall(db1200_dev_init); - -/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ -int board_au1200fb_panel(void) -{ - return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; -} - -int board_au1200fb_panel_init(void) -{ - /* Apply power */ - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); - return 0; -} - -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL, 0); - return 0; -} diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index c41788c59278..7f3dacb60ea5 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -23,6 +23,7 @@ #include #include +#include #include #include #include @@ -636,6 +637,33 @@ static struct platform_device db1300_sndi2s_dev = { /**********************************************************************/ +static int db1300fb_panel_index(void) +{ + return 9; /* DB1300_800x480 */ +} + +static int db1300fb_panel_init(void) +{ + /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, + BCSR_BOARD_LCDBL); + return 0; +} + +static int db1300fb_panel_shutdown(void) +{ + /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, + BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); + return 0; +} + +static struct au1200fb_platdata db1300fb_pd = { + .panel_index = db1300fb_panel_index, + .panel_init = db1300fb_panel_init, + .panel_shutdown = db1300fb_panel_shutdown, +}; + static struct resource au1300_lcd_res[] = { [0] = { .start = AU1200_LCD_PHYS_ADDR, @@ -657,6 +685,7 @@ static struct platform_device db1300_lcd_dev = { .dev = { .dma_mask = &au1300_lcd_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &db1300fb_pd, }, .num_resources = ARRAY_SIZE(au1300_lcd_res), .resource = au1300_lcd_res, @@ -762,26 +791,3 @@ void __init board_setup(void) alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); } - - -/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ -int board_au1200fb_panel(void) -{ - return 9; /* DB1300_800x480 */ -} - -int board_au1200fb_panel_init(void) -{ - /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, - BCSR_BOARD_LCDBL); - return 0; -} - -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, - BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); - return 0; -} diff --git a/arch/mips/alchemy/devboards/pb1200.c b/arch/mips/alchemy/devboards/pb1200.c index a1b64977b471..a2676c95053b 100644 --- a/arch/mips/alchemy/devboards/pb1200.c +++ b/arch/mips/alchemy/devboards/pb1200.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -351,6 +352,33 @@ static struct platform_device pb1200_i2c_dev = { .resource = au1200_psc0_res, }; +static int pb1200fb_panel_index(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +static int pb1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +static int pb1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} + +static struct au1200fb_platdata pb1200fb_pd = { + .panel_index = pb1200fb_panel_index, + .panel_init = pb1200fb_panel_init, + .panel_shutdown = pb1200fb_panel_shutdown, +}; + static struct resource au1200_lcd_res[] = { [0] = { .start = AU1200_LCD_PHYS_ADDR, @@ -366,12 +394,13 @@ static struct resource au1200_lcd_res[] = { static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); -static struct platform_device au1200_lcd_dev = { +static struct platform_device pb1200_lcd_dev = { .name = "au1200-lcd", .id = 0, .dev = { .dma_mask = &au1200_lcd_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &pb1200fb_pd, }, .num_resources = ARRAY_SIZE(au1200_lcd_res), .resource = au1200_lcd_res, @@ -383,7 +412,7 @@ static struct platform_device *board_platform_devices[] __initdata = { &pb1200_i2c_dev, &pb1200_mmc0_dev, &pb1200_mmc1_dev, - &au1200_lcd_dev, + &pb1200_lcd_dev, }; static int __init board_register_devices(void) @@ -440,25 +469,3 @@ static int __init board_register_devices(void) ARRAY_SIZE(board_platform_devices)); } device_initcall(board_register_devices); - - -int board_au1200fb_panel(void) -{ - return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; -} - -int board_au1200fb_panel_init(void) -{ - /* Apply power */ - bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL); - return 0; -} - -int board_au1200fb_panel_shutdown(void) -{ - /* Remove power */ - bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | - BCSR_BOARD_LCDBL, 0); - return 0; -} diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h new file mode 100644 index 000000000000..b3c87cc64bb9 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h @@ -0,0 +1,14 @@ +/* + * platform data for au1200fb driver. + */ + +#ifndef _AU1200FB_PLAT_H_ +#define _AU1200FB_PLAT_H_ + +struct au1200fb_platdata { + int (*panel_index)(void); + int (*panel_init)(void); + int (*panel_shutdown)(void); +}; + +#endif diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c index 6c4342f1d9b4..04e4479d5afd 100644 --- a/drivers/video/au1200fb.c +++ b/drivers/video/au1200fb.c @@ -44,6 +44,7 @@ #include #include +#include /* platform_data */ #include "au1200fb.h" #define DRIVER_NAME "au1200fb" @@ -143,6 +144,7 @@ struct au1200_lcd_iodata_t { /* Private, per-framebuffer management information (independent of the panel itself) */ struct au1200fb_device { struct fb_info *fb_info; /* FB driver info record */ + struct au1200fb_platdata *pd; int plane; unsigned char* fb_mem; /* FrameBuffer memory map */ @@ -201,9 +203,6 @@ struct window_settings { #define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01 #endif -extern int board_au1200fb_panel_init (void); -extern int board_au1200fb_panel_shutdown (void); - /* * Default window configurations */ @@ -334,8 +333,6 @@ struct panel_settings uint32 mode_toyclksrc; uint32 mode_backlight; uint32 mode_auxpll; - int (*device_init)(void); - int (*device_shutdown)(void); #define Xres min_xres #define Yres min_yres u32 min_xres; /* Minimum horizontal resolution */ @@ -385,8 +382,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 320, 320, 240, 240, }, @@ -415,8 +410,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 640, 480, 640, 480, }, @@ -445,8 +438,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 800, 800, 600, 600, }, @@ -475,8 +466,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 6, /* 72MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 1024, 1024, 768, 768, }, @@ -505,8 +494,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 10, /* 120MHz AUXPLL */ - .device_init = NULL, - .device_shutdown = NULL, 1280, 1280, 1024, 1024, }, @@ -535,8 +522,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 1024, 1024, 768, 768, }, @@ -568,8 +553,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 640, 480, 640, 480, }, @@ -601,8 +584,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 320, 320, 240, 240, }, @@ -634,8 +615,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = 8, /* 96MHz AUXPLL */ - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 856, 856, 480, 480, }, @@ -670,8 +649,6 @@ static struct panel_settings known_lcd_panels[] = .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ .mode_backlight = 0x00000000, .mode_auxpll = (48/12) * 2, - .device_init = board_au1200fb_panel_init, - .device_shutdown = board_au1200fb_panel_shutdown, 800, 800, 480, 480, }, @@ -800,7 +777,8 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane, return 0; } -static void au1200_setpanel (struct panel_settings *newpanel) +static void au1200_setpanel(struct panel_settings *newpanel, + struct au1200fb_platdata *pd) { /* * Perform global setup/init of LCD controller @@ -834,8 +812,8 @@ static void au1200_setpanel (struct panel_settings *newpanel) the controller, the clock cannot be turned off before first shutting down the controller. */ - if (panel->device_shutdown != NULL) - panel->device_shutdown(); + if (pd->panel_shutdown) + pd->panel_shutdown(); } /* Newpanel == NULL indicates a shutdown operation only */ @@ -888,7 +866,8 @@ static void au1200_setpanel (struct panel_settings *newpanel) au_sync(); /* Call init of panel */ - if (panel->device_init != NULL) panel->device_init(); + if (pd->panel_init) + pd->panel_init(); /* FIX!!!! not appropriate on panel change!!! Global setup/init */ lcd->intenable = 0; @@ -1221,6 +1200,8 @@ static int au1200fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, */ static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi) { + struct au1200fb_device *fbdev = fbi->par; + /* Short-circuit screen blanking */ if (noblanking) return 0; @@ -1230,13 +1211,13 @@ static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi) case FB_BLANK_UNBLANK: case FB_BLANK_NORMAL: /* printk("turn on panel\n"); */ - au1200_setpanel(panel); + au1200_setpanel(panel, fbdev->pd); break; case FB_BLANK_VSYNC_SUSPEND: case FB_BLANK_HSYNC_SUSPEND: case FB_BLANK_POWERDOWN: /* printk("turn off panel\n"); */ - au1200_setpanel(NULL); + au1200_setpanel(NULL, fbdev->pd); break; default: break; @@ -1464,6 +1445,7 @@ static void get_window(unsigned int plane, static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) { + struct au1200fb_device *fbdev = info->par; int plane; int val; @@ -1508,7 +1490,7 @@ static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, struct panel_settings *newpanel; panel_index = iodata.global.panel_choice; newpanel = &known_lcd_panels[panel_index]; - au1200_setpanel(newpanel); + au1200_setpanel(newpanel, fbdev->pd); } break; @@ -1624,22 +1606,102 @@ static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev) /*-------------------------------------------------------------------------*/ -/* AU1200 LCD controller device driver */ +static int au1200fb_setup(struct au1200fb_platdata *pd) +{ + char *options = NULL; + char *this_opt, *endptr; + int num_panels = ARRAY_SIZE(known_lcd_panels); + int panel_idx = -1; + + fb_get_options(DRIVER_NAME, &options); + + if (!options) + goto out; + + while ((this_opt = strsep(&options, ",")) != NULL) { + /* Panel option - can be panel name, + * "bs" for board-switch, or number/index */ + if (!strncmp(this_opt, "panel:", 6)) { + int i; + long int li; + char *endptr; + this_opt += 6; + /* First check for index, which allows + * to short circuit this mess */ + li = simple_strtol(this_opt, &endptr, 0); + if (*endptr == '\0') + panel_idx = (int)li; + else if (strcmp(this_opt, "bs") == 0) + panel_idx = pd->panel_index(); + else { + for (i = 0; i < num_panels; i++) { + if (!strcmp(this_opt, + known_lcd_panels[i].name)) { + panel_idx = i; + break; + } + } + } + if ((panel_idx < 0) || (panel_idx >= num_panels)) + print_warn("Panel %s not supported!", this_opt); + else + panel_index = panel_idx; + + } else if (strncmp(this_opt, "nohwcursor", 10) == 0) + nohwcursor = 1; + else if (strncmp(this_opt, "devices:", 8) == 0) { + this_opt += 8; + device_count = simple_strtol(this_opt, &endptr, 0); + if ((device_count < 0) || + (device_count > MAX_DEVICE_COUNT)) + device_count = MAX_DEVICE_COUNT; + } else if (strncmp(this_opt, "wincfg:", 7) == 0) { + this_opt += 7; + window_index = simple_strtol(this_opt, &endptr, 0); + if ((window_index < 0) || + (window_index >= ARRAY_SIZE(windows))) + window_index = DEFAULT_WINDOW_INDEX; + } else if (strncmp(this_opt, "off", 3) == 0) + return 1; + else + print_warn("Unsupported option \"%s\"", this_opt); + } + +out: + return 0; +} + +/* AU1200 LCD controller device driver */ static int __devinit au1200fb_drv_probe(struct platform_device *dev) { struct au1200fb_device *fbdev; + struct au1200fb_platdata *pd; struct fb_info *fbi = NULL; unsigned long page; int bpp, plane, ret, irq; + print_info("" DRIVER_DESC ""); + + pd = dev->dev.platform_data; + if (!pd) + return -ENODEV; + + /* Setup driver with options */ + if (au1200fb_setup(pd)) + return -ENODEV; + + /* Point to the panel selected */ + panel = &known_lcd_panels[panel_index]; + win = &windows[window_index]; + + printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name); + printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name); + /* shut gcc up */ ret = 0; fbdev = NULL; - /* Kickstart the panel */ - au1200_setpanel(panel); - for (plane = 0; plane < device_count; ++plane) { bpp = winbpp(win->w[plane].mode_winctrl1); if (win->w[plane].xres == 0) @@ -1655,6 +1717,7 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev) _au1200fb_infos[plane] = fbi; fbdev = fbi->par; fbdev->fb_info = fbi; + fbdev->pd = pd; fbdev->plane = plane; @@ -1716,6 +1779,11 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev) goto failed; } + platform_set_drvdata(dev, pd); + + /* Kickstart the panel */ + au1200_setpanel(panel, pd); + return 0; failed: @@ -1735,12 +1803,13 @@ failed: static int __devexit au1200fb_drv_remove(struct platform_device *dev) { + struct au1200fb_platdata *pd = platform_get_drvdata(dev); struct au1200fb_device *fbdev; struct fb_info *fbi; int plane; /* Turn off the panel */ - au1200_setpanel(NULL); + au1200_setpanel(NULL, pd); for (plane = 0; plane < device_count; ++plane) { fbi = _au1200fb_infos[plane]; @@ -1768,7 +1837,8 @@ static int __devexit au1200fb_drv_remove(struct platform_device *dev) #ifdef CONFIG_PM static int au1200fb_drv_suspend(struct device *dev) { - au1200_setpanel(NULL); + struct au1200fb_platdata *pd = dev_get_drvdata(dev); + au1200_setpanel(NULL, pd); lcd->outmask = 0; au_sync(); @@ -1778,11 +1848,12 @@ static int au1200fb_drv_suspend(struct device *dev) static int au1200fb_drv_resume(struct device *dev) { + struct au1200fb_platdata *pd = dev_get_drvdata(dev); struct fb_info *fbi; int i; /* Kickstart the panel */ - au1200_setpanel(panel); + au1200_setpanel(panel, pd); for (i = 0; i < device_count; i++) { fbi = _au1200fb_infos[i]; @@ -1817,100 +1888,8 @@ static struct platform_driver au1200fb_driver = { /*-------------------------------------------------------------------------*/ -/* Kernel driver */ - -static int au1200fb_setup(void) -{ - char *options = NULL; - char *this_opt, *endptr; - int num_panels = ARRAY_SIZE(known_lcd_panels); - int panel_idx = -1; - - fb_get_options(DRIVER_NAME, &options); - - if (options) { - while ((this_opt = strsep(&options,",")) != NULL) { - /* Panel option - can be panel name, - * "bs" for board-switch, or number/index */ - if (!strncmp(this_opt, "panel:", 6)) { - int i; - long int li; - char *endptr; - this_opt += 6; - /* First check for index, which allows - * to short circuit this mess */ - li = simple_strtol(this_opt, &endptr, 0); - if (*endptr == '\0') { - panel_idx = (int)li; - } - else if (strcmp(this_opt, "bs") == 0) { - extern int board_au1200fb_panel(void); - panel_idx = board_au1200fb_panel(); - } - - else - for (i = 0; i < num_panels; i++) { - if (!strcmp(this_opt, known_lcd_panels[i].name)) { - panel_idx = i; - break; - } - } - - if ((panel_idx < 0) || (panel_idx >= num_panels)) { - print_warn("Panel %s not supported!", this_opt); - } - else - panel_index = panel_idx; - } - - else if (strncmp(this_opt, "nohwcursor", 10) == 0) { - nohwcursor = 1; - } - - else if (strncmp(this_opt, "devices:", 8) == 0) { - this_opt += 8; - device_count = simple_strtol(this_opt, - &endptr, 0); - if ((device_count < 0) || - (device_count > MAX_DEVICE_COUNT)) - device_count = MAX_DEVICE_COUNT; - } - - else if (strncmp(this_opt, "wincfg:", 7) == 0) { - this_opt += 7; - window_index = simple_strtol(this_opt, - &endptr, 0); - if ((window_index < 0) || - (window_index >= ARRAY_SIZE(windows))) - window_index = DEFAULT_WINDOW_INDEX; - } - - else if (strncmp(this_opt, "off", 3) == 0) - return 1; - /* Unsupported option */ - else { - print_warn("Unsupported option \"%s\"", this_opt); - } - } - } - return 0; -} - static int __init au1200fb_init(void) { - print_info("" DRIVER_DESC ""); - - /* Setup driver with options */ - if (au1200fb_setup()) - return -ENODEV; - - /* Point to the panel selected */ - panel = &known_lcd_panels[panel_index]; - win = &windows[window_index]; - - printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name); - printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name); - return platform_driver_register(&au1200fb_driver); } -- cgit v1.2.3 From f59c811f8c44e60a59783e3337594da638a48dff Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 10 Nov 2011 12:06:22 +0000 Subject: MIPS: Alchemy: one kernel for DB1000/DB1500/DB1100 These 3 boards are very similar; with this patch a single kernel image which runs on all three can be built. Tested on DB1500 and DB1100. Signed-off-by: Manuel Lauss To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2872/ Signed-off-by: Ralf Baechle --- arch/mips/alchemy/Kconfig | 21 +- arch/mips/alchemy/Platform | 16 +- arch/mips/alchemy/devboards/Makefile | 4 +- arch/mips/alchemy/devboards/db1000.c | 267 +++++++++++++++++++++++++ arch/mips/alchemy/devboards/db1x00.c | 256 ------------------------ arch/mips/alchemy/devboards/prom.c | 4 +- arch/mips/configs/db1000_defconfig | 369 +++++++++++++++++++++++++++++------ arch/mips/configs/db1100_defconfig | 122 ------------ arch/mips/configs/db1500_defconfig | 128 ------------ drivers/net/irda/au1k_ir.c | 10 +- drivers/video/au1100fb.c | 12 -- 11 files changed, 584 insertions(+), 625 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1000.c delete mode 100644 arch/mips/alchemy/devboards/db1x00.c delete mode 100644 arch/mips/configs/db1100_defconfig delete mode 100644 arch/mips/configs/db1500_defconfig (limited to 'drivers') diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index e1b3be787f80..0faaab24376e 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -27,17 +27,12 @@ config MIPS_MTX1 select SYS_HAS_EARLY_PRINTK config MIPS_DB1000 - bool "Alchemy DB1000 board" + bool "Alchemy DB1000/DB1500/DB1100 boards" select ALCHEMY_GPIOINT_AU1000 select DMA_NONCOHERENT select HW_HAS_PCI - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - -config MIPS_DB1100 - bool "Alchemy DB1100 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK @@ -57,16 +52,6 @@ config MIPS_DB1300 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK -config MIPS_DB1500 - bool "Alchemy DB1500 board" - select ALCHEMY_GPIOINT_AU1000 - select DMA_NONCOHERENT - select HW_HAS_PCI - select MIPS_DISABLE_OBSOLETE_IDE - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_HAS_EARLY_PRINTK - config MIPS_DB1550 bool "Alchemy DB1550 board" select ALCHEMY_GPIOINT_AU1000 diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform index bbdcc150d04d..33f80e8cbd69 100644 --- a/arch/mips/alchemy/Platform +++ b/arch/mips/alchemy/Platform @@ -26,26 +26,12 @@ cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 # -# AMD Alchemy Db1000 eval board +# AMD Alchemy Db1000/Db1500/Db1100 eval boards # platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 -# -# AMD Alchemy Db1100 eval board -# -platform-$(CONFIG_MIPS_DB1100) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 - -# -# AMD Alchemy Db1500 eval board -# -platform-$(CONFIG_MIPS_DB1500) += alchemy/devboards/ -cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 -load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 - # # AMD Alchemy Db1550 eval board # diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 2fbf17909200..3c37fb303364 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -7,9 +7,7 @@ obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MIPS_PB1100) += pb1100.o obj-$(CONFIG_MIPS_PB1500) += pb1500.o obj-$(CONFIG_MIPS_PB1550) += pb1550.o -obj-$(CONFIG_MIPS_DB1000) += db1x00.o -obj-$(CONFIG_MIPS_DB1100) += db1x00.o +obj-$(CONFIG_MIPS_DB1000) += db1000.o obj-$(CONFIG_MIPS_DB1200) += db1200.o obj-$(CONFIG_MIPS_DB1300) += db1300.o -obj-$(CONFIG_MIPS_DB1500) += db1x00.o obj-$(CONFIG_MIPS_DB1550) += db1550.o diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c new file mode 100644 index 000000000000..57ed5f1c4919 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1000.c @@ -0,0 +1,267 @@ +/* + * DBAu1000/1500/1100 board support + * + * Copyright 2000, 2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "platform.h" + +#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) + +struct pci_dev; + +static const char *board_type_str(void) +{ + switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { + case BCSR_WHOAMI_DB1000: + return "DB1000"; + case BCSR_WHOAMI_DB1500: + return "DB1500"; + case BCSR_WHOAMI_DB1100: + return "DB1100"; + default: + return "(unknown)"; + } +} + +const char *get_system_type(void) +{ + return board_type_str(); +} + +void __init board_setup(void) +{ + /* initialize board register space */ + bcsr_init(DB1000_BCSR_PHYS_ADDR, + DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); + + printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str()); + +#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) + { + u32 pin_func; + + /* Set IRFIRSEL instead of GPIO15 */ + pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; + au_writel(pin_func, SYS_PINFUNC); + /* Power off until the driver is in use */ + bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, + BCSR_RESETS_IRDA_MODE_OFF); + } +#endif + bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ + + /* Enable GPIO[31:0] inputs */ + alchemy_gpio1_input_enable(); +} + + +static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) +{ + if ((slot < 12) || (slot > 13) || pin == 0) + return -1; + if (slot == 12) + return (pin == 1) ? AU1500_PCI_INTA : 0xff; + if (slot == 13) { + switch (pin) { + case 1: return AU1500_PCI_INTA; + case 2: return AU1500_PCI_INTB; + case 3: return AU1500_PCI_INTC; + case 4: return AU1500_PCI_INTD; + } + } + return -1; +} + +static struct resource alchemy_pci_host_res[] = { + [0] = { + .start = AU1500_PCI_PHYS_ADDR, + .end = AU1500_PCI_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct alchemy_pci_platdata db1500_pci_pd = { + .board_map_irq = db1500_map_pci_irq, +}; + +static struct platform_device db1500_pci_host_dev = { + .dev.platform_data = &db1500_pci_pd, + .name = "alchemy-pci", + .id = 0, + .num_resources = ARRAY_SIZE(alchemy_pci_host_res), + .resource = alchemy_pci_host_res, +}; + +static int __init db1500_pci_init(void) +{ + if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1500) + return platform_device_register(&db1500_pci_host_dev); + return 0; +} +/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ +arch_initcall(db1500_pci_init); + + +static struct resource au1100_lcd_resources[] = { + [0] = { + .start = AU1100_LCD_PHYS_ADDR, + .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1100_LCD_INT, + .end = AU1100_LCD_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); + +static struct platform_device au1100_lcd_device = { + .name = "au1100-lcd", + .id = 0, + .dev = { + .dma_mask = &au1100_lcd_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(au1100_lcd_resources), + .resource = au1100_lcd_resources, +}; + +static struct resource alchemy_ac97c_res[] = { + [0] = { + .start = AU1000_AC97_PHYS_ADDR, + .end = AU1000_AC97_PHYS_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMA_ID_AC97C_TX, + .end = DMA_ID_AC97C_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMA_ID_AC97C_RX, + .end = DMA_ID_AC97C_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device alchemy_ac97c_dev = { + .name = "alchemy-ac97c", + .id = -1, + .resource = alchemy_ac97c_res, + .num_resources = ARRAY_SIZE(alchemy_ac97c_res), +}; + +static struct platform_device alchemy_ac97c_dma_dev = { + .name = "alchemy-pcm-dma", + .id = 0, +}; + +static struct platform_device db1x00_codec_dev = { + .name = "ac97-codec", + .id = -1, +}; + +static struct platform_device db1x00_audio_dev = { + .name = "db1000-audio", +}; + +static struct platform_device *db1x00_devs[] = { + &db1x00_codec_dev, + &alchemy_ac97c_dma_dev, + &alchemy_ac97c_dev, + &db1x00_audio_dev, +}; + +static struct platform_device *db1100_devs[] = { + &au1100_lcd_device, +}; + +static int __init db1000_dev_init(void) +{ + int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); + int c0, c1, d0, d1, s0, s1; + + if (board == BCSR_WHOAMI_DB1500) { + c0 = AU1500_GPIO2_INT; + c1 = AU1500_GPIO5_INT; + d0 = AU1500_GPIO0_INT; + d1 = AU1500_GPIO3_INT; + s0 = AU1500_GPIO1_INT; + s1 = AU1500_GPIO4_INT; + } else if (board == BCSR_WHOAMI_DB1100) { + c0 = AU1100_GPIO2_INT; + c1 = AU1100_GPIO5_INT; + d0 = AU1100_GPIO0_INT; + d1 = AU1100_GPIO3_INT; + s0 = AU1100_GPIO1_INT; + s1 = AU1100_GPIO4_INT; + platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); + } else if (board == BCSR_WHOAMI_DB1000) { + c0 = AU1000_GPIO2_INT; + c1 = AU1000_GPIO5_INT; + d0 = AU1000_GPIO0_INT; + d1 = AU1000_GPIO3_INT; + s0 = AU1000_GPIO1_INT; + s1 = AU1000_GPIO4_INT; + } else + return 0; /* unknown board, no further dev setup to do */ + + irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH); + irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); + irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, + c0, d0, /*s0*/0, 0, 0); + + db1x_register_pcmcia_socket( + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, + AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, + c1, d1, /*s1*/0, 0, 1); + + platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); + db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED); + return 0; +} +device_initcall(db1000_dev_init); diff --git a/arch/mips/alchemy/devboards/db1x00.c b/arch/mips/alchemy/devboards/db1x00.c deleted file mode 100644 index 589ae2435cbe..000000000000 --- a/arch/mips/alchemy/devboards/db1x00.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * DBAu1000/1500/1100 board support - * - * Copyright 2000, 2008 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "platform.h" - -struct pci_dev; - -const char *get_system_type(void) -{ - return "Alchemy Db1x00"; -} - -void __init board_setup(void) -{ -#ifdef CONFIG_MIPS_DB1000 - printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1500 - printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1100 - printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); -#endif - /* initialize board register space */ - bcsr_init(DB1000_BCSR_PHYS_ADDR, - DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); - -#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR) - { - u32 pin_func; - - /* Set IRFIRSEL instead of GPIO15 */ - pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF; - au_writel(pin_func, SYS_PINFUNC); - /* Power off until the driver is in use */ - bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, - BCSR_RESETS_IRDA_MODE_OFF); - } -#endif - bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */ - - /* Enable GPIO[31:0] inputs */ - alchemy_gpio1_input_enable(); -} - -/* DB1xxx PCMCIA interrupt sources: - * CD0/1 GPIO0/3 - * STSCHG0/1 GPIO1/4 - * CARD0/1 GPIO2/5 - */ - -#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) - -#if defined(CONFIG_MIPS_DB1000) -#define DB1XXX_PCMCIA_CD0 AU1000_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1000_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO5_INT -#elif defined(CONFIG_MIPS_DB1100) -#define DB1XXX_PCMCIA_CD0 AU1100_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1100_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1100_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1100_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1100_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1100_GPIO5_INT -#elif defined(CONFIG_MIPS_DB1500) -#define DB1XXX_PCMCIA_CD0 AU1500_GPIO0_INT -#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO1_INT -#define DB1XXX_PCMCIA_CARD0 AU1500_GPIO2_INT -#define DB1XXX_PCMCIA_CD1 AU1500_GPIO3_INT -#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO4_INT -#define DB1XXX_PCMCIA_CARD1 AU1500_GPIO5_INT - -static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) -{ - if ((slot < 12) || (slot > 13) || pin == 0) - return -1; - if (slot == 12) - return (pin == 1) ? AU1500_PCI_INTA : 0xff; - if (slot == 13) { - switch (pin) { - case 1: return AU1500_PCI_INTA; - case 2: return AU1500_PCI_INTB; - case 3: return AU1500_PCI_INTC; - case 4: return AU1500_PCI_INTD; - } - } - return -1; -} - -static struct resource alchemy_pci_host_res[] = { - [0] = { - .start = AU1500_PCI_PHYS_ADDR, - .end = AU1500_PCI_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct alchemy_pci_platdata db1500_pci_pd = { - .board_map_irq = db1500_map_pci_irq, -}; - -static struct platform_device db1500_pci_host_dev = { - .dev.platform_data = &db1500_pci_pd, - .name = "alchemy-pci", - .id = 0, - .num_resources = ARRAY_SIZE(alchemy_pci_host_res), - .resource = alchemy_pci_host_res, -}; - -static int __init db1500_pci_init(void) -{ - return platform_device_register(&db1500_pci_host_dev); -} -/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ -arch_initcall(db1500_pci_init); -#endif - -#ifdef CONFIG_MIPS_DB1100 -static struct resource au1100_lcd_resources[] = { - [0] = { - .start = AU1100_LCD_PHYS_ADDR, - .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = AU1100_LCD_INT, - .end = AU1100_LCD_INT, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); - -static struct platform_device au1100_lcd_device = { - .name = "au1100-lcd", - .id = 0, - .dev = { - .dma_mask = &au1100_lcd_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .num_resources = ARRAY_SIZE(au1100_lcd_resources), - .resource = au1100_lcd_resources, -}; -#endif - -static struct resource alchemy_ac97c_res[] = { - [0] = { - .start = AU1000_AC97_PHYS_ADDR, - .end = AU1000_AC97_PHYS_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = DMA_ID_AC97C_TX, - .end = DMA_ID_AC97C_TX, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = DMA_ID_AC97C_RX, - .end = DMA_ID_AC97C_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device alchemy_ac97c_dev = { - .name = "alchemy-ac97c", - .id = -1, - .resource = alchemy_ac97c_res, - .num_resources = ARRAY_SIZE(alchemy_ac97c_res), -}; - -static struct platform_device alchemy_ac97c_dma_dev = { - .name = "alchemy-pcm-dma", - .id = 0, -}; - -static struct platform_device db1x00_codec_dev = { - .name = "ac97-codec", - .id = -1, -}; - -static struct platform_device db1x00_audio_dev = { - .name = "db1000-audio", -}; - -static int __init db1xxx_dev_init(void) -{ - irq_set_irq_type(DB1XXX_PCMCIA_CD0, IRQ_TYPE_EDGE_BOTH); - irq_set_irq_type(DB1XXX_PCMCIA_CD1, IRQ_TYPE_EDGE_BOTH); - irq_set_irq_type(DB1XXX_PCMCIA_CARD0, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(DB1XXX_PCMCIA_CARD1, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(DB1XXX_PCMCIA_STSCHG0, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(DB1XXX_PCMCIA_STSCHG1, IRQ_TYPE_LEVEL_LOW); - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, - DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0, - /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0); - - db1x_register_pcmcia_socket( - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, - AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, - DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1, - /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1); -#ifdef CONFIG_MIPS_DB1100 - platform_device_register(&au1100_lcd_device); -#endif - platform_device_register(&db1x00_codec_dev); - platform_device_register(&alchemy_ac97c_dma_dev); - platform_device_register(&alchemy_ac97c_dev); - platform_device_register(&db1x00_audio_dev); - - db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED); - return 0; -} -device_initcall(db1xxx_dev_init); diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index 3a73f9663b0f..93a22107cc41 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -34,8 +34,8 @@ #include #if defined(CONFIG_MIPS_DB1000) || \ - defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \ - defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) + defined(CONFIG_MIPS_PB1100) || \ + defined(CONFIG_MIPS_PB1500) #define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000 #else /* Au1550/Au1200-based develboards */ diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index 4044c9e0fb73..17a36c125172 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -1,118 +1,359 @@ +CONFIG_MIPS=y CONFIG_MIPS_ALCHEMY=y +CONFIG_MIPS_DB1000=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1000" +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="-db1x00" +CONFIG_LOCALVERSION_AUTO=y CONFIG_KERNEL_LZMA=y +CONFIG_DEFAULT_HOSTNAME="db1x00" +CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_FHANDLE=y +CONFIG_AUDIT=y CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SYSCTL=y CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_SLABINFO=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_IOSCHED_NOOP=y +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_FREEZER=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y CONFIG_PCCARD=y +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y CONFIG_PM_RUNTIME=y +CONFIG_PM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y +CONFIG_XFRM=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_NET_IPIP=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_LRO=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_IPV6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_STP=y +CONFIG_GARP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_LLC=y +CONFIG_LLC2=y +CONFIG_DNS_RESOLVER=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +CONFIG_MTD_CFI_I8=y +CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_PHYSMAP=y -# CONFIG_MISC_DEVICES is not set +CONFIG_SCSI_MOD=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_SFF=y +CONFIG_ATA_BMDMA=y +CONFIG_PATA_HPT37X=y +CONFIG_PATA_PCMCIA=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_FIREWIRE=y +CONFIG_FIREWIRE_OHCI=y +CONFIG_FIREWIRE_OHCI_DEBUG=y +CONFIG_FIREWIRE_NET=y CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_NET_ETHERNET=y CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=y +CONFIG_PCMCIA_PCNET=y +CONFIG_PPP=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOE=y +CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_DEVKMEM=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_TTY_PRINTK=y +CONFIG_DEVPORT=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_AU1100=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x16=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +CONFIG_SND_SEQUENCER=y +CONFIG_SND_HRTIMER=y +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XAUDIO=y +CONFIG_SND_SOC_AU1XAC97C=y +CONFIG_SND_SOC_DB1000=y +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y +CONFIG_USB_HID=y +CONFIG_USB_SUPPORT=y CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_SUSPEND=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_JBD2=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_GENERIC_ACL=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y CONFIG_TMPFS=y -CONFIG_CRAMFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +CONFIG_JFFS2_CMODE_PRIORITY=y CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=y CONFIG_ROOT_NFS=y +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_USE_NEW_IDMAPPER=y +CONFIG_NFSD=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="noirqdebug rootwait root=/dev/sda1 rootfstype=ext4 console=ttyS0,115200 video=au1100fb:panel:CRT_800x600_16" CONFIG_DEBUG_ZBOOT=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig deleted file mode 100644 index c6b49938ee84..000000000000 --- a/arch/mips/configs/db1100_defconfig +++ /dev/null @@ -1,122 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_DB1100=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1100" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_IDE_TASK_IOCTL=y -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FB_AU1100=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FONTS=y -CONFIG_FONT_8x16=y -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig deleted file mode 100644 index b6e21c7cb6bd..000000000000 --- a/arch/mips/configs/db1500_defconfig +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_MIPS_ALCHEMY=y -CONFIG_MIPS_DB1500=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HZ_100=y -# CONFIG_SECCOMP is not set -CONFIG_EXPERIMENTAL=y -CONFIG_LOCALVERSION="-db1500" -CONFIG_KERNEL_LZMA=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_PCI=y -CONFIG_PCCARD=y -# CONFIG_CARDBUS is not set -CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_MISC_DEVICES is not set -CONFIG_IDE=y -CONFIG_BLK_DEV_IDECS=y -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -CONFIG_BLK_DEV_HPT366=y -CONFIG_NETDEVICES=y -CONFIG_MARVELL_PHY=y -CONFIG_DAVICOM_PHY=y -CONFIG_QSEMI_PHY=y -CONFIG_LXT_PHY=y -CONFIG_CICADA_PHY=y -CONFIG_VITESSE_PHY=y -CONFIG_SMSC_PHY=y -CONFIG_BROADCOM_PHY=y -CONFIG_ICPLUS_PHY=y -CONFIG_REALTEK_PHY=y -CONFIG_NATIONAL_PHY=y -CONFIG_STE10XP=y -CONFIG_LSI_ET1011C_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_MIPS_AU1X00_ENET=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_PCI is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_ARB is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -CONFIG_USB_OHCI_HCD=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AU1XXX=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_SQUASHFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_UTF8=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_ZBOOT=y -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y -CONFIG_SECURITYFS=y diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index d1a77ef9b9e8..670bb0591217 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c @@ -32,7 +32,7 @@ #include #include #include -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) #include #else #error au1k_ir: unsupported board @@ -274,7 +274,7 @@ static int au1k_irda_net_init(struct net_device *dev) aup->tx_db_inuse[i] = pDB; } -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) /* power on */ bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK, BCSR_RESETS_IRDA_MODE_FULL); @@ -662,7 +662,7 @@ au1k_irda_set_speed(struct net_device *dev, int speed) u32 control; int ret = 0, timeout = 10, i; volatile ring_dest_t *ptxd; -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) unsigned long irda_resets; #endif @@ -711,14 +711,14 @@ au1k_irda_set_speed(struct net_device *dev, int speed) } if (speed == 4000000) { -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_FIR_SEL); #else /* Pb1000 and Pb1100 */ writel(1<<13, CPLD_AUX1); #endif } else { -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) +#if defined(CONFIG_MIPS_DB1000) bcsr_mod(BCSR_RESETS, BCSR_RESETS_FIR_SEL, 0); #else /* Pb1000 and Pb1100 */ writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c index 649cb35de4ed..de9da6774fd9 100644 --- a/drivers/video/au1100fb.c +++ b/drivers/video/au1100fb.c @@ -60,18 +60,6 @@ #include "au1100fb.h" -/* - * Sanity check. If this is a new Au1100 based board, search for - * the PB1100 ifdefs to make sure you modify the code accordingly. - */ -#if defined(CONFIG_MIPS_PB1100) - #include -#elif defined(CONFIG_MIPS_DB1100) - #include -#else - #error "Unknown Au1100 board, Au1100 FB driver not supported" -#endif - #define DRIVER_NAME "au1100fb" #define DRIVER_DESC "LCD controller driver for AU1100 processors" -- cgit v1.2.3 From 9d6b204f93cfeb7ec5e6ec499aca43d2c1d6da3f Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 21:26:09 +0200 Subject: USB: ehci-ath79: Add device_id entry for the AR933X SoCs Also make the USB_EHCI_ATH79 selectable for the AR933X SoCs. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Cc: Greg Kroah-Hartman Cc: Alan Stern Cc: linux-usb@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2529/ Signed-off-by: Ralf Baechle --- drivers/usb/host/Kconfig | 2 +- drivers/usb/host/ehci-ath79.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 060e0e2b1ae6..8b094b4f6531 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI config USB_EHCI_ATH79 bool "EHCI support for AR7XXX/AR9XXX SoCs" - depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X) + depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X) select USB_EHCI_ROOT_HUB_TT default y ---help--- diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c index afb6743cf094..f1424f9bc363 100644 --- a/drivers/usb/host/ehci-ath79.c +++ b/drivers/usb/host/ehci-ath79.c @@ -32,6 +32,10 @@ static const struct platform_device_id ehci_ath79_id_table[] = { .name = "ar913x-ehci", .driver_data = EHCI_ATH79_IP_V2, }, + { + .name = "ar933x-ehci", + .driver_data = EHCI_ATH79_IP_V2, + }, { /* terminating entry */ }, -- cgit v1.2.3 From d57f341ba08c9f34ccd45a89729e73174d4a3325 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 20 Jun 2011 19:26:11 +0200 Subject: SERIAL: AR933X: Add driver for the built-in UART of the SoC This patch adds the driver for the built-in UART of the Atheros AR933X SoCs. Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Cc: Kathy Giori Cc: "Luis R. Rodriguez" Cc: Alan Cox Cc: linux-serial@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2526/ Signed-off-by: Alan Cox Signed-off-by: Ralf Baechle --- .../include/asm/mach-ath79/ar933x_uart_platform.h | 18 + drivers/tty/serial/Kconfig | 23 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/ar933x_uart.c | 688 +++++++++++++++++++++ include/linux/serial_core.h | 4 + 5 files changed, 734 insertions(+) create mode 100644 arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h create mode 100644 drivers/tty/serial/ar933x_uart.c (limited to 'drivers') diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h new file mode 100644 index 000000000000..6cb30f2b7198 --- /dev/null +++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h @@ -0,0 +1,18 @@ +/* + * Platform data definition for Atheros AR933X UART + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _AR933X_UART_PLATFORM_H +#define _AR933X_UART_PLATFORM_H + +struct ar933x_uart_platform_data { + unsigned uartclk; +}; + +#endif /* _AR933X_UART_PLATFORM_H */ diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 925a1e547a83..95a0f5fe7d42 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1610,4 +1610,27 @@ config SERIAL_XILINX_PS_UART_CONSOLE help Enable a Xilinx PS UART port to be the system console. +config SERIAL_AR933X + bool "AR933X serial port support" + depends on SOC_AR933X + select SERIAL_CORE + help + If you have an Atheros AR933X SOC based board and want to use the + built-in UART of the SoC, say Y to this option. + +config SERIAL_AR933X_CONSOLE + bool "Console on AR933X serial port" + depends on SERIAL_AR933X=y + select SERIAL_CORE_CONSOLE + help + Enable a built-in UART port of the AR933X to be the system console. + +config SERIAL_AR933X_NR_UARTS + int "Maximum number of AR933X serial ports" + depends on SERIAL_AR933X + default "2" + help + Set this to the number of serial ports you want the driver + to support. + endmenu diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index e10cf5b54b6d..76811cc58591 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o +obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c new file mode 100644 index 000000000000..e4f60e2b87f3 --- /dev/null +++ b/drivers/tty/serial/ar933x_uart.c @@ -0,0 +1,688 @@ +/* + * Atheros AR933X SoC built-in UART driver + * + * Copyright (C) 2011 Gabor Juhos + * + * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "ar933x-uart" + +#define AR933X_DUMMY_STATUS_RD 0x01 + +static struct uart_driver ar933x_uart_driver; + +struct ar933x_uart_port { + struct uart_port port; + unsigned int ier; /* shadow Interrupt Enable Register */ +}; + +static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up, + int offset) +{ + return readl(up->port.membase + offset); +} + +static inline void ar933x_uart_write(struct ar933x_uart_port *up, + int offset, unsigned int value) +{ + writel(value, up->port.membase + offset); +} + +static inline void ar933x_uart_rmw(struct ar933x_uart_port *up, + unsigned int offset, + unsigned int mask, + unsigned int val) +{ + unsigned int t; + + t = ar933x_uart_read(up, offset); + t &= ~mask; + t |= val; + ar933x_uart_write(up, offset, t); +} + +static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up, + unsigned int offset, + unsigned int val) +{ + ar933x_uart_rmw(up, offset, 0, val); +} + +static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up, + unsigned int offset, + unsigned int val) +{ + ar933x_uart_rmw(up, offset, val, 0); +} + +static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up) +{ + up->ier |= AR933X_UART_INT_TX_EMPTY; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); +} + +static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up) +{ + up->ier &= ~AR933X_UART_INT_TX_EMPTY; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); +} + +static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch) +{ + unsigned int rdata; + + rdata = ch & AR933X_UART_DATA_TX_RX_MASK; + rdata |= AR933X_UART_DATA_TX_CSR; + ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata); +} + +static unsigned int ar933x_uart_tx_empty(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned long flags; + unsigned int rdata; + + spin_lock_irqsave(&up->port.lock, flags); + rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); + spin_unlock_irqrestore(&up->port.lock, flags); + + return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT; +} + +static unsigned int ar933x_uart_get_mctrl(struct uart_port *port) +{ + return TIOCM_CAR; +} + +static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static void ar933x_uart_start_tx(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + ar933x_uart_start_tx_interrupt(up); +} + +static void ar933x_uart_stop_tx(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + ar933x_uart_stop_tx_interrupt(up); +} + +static void ar933x_uart_stop_rx(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + up->ier &= ~AR933X_UART_INT_RX_VALID; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); +} + +static void ar933x_uart_break_ctl(struct uart_port *port, int break_state) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned long flags; + + spin_lock_irqsave(&up->port.lock, flags); + if (break_state == -1) + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_TX_BREAK); + else + ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, + AR933X_UART_CS_TX_BREAK); + spin_unlock_irqrestore(&up->port.lock, flags); +} + +static void ar933x_uart_enable_ms(struct uart_port *port) +{ +} + +static void ar933x_uart_set_termios(struct uart_port *port, + struct ktermios *new, + struct ktermios *old) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned int cs; + unsigned long flags; + unsigned int baud, scale; + + /* Only CS8 is supported */ + new->c_cflag &= ~CSIZE; + new->c_cflag |= CS8; + + /* Only one stop bit is supported */ + new->c_cflag &= ~CSTOPB; + + cs = 0; + if (new->c_cflag & PARENB) { + if (!(new->c_cflag & PARODD)) + cs |= AR933X_UART_CS_PARITY_EVEN; + else + cs |= AR933X_UART_CS_PARITY_ODD; + } else { + cs |= AR933X_UART_CS_PARITY_NONE; + } + + /* Mark/space parity is not supported */ + new->c_cflag &= ~CMSPAR; + + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); + scale = (port->uartclk / (16 * baud)) - 1; + + /* + * Ok, we're now changing the port state. Do it with + * interrupts disabled. + */ + spin_lock_irqsave(&up->port.lock, flags); + + /* Update the per-port timeout. */ + uart_update_timeout(port, new->c_cflag, baud); + + up->port.ignore_status_mask = 0; + + /* ignore all characters if CREAD is not set */ + if ((new->c_cflag & CREAD) == 0) + up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD; + + ar933x_uart_write(up, AR933X_UART_CLOCK_REG, + scale << AR933X_UART_CLOCK_SCALE_S | 8192); + + /* setup configuration register */ + ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs); + + /* enable host interrupt */ + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_HOST_INT_EN); + + spin_unlock_irqrestore(&up->port.lock, flags); + + if (tty_termios_baud_rate(new)) + tty_termios_encode_baud_rate(new, baud, baud); +} + +static void ar933x_uart_rx_chars(struct ar933x_uart_port *up) +{ + struct tty_struct *tty; + int max_count = 256; + + tty = tty_port_tty_get(&up->port.state->port); + do { + unsigned int rdata; + unsigned char ch; + + rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); + if ((rdata & AR933X_UART_DATA_RX_CSR) == 0) + break; + + /* remove the character from the FIFO */ + ar933x_uart_write(up, AR933X_UART_DATA_REG, + AR933X_UART_DATA_RX_CSR); + + if (!tty) { + /* discard the data if no tty available */ + continue; + } + + up->port.icount.rx++; + ch = rdata & AR933X_UART_DATA_TX_RX_MASK; + + if (uart_handle_sysrq_char(&up->port, ch)) + continue; + + if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0) + tty_insert_flip_char(tty, ch, TTY_NORMAL); + } while (max_count-- > 0); + + if (tty) { + tty_flip_buffer_push(tty); + tty_kref_put(tty); + } +} + +static void ar933x_uart_tx_chars(struct ar933x_uart_port *up) +{ + struct circ_buf *xmit = &up->port.state->xmit; + int count; + + if (uart_tx_stopped(&up->port)) + return; + + count = up->port.fifosize; + do { + unsigned int rdata; + + rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); + if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) + break; + + if (up->port.x_char) { + ar933x_uart_putc(up, up->port.x_char); + up->port.icount.tx++; + up->port.x_char = 0; + continue; + } + + if (uart_circ_empty(xmit)) + break; + + ar933x_uart_putc(up, xmit->buf[xmit->tail]); + + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + up->port.icount.tx++; + } while (--count > 0); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(&up->port); + + if (!uart_circ_empty(xmit)) + ar933x_uart_start_tx_interrupt(up); +} + +static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id) +{ + struct ar933x_uart_port *up = dev_id; + unsigned int status; + + status = ar933x_uart_read(up, AR933X_UART_CS_REG); + if ((status & AR933X_UART_CS_HOST_INT) == 0) + return IRQ_NONE; + + spin_lock(&up->port.lock); + + status = ar933x_uart_read(up, AR933X_UART_INT_REG); + status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG); + + if (status & AR933X_UART_INT_RX_VALID) { + ar933x_uart_write(up, AR933X_UART_INT_REG, + AR933X_UART_INT_RX_VALID); + ar933x_uart_rx_chars(up); + } + + if (status & AR933X_UART_INT_TX_EMPTY) { + ar933x_uart_write(up, AR933X_UART_INT_REG, + AR933X_UART_INT_TX_EMPTY); + ar933x_uart_stop_tx_interrupt(up); + ar933x_uart_tx_chars(up); + } + + spin_unlock(&up->port.lock); + + return IRQ_HANDLED; +} + +static int ar933x_uart_startup(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + unsigned long flags; + int ret; + + ret = request_irq(up->port.irq, ar933x_uart_interrupt, + up->port.irqflags, dev_name(up->port.dev), up); + if (ret) + return ret; + + spin_lock_irqsave(&up->port.lock, flags); + + /* Enable HOST interrupts */ + ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, + AR933X_UART_CS_HOST_INT_EN); + + /* Enable RX interrupts */ + up->ier = AR933X_UART_INT_RX_VALID; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); + + spin_unlock_irqrestore(&up->port.lock, flags); + + return 0; +} + +static void ar933x_uart_shutdown(struct uart_port *port) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + /* Disable all interrupts */ + up->ier = 0; + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); + + /* Disable break condition */ + ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, + AR933X_UART_CS_TX_BREAK); + + free_irq(up->port.irq, up); +} + +static const char *ar933x_uart_type(struct uart_port *port) +{ + return (port->type == PORT_AR933X) ? "AR933X UART" : NULL; +} + +static void ar933x_uart_release_port(struct uart_port *port) +{ + /* Nothing to release ... */ +} + +static int ar933x_uart_request_port(struct uart_port *port) +{ + /* UARTs always present */ + return 0; +} + +static void ar933x_uart_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) + port->type = PORT_AR933X; +} + +static int ar933x_uart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (ser->type != PORT_UNKNOWN && + ser->type != PORT_AR933X) + return -EINVAL; + + if (ser->irq < 0 || ser->irq >= NR_IRQS) + return -EINVAL; + + if (ser->baud_base < 28800) + return -EINVAL; + + return 0; +} + +static struct uart_ops ar933x_uart_ops = { + .tx_empty = ar933x_uart_tx_empty, + .set_mctrl = ar933x_uart_set_mctrl, + .get_mctrl = ar933x_uart_get_mctrl, + .stop_tx = ar933x_uart_stop_tx, + .start_tx = ar933x_uart_start_tx, + .stop_rx = ar933x_uart_stop_rx, + .enable_ms = ar933x_uart_enable_ms, + .break_ctl = ar933x_uart_break_ctl, + .startup = ar933x_uart_startup, + .shutdown = ar933x_uart_shutdown, + .set_termios = ar933x_uart_set_termios, + .type = ar933x_uart_type, + .release_port = ar933x_uart_release_port, + .request_port = ar933x_uart_request_port, + .config_port = ar933x_uart_config_port, + .verify_port = ar933x_uart_verify_port, +}; + +#ifdef CONFIG_SERIAL_AR933X_CONSOLE + +static struct ar933x_uart_port * +ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS]; + +static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up) +{ + unsigned int status; + unsigned int timeout = 60000; + + /* Wait up to 60ms for the character(s) to be sent. */ + do { + status = ar933x_uart_read(up, AR933X_UART_DATA_REG); + if (--timeout == 0) + break; + udelay(1); + } while ((status & AR933X_UART_DATA_TX_CSR) == 0); +} + +static void ar933x_uart_console_putchar(struct uart_port *port, int ch) +{ + struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; + + ar933x_uart_wait_xmitr(up); + ar933x_uart_putc(up, ch); +} + +static void ar933x_uart_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct ar933x_uart_port *up = ar933x_console_ports[co->index]; + unsigned long flags; + unsigned int int_en; + int locked = 1; + + local_irq_save(flags); + + if (up->port.sysrq) + locked = 0; + else if (oops_in_progress) + locked = spin_trylock(&up->port.lock); + else + spin_lock(&up->port.lock); + + /* + * First save the IER then disable the interrupts + */ + int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG); + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0); + + uart_console_write(&up->port, s, count, ar933x_uart_console_putchar); + + /* + * Finally, wait for transmitter to become empty + * and restore the IER + */ + ar933x_uart_wait_xmitr(up); + ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en); + + ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS); + + if (locked) + spin_unlock(&up->port.lock); + + local_irq_restore(flags); +} + +static int ar933x_uart_console_setup(struct console *co, char *options) +{ + struct ar933x_uart_port *up; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS) + return -EINVAL; + + up = ar933x_console_ports[co->index]; + if (!up) + return -ENODEV; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(&up->port, co, baud, parity, bits, flow); +} + +static struct console ar933x_uart_console = { + .name = "ttyATH", + .write = ar933x_uart_console_write, + .device = uart_console_device, + .setup = ar933x_uart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &ar933x_uart_driver, +}; + +static void ar933x_uart_add_console_port(struct ar933x_uart_port *up) +{ + ar933x_console_ports[up->port.line] = up; +} + +#define AR933X_SERIAL_CONSOLE (&ar933x_uart_console) + +#else + +static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {} + +#define AR933X_SERIAL_CONSOLE NULL + +#endif /* CONFIG_SERIAL_AR933X_CONSOLE */ + +static struct uart_driver ar933x_uart_driver = { + .owner = THIS_MODULE, + .driver_name = DRIVER_NAME, + .dev_name = "ttyATH", + .nr = CONFIG_SERIAL_AR933X_NR_UARTS, + .cons = AR933X_SERIAL_CONSOLE, +}; + +static int __devinit ar933x_uart_probe(struct platform_device *pdev) +{ + struct ar933x_uart_platform_data *pdata; + struct ar933x_uart_port *up; + struct uart_port *port; + struct resource *mem_res; + struct resource *irq_res; + int id; + int ret; + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + id = pdev->id; + if (id == -1) + id = 0; + + if (id > CONFIG_SERIAL_AR933X_NR_UARTS) + return -EINVAL; + + mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem_res) { + dev_err(&pdev->dev, "no MEM resource\n"); + return -EINVAL; + } + + irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!irq_res) { + dev_err(&pdev->dev, "no IRQ resource\n"); + return -EINVAL; + } + + up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL); + if (!up) + return -ENOMEM; + + port = &up->port; + port->mapbase = mem_res->start; + + port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE); + if (!port->membase) { + ret = -ENOMEM; + goto err_free_up; + } + + port->line = id; + port->irq = irq_res->start; + port->dev = &pdev->dev; + port->type = PORT_AR933X; + port->iotype = UPIO_MEM32; + port->uartclk = pdata->uartclk; + + port->regshift = 2; + port->fifosize = AR933X_UART_FIFO_SIZE; + port->ops = &ar933x_uart_ops; + + ar933x_uart_add_console_port(up); + + ret = uart_add_one_port(&ar933x_uart_driver, &up->port); + if (ret) + goto err_unmap; + + platform_set_drvdata(pdev, up); + return 0; + +err_unmap: + iounmap(up->port.membase); +err_free_up: + kfree(up); + return ret; +} + +static int __devexit ar933x_uart_remove(struct platform_device *pdev) +{ + struct ar933x_uart_port *up; + + up = platform_get_drvdata(pdev); + platform_set_drvdata(pdev, NULL); + + if (up) { + uart_remove_one_port(&ar933x_uart_driver, &up->port); + iounmap(up->port.membase); + kfree(up); + } + + return 0; +} + +static struct platform_driver ar933x_uart_platform_driver = { + .probe = ar933x_uart_probe, + .remove = __devexit_p(ar933x_uart_remove), + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ar933x_uart_init(void) +{ + int ret; + + ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS; + ret = uart_register_driver(&ar933x_uart_driver); + if (ret) + goto err_out; + + ret = platform_driver_register(&ar933x_uart_platform_driver); + if (ret) + goto err_unregister_uart_driver; + + return 0; + +err_unregister_uart_driver: + uart_unregister_driver(&ar933x_uart_driver); +err_out: + return ret; +} + +static void __exit ar933x_uart_exit(void) +{ + platform_driver_unregister(&ar933x_uart_platform_driver); + uart_unregister_driver(&ar933x_uart_driver); +} + +module_init(ar933x_uart_init); +module_exit(ar933x_uart_exit); + +MODULE_DESCRIPTION("Atheros AR933X UART driver"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index eadf33d0abba..3c35fb2f688f 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -207,6 +207,10 @@ /* Xilinx PSS UART */ #define PORT_XUARTPS 98 +/* Atheros AR933X SoC */ +#define PORT_AR933X 99 + + #ifdef __KERNEL__ #include -- cgit v1.2.3 From af866496c7752d2c0bd97fcbb4627cac72aa9a64 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 22 Nov 2011 14:47:00 +0000 Subject: MIPS: Octeon: Move some Ethernet support files out of staging. Signed-off-by: David Daney Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Cc: devel@driverdev.osuosl.org Acked-by: Greg Kroah-Hartman Patchwork: https://patchwork.linux-mips.org/patch/2942/ Patchwork: https://patchwork.linux-mips.org/patch/3012/ Signed-off-by: Ralf Baechle --- arch/mips/cavium-octeon/Kconfig | 4 - arch/mips/cavium-octeon/executive/Makefile | 7 +- arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c | 306 +++ arch/mips/cavium-octeon/executive/cvmx-fpa.c | 183 ++ .../cavium-octeon/executive/cvmx-helper-board.c | 691 ++++++ .../mips/cavium-octeon/executive/cvmx-helper-fpa.c | 243 ++ .../cavium-octeon/executive/cvmx-helper-loop.c | 85 + .../mips/cavium-octeon/executive/cvmx-helper-npi.c | 113 + .../cavium-octeon/executive/cvmx-helper-rgmii.c | 526 ++++ .../cavium-octeon/executive/cvmx-helper-sgmii.c | 550 +++++ .../mips/cavium-octeon/executive/cvmx-helper-spi.c | 195 ++ .../cavium-octeon/executive/cvmx-helper-util.c | 433 ++++ .../cavium-octeon/executive/cvmx-helper-xaui.c | 348 +++ arch/mips/cavium-octeon/executive/cvmx-helper.c | 1053 ++++++++ .../executive/cvmx-interrupt-decodes.c | 371 +++ .../cavium-octeon/executive/cvmx-interrupt-rsl.c | 140 ++ arch/mips/cavium-octeon/executive/cvmx-pko.c | 506 ++++ arch/mips/cavium-octeon/executive/cvmx-spi.c | 667 ++++++ arch/mips/include/asm/octeon/cvmx-address.h | 274 +++ arch/mips/include/asm/octeon/cvmx-asxx-defs.h | 475 ++++ arch/mips/include/asm/octeon/cvmx-cmd-queue.h | 617 +++++ arch/mips/include/asm/octeon/cvmx-config.h | 168 ++ arch/mips/include/asm/octeon/cvmx-dbg-defs.h | 72 + arch/mips/include/asm/octeon/cvmx-fau.h | 597 +++++ arch/mips/include/asm/octeon/cvmx-fpa-defs.h | 403 ++++ arch/mips/include/asm/octeon/cvmx-fpa.h | 299 +++ arch/mips/include/asm/octeon/cvmx-gmxx-defs.h | 2529 ++++++++++++++++++++ arch/mips/include/asm/octeon/cvmx-helper-board.h | 151 ++ arch/mips/include/asm/octeon/cvmx-helper-fpa.h | 64 + arch/mips/include/asm/octeon/cvmx-helper-loop.h | 59 + arch/mips/include/asm/octeon/cvmx-helper-npi.h | 60 + arch/mips/include/asm/octeon/cvmx-helper-rgmii.h | 110 + arch/mips/include/asm/octeon/cvmx-helper-sgmii.h | 104 + arch/mips/include/asm/octeon/cvmx-helper-spi.h | 84 + arch/mips/include/asm/octeon/cvmx-helper-util.h | 215 ++ arch/mips/include/asm/octeon/cvmx-helper-xaui.h | 103 + arch/mips/include/asm/octeon/cvmx-helper.h | 227 ++ arch/mips/include/asm/octeon/cvmx-ipd.h | 338 +++ arch/mips/include/asm/octeon/cvmx-mdio.h | 506 ++++ arch/mips/include/asm/octeon/cvmx-pcsx-defs.h | 370 +++ arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h | 316 +++ arch/mips/include/asm/octeon/cvmx-pip-defs.h | 1267 ++++++++++ arch/mips/include/asm/octeon/cvmx-pip.h | 524 ++++ arch/mips/include/asm/octeon/cvmx-pko-defs.h | 1133 +++++++++ arch/mips/include/asm/octeon/cvmx-pko.h | 610 +++++ arch/mips/include/asm/octeon/cvmx-pow.h | 1982 +++++++++++++++ arch/mips/include/asm/octeon/cvmx-scratch.h | 139 ++ arch/mips/include/asm/octeon/cvmx-spi.h | 269 +++ arch/mips/include/asm/octeon/cvmx-spxx-defs.h | 347 +++ arch/mips/include/asm/octeon/cvmx-srxx-defs.h | 126 + arch/mips/include/asm/octeon/cvmx-stxx-defs.h | 292 +++ arch/mips/include/asm/octeon/cvmx-wqe.h | 397 +++ drivers/staging/octeon/Makefile | 5 - drivers/staging/octeon/cvmx-address.h | 274 --- drivers/staging/octeon/cvmx-asxx-defs.h | 475 ---- drivers/staging/octeon/cvmx-cmd-queue.c | 306 --- drivers/staging/octeon/cvmx-cmd-queue.h | 617 ----- drivers/staging/octeon/cvmx-config.h | 169 -- drivers/staging/octeon/cvmx-dbg-defs.h | 72 - drivers/staging/octeon/cvmx-fau.h | 597 ----- drivers/staging/octeon/cvmx-fpa-defs.h | 403 ---- drivers/staging/octeon/cvmx-fpa.c | 183 -- drivers/staging/octeon/cvmx-fpa.h | 299 --- drivers/staging/octeon/cvmx-gmxx-defs.h | 2529 -------------------- drivers/staging/octeon/cvmx-helper-board.c | 695 ------ drivers/staging/octeon/cvmx-helper-board.h | 151 -- drivers/staging/octeon/cvmx-helper-fpa.c | 243 -- drivers/staging/octeon/cvmx-helper-fpa.h | 64 - drivers/staging/octeon/cvmx-helper-loop.c | 85 - drivers/staging/octeon/cvmx-helper-loop.h | 59 - drivers/staging/octeon/cvmx-helper-npi.c | 113 - drivers/staging/octeon/cvmx-helper-npi.h | 60 - drivers/staging/octeon/cvmx-helper-rgmii.c | 525 ---- drivers/staging/octeon/cvmx-helper-rgmii.h | 110 - drivers/staging/octeon/cvmx-helper-sgmii.c | 550 ----- drivers/staging/octeon/cvmx-helper-sgmii.h | 104 - drivers/staging/octeon/cvmx-helper-spi.c | 195 -- drivers/staging/octeon/cvmx-helper-spi.h | 84 - drivers/staging/octeon/cvmx-helper-util.c | 433 ---- drivers/staging/octeon/cvmx-helper-util.h | 215 -- drivers/staging/octeon/cvmx-helper-xaui.c | 348 --- drivers/staging/octeon/cvmx-helper-xaui.h | 103 - drivers/staging/octeon/cvmx-helper.c | 1058 -------- drivers/staging/octeon/cvmx-helper.h | 227 -- drivers/staging/octeon/cvmx-interrupt-decodes.c | 371 --- drivers/staging/octeon/cvmx-interrupt-rsl.c | 140 -- drivers/staging/octeon/cvmx-ipd.h | 338 --- drivers/staging/octeon/cvmx-mdio.h | 506 ---- drivers/staging/octeon/cvmx-packet.h | 65 - drivers/staging/octeon/cvmx-pcsx-defs.h | 370 --- drivers/staging/octeon/cvmx-pcsxx-defs.h | 316 --- drivers/staging/octeon/cvmx-pip-defs.h | 1267 ---------- drivers/staging/octeon/cvmx-pip.h | 524 ---- drivers/staging/octeon/cvmx-pko-defs.h | 1133 --------- drivers/staging/octeon/cvmx-pko.c | 506 ---- drivers/staging/octeon/cvmx-pko.h | 610 ----- drivers/staging/octeon/cvmx-pow.h | 1982 --------------- drivers/staging/octeon/cvmx-scratch.h | 139 -- drivers/staging/octeon/cvmx-smix-defs.h | 178 -- drivers/staging/octeon/cvmx-spi.c | 667 ------ drivers/staging/octeon/cvmx-spi.h | 269 --- drivers/staging/octeon/cvmx-spxx-defs.h | 347 --- drivers/staging/octeon/cvmx-srxx-defs.h | 126 - drivers/staging/octeon/cvmx-stxx-defs.h | 292 --- drivers/staging/octeon/cvmx-wqe.h | 397 --- drivers/staging/octeon/ethernet-defines.h | 2 +- drivers/staging/octeon/ethernet-mdio.c | 4 +- drivers/staging/octeon/ethernet-mem.c | 2 +- drivers/staging/octeon/ethernet-rgmii.c | 4 +- drivers/staging/octeon/ethernet-rx.c | 16 +- drivers/staging/octeon/ethernet-rx.h | 2 +- drivers/staging/octeon/ethernet-sgmii.c | 4 +- drivers/staging/octeon/ethernet-spi.c | 6 +- drivers/staging/octeon/ethernet-tx.c | 12 +- drivers/staging/octeon/ethernet-xaui.c | 4 +- drivers/staging/octeon/ethernet.c | 16 +- 116 files changed, 21679 insertions(+), 21935 deletions(-) create mode 100644 arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-fpa.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-board.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-loop.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-npi.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-spi.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-util.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-pko.c create mode 100644 arch/mips/cavium-octeon/executive/cvmx-spi.c create mode 100644 arch/mips/include/asm/octeon/cvmx-address.h create mode 100644 arch/mips/include/asm/octeon/cvmx-asxx-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-cmd-queue.h create mode 100644 arch/mips/include/asm/octeon/cvmx-config.h create mode 100644 arch/mips/include/asm/octeon/cvmx-dbg-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-fau.h create mode 100644 arch/mips/include/asm/octeon/cvmx-fpa-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-fpa.h create mode 100644 arch/mips/include/asm/octeon/cvmx-gmxx-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-board.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-fpa.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-loop.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-npi.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-rgmii.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-sgmii.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-spi.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-util.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-xaui.h create mode 100644 arch/mips/include/asm/octeon/cvmx-helper.h create mode 100644 arch/mips/include/asm/octeon/cvmx-ipd.h create mode 100644 arch/mips/include/asm/octeon/cvmx-mdio.h create mode 100644 arch/mips/include/asm/octeon/cvmx-pcsx-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-pip-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-pip.h create mode 100644 arch/mips/include/asm/octeon/cvmx-pko-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-pko.h create mode 100644 arch/mips/include/asm/octeon/cvmx-pow.h create mode 100644 arch/mips/include/asm/octeon/cvmx-scratch.h create mode 100644 arch/mips/include/asm/octeon/cvmx-spi.h create mode 100644 arch/mips/include/asm/octeon/cvmx-spxx-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-srxx-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-stxx-defs.h create mode 100644 arch/mips/include/asm/octeon/cvmx-wqe.h delete mode 100644 drivers/staging/octeon/cvmx-address.h delete mode 100644 drivers/staging/octeon/cvmx-asxx-defs.h delete mode 100644 drivers/staging/octeon/cvmx-cmd-queue.c delete mode 100644 drivers/staging/octeon/cvmx-cmd-queue.h delete mode 100644 drivers/staging/octeon/cvmx-config.h delete mode 100644 drivers/staging/octeon/cvmx-dbg-defs.h delete mode 100644 drivers/staging/octeon/cvmx-fau.h delete mode 100644 drivers/staging/octeon/cvmx-fpa-defs.h delete mode 100644 drivers/staging/octeon/cvmx-fpa.c delete mode 100644 drivers/staging/octeon/cvmx-fpa.h delete mode 100644 drivers/staging/octeon/cvmx-gmxx-defs.h delete mode 100644 drivers/staging/octeon/cvmx-helper-board.c delete mode 100644 drivers/staging/octeon/cvmx-helper-board.h delete mode 100644 drivers/staging/octeon/cvmx-helper-fpa.c delete mode 100644 drivers/staging/octeon/cvmx-helper-fpa.h delete mode 100644 drivers/staging/octeon/cvmx-helper-loop.c delete mode 100644 drivers/staging/octeon/cvmx-helper-loop.h delete mode 100644 drivers/staging/octeon/cvmx-helper-npi.c delete mode 100644 drivers/staging/octeon/cvmx-helper-npi.h delete mode 100644 drivers/staging/octeon/cvmx-helper-rgmii.c delete mode 100644 drivers/staging/octeon/cvmx-helper-rgmii.h delete mode 100644 drivers/staging/octeon/cvmx-helper-sgmii.c delete mode 100644 drivers/staging/octeon/cvmx-helper-sgmii.h delete mode 100644 drivers/staging/octeon/cvmx-helper-spi.c delete mode 100644 drivers/staging/octeon/cvmx-helper-spi.h delete mode 100644 drivers/staging/octeon/cvmx-helper-util.c delete mode 100644 drivers/staging/octeon/cvmx-helper-util.h delete mode 100644 drivers/staging/octeon/cvmx-helper-xaui.c delete mode 100644 drivers/staging/octeon/cvmx-helper-xaui.h delete mode 100644 drivers/staging/octeon/cvmx-helper.c delete mode 100644 drivers/staging/octeon/cvmx-helper.h delete mode 100644 drivers/staging/octeon/cvmx-interrupt-decodes.c delete mode 100644 drivers/staging/octeon/cvmx-interrupt-rsl.c delete mode 100644 drivers/staging/octeon/cvmx-ipd.h delete mode 100644 drivers/staging/octeon/cvmx-mdio.h delete mode 100644 drivers/staging/octeon/cvmx-packet.h delete mode 100644 drivers/staging/octeon/cvmx-pcsx-defs.h delete mode 100644 drivers/staging/octeon/cvmx-pcsxx-defs.h delete mode 100644 drivers/staging/octeon/cvmx-pip-defs.h delete mode 100644 drivers/staging/octeon/cvmx-pip.h delete mode 100644 drivers/staging/octeon/cvmx-pko-defs.h delete mode 100644 drivers/staging/octeon/cvmx-pko.c delete mode 100644 drivers/staging/octeon/cvmx-pko.h delete mode 100644 drivers/staging/octeon/cvmx-pow.h delete mode 100644 drivers/staging/octeon/cvmx-scratch.h delete mode 100644 drivers/staging/octeon/cvmx-smix-defs.h delete mode 100644 drivers/staging/octeon/cvmx-spi.c delete mode 100644 drivers/staging/octeon/cvmx-spi.h delete mode 100644 drivers/staging/octeon/cvmx-spxx-defs.h delete mode 100644 drivers/staging/octeon/cvmx-srxx-defs.h delete mode 100644 drivers/staging/octeon/cvmx-stxx-defs.h delete mode 100644 drivers/staging/octeon/cvmx-wqe.h (limited to 'drivers') diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index cad555ebeca3..f9e275a50d98 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -86,10 +86,6 @@ config ARCH_SPARSEMEM_ENABLE def_bool y select SPARSEMEM_STATIC -config CAVIUM_OCTEON_HELPER - def_bool y - depends on OCTEON_ETHERNET || PCI - config IOMMU_HELPER bool diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile index 7f41c5be2190..b6d6e841a984 100644 --- a/arch/mips/cavium-octeon/executive/Makefile +++ b/arch/mips/cavium-octeon/executive/Makefile @@ -10,5 +10,10 @@ # obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o +obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ + cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ + cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ + cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ + cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o -obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o +obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o diff --git a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c new file mode 100644 index 000000000000..132bccc66a93 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c @@ -0,0 +1,306 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Support functions for managing command queues used for + * various hardware blocks. + */ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +/** + * This application uses this pointer to access the global queue + * state. It points to a bootmem named block. + */ +__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; + +/** + * Initialize the Global queue state pointer. + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void) +{ + char *alloc_name = "cvmx_cmd_queues"; +#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32 + extern uint64_t octeon_reserve32_memory; +#endif + + if (likely(__cvmx_cmd_queue_state_ptr)) + return CVMX_CMD_QUEUE_SUCCESS; + +#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32 + if (octeon_reserve32_memory) + __cvmx_cmd_queue_state_ptr = + cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr), + octeon_reserve32_memory, + octeon_reserve32_memory + + (CONFIG_CAVIUM_RESERVE32 << + 20) - 1, 128, alloc_name); + else +#endif + __cvmx_cmd_queue_state_ptr = + cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr), + 128, + alloc_name); + if (__cvmx_cmd_queue_state_ptr) + memset(__cvmx_cmd_queue_state_ptr, 0, + sizeof(*__cvmx_cmd_queue_state_ptr)); + else { + struct cvmx_bootmem_named_block_desc *block_desc = + cvmx_bootmem_find_named_block(alloc_name); + if (block_desc) + __cvmx_cmd_queue_state_ptr = + cvmx_phys_to_ptr(block_desc->base_addr); + else { + cvmx_dprintf + ("ERROR: cvmx_cmd_queue_initialize: Unable to get named block %s.\n", + alloc_name); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + } + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Initialize a command queue for use. The initial FPA buffer is + * allocated and the hardware unit is configured to point to the + * new command queue. + * + * @queue_id: Hardware command queue to initialize. + * @max_depth: Maximum outstanding commands that can be queued. + * @fpa_pool: FPA pool the command queues should come from. + * @pool_size: Size of each buffer in the FPA pool (bytes) + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, + int max_depth, int fpa_pool, + int pool_size) +{ + __cvmx_cmd_queue_state_t *qstate; + cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr(); + if (result != CVMX_CMD_QUEUE_SUCCESS) + return result; + + qstate = __cvmx_cmd_queue_get_state(queue_id); + if (qstate == NULL) + return CVMX_CMD_QUEUE_INVALID_PARAM; + + /* + * We artificially limit max_depth to 1<<20 words. It is an + * arbitrary limit. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH) { + if ((max_depth < 0) || (max_depth > 1 << 20)) + return CVMX_CMD_QUEUE_INVALID_PARAM; + } else if (max_depth != 0) + return CVMX_CMD_QUEUE_INVALID_PARAM; + + if ((fpa_pool < 0) || (fpa_pool > 7)) + return CVMX_CMD_QUEUE_INVALID_PARAM; + if ((pool_size < 128) || (pool_size > 65536)) + return CVMX_CMD_QUEUE_INVALID_PARAM; + + /* See if someone else has already initialized the queue */ + if (qstate->base_ptr_div128) { + if (max_depth != (int)qstate->max_depth) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "Queue already initialized with different " + "max_depth (%d).\n", + (int)qstate->max_depth); + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + if (fpa_pool != qstate->fpa_pool) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "Queue already initialized with different " + "FPA pool (%u).\n", + qstate->fpa_pool); + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + if ((pool_size >> 3) - 1 != qstate->pool_size_m1) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "Queue already initialized with different " + "FPA pool size (%u).\n", + (qstate->pool_size_m1 + 1) << 3); + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + CVMX_SYNCWS; + return CVMX_CMD_QUEUE_ALREADY_SETUP; + } else { + union cvmx_fpa_ctl_status status; + void *buffer; + + status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); + if (!status.s.enb) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "FPA is not enabled.\n"); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + buffer = cvmx_fpa_alloc(fpa_pool); + if (buffer == NULL) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "Unable to allocate initial buffer.\n"); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + + memset(qstate, 0, sizeof(*qstate)); + qstate->max_depth = max_depth; + qstate->fpa_pool = fpa_pool; + qstate->pool_size_m1 = (pool_size >> 3) - 1; + qstate->base_ptr_div128 = cvmx_ptr_to_phys(buffer) / 128; + /* + * We zeroed the now serving field so we need to also + * zero the ticket. + */ + __cvmx_cmd_queue_state_ptr-> + ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0; + CVMX_SYNCWS; + return CVMX_CMD_QUEUE_SUCCESS; + } +} + +/** + * Shutdown a queue a free it's command buffers to the FPA. The + * hardware connected to the queue must be stopped before this + * function is called. + * + * @queue_id: Queue to shutdown + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + if (qptr == NULL) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to " + "get queue information.\n"); + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + + if (cvmx_cmd_queue_length(queue_id) > 0) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still " + "has data in it.\n"); + return CVMX_CMD_QUEUE_FULL; + } + + __cvmx_cmd_queue_lock(queue_id, qptr); + if (qptr->base_ptr_div128) { + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) qptr->base_ptr_div128 << 7), + qptr->fpa_pool, 0); + qptr->base_ptr_div128 = 0; + } + __cvmx_cmd_queue_unlock(qptr); + + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Return the number of command words pending in the queue. This + * function may be relatively slow for some hardware units. + * + * @queue_id: Hardware command queue to query + * + * Returns Number of outstanding commands + */ +int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) +{ + if (CVMX_ENABLE_PARAMETER_CHECKING) { + if (__cvmx_cmd_queue_get_state(queue_id) == NULL) + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + + /* + * The cast is here so gcc with check that all values in the + * cvmx_cmd_queue_id_t enumeration are here. + */ + switch ((cvmx_cmd_queue_id_t) (queue_id & 0xff0000)) { + case CVMX_CMD_QUEUE_PKO_BASE: + /* + * FIXME: Need atomic lock on + * CVMX_PKO_REG_READ_IDX. Right now we are normally + * called with the queue lock, so that is a SLIGHT + * amount of protection. + */ + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff); + if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { + union cvmx_pko_mem_debug9 debug9; + debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); + return debug9.cn38xx.doorbell; + } else { + union cvmx_pko_mem_debug8 debug8; + debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); + return debug8.cn58xx.doorbell; + } + case CVMX_CMD_QUEUE_ZIP: + case CVMX_CMD_QUEUE_DFA: + case CVMX_CMD_QUEUE_RAID: + /* FIXME: Implement other lengths */ + return 0; + case CVMX_CMD_QUEUE_DMA_BASE: + { + union cvmx_npei_dmax_counts dmax_counts; + dmax_counts.u64 = + cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS + (queue_id & 0x7)); + return dmax_counts.s.dbell; + } + case CVMX_CMD_QUEUE_END: + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + return CVMX_CMD_QUEUE_INVALID_PARAM; +} + +/** + * Return the command buffer to be written to. The purpose of this + * function is to allow CVMX routine access t othe low level buffer + * for initial hardware setup. User applications should not call this + * function directly. + * + * @queue_id: Command queue to query + * + * Returns Command buffer or NULL on failure + */ +void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + if (qptr && qptr->base_ptr_div128) + return cvmx_phys_to_ptr((uint64_t) qptr->base_ptr_div128 << 7); + else + return NULL; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c new file mode 100644 index 000000000000..ad44b8bd8057 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-fpa.c @@ -0,0 +1,183 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Support library for the hardware Free Pool Allocator. + * + * + */ + +#include "cvmx-config.h" +#include "cvmx.h" +#include "cvmx-fpa.h" +#include "cvmx-ipd.h" + +/** + * Current state of all the pools. Use access functions + * instead of using it directly. + */ +CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; + +/** + * Setup a FPA pool to control a new block of memory. The + * buffer pointer must be a physical address. + * + * @pool: Pool to initialize + * 0 <= pool < 8 + * @name: Constant character string to name this pool. + * String is not copied. + * @buffer: Pointer to the block of memory to use. This must be + * accessible by all processors and external hardware. + * @block_size: Size for each block controlled by the FPA + * @num_blocks: Number of blocks + * + * Returns 0 on Success, + * -1 on failure + */ +int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, + uint64_t block_size, uint64_t num_blocks) +{ + char *ptr; + if (!buffer) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n"); + return -1; + } + if (pool >= CVMX_FPA_NUM_POOLS) { + cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n"); + return -1; + } + + if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n"); + return -1; + } + + if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n"); + return -1; + } + + cvmx_fpa_pool_info[pool].name = name; + cvmx_fpa_pool_info[pool].size = block_size; + cvmx_fpa_pool_info[pool].starting_element_count = num_blocks; + cvmx_fpa_pool_info[pool].base = buffer; + + ptr = (char *)buffer; + while (num_blocks--) { + cvmx_fpa_free(ptr, pool, 0); + ptr += block_size; + } + return 0; +} + +/** + * Shutdown a Memory pool and validate that it had all of + * the buffers originally placed in it. + * + * @pool: Pool to shutdown + * Returns Zero on success + * - Positive is count of missing buffers + * - Negative is too many buffers or corrupted pointers + */ +uint64_t cvmx_fpa_shutdown_pool(uint64_t pool) +{ + uint64_t errors = 0; + uint64_t count = 0; + uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base); + uint64_t finish = + base + + cvmx_fpa_pool_info[pool].size * + cvmx_fpa_pool_info[pool].starting_element_count; + void *ptr; + uint64_t address; + + count = 0; + do { + ptr = cvmx_fpa_alloc(pool); + if (ptr) + address = cvmx_ptr_to_phys(ptr); + else + address = 0; + if (address) { + if ((address >= base) && (address < finish) && + (((address - + base) % cvmx_fpa_pool_info[pool].size) == 0)) { + count++; + } else { + cvmx_dprintf + ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n", + (unsigned long long)address, + cvmx_fpa_pool_info[pool].name, (int)pool); + errors++; + } + } + } while (address); + +#ifdef CVMX_ENABLE_PKO_FUNCTIONS + if (pool == 0) + cvmx_ipd_free_ptr(); +#endif + + if (errors) { + cvmx_dprintf + ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n", + cvmx_fpa_pool_info[pool].name, (int)pool, + (unsigned long long)base, (unsigned long long)finish, + (unsigned long long)cvmx_fpa_pool_info[pool].size); + return -errors; + } else + return 0; +} + +uint64_t cvmx_fpa_get_block_size(uint64_t pool) +{ + switch (pool) { + case 0: + return CVMX_FPA_POOL_0_SIZE; + case 1: + return CVMX_FPA_POOL_1_SIZE; + case 2: + return CVMX_FPA_POOL_2_SIZE; + case 3: + return CVMX_FPA_POOL_3_SIZE; + case 4: + return CVMX_FPA_POOL_4_SIZE; + case 5: + return CVMX_FPA_POOL_5_SIZE; + case 6: + return CVMX_FPA_POOL_6_SIZE; + case 7: + return CVMX_FPA_POOL_7_SIZE; + default: + return 0; + } +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c new file mode 100644 index 000000000000..71590a35163b --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c @@ -0,0 +1,691 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Helper functions to abstract board specific data about + * network ports from the rest of the cvmx-helper files. + */ + +#include +#include + +#include + +#include + +#include +#include +#include + +#include +#include + +/** + * cvmx_override_board_link_get(int ipd_port) is a function + * pointer. It is meant to allow customization of the process of + * talking to a PHY to determine link speed. It is called every + * time a PHY must be polled for link status. Users should set + * this pointer to a function before calling any cvmx-helper + * operations. + */ +cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) = + NULL; + +/** + * Return the MII PHY address associated with the given IPD + * port. A result of -1 means there isn't a MII capable PHY + * connected to this port. On chips supporting multiple MII + * busses the bus number is encoded in bits <15:8>. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It replies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: Octeon IPD port to get the MII address for. + * + * Returns MII PHY address and bus number or -1. + */ +int cvmx_helper_board_get_mii_address(int ipd_port) +{ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_SIM: + /* Simulator doesn't have MII */ + return -1; + case CVMX_BOARD_TYPE_EBT3000: + case CVMX_BOARD_TYPE_EBT5800: + case CVMX_BOARD_TYPE_THUNDER: + case CVMX_BOARD_TYPE_NICPRO2: + /* Interface 0 is SPI4, interface 1 is RGMII */ + if ((ipd_port >= 16) && (ipd_port < 20)) + return ipd_port - 16; + else + return -1; + case CVMX_BOARD_TYPE_KODAMA: + case CVMX_BOARD_TYPE_EBH3100: + case CVMX_BOARD_TYPE_HIKARI: + case CVMX_BOARD_TYPE_CN3010_EVB_HS5: + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: + case CVMX_BOARD_TYPE_CN3020_EVB_HS5: + /* + * Port 0 is WAN connected to a PHY, Port 1 is GMII + * connected to a switch + */ + if (ipd_port == 0) + return 4; + else if (ipd_port == 1) + return 9; + else + return -1; + case CVMX_BOARD_TYPE_NAC38: + /* Board has 8 RGMII ports PHYs are 0-7 */ + if ((ipd_port >= 0) && (ipd_port < 4)) + return ipd_port; + else if ((ipd_port >= 16) && (ipd_port < 20)) + return ipd_port - 16 + 4; + else + return -1; + case CVMX_BOARD_TYPE_EBH3000: + /* Board has dual SPI4 and no PHYs */ + return -1; + case CVMX_BOARD_TYPE_EBH5200: + case CVMX_BOARD_TYPE_EBH5201: + case CVMX_BOARD_TYPE_EBT5200: + /* + * Board has 4 SGMII ports. The PHYs start right after the MII + * ports MII0 = 0, MII1 = 1, SGMII = 2-5. + */ + if ((ipd_port >= 0) && (ipd_port < 4)) + return ipd_port + 2; + else + return -1; + case CVMX_BOARD_TYPE_EBH5600: + case CVMX_BOARD_TYPE_EBH5601: + case CVMX_BOARD_TYPE_EBH5610: + /* + * Board has 8 SGMII ports. 4 connect out, two connect + * to a switch, and 2 loop to each other + */ + if ((ipd_port >= 0) && (ipd_port < 4)) + return ipd_port + 1; + else + return -1; + case CVMX_BOARD_TYPE_CUST_NB5: + if (ipd_port == 2) + return 4; + else + return -1; + case CVMX_BOARD_TYPE_NIC_XLE_4G: + /* Board has 4 SGMII ports. connected QLM3(interface 1) */ + if ((ipd_port >= 16) && (ipd_port < 20)) + return ipd_port - 16 + 1; + else + return -1; + case CVMX_BOARD_TYPE_BBGW_REF: + /* + * No PHYs are connected to Octeon, everything is + * through switch. + */ + return -1; + + case CVMX_BOARD_TYPE_CUST_WSX16: + if (ipd_port >= 0 && ipd_port <= 3) + return ipd_port; + else if (ipd_port >= 16 && ipd_port <= 19) + return ipd_port - 16 + 4; + else + return -1; + } + + /* Some unknown board. Somebody forgot to update this function... */ + cvmx_dprintf + ("cvmx_helper_board_get_mii_address: Unknown board type %d\n", + cvmx_sysinfo_get()->board_type); + return -1; +} + +/** + * This function is the board specific method of determining an + * ethernet ports link speed. Most Octeon boards have Marvell PHYs + * and are handled by the fall through case. This function must be + * updated for boards that don't have the normal Marvell PHYs. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: IPD input port associated with the port we want to get link + * status for. + * + * Returns The ports link status. If the link isn't fully resolved, this must + * return zero. + */ +cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) +{ + cvmx_helper_link_info_t result; + int phy_addr; + int is_broadcom_phy = 0; + + /* Give the user a chance to override the processing of this function */ + if (cvmx_override_board_link_get) + return cvmx_override_board_link_get(ipd_port); + + /* Unless we fix it later, all links are defaulted to down */ + result.u64 = 0; + + /* + * This switch statement should handle all ports that either don't use + * Marvell PHYS, or don't support in-band status. + */ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_SIM: + /* The simulator gives you a simulated 1Gbps full duplex link */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + case CVMX_BOARD_TYPE_EBH3100: + case CVMX_BOARD_TYPE_CN3010_EVB_HS5: + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: + case CVMX_BOARD_TYPE_CN3020_EVB_HS5: + /* Port 1 on these boards is always Gigabit */ + if (ipd_port == 1) { + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } + /* Fall through to the generic code below */ + break; + case CVMX_BOARD_TYPE_CUST_NB5: + /* Port 1 on these boards is always Gigabit */ + if (ipd_port == 1) { + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } else /* The other port uses a broadcom PHY */ + is_broadcom_phy = 1; + break; + case CVMX_BOARD_TYPE_BBGW_REF: + /* Port 1 on these boards is always Gigabit */ + if (ipd_port == 2) { + /* Port 2 is not hooked up */ + result.u64 = 0; + return result; + } else { + /* Ports 0 and 1 connect to the switch */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } + break; + } + + phy_addr = cvmx_helper_board_get_mii_address(ipd_port); + if (phy_addr != -1) { + if (is_broadcom_phy) { + /* + * Below we are going to read SMI/MDIO + * register 0x19 which works on Broadcom + * parts + */ + int phy_status = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + 0x19); + switch ((phy_status >> 8) & 0x7) { + case 0: + result.u64 = 0; + break; + case 1: + result.s.link_up = 1; + result.s.full_duplex = 0; + result.s.speed = 10; + break; + case 2: + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10; + break; + case 3: + result.s.link_up = 1; + result.s.full_duplex = 0; + result.s.speed = 100; + break; + case 4: + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 100; + break; + case 5: + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 100; + break; + case 6: + result.s.link_up = 1; + result.s.full_duplex = 0; + result.s.speed = 1000; + break; + case 7: + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + break; + } + } else { + /* + * This code assumes we are using a Marvell + * Gigabit PHY. All the speed information can + * be read from register 17 in one + * go. Somebody using a different PHY will + * need to handle it above in the board + * specific area. + */ + int phy_status = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17); + + /* + * If the resolve bit 11 isn't set, see if + * autoneg is turned off (bit 12, reg 0). The + * resolve bit doesn't get set properly when + * autoneg is off, so force it. + */ + if ((phy_status & (1 << 11)) == 0) { + int auto_status = + cvmx_mdio_read(phy_addr >> 8, + phy_addr & 0xff, 0); + if ((auto_status & (1 << 12)) == 0) + phy_status |= 1 << 11; + } + + /* + * Only return a link if the PHY has finished + * auto negotiation and set the resolved bit + * (bit 11) + */ + if (phy_status & (1 << 11)) { + result.s.link_up = 1; + result.s.full_duplex = ((phy_status >> 13) & 1); + switch ((phy_status >> 14) & 3) { + case 0: /* 10 Mbps */ + result.s.speed = 10; + break; + case 1: /* 100 Mbps */ + result.s.speed = 100; + break; + case 2: /* 1 Gbps */ + result.s.speed = 1000; + break; + case 3: /* Illegal */ + result.u64 = 0; + break; + } + } + } + } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) + || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* + * We don't have a PHY address, so attempt to use + * in-band status. It is really important that boards + * not supporting in-band status never get + * here. Reading broken in-band status tends to do bad + * things + */ + union cvmx_gmxx_rxx_rx_inbnd inband_status; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + inband_status.u64 = + cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); + + result.s.link_up = inband_status.s.status; + result.s.full_duplex = inband_status.s.duplex; + switch (inband_status.s.speed) { + case 0: /* 10 Mbps */ + result.s.speed = 10; + break; + case 1: /* 100 Mbps */ + result.s.speed = 100; + break; + case 2: /* 1 Gbps */ + result.s.speed = 1000; + break; + case 3: /* Illegal */ + result.u64 = 0; + break; + } + } else { + /* + * We don't have a PHY address and we don't have + * in-band status. There is no way to determine the + * link speed. Return down assuming this port isn't + * wired + */ + result.u64 = 0; + } + + /* If link is down, return all fields as zero. */ + if (!result.s.link_up) + result.u64 = 0; + + return result; +} + +/** + * This function as a board specific method of changing the PHY + * speed, duplex, and auto-negotiation. This programs the PHY and + * not Octeon. This can be used to force Octeon's links to + * specific settings. + * + * @phy_addr: The address of the PHY to program + * @enable_autoneg: + * Non zero if you want to enable auto-negotiation. + * @link_info: Link speed to program. If the speed is zero and auto-negotiation + * is enabled, all possible negotiation speeds are advertised. + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_board_link_set_phy(int phy_addr, + cvmx_helper_board_set_phy_link_flags_types_t + link_flags, + cvmx_helper_link_info_t link_info) +{ + + /* Set the flow control settings based on link_flags */ + if ((link_flags & set_phy_link_flags_flow_control_mask) != + set_phy_link_flags_flow_control_dont_touch) { + cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; + reg_autoneg_adver.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER); + reg_autoneg_adver.s.asymmetric_pause = + (link_flags & set_phy_link_flags_flow_control_mask) == + set_phy_link_flags_flow_control_enable; + reg_autoneg_adver.s.pause = + (link_flags & set_phy_link_flags_flow_control_mask) == + set_phy_link_flags_flow_control_enable; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER, + reg_autoneg_adver.u16); + } + + /* If speed isn't set and autoneg is on advertise all supported modes */ + if ((link_flags & set_phy_link_flags_autoneg) + && (link_info.s.speed == 0)) { + cvmx_mdio_phy_reg_control_t reg_control; + cvmx_mdio_phy_reg_status_t reg_status; + cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; + cvmx_mdio_phy_reg_extended_status_t reg_extended_status; + cvmx_mdio_phy_reg_control_1000_t reg_control_1000; + + reg_status.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_STATUS); + reg_autoneg_adver.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER); + reg_autoneg_adver.s.advert_100base_t4 = + reg_status.s.capable_100base_t4; + reg_autoneg_adver.s.advert_10base_tx_full = + reg_status.s.capable_10_full; + reg_autoneg_adver.s.advert_10base_tx_half = + reg_status.s.capable_10_half; + reg_autoneg_adver.s.advert_100base_tx_full = + reg_status.s.capable_100base_x_full; + reg_autoneg_adver.s.advert_100base_tx_half = + reg_status.s.capable_100base_x_half; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER, + reg_autoneg_adver.u16); + if (reg_status.s.capable_extended_status) { + reg_extended_status.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_EXTENDED_STATUS); + reg_control_1000.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL_1000); + reg_control_1000.s.advert_1000base_t_full = + reg_extended_status.s.capable_1000base_t_full; + reg_control_1000.s.advert_1000base_t_half = + reg_extended_status.s.capable_1000base_t_half; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL_1000, + reg_control_1000.u16); + } + reg_control.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL); + reg_control.s.autoneg_enable = 1; + reg_control.s.restart_autoneg = 1; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); + } else if ((link_flags & set_phy_link_flags_autoneg)) { + cvmx_mdio_phy_reg_control_t reg_control; + cvmx_mdio_phy_reg_status_t reg_status; + cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; + cvmx_mdio_phy_reg_control_1000_t reg_control_1000; + + reg_status.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_STATUS); + reg_autoneg_adver.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER); + reg_autoneg_adver.s.advert_100base_t4 = 0; + reg_autoneg_adver.s.advert_10base_tx_full = 0; + reg_autoneg_adver.s.advert_10base_tx_half = 0; + reg_autoneg_adver.s.advert_100base_tx_full = 0; + reg_autoneg_adver.s.advert_100base_tx_half = 0; + if (reg_status.s.capable_extended_status) { + reg_control_1000.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL_1000); + reg_control_1000.s.advert_1000base_t_full = 0; + reg_control_1000.s.advert_1000base_t_half = 0; + } + switch (link_info.s.speed) { + case 10: + reg_autoneg_adver.s.advert_10base_tx_full = + link_info.s.full_duplex; + reg_autoneg_adver.s.advert_10base_tx_half = + !link_info.s.full_duplex; + break; + case 100: + reg_autoneg_adver.s.advert_100base_tx_full = + link_info.s.full_duplex; + reg_autoneg_adver.s.advert_100base_tx_half = + !link_info.s.full_duplex; + break; + case 1000: + reg_control_1000.s.advert_1000base_t_full = + link_info.s.full_duplex; + reg_control_1000.s.advert_1000base_t_half = + !link_info.s.full_duplex; + break; + } + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER, + reg_autoneg_adver.u16); + if (reg_status.s.capable_extended_status) + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL_1000, + reg_control_1000.u16); + reg_control.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL); + reg_control.s.autoneg_enable = 1; + reg_control.s.restart_autoneg = 1; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); + } else { + cvmx_mdio_phy_reg_control_t reg_control; + reg_control.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL); + reg_control.s.autoneg_enable = 0; + reg_control.s.restart_autoneg = 1; + reg_control.s.duplex = link_info.s.full_duplex; + if (link_info.s.speed == 1000) { + reg_control.s.speed_msb = 1; + reg_control.s.speed_lsb = 0; + } else if (link_info.s.speed == 100) { + reg_control.s.speed_msb = 0; + reg_control.s.speed_lsb = 1; + } else if (link_info.s.speed == 10) { + reg_control.s.speed_msb = 0; + reg_control.s.speed_lsb = 0; + } + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); + } + return 0; +} + +/** + * This function is called by cvmx_helper_interface_probe() after it + * determines the number of ports Octeon can support on a specific + * interface. This function is the per board location to override + * this value. It is called with the number of ports Octeon might + * support and should return the number of actual ports on the + * board. + * + * This function must be modifed for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relys on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @interface: Interface to probe + * @supported_ports: + * Number of ports Octeon supports. + * + * Returns Number of ports the actual board supports. Many times this will + * simple be "support_ports". + */ +int __cvmx_helper_board_interface_probe(int interface, int supported_ports) +{ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: + if (interface == 0) + return 2; + break; + case CVMX_BOARD_TYPE_BBGW_REF: + if (interface == 0) + return 2; + break; + case CVMX_BOARD_TYPE_NIC_XLE_4G: + if (interface == 0) + return 0; + break; + /* The 2nd interface on the EBH5600 is connected to the Marvel switch, + which we don't support. Disable ports connected to it */ + case CVMX_BOARD_TYPE_EBH5600: + if (interface == 1) + return 0; + break; + } + return supported_ports; +} + +/** + * Enable packet input/output from the hardware. This function is + * called after by cvmx_helper_packet_hardware_enable() to + * perform board specific initialization. For most boards + * nothing is needed. + * + * @interface: Interface to enable + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_board_hardware_enable(int interface) +{ + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) { + if (interface == 0) { + /* Different config for switch port */ + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); + /* + * Boards with gigabit WAN ports need a + * different setting that is compatible with + * 100 Mbit settings + */ + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), + 0xc); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), + 0xc); + } + } else if (cvmx_sysinfo_get()->board_type == + CVMX_BOARD_TYPE_CN3010_EVB_HS5) { + /* + * Broadcom PHYs require differnet ASX + * clocks. Unfortunately many boards don't define a + * new board Id and simply mangle the + * CN3010_EVB_HS5 + */ + if (interface == 0) { + /* + * Some boards use a hacked up bootloader that + * identifies them as CN3010_EVB_HS5 + * evaluation boards. This leads to all kinds + * of configuration problems. Detect one + * case, and print warning, while trying to do + * the right thing. + */ + int phy_addr = cvmx_helper_board_get_mii_address(0); + if (phy_addr != -1) { + int phy_identifier = + cvmx_mdio_read(phy_addr >> 8, + phy_addr & 0xff, 0x2); + /* Is it a Broadcom PHY? */ + if (phy_identifier == 0x0143) { + cvmx_dprintf("\n"); + cvmx_dprintf("ERROR:\n"); + cvmx_dprintf + ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n"); + cvmx_dprintf + ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n"); + cvmx_dprintf + ("ERROR: All boards require a unique board type to identify them.\n"); + cvmx_dprintf("ERROR:\n"); + cvmx_dprintf("\n"); + cvmx_wait(1000000000); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX + (0, interface), 5); + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX + (0, interface), 5); + } + } + } + } + return 0; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c new file mode 100644 index 000000000000..c239e5f4ab9a --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c @@ -0,0 +1,243 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Helper functions for FPA setup. + * + */ +#include "executive-config.h" +#include "cvmx-config.h" +#include "cvmx.h" +#include "cvmx-bootmem.h" +#include "cvmx-fpa.h" +#include "cvmx-helper-fpa.h" + +/** + * Allocate memory for and initialize a single FPA pool. + * + * @pool: Pool to initialize + * @buffer_size: Size of buffers to allocate in bytes + * @buffers: Number of buffers to put in the pool. Zero is allowed + * @name: String name of the pool for debugging purposes + * Returns Zero on success, non-zero on failure + */ +static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size, + uint64_t buffers, const char *name) +{ + uint64_t current_num; + void *memory; + uint64_t align = CVMX_CACHE_LINE_SIZE; + + /* + * Align the allocation so that power of 2 size buffers are + * naturally aligned. + */ + while (align < buffer_size) + align = align << 1; + + if (buffers == 0) + return 0; + + current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool)); + if (current_num) { + cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. " + "Skipping setup.\n", + pool, name, (unsigned long long)current_num); + return 0; + } + + memory = cvmx_bootmem_alloc(buffer_size * buffers, align); + if (memory == NULL) { + cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n", + pool, name); + return -1; + } + cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers); + return 0; +} + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Specifying zero for the number of + * buffers will cause that FPA pool to not be setup. This is + * useful if you aren't using some of the hardware and want + * to save memory. Use cvmx_helper_initialize_fpa instead of + * this function directly. + * + * @pip_pool: Should always be CVMX_FPA_PACKET_POOL + * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE + * @pip_buffers: + * Number of packet buffers. + * @wqe_pool: Should always be CVMX_FPA_WQE_POOL + * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE + * @wqe_entries: + * Number of work queue entries + * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL + * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_pool: Should always be CVMX_FPA_TIMER_POOL + * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_pool: Should always be CVMX_FPA_DFA_POOL + * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size, + int pip_buffers, int wqe_pool, + int wqe_size, int wqe_entries, + int pko_pool, int pko_size, + int pko_buffers, int tim_pool, + int tim_size, int tim_buffers, + int dfa_pool, int dfa_size, + int dfa_buffers) +{ + int status; + + cvmx_fpa_enable(); + + if ((pip_buffers > 0) && (pip_buffers <= 64)) + cvmx_dprintf + ("Warning: %d packet buffers may not be enough for hardware" + " prefetch. 65 or more is recommended.\n", pip_buffers); + + if (pip_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size, + pip_buffers, + "Packet Buffers"); + if (status) + return status; + } + + if (wqe_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size, + wqe_entries, + "Work Queue Entries"); + if (status) + return status; + } + + if (pko_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size, + pko_buffers, + "PKO Command Buffers"); + if (status) + return status; + } + + if (tim_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size, + tim_buffers, + "TIM Command Buffers"); + if (status) + return status; + } + + if (dfa_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size, + dfa_buffers, + "DFA Command Buffers"); + if (status) + return status; + } + + return 0; +} + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Sizes of each element in the pools is + * controlled by the cvmx-config.h header file. Specifying + * zero for any parameter will cause that FPA pool to not be + * setup. This is useful if you aren't using some of the + * hardware and want to save memory. + * + * @packet_buffers: + * Number of packet buffers to allocate + * @work_queue_entries: + * Number of work queue entries + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries, + int pko_buffers, int tim_buffers, + int dfa_buffers) +{ +#ifndef CVMX_FPA_PACKET_POOL +#define CVMX_FPA_PACKET_POOL -1 +#define CVMX_FPA_PACKET_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_WQE_POOL +#define CVMX_FPA_WQE_POOL -1 +#define CVMX_FPA_WQE_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL +#define CVMX_FPA_OUTPUT_BUFFER_POOL -1 +#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_TIMER_POOL +#define CVMX_FPA_TIMER_POOL -1 +#define CVMX_FPA_TIMER_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_DFA_POOL +#define CVMX_FPA_DFA_POOL -1 +#define CVMX_FPA_DFA_POOL_SIZE 0 +#endif + return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL, + CVMX_FPA_PACKET_POOL_SIZE, + packet_buffers, CVMX_FPA_WQE_POOL, + CVMX_FPA_WQE_POOL_SIZE, + work_queue_entries, + CVMX_FPA_OUTPUT_BUFFER_POOL, + CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, + pko_buffers, CVMX_FPA_TIMER_POOL, + CVMX_FPA_TIMER_POOL_SIZE, + tim_buffers, CVMX_FPA_DFA_POOL, + CVMX_FPA_DFA_POOL_SIZE, + dfa_buffers); +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c new file mode 100644 index 000000000000..bfbd46115e71 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c @@ -0,0 +1,85 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for LOOP initialization, configuration, + * and monitoring. + */ +#include + +#include + +#include +#include + +/** + * Probe a LOOP interface and determine the number of ports + * connected to it. The LOOP interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_loop_probe(int interface) +{ + union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs; + int num_ports = 4; + int port; + + /* We need to disable length checking so packet < 64 bytes and jumbo + frames don't get errors */ + for (port = 0; port < num_ports; port++) { + union cvmx_pip_prt_cfgx port_cfg; + int ipd_port = cvmx_helper_get_ipd_port(interface, port); + port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + port_cfg.s.maxerr_en = 0; + port_cfg.s.minerr_en = 0; + cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); + } + + /* Disable FCS stripping for loopback ports */ + ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); + ipd_sub_port_fcs.s.port_bit2 = 0; + cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); + return num_ports; +} + +/** + * Bringup and enable a LOOP interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_loop_enable(int interface) +{ + /* Do nothing. */ + return 0; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c new file mode 100644 index 000000000000..cc94cfa545b4 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c @@ -0,0 +1,113 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for NPI initialization, configuration, + * and monitoring. + */ +#include + +#include + +#include + +#include + +/** + * Probe a NPI interface and determine the number of ports + * connected to it. The NPI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_npi_probe(int interface) +{ +#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0 + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) + return 4; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX) + && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) + /* The packet engines didn't exist before pass 2 */ + return 4; + else if (OCTEON_IS_MODEL(OCTEON_CN52XX) + && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) + /* The packet engines didn't exist before pass 2 */ + return 4; +#if 0 + /* + * Technically CN30XX, CN31XX, and CN50XX contain packet + * engines, but nobody ever uses them. Since this is the case, + * we disable them here. + */ + else if (OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) + return 2; + else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) + return 1; +#endif +#endif + return 0; +} + +/** + * Bringup and enable a NPI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_npi_enable(int interface) +{ + /* + * On CN50XX, CN52XX, and CN56XX we need to disable length + * checking so packet < 64 bytes and jumbo frames don't get + * errors. + */ + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && + !OCTEON_IS_MODEL(OCTEON_CN58XX)) { + int num_ports = cvmx_helper_ports_on_interface(interface); + int port; + for (port = 0; port < num_ports; port++) { + union cvmx_pip_prt_cfgx port_cfg; + int ipd_port = + cvmx_helper_get_ipd_port(interface, port); + port_cfg.u64 = + cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + port_cfg.s.maxerr_en = 0; + port_cfg.s.minerr_en = 0; + cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), + port_cfg.u64); + } + } + + /* Enables are controlled by the remote host, so nothing to do here */ + return 0; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c new file mode 100644 index 000000000000..82b21843421c --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c @@ -0,0 +1,526 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for RGMII/GMII/MII initialization, configuration, + * and monitoring. + */ +#include + +#include + + +#include +#include +#include +#include + +#include +#include +#include +#include + +void __cvmx_interrupt_gmxx_enable(int interface); +void __cvmx_interrupt_asxx_enable(int block); + +/** + * Probe RGMII ports and determine the number present + * + * @interface: Interface to probe + * + * Returns Number of RGMII/GMII/MII ports (0-4). + */ +int __cvmx_helper_rgmii_probe(int interface) +{ + int num_ports = 0; + union cvmx_gmxx_inf_mode mode; + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + if (mode.s.type) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + cvmx_dprintf("ERROR: RGMII initialize called in " + "SPI interface\n"); + } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN30XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* + * On these chips "type" says we're in + * GMII/MII mode. This limits us to 2 ports + */ + num_ports = 2; + } else { + cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", + __func__); + } + } else { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + num_ports = 4; + } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN30XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + num_ports = 3; + } else { + cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", + __func__); + } + } + return num_ports; +} + +/** + * Put an RGMII interface in loopback mode. Internal packets sent + * out will be received back again on the same port. Externally + * received packets will echo back out. + * + * @port: IPD port number to loop. + */ +void cvmx_helper_rgmii_internal_loopback(int port) +{ + int interface = (port >> 4) & 1; + int index = port & 0xf; + uint64_t tmp; + + union cvmx_gmxx_prtx_cfg gmx_cfg; + gmx_cfg.u64 = 0; + gmx_cfg.s.duplex = 1; + gmx_cfg.s.slottime = 1; + gmx_cfg.s.speed = 1; + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); + tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); + tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); + tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); +} + +/** + * Workaround ASX setup errata with CN38XX pass1 + * + * @interface: Interface to setup + * @port: Port to setup (0..3) + * @cpu_clock_hz: + * Chip frequency in Hertz + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_errata_asx_pass1(int interface, int port, + int cpu_clock_hz) +{ + /* Set hi water mark as per errata GMX-4 */ + if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000) + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12); + else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000) + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11); + else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000) + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10); + else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000) + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9); + else + cvmx_dprintf("Illegal clock frequency (%d). " + "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz); + return 0; +} + +/** + * Configure all of the ASX, GMX, and PKO regsiters required + * to get RGMII to function on the supplied interface. + * + * @interface: PKO Interface to configure (0 or 1) + * + * Returns Zero on success + */ +int __cvmx_helper_rgmii_enable(int interface) +{ + int num_ports = cvmx_helper_ports_on_interface(interface); + int port; + struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get(); + union cvmx_gmxx_inf_mode mode; + union cvmx_asxx_tx_prt_en asx_tx; + union cvmx_asxx_rx_prt_en asx_rx; + + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + if (mode.s.en == 0) + return -1; + if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || + OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1) + /* Ignore SPI interfaces */ + return -1; + + /* Configure the ASX registers needed to use the RGMII ports */ + asx_tx.u64 = 0; + asx_tx.s.prt_en = cvmx_build_mask(num_ports); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); + + asx_rx.u64 = 0; + asx_rx.s.prt_en = cvmx_build_mask(num_ports); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64); + + /* Configure the GMX registers needed to use the RGMII ports */ + for (port = 0; port < num_ports; port++) { + /* Setting of CVMX_GMXX_TXX_THRESH has been moved to + __cvmx_helper_setup_gmx() */ + + if (cvmx_octeon_is_pass1()) + __cvmx_helper_errata_asx_pass1(interface, port, + sys_info_ptr-> + cpu_clock_hz); + else { + /* + * Configure more flexible RGMII preamble + * checking. Pass 1 doesn't support this + * feature. + */ + union cvmx_gmxx_rxx_frm_ctl frm_ctl; + frm_ctl.u64 = + cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL + (port, interface)); + /* New field, so must be compile time */ + frm_ctl.s.pre_free = 1; + cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), + frm_ctl.u64); + } + + /* + * Each pause frame transmitted will ask for about 10M + * bit times before resume. If buffer space comes + * available before that time has expired, an XON + * pause frame (0 time) will be transmitted to restart + * the flow. + */ + cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), + 20000); + cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL + (port, interface), 19000); + + if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), + 16); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), + 16); + } else { + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), + 24); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), + 24); + } + } + + __cvmx_helper_setup_gmx(interface, num_ports); + + /* enable the ports now */ + for (port = 0; port < num_ports; port++) { + union cvmx_gmxx_prtx_cfg gmx_cfg; + cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port + (interface, port)); + gmx_cfg.u64 = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface)); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), + gmx_cfg.u64); + } + __cvmx_interrupt_asxx_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + + return 0; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + union cvmx_asxx_prt_loop asxx_prt_loop; + + asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); + if (asxx_prt_loop.s.int_loop & (1 << index)) { + /* Force 1Gbps full duplex on internal loopback */ + cvmx_helper_link_info_t result; + result.u64 = 0; + result.s.full_duplex = 1; + result.s.link_up = 1; + result.s.speed = 1000; + return result; + } else + return __cvmx_helper_board_link_get(ipd_port); +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_rgmii_link_set(int ipd_port, + cvmx_helper_link_info_t link_info) +{ + int result = 0; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + union cvmx_gmxx_prtx_cfg original_gmx_cfg; + union cvmx_gmxx_prtx_cfg new_gmx_cfg; + union cvmx_pko_mem_queue_qos pko_mem_queue_qos; + union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16]; + union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp; + union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save; + int i; + + /* Ignore speed sets in the simulator */ + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) + return 0; + + /* Read the current settings so we know the current enable state */ + original_gmx_cfg.u64 = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + new_gmx_cfg = original_gmx_cfg; + + /* Disable the lowest level RX */ + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), + cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & + ~(1 << index)); + + memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save)); + /* Disable all queues so that TX should become idle */ + for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { + int queue = cvmx_pko_get_base_queue(ipd_port) + i; + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); + pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS); + pko_mem_queue_qos.s.pid = ipd_port; + pko_mem_queue_qos.s.qid = queue; + pko_mem_queue_qos_save[i] = pko_mem_queue_qos; + pko_mem_queue_qos.s.qos_mask = 0; + cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64); + } + + /* Disable backpressure */ + gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); + gmx_tx_ovr_bp_save = gmx_tx_ovr_bp; + gmx_tx_ovr_bp.s.bp &= ~(1 << index); + gmx_tx_ovr_bp.s.en |= 1 << index; + cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); + cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); + + /* + * Poll the GMX state machine waiting for it to become + * idle. Preferably we should only change speed when it is + * idle. If it doesn't become idle we will still do the speed + * change, but there is a slight chance that GMX will + * lockup. + */ + cvmx_write_csr(CVMX_NPI_DBG_SELECT, + interface * 0x800 + index * 0x100 + 0x880); + CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7, + ==, 0, 10000); + CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf, + ==, 0, 10000); + + /* Disable the port before we make any changes */ + new_gmx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + + /* Set full/half duplex */ + if (cvmx_octeon_is_pass1()) + /* Half duplex is broken for 38XX Pass 1 */ + new_gmx_cfg.s.duplex = 1; + else if (!link_info.s.link_up) + /* Force full duplex on down links */ + new_gmx_cfg.s.duplex = 1; + else + new_gmx_cfg.s.duplex = link_info.s.full_duplex; + + /* Set the link speed. Anything unknown is set to 1Gbps */ + if (link_info.s.speed == 10) { + new_gmx_cfg.s.slottime = 0; + new_gmx_cfg.s.speed = 0; + } else if (link_info.s.speed == 100) { + new_gmx_cfg.s.slottime = 0; + new_gmx_cfg.s.speed = 0; + } else { + new_gmx_cfg.s.slottime = 1; + new_gmx_cfg.s.speed = 1; + } + + /* Adjust the clocks */ + if (link_info.s.speed == 10) { + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); + } else if (link_info.s.speed == 100) { + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); + } else { + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); + } + + if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) { + union cvmx_gmxx_inf_mode mode; + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + /* + * Port .en .type .p0mii Configuration + * ---- --- ----- ------ ----------------------------------------- + * X 0 X X All links are disabled. + * 0 1 X 0 Port 0 is RGMII + * 0 1 X 1 Port 0 is MII + * 1 1 0 X Ports 1 and 2 are configured as RGMII ports. + * 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or + * MII port is selected by GMX_PRT1_CFG[SPEED]. + */ + + /* In MII mode, CLK_CNT = 1. */ + if (((index == 0) && (mode.s.p0mii == 1)) + || ((index != 0) && (mode.s.type == 1))) { + cvmx_write_csr(CVMX_GMXX_TXX_CLK + (index, interface), 1); + } + } + } + + /* Do a read to make sure all setup stuff is complete */ + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + + /* Save the new GMX setting without enabling the port */ + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); + + /* Enable the lowest level RX */ + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), + cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 << + index)); + + /* Re-enable the TX path */ + for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { + int queue = cvmx_pko_get_base_queue(ipd_port) + i; + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); + cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, + pko_mem_queue_qos_save[i].u64); + } + + /* Restore backpressure */ + cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64); + + /* Restore the GMX enable state. Port config is complete */ + new_gmx_cfg.s.en = original_gmx_cfg.s.en; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); + + return result; +} + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal, + int enable_external) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + int original_enable; + union cvmx_gmxx_prtx_cfg gmx_cfg; + union cvmx_asxx_prt_loop asxx_prt_loop; + + /* Read the current enable state and save it */ + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + original_enable = gmx_cfg.s.en; + /* Force port to be disabled */ + gmx_cfg.s.en = 0; + if (enable_internal) { + /* Force speed if we're doing internal loopback */ + gmx_cfg.s.duplex = 1; + gmx_cfg.s.slottime = 1; + gmx_cfg.s.speed = 1; + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); + } + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); + + /* Set the loopback bits */ + asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); + if (enable_internal) + asxx_prt_loop.s.int_loop |= 1 << index; + else + asxx_prt_loop.s.int_loop &= ~(1 << index); + if (enable_external) + asxx_prt_loop.s.ext_loop |= 1 << index; + else + asxx_prt_loop.s.ext_loop &= ~(1 << index); + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64); + + /* Force enables in internal loopback */ + if (enable_internal) { + uint64_t tmp; + tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), + (1 << index) | tmp); + tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), + (1 << index) | tmp); + original_enable = 1; + } + + /* Restore the enable state */ + gmx_cfg.s.en = original_enable; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); + return 0; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c new file mode 100644 index 000000000000..464347ffd362 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -0,0 +1,550 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for SGMII initialization, configuration, + * and monitoring. + */ + +#include + +#include + +#include +#include +#include + +#include +#include + +void __cvmx_interrupt_gmxx_enable(int interface); +void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); +void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); + +/** + * Perform initialization required only once for an SGMII port. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) +{ + const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; + union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; + union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg; + union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; + + /* Disable GMX */ + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + gmxx_prtx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); + + /* + * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the + * appropriate value. 1000BASE-X specifies a 10ms + * interval. SGMII specifies a 1.6ms interval. + */ + pcs_misc_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + pcsx_linkx_timer_count_reg.u64 = + cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); + if (pcs_misc_ctl_reg.s.mode) { + /* 1000BASE-X */ + pcsx_linkx_timer_count_reg.s.count = + (10000ull * clock_mhz) >> 10; + } else { + /* SGMII */ + pcsx_linkx_timer_count_reg.s.count = + (1600ull * clock_mhz) >> 10; + } + cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), + pcsx_linkx_timer_count_reg.u64); + + /* + * Write the advertisement register to be used as the + * tx_Config_Reg of the autonegotiation. In + * 1000BASE-X mode, tx_Config_Reg is PCS*_AN*_ADV_REG. + * In SGMII PHY mode, tx_Config_Reg is + * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, + * tx_Config_Reg is the fixed value 0x4001, so this + * step can be skipped. + */ + if (pcs_misc_ctl_reg.s.mode) { + /* 1000BASE-X */ + union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg; + pcsx_anx_adv_reg.u64 = + cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); + pcsx_anx_adv_reg.s.rem_flt = 0; + pcsx_anx_adv_reg.s.pause = 3; + pcsx_anx_adv_reg.s.hfd = 1; + pcsx_anx_adv_reg.s.fd = 1; + cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), + pcsx_anx_adv_reg.u64); + } else { + union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + pcsx_miscx_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + if (pcsx_miscx_ctl_reg.s.mac_phy) { + /* PHY Mode */ + union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg; + pcsx_sgmx_an_adv_reg.u64 = + cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG + (index, interface)); + pcsx_sgmx_an_adv_reg.s.link = 1; + pcsx_sgmx_an_adv_reg.s.dup = 1; + pcsx_sgmx_an_adv_reg.s.speed = 2; + cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG + (index, interface), + pcsx_sgmx_an_adv_reg.u64); + } else { + /* MAC Mode - Nothing to do */ + } + } + return 0; +} + +/** + * Initialize the SERTES link for the first time or after a loss + * of link. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index) +{ + union cvmx_pcsx_mrx_control_reg control_reg; + + /* + * Take PCS through a reset sequence. + * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. + * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the + * value of the other PCS*_MR*_CONTROL_REG bits). Read + * PCS*_MR*_CONTROL_REG[RESET] until it changes value to + * zero. + */ + control_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); + if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { + control_reg.s.reset = 1; + cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), + control_reg.u64); + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSX_MRX_CONTROL_REG(index, interface), + union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) { + cvmx_dprintf("SGMII%d: Timeout waiting for port %d " + "to finish reset\n", + interface, index); + return -1; + } + } + + /* + * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh + * sgmii negotiation starts. + */ + control_reg.s.rst_an = 1; + control_reg.s.an_en = 1; + control_reg.s.pwr_dn = 0; + cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), + control_reg.u64); + + /* + * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating + * that sgmii autonegotiation is complete. In MAC mode this + * isn't an ethernet link, but a link between Octeon and the + * PHY. + */ + if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && + CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface), + union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1, + 10000)) { + /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */ + return -1; + } + return 0; +} + +/** + * Configure an SGMII link to the specified speed after the SERTES + * link is up. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * @link_info: Link state to configure + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, + int index, + cvmx_helper_link_info_t + link_info) +{ + int is_enabled; + union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; + union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + + /* Disable GMX before we make any changes. Remember the enable state */ + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + is_enabled = gmxx_prtx_cfg.s.en; + gmxx_prtx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); + + /* Wait for GMX to be idle */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg, + rx_idle, ==, 1, 10000) + || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), + union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1, + 10000)) { + cvmx_dprintf + ("SGMII%d: Timeout waiting for port %d to be idle\n", + interface, index); + return -1; + } + + /* Read GMX CFG again to make sure the disable completed */ + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + + /* + * Get the misc control for PCS. We will need to set the + * duplication amount. + */ + pcsx_miscx_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + + /* + * Use GMXENO to force the link down if the status we get says + * it should be down. + */ + pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up; + + /* Only change the duplex setting if the link is up */ + if (link_info.s.link_up) + gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex; + + /* Do speed based setting for GMX */ + switch (link_info.s.speed) { + case 10: + gmxx_prtx_cfg.s.speed = 0; + gmxx_prtx_cfg.s.speed_msb = 1; + gmxx_prtx_cfg.s.slottime = 0; + /* Setting from GMX-603 */ + pcsx_miscx_ctl_reg.s.samp_pt = 25; + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); + break; + case 100: + gmxx_prtx_cfg.s.speed = 0; + gmxx_prtx_cfg.s.speed_msb = 0; + gmxx_prtx_cfg.s.slottime = 0; + pcsx_miscx_ctl_reg.s.samp_pt = 0x5; + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); + break; + case 1000: + gmxx_prtx_cfg.s.speed = 1; + gmxx_prtx_cfg.s.speed_msb = 0; + gmxx_prtx_cfg.s.slottime = 1; + pcsx_miscx_ctl_reg.s.samp_pt = 1; + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192); + break; + default: + break; + } + + /* Write the new misc control for PCS */ + cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), + pcsx_miscx_ctl_reg.u64); + + /* Write the new GMX settings with the port still disabled */ + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); + + /* Read GMX CFG again to make sure the config completed */ + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + + /* Restore the enabled / disabled state */ + gmxx_prtx_cfg.s.en = is_enabled; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); + + return 0; +} + +/** + * Bring up the SGMII interface to be ready for packet I/O but + * leave I/O disabled using the GMX override. This function + * follows the bringup documented in 10.6.3 of the manual. + * + * @interface: Interface to bringup + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) +{ + int index; + + __cvmx_helper_setup_gmx(interface, num_ports); + + for (index = 0; index < num_ports; index++) { + int ipd_port = cvmx_helper_get_ipd_port(interface, index); + __cvmx_helper_sgmii_hardware_init_one_time(interface, index); + __cvmx_helper_sgmii_link_set(ipd_port, + __cvmx_helper_sgmii_link_get + (ipd_port)); + + } + + return 0; +} + +/** + * Probe a SGMII interface and determine the number of ports + * connected to it. The SGMII interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_sgmii_probe(int interface) +{ + union cvmx_gmxx_inf_mode mode; + + /* + * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the + * interface needs to be enabled before IPD otherwise per port + * backpressure may not work properly + */ + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + mode.s.en = 1; + cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); + return 4; +} + +/** + * Bringup and enable a SGMII interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_sgmii_enable(int interface) +{ + int num_ports = cvmx_helper_ports_on_interface(interface); + int index; + + __cvmx_helper_sgmii_hardware_init(interface, num_ports); + + for (index = 0; index < num_ports; index++) { + union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; + gmxx_prtx_cfg.u64 = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + gmxx_prtx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), + gmxx_prtx_cfg.u64); + __cvmx_interrupt_pcsx_intx_en_reg_enable(index, interface); + } + __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + return 0; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port) +{ + cvmx_helper_link_info_t result; + union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg; + + result.u64 = 0; + + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { + /* The simulator gives you a simulated 1Gbps full duplex link */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } + + pcsx_mrx_control_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); + if (pcsx_mrx_control_reg.s.loopbck1) { + /* Force 1Gbps full duplex link for internal loopback */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } + + pcs_misc_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + if (pcs_misc_ctl_reg.s.mode) { + /* 1000BASE-X */ + /* FIXME */ + } else { + union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + pcsx_miscx_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + if (pcsx_miscx_ctl_reg.s.mac_phy) { + /* PHY Mode */ + union cvmx_pcsx_mrx_status_reg pcsx_mrx_status_reg; + union cvmx_pcsx_anx_results_reg pcsx_anx_results_reg; + + /* + * Don't bother continuing if the SERTES low + * level link is down + */ + pcsx_mrx_status_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG + (index, interface)); + if (pcsx_mrx_status_reg.s.lnk_st == 0) { + if (__cvmx_helper_sgmii_hardware_init_link + (interface, index) != 0) + return result; + } + + /* Read the autoneg results */ + pcsx_anx_results_reg.u64 = + cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG + (index, interface)); + if (pcsx_anx_results_reg.s.an_cpt) { + /* + * Auto negotiation is complete. Set + * status accordingly. + */ + result.s.full_duplex = + pcsx_anx_results_reg.s.dup; + result.s.link_up = + pcsx_anx_results_reg.s.link_ok; + switch (pcsx_anx_results_reg.s.spd) { + case 0: + result.s.speed = 10; + break; + case 1: + result.s.speed = 100; + break; + case 2: + result.s.speed = 1000; + break; + default: + result.s.speed = 0; + result.s.link_up = 0; + break; + } + } else { + /* + * Auto negotiation isn't + * complete. Return link down. + */ + result.s.speed = 0; + result.s.link_up = 0; + } + } else { /* MAC Mode */ + + result = __cvmx_helper_board_link_get(ipd_port); + } + } + return result; +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_sgmii_link_set(int ipd_port, + cvmx_helper_link_info_t link_info) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + __cvmx_helper_sgmii_hardware_init_link(interface, index); + return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, + link_info); +} + +/** + * Configure a port for internal and/or external loopback. Internal + * loopback causes packets sent by the port to be received by + * Octeon. External loopback causes packets received from the wire to + * sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal, + int enable_external) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg; + union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + + pcsx_mrx_control_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); + pcsx_mrx_control_reg.s.loopbck1 = enable_internal; + cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), + pcsx_mrx_control_reg.u64); + + pcsx_miscx_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + pcsx_miscx_ctl_reg.s.loopbck2 = enable_external; + cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), + pcsx_miscx_ctl_reg.u64); + + __cvmx_helper_sgmii_hardware_init_link(interface, index); + return 0; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c new file mode 100644 index 000000000000..02a444230ef7 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -0,0 +1,195 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +void __cvmx_interrupt_gmxx_enable(int interface); +void __cvmx_interrupt_spxx_int_msk_enable(int index); +void __cvmx_interrupt_stxx_int_msk_enable(int index); + +/* + * Functions for SPI initialization, configuration, + * and monitoring. + */ +#include + +#include +#include +#include + +#include +#include + +/* + * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI + * initialization routines wait for SPI training. You can override the + * value using executive-config.h if necessary. + */ +#ifndef CVMX_HELPER_SPI_TIMEOUT +#define CVMX_HELPER_SPI_TIMEOUT 10 +#endif + +/** + * Probe a SPI interface and determine the number of ports + * connected to it. The SPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_spi_probe(int interface) +{ + int num_ports = 0; + + if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && + cvmx_spi4000_is_present(interface)) { + num_ports = 10; + } else { + union cvmx_pko_reg_crc_enable enable; + num_ports = 16; + /* + * Unlike the SPI4000, most SPI devices don't + * automatically put on the L2 CRC. For everything + * except for the SPI4000 have PKO append the L2 CRC + * to the packet. + */ + enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE); + enable.s.enable |= 0xffff << (interface * 16); + cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64); + } + __cvmx_helper_setup_gmx(interface, num_ports); + return num_ports; +} + +/** + * Bringup and enable a SPI interface. After this call packet I/O + * should be fully functional. This is called with IPD enabled but + * PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_spi_enable(int interface) +{ + /* + * Normally the ethernet L2 CRC is checked and stripped in the + * GMX block. When you are using SPI, this isn' the case and + * IPD needs to check the L2 CRC. + */ + int num_ports = cvmx_helper_ports_on_interface(interface); + int ipd_port; + for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports; + ipd_port++) { + union cvmx_pip_prt_cfgx port_config; + port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + port_config.s.crc_en = 1; + cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); + } + + if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { + cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX, + CVMX_HELPER_SPI_TIMEOUT, num_ports); + if (cvmx_spi4000_is_present(interface)) + cvmx_spi4000_initialize(interface); + } + __cvmx_interrupt_spxx_int_msk_enable(interface); + __cvmx_interrupt_stxx_int_msk_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + return 0; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port) +{ + cvmx_helper_link_info_t result; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + result.u64 = 0; + + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { + /* The simulator gives you a simulated full duplex link */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10000; + } else if (cvmx_spi4000_is_present(interface)) { + union cvmx_gmxx_rxx_rx_inbnd inband = + cvmx_spi4000_check_speed(interface, index); + result.s.link_up = inband.s.status; + result.s.full_duplex = inband.s.duplex; + switch (inband.s.speed) { + case 0: /* 10 Mbps */ + result.s.speed = 10; + break; + case 1: /* 100 Mbps */ + result.s.speed = 100; + break; + case 2: /* 1 Gbps */ + result.s.speed = 1000; + break; + case 3: /* Illegal */ + result.s.speed = 0; + result.s.link_up = 0; + break; + } + } else { + /* For generic SPI we can't determine the link, just return some + sane results */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10000; + } + return result; +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info) +{ + /* Nothing to do. If we have a SPI4000 then the setup was already performed + by cvmx_spi4000_check_speed(). If not then there isn't any link + info */ + return 0; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c new file mode 100644 index 000000000000..116dea17acf5 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c @@ -0,0 +1,433 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Small helper utilities. + */ +#include + +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include + +/** + * Convert a interface mode into a human readable string + * + * @mode: Mode to convert + * + * Returns String + */ +const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t + mode) +{ + switch (mode) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + return "DISABLED"; + case CVMX_HELPER_INTERFACE_MODE_RGMII: + return "RGMII"; + case CVMX_HELPER_INTERFACE_MODE_GMII: + return "GMII"; + case CVMX_HELPER_INTERFACE_MODE_SPI: + return "SPI"; + case CVMX_HELPER_INTERFACE_MODE_PCIE: + return "PCIE"; + case CVMX_HELPER_INTERFACE_MODE_XAUI: + return "XAUI"; + case CVMX_HELPER_INTERFACE_MODE_SGMII: + return "SGMII"; + case CVMX_HELPER_INTERFACE_MODE_PICMG: + return "PICMG"; + case CVMX_HELPER_INTERFACE_MODE_NPI: + return "NPI"; + case CVMX_HELPER_INTERFACE_MODE_LOOP: + return "LOOP"; + } + return "UNKNOWN"; +} + +/** + * Debug routine to dump the packet structure to the console + * + * @work: Work queue entry containing the packet to dump + * Returns + */ +int cvmx_helper_dump_packet(cvmx_wqe_t *work) +{ + uint64_t count; + uint64_t remaining_bytes; + union cvmx_buf_ptr buffer_ptr; + uint64_t start_of_buffer; + uint8_t *data_address; + uint8_t *end_of_data; + + cvmx_dprintf("Packet Length: %u\n", work->len); + cvmx_dprintf(" Input Port: %u\n", work->ipprt); + cvmx_dprintf(" QoS: %u\n", work->qos); + cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs); + + if (work->word2.s.bufs == 0) { + union cvmx_ipd_wqe_fpa_queue wqe_pool; + wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE); + buffer_ptr.u64 = 0; + buffer_ptr.s.pool = wqe_pool.s.wqe_pool; + buffer_ptr.s.size = 128; + buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data); + if (likely(!work->word2.s.not_IP)) { + union cvmx_pip_ip_offset pip_ip_offset; + pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET); + buffer_ptr.s.addr += + (pip_ip_offset.s.offset << 3) - + work->word2.s.ip_offset; + buffer_ptr.s.addr += (work->word2.s.is_v6 ^ 1) << 2; + } else { + /* + * WARNING: This code assumes that the packet + * is not RAW. If it was, we would use + * PIP_GBL_CFG[RAW_SHF] instead of + * PIP_GBL_CFG[NIP_SHF]. + */ + union cvmx_pip_gbl_cfg pip_gbl_cfg; + pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG); + buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf; + } + } else + buffer_ptr = work->packet_ptr; + remaining_bytes = work->len; + + while (remaining_bytes) { + start_of_buffer = + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; + cvmx_dprintf(" Buffer Start:%llx\n", + (unsigned long long)start_of_buffer); + cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i); + cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back); + cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool); + cvmx_dprintf(" Buffer Data: %llx\n", + (unsigned long long)buffer_ptr.s.addr); + cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size); + + cvmx_dprintf("\t\t"); + data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr); + end_of_data = data_address + buffer_ptr.s.size; + count = 0; + while (data_address < end_of_data) { + if (remaining_bytes == 0) + break; + else + remaining_bytes--; + cvmx_dprintf("%02x", (unsigned int)*data_address); + data_address++; + if (remaining_bytes && (count == 7)) { + cvmx_dprintf("\n\t\t"); + count = 0; + } else + count++; + } + cvmx_dprintf("\n"); + + if (remaining_bytes) + buffer_ptr = *(union cvmx_buf_ptr *) + cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); + } + return 0; +} + +/** + * Setup Random Early Drop on a specific input queue + * + * @queue: Input queue to setup RED on (0-7) + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incomming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh) +{ + union cvmx_ipd_qosx_red_marks red_marks; + union cvmx_ipd_red_quex_param red_param; + + /* Set RED to begin dropping packets when there are pass_thresh buffers + left. It will linearly drop more packets until reaching drop_thresh + buffers */ + red_marks.u64 = 0; + red_marks.s.drop = drop_thresh; + red_marks.s.pass = pass_thresh; + cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); + + /* Use the actual queue 0 counter, not the average */ + red_param.u64 = 0; + red_param.s.prb_con = + (255ul << 24) / (red_marks.s.pass - red_marks.s.drop); + red_param.s.avg_con = 1; + red_param.s.new_con = 255; + red_param.s.use_pcnt = 1; + cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); + return 0; +} + +/** + * Setup Random Early Drop to automatically begin dropping packets. + * + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incomming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) +{ + union cvmx_ipd_portx_bp_page_cnt page_cnt; + union cvmx_ipd_bp_prt_red_end ipd_bp_prt_red_end; + union cvmx_ipd_red_port_enable red_port_enable; + int queue; + int interface; + int port; + + /* Disable backpressure based on queued buffers. It needs SW support */ + page_cnt.u64 = 0; + page_cnt.s.bp_enb = 0; + page_cnt.s.page_cnt = 100; + for (interface = 0; interface < 2; interface++) { + for (port = cvmx_helper_get_first_ipd_port(interface); + port < cvmx_helper_get_last_ipd_port(interface); port++) + cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), + page_cnt.u64); + } + + for (queue = 0; queue < 8; queue++) + cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh); + + /* Shutoff the dropping based on the per port page count. SW isn't + decrementing it right now */ + ipd_bp_prt_red_end.u64 = 0; + ipd_bp_prt_red_end.s.prt_enb = 0; + cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); + + red_port_enable.u64 = 0; + red_port_enable.s.prt_enb = 0xfffffffffull; + red_port_enable.s.avg_dly = 10000; + red_port_enable.s.prb_dly = 10000; + cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); + + return 0; +} + +/** + * Setup the common GMX settings that determine the number of + * ports. These setting apply to almost all configurations of all + * chips. + * + * @interface: Interface to configure + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_setup_gmx(int interface, int num_ports) +{ + union cvmx_gmxx_tx_prts gmx_tx_prts; + union cvmx_gmxx_rx_prts gmx_rx_prts; + union cvmx_pko_reg_gmx_port_mode pko_mode; + union cvmx_gmxx_txx_thresh gmx_tx_thresh; + int index; + + /* Tell GMX the number of TX ports on this interface */ + gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); + gmx_tx_prts.s.prts = num_ports; + cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); + + /* Tell GMX the number of RX ports on this interface. This only + ** applies to *GMII and XAUI ports */ + if (cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_RGMII + || cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_SGMII + || cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_GMII + || cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_XAUI) { + if (num_ports > 4) { + cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal " + "num_ports\n"); + return -1; + } + + gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); + gmx_rx_prts.s.prts = num_ports; + cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); + } + + /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */ + if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) + && !OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* Tell PKO the number of ports on this interface */ + pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); + if (interface == 0) { + if (num_ports == 1) + pko_mode.s.mode0 = 4; + else if (num_ports == 2) + pko_mode.s.mode0 = 3; + else if (num_ports <= 4) + pko_mode.s.mode0 = 2; + else if (num_ports <= 8) + pko_mode.s.mode0 = 1; + else + pko_mode.s.mode0 = 0; + } else { + if (num_ports == 1) + pko_mode.s.mode1 = 4; + else if (num_ports == 2) + pko_mode.s.mode1 = 3; + else if (num_ports <= 4) + pko_mode.s.mode1 = 2; + else if (num_ports <= 8) + pko_mode.s.mode1 = 1; + else + pko_mode.s.mode1 = 0; + } + cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); + } + + /* + * Set GMX to buffer as much data as possible before starting + * transmit. This reduces the chances that we have a TX under + * run due to memory contention. Any packet that fits entirely + * in the GMX FIFO can never have an under run regardless of + * memory load. + */ + gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); + if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* These chips have a fixed max threshold of 0x40 */ + gmx_tx_thresh.s.cnt = 0x40; + } else { + /* Choose the max value for the number of ports */ + if (num_ports <= 1) + gmx_tx_thresh.s.cnt = 0x100 / 1; + else if (num_ports == 2) + gmx_tx_thresh.s.cnt = 0x100 / 2; + else + gmx_tx_thresh.s.cnt = 0x100 / 4; + } + /* + * SPI and XAUI can have lots of ports but the GMX hardware + * only ever has a max of 4. + */ + if (num_ports > 4) + num_ports = 4; + for (index = 0; index < num_ports; index++) + cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), + gmx_tx_thresh.u64); + + return 0; +} + +/** + * Returns the IPD/PKO port number for a port on the given + * interface. + * + * @interface: Interface to use + * @port: Port on the interface + * + * Returns IPD/PKO port number + */ +int cvmx_helper_get_ipd_port(int interface, int port) +{ + switch (interface) { + case 0: + return port; + case 1: + return port + 16; + case 2: + return port + 32; + case 3: + return port + 36; + } + return -1; +} + +/** + * Returns the interface number for an IPD/PKO port number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface number + */ +int cvmx_helper_get_interface_num(int ipd_port) +{ + if (ipd_port < 16) + return 0; + else if (ipd_port < 32) + return 1; + else if (ipd_port < 36) + return 2; + else if (ipd_port < 40) + return 3; + else + cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD " + "port number\n"); + + return -1; +} + +/** + * Returns the interface index number for an IPD/PKO port + * number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface index number + */ +int cvmx_helper_get_interface_index_num(int ipd_port) +{ + if (ipd_port < 32) + return ipd_port & 15; + else if (ipd_port < 36) + return ipd_port & 3; + else if (ipd_port < 40) + return ipd_port & 3; + else + cvmx_dprintf("cvmx_helper_get_interface_index_num: " + "Illegal IPD port number\n"); + + return -1; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c new file mode 100644 index 000000000000..667a8e3cb142 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -0,0 +1,348 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for XAUI initialization, configuration, + * and monitoring. + * + */ + +#include + +#include + +#include + +#include +#include +#include + +void __cvmx_interrupt_gmxx_enable(int interface); +void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); +void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); +/** + * Probe a XAUI interface and determine the number of ports + * connected to it. The XAUI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_xaui_probe(int interface) +{ + int i; + union cvmx_gmxx_hg2_control gmx_hg2_control; + union cvmx_gmxx_inf_mode mode; + + /* + * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the + * interface needs to be enabled before IPD otherwise per port + * backpressure may not work properly. + */ + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + mode.s.en = 1; + cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); + + __cvmx_helper_setup_gmx(interface, 1); + + /* + * Setup PKO to support 16 ports for HiGig2 virtual + * ports. We're pointing all of the PKO packet ports for this + * interface to the XAUI. This allows us to use HiGig2 + * backpressure per port. + */ + for (i = 0; i < 16; i++) { + union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs; + pko_mem_port_ptrs.u64 = 0; + /* + * We set each PKO port to have equal priority in a + * round robin fashion. + */ + pko_mem_port_ptrs.s.static_p = 0; + pko_mem_port_ptrs.s.qos_mask = 0xff; + /* All PKO ports map to the same XAUI hardware port */ + pko_mem_port_ptrs.s.eid = interface * 4; + pko_mem_port_ptrs.s.pid = interface * 16 + i; + cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); + } + + /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ + gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); + if (gmx_hg2_control.s.hg2tx_en) + return 16; + else + return 1; +} + +/** + * Bringup and enable a XAUI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_xaui_enable(int interface) +{ + union cvmx_gmxx_prtx_cfg gmx_cfg; + union cvmx_pcsxx_control1_reg xauiCtl; + union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl; + union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl; + union cvmx_gmxx_rxx_int_en gmx_rx_int_en; + union cvmx_gmxx_tx_int_en gmx_tx_int_en; + union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; + + /* (1) Interface has already been enabled. */ + + /* (2) Disable GMX. */ + xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface)); + xauiMiscCtl.s.gmxeno = 1; + cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); + + /* (3) Disable GMX and PCSX interrupts. */ + gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface)); + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); + gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface)); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); + pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface)); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); + + /* (4) Bring up the PCSX and GMX reconciliation layer. */ + /* (4)a Set polarity and lane swapping. */ + /* (4)b */ + gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + /* Enable better IFG packing and improves performance */ + gmxXauiTxCtl.s.dic_en = 1; + gmxXauiTxCtl.s.uni_en = 0; + cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); + + /* (4)c Aply reset sequence */ + xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); + xauiCtl.s.lo_pwr = 0; + xauiCtl.s.reset = 1; + cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64); + + /* Wait for PCS to come out of reset */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg, + reset, ==, 0, 10000)) + return -1; + /* Wait for PCS to be aligned */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_10GBX_STATUS_REG(interface), + union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000)) + return -1; + /* Wait for RX to be ready */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl, + status, ==, 0, 10000)) + return -1; + + /* (6) Configure GMX */ + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + /* Wait for GMX RX to be idle */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, + rx_idle, ==, 1, 10000)) + return -1; + /* Wait for GMX TX to be idle */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, + tx_idle, ==, 1, 10000)) + return -1; + + /* GMX configure */ + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.speed = 1; + gmx_cfg.s.speed_msb = 0; + gmx_cfg.s.slottime = 1; + cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192); + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + /* (7) Clear out any error state */ + cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface), + cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface))); + cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), + cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface))); + cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), + cvmx_read_csr(CVMX_PCSXX_INT_REG(interface))); + + /* Wait for receive link */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg, + rcv_lnk, ==, 1, 10000)) + return -1; + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, + xmtflt, ==, 0, 10000)) + return -1; + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, + rcvflt, ==, 0, 10000)) + return -1; + + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64); + + cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0)); + + /* (8) Enable packet reception */ + xauiMiscCtl.s.gmxeno = 0; + cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); + + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface); + __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + + return 0; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; + union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; + union cvmx_pcsxx_status1_reg pcsxx_status1_reg; + cvmx_helper_link_info_t result; + + gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); + pcsxx_status1_reg.u64 = + cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface)); + result.u64 = 0; + + /* Only return a link if both RX and TX are happy */ + if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) && + (pcsxx_status1_reg.s.rcv_lnk == 1)) { + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10000; + } else { + /* Disable GMX and PCSX interrupts. */ + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); + } + return result; +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; + union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; + + gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); + + /* If the link shouldn't be up, then just return */ + if (!link_info.s.link_up) + return 0; + + /* Do nothing if both RX and TX are happy */ + if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0)) + return 0; + + /* Bring the link up */ + return __cvmx_helper_xaui_enable(interface); +} + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, + int enable_internal, + int enable_external) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + union cvmx_pcsxx_control1_reg pcsxx_control1_reg; + union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback; + + /* Set the internal loop */ + pcsxx_control1_reg.u64 = + cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); + pcsxx_control1_reg.s.loopbck1 = enable_internal; + cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), + pcsxx_control1_reg.u64); + + /* Set the external loop */ + gmxx_xaui_ext_loopback.u64 = + cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface)); + gmxx_xaui_ext_loopback.s.en = enable_external; + cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), + gmxx_xaui_ext_loopback.u64); + + /* Take the link through a reset */ + return __cvmx_helper_xaui_enable(interface); +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c new file mode 100644 index 000000000000..daa8c8bbcfe4 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -0,0 +1,1053 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Helper functions for common, but complicated tasks. + * + */ +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/** + * cvmx_override_pko_queue_priority(int ipd_port, uint64_t + * priorities[16]) is a function pointer. It is meant to allow + * customization of the PKO queue priorities based on the port + * number. Users should set this pointer to a function before + * calling any cvmx-helper operations. + */ +void (*cvmx_override_pko_queue_priority) (int pko_port, + uint64_t priorities[16]); + +/** + * cvmx_override_ipd_port_setup(int ipd_port) is a function + * pointer. It is meant to allow customization of the IPD port + * setup before packet input/output comes online. It is called + * after cvmx-helper does the default IPD configuration, but + * before IPD is enabled. Users should set this pointer to a + * function before calling any cvmx-helper operations. + */ +void (*cvmx_override_ipd_port_setup) (int ipd_port); + +/* Port count per interface */ +static int interface_port_count[4] = { 0, 0, 0, 0 }; + +/* Port last configured link info index by IPD/PKO port */ +static cvmx_helper_link_info_t + port_link_info[CVMX_PIP_NUM_INPUT_PORTS]; + +/** + * Return the number of interfaces the chip has. Each interface + * may have multiple ports. Most chips support two interfaces, + * but the CNX0XX and CNX1XX are exceptions. These only support + * one interface. + * + * Returns Number of interfaces on chip + */ +int cvmx_helper_get_number_of_interfaces(void) +{ + if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) + return 4; + else + return 3; +} + +/** + * Return the number of ports on an interface. Depending on the + * chip and configuration, this can be 1-16. A value of 0 + * specifies that the interface doesn't exist or isn't usable. + * + * @interface: Interface to get the port count for + * + * Returns Number of ports on interface. Can be Zero. + */ +int cvmx_helper_ports_on_interface(int interface) +{ + return interface_port_count[interface]; +} + +/** + * Get the operating mode of an interface. Depending on the Octeon + * chip and configuration, this function returns an enumeration + * of the type of packet I/O supported by an interface. + * + * @interface: Interface to probe + * + * Returns Mode of the interface. Unknown or unsupported interfaces return + * DISABLED. + */ +cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) +{ + union cvmx_gmxx_inf_mode mode; + if (interface == 2) + return CVMX_HELPER_INTERFACE_MODE_NPI; + + if (interface == 3) { + if (OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX)) + return CVMX_HELPER_INTERFACE_MODE_LOOP; + else + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + } + + if (interface == 0 + && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 + && cvmx_sysinfo_get()->board_rev_major == 1) { + /* + * Lie about interface type of CN3005 board. This + * board has a switch on port 1 like the other + * evaluation boards, but it is connected over RGMII + * instead of GMII. Report GMII mode so that the + * speed is forced to 1 Gbit full duplex. Other than + * some initial configuration (which does not use the + * output of this function) there is no difference in + * setup between GMII and RGMII modes. + */ + return CVMX_HELPER_INTERFACE_MODE_GMII; + } + + /* Interface 1 is always disabled on CN31XX and CN30XX */ + if ((interface == 1) + && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX))) + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { + switch (mode.cn56xx.mode) { + case 0: + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + case 1: + return CVMX_HELPER_INTERFACE_MODE_XAUI; + case 2: + return CVMX_HELPER_INTERFACE_MODE_SGMII; + case 3: + return CVMX_HELPER_INTERFACE_MODE_PICMG; + default: + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + } + } else { + if (!mode.s.en) + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + + if (mode.s.type) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) + return CVMX_HELPER_INTERFACE_MODE_SPI; + else + return CVMX_HELPER_INTERFACE_MODE_GMII; + } else + return CVMX_HELPER_INTERFACE_MODE_RGMII; + } +} + +/** + * Configure the IPD/PIP tagging and QoS options for a specific + * port. This function determines the POW work queue entry + * contents for a port. The setup performed here is controlled by + * the defines in executive-config.h. + * + * @ipd_port: Port to configure. This follows the IPD numbering, not the + * per interface numbering + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_port_setup_ipd(int ipd_port) +{ + union cvmx_pip_prt_cfgx port_config; + union cvmx_pip_prt_tagx tag_config; + + port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port)); + + /* Have each port go to a different POW queue */ + port_config.s.qos = ipd_port & 0x7; + + /* Process the headers and place the IP header in the work queue */ + port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE; + + tag_config.s.ip6_src_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP; + tag_config.s.ip6_dst_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_IP; + tag_config.s.ip6_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT; + tag_config.s.ip6_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT; + tag_config.s.ip6_nxth_flag = CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER; + tag_config.s.ip4_src_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP; + tag_config.s.ip4_dst_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_IP; + tag_config.s.ip4_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT; + tag_config.s.ip4_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT; + tag_config.s.ip4_pctl_flag = CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL; + tag_config.s.inc_prt_flag = CVMX_HELPER_INPUT_TAG_INPUT_PORT; + tag_config.s.tcp6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + tag_config.s.tcp4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + tag_config.s.ip6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + tag_config.s.ip4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + tag_config.s.non_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + /* Put all packets in group 0. Other groups can be used by the app */ + tag_config.s.grp = 0; + + cvmx_pip_config_port(ipd_port, port_config, tag_config); + + /* Give the user a chance to override our setting for each port */ + if (cvmx_override_ipd_port_setup) + cvmx_override_ipd_port_setup(ipd_port); + + return 0; +} + +/** + * This function probes an interface to determine the actual + * number of hardware ports connected to it. It doesn't setup the + * ports or enable them. The main goal here is to set the global + * interface_port_count[interface] correctly. Hardware setup of the + * ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_interface_probe(int interface) +{ + /* At this stage in the game we don't want packets to be moving yet. + The following probe calls should perform hardware setup + needed to determine port counts. Receive must still be disabled */ + switch (cvmx_helper_interface_get_mode(interface)) { + /* These types don't support ports to IPD/PKO */ + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + interface_port_count[interface] = 0; + break; + /* XAUI is a single high speed port */ + case CVMX_HELPER_INTERFACE_MODE_XAUI: + interface_port_count[interface] = + __cvmx_helper_xaui_probe(interface); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII. + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + interface_port_count[interface] = + __cvmx_helper_rgmii_probe(interface); + break; + /* + * SPI4 can have 1-16 ports depending on the device at + * the other end. + */ + case CVMX_HELPER_INTERFACE_MODE_SPI: + interface_port_count[interface] = + __cvmx_helper_spi_probe(interface); + break; + /* + * SGMII can have 1-4 ports depending on how many are + * hooked up. + */ + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + interface_port_count[interface] = + __cvmx_helper_sgmii_probe(interface); + break; + /* PCI target Network Packet Interface */ + case CVMX_HELPER_INTERFACE_MODE_NPI: + interface_port_count[interface] = + __cvmx_helper_npi_probe(interface); + break; + /* + * Special loopback only ports. These are not the same + * as other ports in loopback mode. + */ + case CVMX_HELPER_INTERFACE_MODE_LOOP: + interface_port_count[interface] = + __cvmx_helper_loop_probe(interface); + break; + } + + interface_port_count[interface] = + __cvmx_helper_board_interface_probe(interface, + interface_port_count + [interface]); + + /* Make sure all global variables propagate to other cores */ + CVMX_SYNCWS; + + return 0; +} + +/** + * Setup the IPD/PIP for the ports on an interface. Packet + * classification and tagging are set for every port on the + * interface. The number of ports on the interface must already + * have been probed. + * + * @interface: Interface to setup IPD/PIP for + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_interface_setup_ipd(int interface) +{ + int ipd_port = cvmx_helper_get_ipd_port(interface, 0); + int num_ports = interface_port_count[interface]; + + while (num_ports--) { + __cvmx_helper_port_setup_ipd(ipd_port); + ipd_port++; + } + return 0; +} + +/** + * Setup global setting for IPD/PIP not related to a specific + * interface or port. This must be called before IPD is enabled. + * + * Returns Zero on success, negative on failure. + */ +static int __cvmx_helper_global_setup_ipd(void) +{ + /* Setup the global packet input options */ + cvmx_ipd_config(CVMX_FPA_PACKET_POOL_SIZE / 8, + CVMX_HELPER_FIRST_MBUFF_SKIP / 8, + CVMX_HELPER_NOT_FIRST_MBUFF_SKIP / 8, + /* The +8 is to account for the next ptr */ + (CVMX_HELPER_FIRST_MBUFF_SKIP + 8) / 128, + /* The +8 is to account for the next ptr */ + (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP + 8) / 128, + CVMX_FPA_WQE_POOL, + CVMX_IPD_OPC_MODE_STT, + CVMX_HELPER_ENABLE_BACK_PRESSURE); + return 0; +} + +/** + * Setup the PKO for the ports on an interface. The number of + * queues per port and the priority of each PKO output queue + * is set here. PKO must be disabled when this function is called. + * + * @interface: Interface to setup PKO for + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_interface_setup_pko(int interface) +{ + /* + * Each packet output queue has an associated priority. The + * higher the priority, the more often it can send a packet. A + * priority of 8 means it can send in all 8 rounds of + * contention. We're going to make each queue one less than + * the last. The vector of priorities has been extended to + * support CN5xxx CPUs, where up to 16 queues can be + * associated to a port. To keep backward compatibility we + * don't change the initial 8 priorities and replicate them in + * the second half. With per-core PKO queues (PKO lockless + * operation) all queues have the same priority. + */ + uint64_t priorities[16] = + { 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 }; + + /* + * Setup the IPD/PIP and PKO for the ports discovered + * above. Here packet classification, tagging and output + * priorities are set. + */ + int ipd_port = cvmx_helper_get_ipd_port(interface, 0); + int num_ports = interface_port_count[interface]; + while (num_ports--) { + /* + * Give the user a chance to override the per queue + * priorities. + */ + if (cvmx_override_pko_queue_priority) + cvmx_override_pko_queue_priority(ipd_port, priorities); + + cvmx_pko_config_port(ipd_port, + cvmx_pko_get_base_queue_per_core(ipd_port, + 0), + cvmx_pko_get_num_queues(ipd_port), + priorities); + ipd_port++; + } + return 0; +} + +/** + * Setup global setting for PKO not related to a specific + * interface or port. This must be called before PKO is enabled. + * + * Returns Zero on success, negative on failure. + */ +static int __cvmx_helper_global_setup_pko(void) +{ + /* + * Disable tagwait FAU timeout. This needs to be done before + * anyone might start packet output using tags. + */ + union cvmx_iob_fau_timeout fau_to; + fau_to.u64 = 0; + fau_to.s.tout_val = 0xfff; + fau_to.s.tout_enb = 0; + cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); + return 0; +} + +/** + * Setup global backpressure setting. + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_global_setup_backpressure(void) +{ +#if CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE + /* Disable backpressure if configured to do so */ + /* Disable backpressure (pause frame) generation */ + int num_interfaces = cvmx_helper_get_number_of_interfaces(); + int interface; + for (interface = 0; interface < num_interfaces; interface++) { + switch (cvmx_helper_interface_get_mode(interface)) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + case CVMX_HELPER_INTERFACE_MODE_NPI: + case CVMX_HELPER_INTERFACE_MODE_LOOP: + case CVMX_HELPER_INTERFACE_MODE_XAUI: + break; + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + case CVMX_HELPER_INTERFACE_MODE_SPI: + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + cvmx_gmx_set_backpressure_override(interface, 0xf); + break; + } + } +#endif + + return 0; +} + +/** + * Enable packet input/output from the hardware. This function is + * called after all internal setup is complete and IPD is enabled. + * After this function completes, packets will be accepted from the + * hardware ports. PKO should still be disabled to make sure packets + * aren't sent out partially setup hardware. + * + * @interface: Interface to enable + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_packet_hardware_enable(int interface) +{ + int result = 0; + switch (cvmx_helper_interface_get_mode(interface)) { + /* These types don't support ports to IPD/PKO */ + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + /* Nothing to do */ + break; + /* XAUI is a single high speed port */ + case CVMX_HELPER_INTERFACE_MODE_XAUI: + result = __cvmx_helper_xaui_enable(interface); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + result = __cvmx_helper_rgmii_enable(interface); + break; + /* + * SPI4 can have 1-16 ports depending on the device at + * the other end + */ + case CVMX_HELPER_INTERFACE_MODE_SPI: + result = __cvmx_helper_spi_enable(interface); + break; + /* + * SGMII can have 1-4 ports depending on how many are + * hooked up + */ + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + result = __cvmx_helper_sgmii_enable(interface); + break; + /* PCI target Network Packet Interface */ + case CVMX_HELPER_INTERFACE_MODE_NPI: + result = __cvmx_helper_npi_enable(interface); + break; + /* + * Special loopback only ports. These are not the same + * as other ports in loopback mode + */ + case CVMX_HELPER_INTERFACE_MODE_LOOP: + result = __cvmx_helper_loop_enable(interface); + break; + } + result |= __cvmx_helper_board_hardware_enable(interface); + return result; +} + +/** + * Function to adjust internal IPD pointer alignments + * + * Returns 0 on success + * !0 on failure + */ +int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) +{ +#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \ + (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP) +#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \ + (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP) +#define FIX_IPD_OUTPORT 0 + /* Ports 0-15 are interface 0, 16-31 are interface 1 */ +#define INTERFACE(port) (port >> 4) +#define INDEX(port) (port & 0xf) + uint64_t *p64; + cvmx_pko_command_word0_t pko_command; + union cvmx_buf_ptr g_buffer, pkt_buffer; + cvmx_wqe_t *work; + int size, num_segs = 0, wqe_pcnt, pkt_pcnt; + union cvmx_gmxx_prtx_cfg gmx_cfg; + int retry_cnt; + int retry_loop_cnt; + int i; + cvmx_helper_link_info_t link_info; + + /* Save values for restore at end */ + uint64_t prtx_cfg = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); + uint64_t tx_ptr_en = + cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); + uint64_t rx_ptr_en = + cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); + uint64_t rxx_jabber = + cvmx_read_csr(CVMX_GMXX_RXX_JABBER + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); + uint64_t frame_max = + cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); + + /* Configure port to gig FDX as required for loopback mode */ + cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT); + + /* + * Disable reception on all ports so if traffic is present it + * will not interfere. + */ + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); + + cvmx_wait(100000000ull); + + for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) { + retry_cnt = 100000; + wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT); + pkt_pcnt = (wqe_pcnt >> 7) & 0x7f; + wqe_pcnt &= 0x7f; + + num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3; + + if (num_segs == 0) + goto fix_ipd_exit; + + num_segs += 1; + + size = + FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES + + ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) - + (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2); + + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), + 1 << INDEX(FIX_IPD_OUTPORT)); + CVMX_SYNC; + + g_buffer.u64 = 0; + g_buffer.s.addr = + cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL)); + if (g_buffer.s.addr == 0) { + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " + "buffer allocation failure.\n"); + goto fix_ipd_exit; + } + + g_buffer.s.pool = CVMX_FPA_WQE_POOL; + g_buffer.s.size = num_segs; + + pkt_buffer.u64 = 0; + pkt_buffer.s.addr = + cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL)); + if (pkt_buffer.s.addr == 0) { + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " + "buffer allocation failure.\n"); + goto fix_ipd_exit; + } + pkt_buffer.s.i = 1; + pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL; + pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES; + + p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr); + p64[0] = 0xffffffffffff0000ull; + p64[1] = 0x08004510ull; + p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull; + p64[3] = 0x3a5fc0a81073c0a8ull; + + for (i = 0; i < num_segs; i++) { + if (i > 0) + pkt_buffer.s.size = + FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES; + + if (i == (num_segs - 1)) + pkt_buffer.s.i = 0; + + *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr + + 8 * i) = pkt_buffer.u64; + } + + /* Build the PKO command */ + pko_command.u64 = 0; + pko_command.s.segs = num_segs; + pko_command.s.total_bytes = size; + pko_command.s.dontfree = 0; + pko_command.s.gather = 1; + + gmx_cfg.u64 = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT))); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), + 1 << INDEX(FIX_IPD_OUTPORT)); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), + 1 << INDEX(FIX_IPD_OUTPORT)); + + cvmx_write_csr(CVMX_GMXX_RXX_JABBER + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); + + cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT, + cvmx_pko_get_base_queue + (FIX_IPD_OUTPORT), + CVMX_PKO_LOCK_CMD_QUEUE); + cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT, + cvmx_pko_get_base_queue + (FIX_IPD_OUTPORT), pko_command, + g_buffer, CVMX_PKO_LOCK_CMD_QUEUE); + + CVMX_SYNC; + + do { + work = cvmx_pow_work_request_sync(CVMX_POW_WAIT); + retry_cnt--; + } while ((work == NULL) && (retry_cnt > 0)); + + if (!retry_cnt) + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " + "get_work() timeout occurred.\n"); + + /* Free packet */ + if (work) + cvmx_helper_free_packet_data(work); + } + +fix_ipd_exit: + + /* Return CSR configs to saved values */ + cvmx_write_csr(CVMX_GMXX_PRTX_CFG + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), + prtx_cfg); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), + tx_ptr_en); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), + rx_ptr_en); + cvmx_write_csr(CVMX_GMXX_RXX_JABBER + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), + rxx_jabber); + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), + frame_max); + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0); + /* Set link to down so autonegotiation will set it up again */ + link_info.u64 = 0; + cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info); + + /* + * Bring the link back up as autonegotiation is not done in + * user applications. + */ + cvmx_helper_link_autoconf(FIX_IPD_OUTPORT); + + CVMX_SYNC; + if (num_segs) + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n"); + + return !!num_segs; + +} + +/** + * Called after all internal packet IO paths are setup. This + * function enables IPD/PIP and begins packet input and output. + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_ipd_and_packet_input_enable(void) +{ + int num_interfaces; + int interface; + + /* Enable IPD */ + cvmx_ipd_enable(); + + /* + * Time to enable hardware ports packet input and output. Note + * that at this point IPD/PIP must be fully functional and PKO + * must be disabled + */ + num_interfaces = cvmx_helper_get_number_of_interfaces(); + for (interface = 0; interface < num_interfaces; interface++) { + if (cvmx_helper_ports_on_interface(interface) > 0) + __cvmx_helper_packet_hardware_enable(interface); + } + + /* Finally enable PKO now that the entire path is up and running */ + cvmx_pko_enable(); + + if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1) + || OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1)) + && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)) + __cvmx_helper_errata_fix_ipd_ptr_alignment(); + return 0; +} + +/** + * Initialize the PIP, IPD, and PKO hardware to support + * simple priority based queues for the ethernet ports. Each + * port is configured with a number of priority queues based + * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower + * priority than the previous. + * + * Returns Zero on success, non-zero on failure + */ +int cvmx_helper_initialize_packet_io_global(void) +{ + int result = 0; + int interface; + union cvmx_l2c_cfg l2c_cfg; + union cvmx_smix_en smix_en; + const int num_interfaces = cvmx_helper_get_number_of_interfaces(); + + /* + * CN52XX pass 1: Due to a bug in 2nd order CDR, it needs to + * be disabled. + */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0)) + __cvmx_helper_errata_qlm_disable_2nd_order_cdr(1); + + /* + * Tell L2 to give the IOB statically higher priority compared + * to the cores. This avoids conditions where IO blocks might + * be starved under very high L2 loads. + */ + l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); + l2c_cfg.s.lrf_arb_mode = 0; + l2c_cfg.s.rfb_arb_mode = 0; + cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64); + + /* Make sure SMI/MDIO is enabled so we can query PHYs */ + smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0)); + if (!smix_en.s.en) { + smix_en.s.en = 1; + cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64); + } + + /* Newer chips actually have two SMI/MDIO interfaces */ + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && + !OCTEON_IS_MODEL(OCTEON_CN58XX) && + !OCTEON_IS_MODEL(OCTEON_CN50XX)) { + smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1)); + if (!smix_en.s.en) { + smix_en.s.en = 1; + cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64); + } + } + + cvmx_pko_initialize_global(); + for (interface = 0; interface < num_interfaces; interface++) { + result |= cvmx_helper_interface_probe(interface); + if (cvmx_helper_ports_on_interface(interface) > 0) + cvmx_dprintf("Interface %d has %d ports (%s)\n", + interface, + cvmx_helper_ports_on_interface(interface), + cvmx_helper_interface_mode_to_string + (cvmx_helper_interface_get_mode + (interface))); + result |= __cvmx_helper_interface_setup_ipd(interface); + result |= __cvmx_helper_interface_setup_pko(interface); + } + + result |= __cvmx_helper_global_setup_ipd(); + result |= __cvmx_helper_global_setup_pko(); + + /* Enable any flow control and backpressure */ + result |= __cvmx_helper_global_setup_backpressure(); + +#if CVMX_HELPER_ENABLE_IPD + result |= cvmx_helper_ipd_and_packet_input_enable(); +#endif + return result; +} + +/** + * Does core local initialization for packet io + * + * Returns Zero on success, non-zero on failure + */ +int cvmx_helper_initialize_packet_io_local(void) +{ + return cvmx_pko_initialize_local(); +} + +/** + * Auto configure an IPD/PKO port link state and speed. This + * function basically does the equivalent of: + * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); + * + * @ipd_port: IPD/PKO port to auto configure + * + * Returns Link state after configure + */ +cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port) +{ + cvmx_helper_link_info_t link_info; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + + if (index >= cvmx_helper_ports_on_interface(interface)) { + link_info.u64 = 0; + return link_info; + } + + link_info = cvmx_helper_link_get(ipd_port); + if (link_info.u64 == port_link_info[ipd_port].u64) + return link_info; + + /* If we fail to set the link speed, port_link_info will not change */ + cvmx_helper_link_set(ipd_port, link_info); + + /* + * port_link_info should be the current value, which will be + * different than expect if cvmx_helper_link_set() failed. + */ + return port_link_info[ipd_port]; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port) +{ + cvmx_helper_link_info_t result; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + + /* The default result will be a down link unless the code below + changes it */ + result.u64 = 0; + + if (index >= cvmx_helper_ports_on_interface(interface)) + return result; + + switch (cvmx_helper_interface_get_mode(interface)) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + /* Network links are not supported */ + break; + case CVMX_HELPER_INTERFACE_MODE_XAUI: + result = __cvmx_helper_xaui_link_get(ipd_port); + break; + case CVMX_HELPER_INTERFACE_MODE_GMII: + if (index == 0) + result = __cvmx_helper_rgmii_link_get(ipd_port); + else { + result.s.full_duplex = 1; + result.s.link_up = 1; + result.s.speed = 1000; + } + break; + case CVMX_HELPER_INTERFACE_MODE_RGMII: + result = __cvmx_helper_rgmii_link_get(ipd_port); + break; + case CVMX_HELPER_INTERFACE_MODE_SPI: + result = __cvmx_helper_spi_link_get(ipd_port); + break; + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + result = __cvmx_helper_sgmii_link_get(ipd_port); + break; + case CVMX_HELPER_INTERFACE_MODE_NPI: + case CVMX_HELPER_INTERFACE_MODE_LOOP: + /* Network links are not supported */ + break; + } + return result; +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info) +{ + int result = -1; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + + if (index >= cvmx_helper_ports_on_interface(interface)) + return -1; + + switch (cvmx_helper_interface_get_mode(interface)) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + break; + case CVMX_HELPER_INTERFACE_MODE_XAUI: + result = __cvmx_helper_xaui_link_set(ipd_port, link_info); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII. + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + result = __cvmx_helper_rgmii_link_set(ipd_port, link_info); + break; + case CVMX_HELPER_INTERFACE_MODE_SPI: + result = __cvmx_helper_spi_link_set(ipd_port, link_info); + break; + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + result = __cvmx_helper_sgmii_link_set(ipd_port, link_info); + break; + case CVMX_HELPER_INTERFACE_MODE_NPI: + case CVMX_HELPER_INTERFACE_MODE_LOOP: + break; + } + /* Set the port_link_info here so that the link status is updated + no matter how cvmx_helper_link_set is called. We don't change + the value if link_set failed */ + if (result == 0) + port_link_info[ipd_port].u64 = link_info.u64; + return result; +} + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, + int enable_external) +{ + int result = -1; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + + if (index >= cvmx_helper_ports_on_interface(interface)) + return -1; + + switch (cvmx_helper_interface_get_mode(interface)) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + case CVMX_HELPER_INTERFACE_MODE_SPI: + case CVMX_HELPER_INTERFACE_MODE_NPI: + case CVMX_HELPER_INTERFACE_MODE_LOOP: + break; + case CVMX_HELPER_INTERFACE_MODE_XAUI: + result = + __cvmx_helper_xaui_configure_loopback(ipd_port, + enable_internal, + enable_external); + break; + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + result = + __cvmx_helper_rgmii_configure_loopback(ipd_port, + enable_internal, + enable_external); + break; + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + result = + __cvmx_helper_sgmii_configure_loopback(ipd_port, + enable_internal, + enable_external); + break; + } + return result; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c new file mode 100644 index 000000000000..e59d1b79f24c --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c @@ -0,0 +1,371 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2009 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Automatically generated functions useful for enabling + * and decoding RSL_INT_BLOCKS interrupts. + * + */ + +#include + +#include +#include +#include +#include +#include + +#ifndef PRINT_ERROR +#define PRINT_ERROR(format, ...) +#endif + + +/** + * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t + */ +void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) +{ + union cvmx_gmxx_rxx_int_en gmx_rx_int_en; + cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), + cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); + gmx_rx_int_en.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { + /* Skipping gmx_rx_int_en.s.reserved_29_63 */ + gmx_rx_int_en.s.hg2cc = 1; + gmx_rx_int_en.s.hg2fld = 1; + gmx_rx_int_en.s.undat = 1; + gmx_rx_int_en.s.uneop = 1; + gmx_rx_int_en.s.unsop = 1; + gmx_rx_int_en.s.bad_term = 1; + gmx_rx_int_en.s.bad_seq = 1; + gmx_rx_int_en.s.rem_fault = 1; + gmx_rx_int_en.s.loc_fault = 1; + gmx_rx_int_en.s.pause_drp = 1; + /* Skipping gmx_rx_int_en.s.reserved_16_18 */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + /* Skipping gmx_rx_int_en.s.reserved_9_9 */ + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /* Skipping gmx_rx_int_en.s.reserved_5_6 */ + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + /* Skipping gmx_rx_int_en.s.reserved_2_2 */ + gmx_rx_int_en.s.carext = 1; + /* Skipping gmx_rx_int_en.s.reserved_0_0 */ + } + if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { + /* Skipping gmx_rx_int_en.s.reserved_19_63 */ + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + gmx_rx_int_en.s.maxerr = 1; + gmx_rx_int_en.s.carext = 1; + gmx_rx_int_en.s.minerr = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* Skipping gmx_rx_int_en.s.reserved_20_63 */ + gmx_rx_int_en.s.pause_drp = 1; + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /* Skipping gmx_rx_int_en.s.reserved_6_6 */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + /* Skipping gmx_rx_int_en.s.reserved_2_2 */ + gmx_rx_int_en.s.carext = 1; + /* Skipping gmx_rx_int_en.s.reserved_0_0 */ + } + if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { + /* Skipping gmx_rx_int_en.s.reserved_19_63 */ + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + gmx_rx_int_en.s.maxerr = 1; + gmx_rx_int_en.s.carext = 1; + gmx_rx_int_en.s.minerr = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN31XX)) { + /* Skipping gmx_rx_int_en.s.reserved_19_63 */ + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + gmx_rx_int_en.s.maxerr = 1; + gmx_rx_int_en.s.carext = 1; + gmx_rx_int_en.s.minerr = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { + /* Skipping gmx_rx_int_en.s.reserved_20_63 */ + gmx_rx_int_en.s.pause_drp = 1; + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + gmx_rx_int_en.s.maxerr = 1; + gmx_rx_int_en.s.carext = 1; + gmx_rx_int_en.s.minerr = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { + /* Skipping gmx_rx_int_en.s.reserved_29_63 */ + gmx_rx_int_en.s.hg2cc = 1; + gmx_rx_int_en.s.hg2fld = 1; + gmx_rx_int_en.s.undat = 1; + gmx_rx_int_en.s.uneop = 1; + gmx_rx_int_en.s.unsop = 1; + gmx_rx_int_en.s.bad_term = 1; + gmx_rx_int_en.s.bad_seq = 0; + gmx_rx_int_en.s.rem_fault = 1; + gmx_rx_int_en.s.loc_fault = 0; + gmx_rx_int_en.s.pause_drp = 1; + /* Skipping gmx_rx_int_en.s.reserved_16_18 */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + /* Skipping gmx_rx_int_en.s.reserved_9_9 */ + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /* Skipping gmx_rx_int_en.s.reserved_5_6 */ + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + /* Skipping gmx_rx_int_en.s.reserved_2_2 */ + gmx_rx_int_en.s.carext = 1; + /* Skipping gmx_rx_int_en.s.reserved_0_0 */ + } + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); +} +/** + * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t + */ +void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block) +{ + union cvmx_pcsx_intx_en_reg pcs_int_en_reg; + cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), + cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); + pcs_int_en_reg.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { + /* Skipping pcs_int_en_reg.s.reserved_12_63 */ + /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ + pcs_int_en_reg.s.sync_bad_en = 1; + pcs_int_en_reg.s.an_bad_en = 1; + pcs_int_en_reg.s.rxlock_en = 1; + pcs_int_en_reg.s.rxbad_en = 1; + /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ + pcs_int_en_reg.s.txbad_en = 1; + pcs_int_en_reg.s.txfifo_en = 1; + pcs_int_en_reg.s.txfifu_en = 1; + pcs_int_en_reg.s.an_err_en = 1; + /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ + /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ + } + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { + /* Skipping pcs_int_en_reg.s.reserved_12_63 */ + /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ + pcs_int_en_reg.s.sync_bad_en = 1; + pcs_int_en_reg.s.an_bad_en = 1; + pcs_int_en_reg.s.rxlock_en = 1; + pcs_int_en_reg.s.rxbad_en = 1; + /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ + pcs_int_en_reg.s.txbad_en = 1; + pcs_int_en_reg.s.txfifo_en = 1; + pcs_int_en_reg.s.txfifu_en = 1; + pcs_int_en_reg.s.an_err_en = 1; + /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ + /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ + } + cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); +} +/** + * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t + */ +void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index) +{ + union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; + cvmx_write_csr(CVMX_PCSXX_INT_REG(index), + cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); + pcsx_int_en_reg.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { + /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ + pcsx_int_en_reg.s.algnlos_en = 1; + pcsx_int_en_reg.s.synlos_en = 1; + pcsx_int_en_reg.s.bitlckls_en = 1; + pcsx_int_en_reg.s.rxsynbad_en = 1; + pcsx_int_en_reg.s.rxbad_en = 1; + pcsx_int_en_reg.s.txflt_en = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { + /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ + pcsx_int_en_reg.s.algnlos_en = 1; + pcsx_int_en_reg.s.synlos_en = 1; + pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */ + pcsx_int_en_reg.s.rxsynbad_en = 1; + pcsx_int_en_reg.s.rxbad_en = 1; + pcsx_int_en_reg.s.txflt_en = 1; + } + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); +} + +/** + * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t + */ +void __cvmx_interrupt_spxx_int_msk_enable(int index) +{ + union cvmx_spxx_int_msk spx_int_msk; + cvmx_write_csr(CVMX_SPXX_INT_REG(index), + cvmx_read_csr(CVMX_SPXX_INT_REG(index))); + spx_int_msk.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { + /* Skipping spx_int_msk.s.reserved_12_63 */ + spx_int_msk.s.calerr = 1; + spx_int_msk.s.syncerr = 1; + spx_int_msk.s.diperr = 1; + spx_int_msk.s.tpaovr = 1; + spx_int_msk.s.rsverr = 1; + spx_int_msk.s.drwnng = 1; + spx_int_msk.s.clserr = 1; + spx_int_msk.s.spiovr = 1; + /* Skipping spx_int_msk.s.reserved_2_3 */ + spx_int_msk.s.abnorm = 1; + spx_int_msk.s.prtnxa = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { + /* Skipping spx_int_msk.s.reserved_12_63 */ + spx_int_msk.s.calerr = 1; + spx_int_msk.s.syncerr = 1; + spx_int_msk.s.diperr = 1; + spx_int_msk.s.tpaovr = 1; + spx_int_msk.s.rsverr = 1; + spx_int_msk.s.drwnng = 1; + spx_int_msk.s.clserr = 1; + spx_int_msk.s.spiovr = 1; + /* Skipping spx_int_msk.s.reserved_2_3 */ + spx_int_msk.s.abnorm = 1; + spx_int_msk.s.prtnxa = 1; + } + cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); +} +/** + * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t + */ +void __cvmx_interrupt_stxx_int_msk_enable(int index) +{ + union cvmx_stxx_int_msk stx_int_msk; + cvmx_write_csr(CVMX_STXX_INT_REG(index), + cvmx_read_csr(CVMX_STXX_INT_REG(index))); + stx_int_msk.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { + /* Skipping stx_int_msk.s.reserved_8_63 */ + stx_int_msk.s.frmerr = 1; + stx_int_msk.s.unxfrm = 1; + stx_int_msk.s.nosync = 1; + stx_int_msk.s.diperr = 1; + stx_int_msk.s.datovr = 1; + stx_int_msk.s.ovrbst = 1; + stx_int_msk.s.calpar1 = 1; + stx_int_msk.s.calpar0 = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { + /* Skipping stx_int_msk.s.reserved_8_63 */ + stx_int_msk.s.frmerr = 1; + stx_int_msk.s.unxfrm = 1; + stx_int_msk.s.nosync = 1; + stx_int_msk.s.diperr = 1; + stx_int_msk.s.datovr = 1; + stx_int_msk.s.ovrbst = 1; + stx_int_msk.s.calpar1 = 1; + stx_int_msk.s.calpar0 = 1; + } + cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c new file mode 100644 index 000000000000..bea7538ea4e9 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c @@ -0,0 +1,140 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Utility functions to decode Octeon's RSL_INT_BLOCKS + * interrupts into error messages. + */ + +#include + +#include +#include + +#ifndef PRINT_ERROR +#define PRINT_ERROR(format, ...) +#endif + +void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block); + +/** + * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and + * CN58XX. + * + * @block: Interface to enable 0-1 + */ +void __cvmx_interrupt_asxx_enable(int block) +{ + int mask; + union cvmx_asxx_int_en csr; + /* + * CN38XX and CN58XX have two interfaces with 4 ports per + * interface. All other chips have a max of 3 ports on + * interface 0 + */ + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) + mask = 0xf; /* Set enables for 4 ports */ + else + mask = 0x7; /* Set enables for 3 ports */ + + /* Enable interface interrupts */ + csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); + csr.s.txpsh = mask; + csr.s.txpop = mask; + csr.s.ovrflw = mask; + cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); +} +/** + * Enable GMX error reporting for the supplied interface + * + * @interface: Interface to enable + */ +void __cvmx_interrupt_gmxx_enable(int interface) +{ + union cvmx_gmxx_inf_mode mode; + union cvmx_gmxx_tx_int_en gmx_tx_int_en; + int num_ports; + int index; + + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { + if (mode.s.en) { + switch (mode.cn56xx.mode) { + case 1: /* XAUI */ + num_ports = 1; + break; + case 2: /* SGMII */ + case 3: /* PICMG */ + num_ports = 4; + break; + default: /* Disabled */ + num_ports = 0; + break; + } + } else + num_ports = 0; + } else { + if (mode.s.en) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + /* + * SPI on CN38XX and CN58XX report all + * errors through port 0. RGMII needs + * to check all 4 ports + */ + if (mode.s.type) + num_ports = 1; + else + num_ports = 4; + } else { + /* + * CN30XX, CN31XX, and CN50XX have two + * or three ports. GMII and MII has 2, + * RGMII has three + */ + if (mode.s.type) + num_ports = 2; + else + num_ports = 3; + } + } else + num_ports = 0; + } + + gmx_tx_int_en.u64 = 0; + if (num_ports) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) + gmx_tx_int_en.s.ncb_nxa = 1; + gmx_tx_int_en.s.pko_nxa = 1; + } + gmx_tx_int_en.s.undflw = (1 << num_ports) - 1; + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); + for (index = 0; index < num_ports; index++) + __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface); +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c new file mode 100644 index 000000000000..f557084b1092 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c @@ -0,0 +1,506 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Support library for the hardware Packet Output unit. + */ + +#include + +#include +#include +#include + +/** + * Internal state of packet output + */ + +/** + * Call before any other calls to initialize the packet + * output system. This does chip global config, and should only be + * done by one core. + */ + +void cvmx_pko_initialize_global(void) +{ + int i; + uint64_t priority = 8; + union cvmx_pko_reg_cmd_buf config; + + /* + * Set the size of the PKO command buffers to an odd number of + * 64bit words. This allows the normal two word send to stay + * aligned and never span a comamnd word buffer. + */ + config.u64 = 0; + config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL; + config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1; + + cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); + + for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) + cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, + &priority); + + /* + * If we aren't using all of the queues optimize PKO's + * internal memory. + */ + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX)) { + int num_interfaces = cvmx_helper_get_number_of_interfaces(); + int last_port = + cvmx_helper_get_last_ipd_port(num_interfaces - 1); + int max_queues = + cvmx_pko_get_base_queue(last_port) + + cvmx_pko_get_num_queues(last_port); + if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { + if (max_queues <= 32) + cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); + else if (max_queues <= 64) + cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); + } else { + if (max_queues <= 64) + cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); + else if (max_queues <= 128) + cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); + } + } +} + +/** + * This function does per-core initialization required by the PKO routines. + * This must be called on all cores that will do packet output, and must + * be called after the FPA has been initialized and filled with pages. + * + * Returns 0 on success + * !0 on failure + */ +int cvmx_pko_initialize_local(void) +{ + /* Nothing to do */ + return 0; +} + +/** + * Enables the packet output hardware. It must already be + * configured. + */ +void cvmx_pko_enable(void) +{ + union cvmx_pko_reg_flags flags; + + flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); + if (flags.s.ena_pko) + cvmx_dprintf + ("Warning: Enabling PKO when PKO already enabled.\n"); + + flags.s.ena_dwb = 1; + flags.s.ena_pko = 1; + /* + * always enable big endian for 3-word command. Does nothing + * for 2-word. + */ + flags.s.store_be = 1; + cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); +} + +/** + * Disables the packet output. Does not affect any configuration. + */ +void cvmx_pko_disable(void) +{ + union cvmx_pko_reg_flags pko_reg_flags; + pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); + pko_reg_flags.s.ena_pko = 0; + cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); +} + + +/** + * Reset the packet output. + */ +static void __cvmx_pko_reset(void) +{ + union cvmx_pko_reg_flags pko_reg_flags; + pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); + pko_reg_flags.s.reset = 1; + cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); +} + +/** + * Shutdown and free resources required by packet output. + */ +void cvmx_pko_shutdown(void) +{ + union cvmx_pko_mem_queue_ptrs config; + int queue; + + cvmx_pko_disable(); + + for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) { + config.u64 = 0; + config.s.tail = 1; + config.s.index = 0; + config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID; + config.s.queue = queue & 0x7f; + config.s.qos_mask = 0; + config.s.buf_ptr = 0; + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { + union cvmx_pko_reg_queue_ptrs1 config1; + config1.u64 = 0; + config1.s.qid7 = queue >> 7; + cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); + } + cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); + cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue)); + } + __cvmx_pko_reset(); +} + +/** + * Configure a output port and the associated queues for use. + * + * @port: Port to configure. + * @base_queue: First queue number to associate with this port. + * @num_queues: Number of queues to associate with this port + * @priority: Array of priority levels for each queue. Values are + * allowed to be 0-8. A value of 8 get 8 times the traffic + * of a value of 1. A value of 0 indicates that no rounds + * will be participated in. These priorities can be changed + * on the fly while the pko is enabled. A priority of 9 + * indicates that static priority should be used. If static + * priority is used all queues with static priority must be + * contiguous starting at the base_queue, and lower numbered + * queues have higher priority than higher numbered queues. + * There must be num_queues elements in the array. + */ +cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, + uint64_t num_queues, + const uint64_t priority[]) +{ + cvmx_pko_status_t result_code; + uint64_t queue; + union cvmx_pko_mem_queue_ptrs config; + union cvmx_pko_reg_queue_ptrs1 config1; + int static_priority_base = -1; + int static_priority_end = -1; + + if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) + && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) { + cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", + (unsigned long long)port); + return CVMX_PKO_INVALID_PORT; + } + + if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES) { + cvmx_dprintf + ("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n", + (unsigned long long)(base_queue + num_queues)); + return CVMX_PKO_INVALID_QUEUE; + } + + if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) { + /* + * Validate the static queue priority setup and set + * static_priority_base and static_priority_end + * accordingly. + */ + for (queue = 0; queue < num_queues; queue++) { + /* Find first queue of static priority */ + if (static_priority_base == -1 + && priority[queue] == + CVMX_PKO_QUEUE_STATIC_PRIORITY) + static_priority_base = queue; + /* Find last queue of static priority */ + if (static_priority_base != -1 + && static_priority_end == -1 + && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY + && queue) + static_priority_end = queue - 1; + else if (static_priority_base != -1 + && static_priority_end == -1 + && queue == num_queues - 1) + /* all queues are static priority */ + static_priority_end = queue; + /* + * Check to make sure all static priority + * queues are contiguous. Also catches some + * cases of static priorites not starting at + * queue 0. + */ + if (static_priority_end != -1 + && (int)queue > static_priority_end + && priority[queue] == + CVMX_PKO_QUEUE_STATIC_PRIORITY) { + cvmx_dprintf("ERROR: cvmx_pko_config_port: " + "Static priority queues aren't " + "contiguous or don't start at " + "base queue. q: %d, eq: %d\n", + (int)queue, static_priority_end); + return CVMX_PKO_INVALID_PRIORITY; + } + } + if (static_priority_base > 0) { + cvmx_dprintf("ERROR: cvmx_pko_config_port: Static " + "priority queues don't start at base " + "queue. sq: %d\n", + static_priority_base); + return CVMX_PKO_INVALID_PRIORITY; + } +#if 0 + cvmx_dprintf("Port %d: Static priority queue base: %d, " + "end: %d\n", port, + static_priority_base, static_priority_end); +#endif + } + /* + * At this point, static_priority_base and static_priority_end + * are either both -1, or are valid start/end queue + * numbers. + */ + + result_code = CVMX_PKO_SUCCESS; + +#ifdef PKO_DEBUG + cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues, + CVMX_PKO_QUEUES_PER_PORT_INTERFACE0, + CVMX_PKO_QUEUES_PER_PORT_INTERFACE1); +#endif + + for (queue = 0; queue < num_queues; queue++) { + uint64_t *buf_ptr = NULL; + + config1.u64 = 0; + config1.s.idx3 = queue >> 3; + config1.s.qid7 = (base_queue + queue) >> 7; + + config.u64 = 0; + config.s.tail = queue == (num_queues - 1); + config.s.index = queue; + config.s.port = port; + config.s.queue = base_queue + queue; + + if (!cvmx_octeon_is_pass1()) { + config.s.static_p = static_priority_base >= 0; + config.s.static_q = (int)queue <= static_priority_end; + config.s.s_tail = (int)queue == static_priority_end; + } + /* + * Convert the priority into an enable bit field. Try + * to space the bits out evenly so the packet don't + * get grouped up + */ + switch ((int)priority[queue]) { + case 0: + config.s.qos_mask = 0x00; + break; + case 1: + config.s.qos_mask = 0x01; + break; + case 2: + config.s.qos_mask = 0x11; + break; + case 3: + config.s.qos_mask = 0x49; + break; + case 4: + config.s.qos_mask = 0x55; + break; + case 5: + config.s.qos_mask = 0x57; + break; + case 6: + config.s.qos_mask = 0x77; + break; + case 7: + config.s.qos_mask = 0x7f; + break; + case 8: + config.s.qos_mask = 0xff; + break; + case CVMX_PKO_QUEUE_STATIC_PRIORITY: + /* Pass 1 will fall through to the error case */ + if (!cvmx_octeon_is_pass1()) { + config.s.qos_mask = 0xff; + break; + } + default: + cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid " + "priority %llu\n", + (unsigned long long)priority[queue]); + config.s.qos_mask = 0xff; + result_code = CVMX_PKO_INVALID_PRIORITY; + break; + } + + if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) { + cvmx_cmd_queue_result_t cmd_res = + cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO + (base_queue + queue), + CVMX_PKO_MAX_QUEUE_DEPTH, + CVMX_FPA_OUTPUT_BUFFER_POOL, + CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE + - + CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST + * 8); + if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) { + switch (cmd_res) { + case CVMX_CMD_QUEUE_NO_MEMORY: + cvmx_dprintf("ERROR: " + "cvmx_pko_config_port: " + "Unable to allocate " + "output buffer.\n"); + return CVMX_PKO_NO_MEMORY; + case CVMX_CMD_QUEUE_ALREADY_SETUP: + cvmx_dprintf + ("ERROR: cvmx_pko_config_port: Port already setup.\n"); + return CVMX_PKO_PORT_ALREADY_SETUP; + case CVMX_CMD_QUEUE_INVALID_PARAM: + default: + cvmx_dprintf + ("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n"); + return CVMX_PKO_CMD_QUEUE_INIT_ERROR; + } + } + + buf_ptr = + (uint64_t *) + cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO + (base_queue + queue)); + config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr); + } else + config.s.buf_ptr = 0; + + CVMX_SYNCWS; + + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) + cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); + cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); + } + + return result_code; +} + +#ifdef PKO_DEBUG +/** + * Show map of ports -> queues for different cores. + */ +void cvmx_pko_show_queue_map() +{ + int core, port; + int pko_output_ports = 36; + + cvmx_dprintf("port"); + for (port = 0; port < pko_output_ports; port++) + cvmx_dprintf("%3d ", port); + cvmx_dprintf("\n"); + + for (core = 0; core < CVMX_MAX_CORES; core++) { + cvmx_dprintf("\n%2d: ", core); + for (port = 0; port < pko_output_ports; port++) { + cvmx_dprintf("%3d ", + cvmx_pko_get_base_queue_per_core(port, + core)); + } + } + cvmx_dprintf("\n"); +} +#endif + +/** + * Rate limit a PKO port to a max packets/sec. This function is only + * supported on CN51XX and higher, excluding CN58XX. + * + * @port: Port to rate limit + * @packets_s: Maximum packet/sec + * @burst: Maximum number of packets to burst in a row before rate + * limiting cuts in. + * + * Returns Zero on success, negative on failure + */ +int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst) +{ + union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; + union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; + + pko_mem_port_rate0.u64 = 0; + pko_mem_port_rate0.s.pid = port; + pko_mem_port_rate0.s.rate_pkt = + cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16; + /* No cost per word since we are limited by packets/sec, not bits/sec */ + pko_mem_port_rate0.s.rate_word = 0; + + pko_mem_port_rate1.u64 = 0; + pko_mem_port_rate1.s.pid = port; + pko_mem_port_rate1.s.rate_lim = + ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8; + + cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); + cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); + return 0; +} + +/** + * Rate limit a PKO port to a max bits/sec. This function is only + * supported on CN51XX and higher, excluding CN58XX. + * + * @port: Port to rate limit + * @bits_s: PKO rate limit in bits/sec + * @burst: Maximum number of bits to burst before rate + * limiting cuts in. + * + * Returns Zero on success, negative on failure + */ +int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst) +{ + union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; + union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; + uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz; + uint64_t tokens_per_bit = clock_rate * 16 / bits_s; + + pko_mem_port_rate0.u64 = 0; + pko_mem_port_rate0.s.pid = port; + /* + * Each packet has a 12 bytes of interframe gap, an 8 byte + * preamble, and a 4 byte CRC. These are not included in the + * per word count. Multiply by 8 to covert to bits and divide + * by 256 for limit granularity. + */ + pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256; + /* Each 8 byte word has 64bits */ + pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit; + + pko_mem_port_rate1.u64 = 0; + pko_mem_port_rate1.s.pid = port; + pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256; + + cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); + cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); + return 0; +} diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c new file mode 100644 index 000000000000..74afb1710cd9 --- /dev/null +++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c @@ -0,0 +1,667 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Support library for the SPI + */ +#include + +#include + +#include +#include + +#include +#include +#include + +#define INVOKE_CB(function_p, args...) \ + do { \ + if (function_p) { \ + res = function_p(args); \ + if (res) \ + return res; \ + } \ + } while (0) + +#if CVMX_ENABLE_DEBUG_PRINTS +static const char *modes[] = + { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" }; +#endif + +/* Default callbacks, can be overridden + * using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks + */ +static cvmx_spi_callbacks_t cvmx_spi_callbacks = { + .reset_cb = cvmx_spi_reset_cb, + .calendar_setup_cb = cvmx_spi_calendar_setup_cb, + .clock_detect_cb = cvmx_spi_clock_detect_cb, + .training_cb = cvmx_spi_training_cb, + .calendar_sync_cb = cvmx_spi_calendar_sync_cb, + .interface_up_cb = cvmx_spi_interface_up_cb +}; + +/** + * Get current SPI4 initialization callbacks + * + * @callbacks: Pointer to the callbacks structure.to fill + * + * Returns Pointer to cvmx_spi_callbacks_t structure. + */ +void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks) +{ + memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks)); +} + +/** + * Set new SPI4 initialization callbacks + * + * @new_callbacks: Pointer to an updated callbacks structure. + */ +void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks) +{ + memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks)); +} + +/** + * Initialize and start the SPI interface. + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * @num_ports: Number of SPI ports to configure + * + * Returns Zero on success, negative of failure. + */ +int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, + int num_ports) +{ + int res = -1; + + if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) + return res; + + /* Callback to perform SPI4 reset */ + INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); + + /* Callback to perform calendar setup */ + INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode, + num_ports); + + /* Callback to perform clock detection */ + INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); + + /* Callback to perform SPI4 link training */ + INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); + + /* Callback to perform calendar sync */ + INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, + timeout); + + /* Callback to handle interface coming up */ + INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); + + return res; +} + +/** + * This routine restarts the SPI interface after it has lost synchronization + * with its correspondent system. + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * + * Returns Zero on success, negative of failure. + */ +int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout) +{ + int res = -1; + + if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) + return res; + + cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]); + + /* Callback to perform SPI4 reset */ + INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); + + /* NOTE: Calendar setup is not performed during restart */ + /* Refer to cvmx_spi_start_interface() for the full sequence */ + + /* Callback to perform clock detection */ + INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); + + /* Callback to perform SPI4 link training */ + INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); + + /* Callback to perform calendar sync */ + INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, + timeout); + + /* Callback to handle interface coming up */ + INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); + + return res; +} + +/** + * Callback to perform SPI4 reset + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) +{ + union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl; + union cvmx_spxx_clk_ctl spxx_clk_ctl; + union cvmx_spxx_bist_stat spxx_bist_stat; + union cvmx_spxx_int_msk spxx_int_msk; + union cvmx_stxx_int_msk stxx_int_msk; + union cvmx_spxx_trn4_ctl spxx_trn4_ctl; + int index; + uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + + /* Disable SPI error events while we run BIST */ + spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); + cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); + stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); + cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); + + /* Run BIST in the SPI interface */ + cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); + cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); + spxx_clk_ctl.u64 = 0; + spxx_clk_ctl.s.runbist = 1; + cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); + cvmx_wait(10 * MS); + spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface)); + if (spxx_bist_stat.s.stat0) + cvmx_dprintf + ("ERROR SPI%d: BIST failed on receive datapath FIFO\n", + interface); + if (spxx_bist_stat.s.stat1) + cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n", + interface); + if (spxx_bist_stat.s.stat2) + cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n", + interface); + + /* Clear the calendar table after BIST to fix parity errors */ + for (index = 0; index < 32; index++) { + union cvmx_srxx_spi4_calx srxx_spi4_calx; + union cvmx_stxx_spi4_calx stxx_spi4_calx; + + srxx_spi4_calx.u64 = 0; + srxx_spi4_calx.s.oddpar = 1; + cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), + srxx_spi4_calx.u64); + + stxx_spi4_calx.u64 = 0; + stxx_spi4_calx.s.oddpar = 1; + cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), + stxx_spi4_calx.u64); + } + + /* Re enable reporting of error interrupts */ + cvmx_write_csr(CVMX_SPXX_INT_REG(interface), + cvmx_read_csr(CVMX_SPXX_INT_REG(interface))); + cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); + cvmx_write_csr(CVMX_STXX_INT_REG(interface), + cvmx_read_csr(CVMX_STXX_INT_REG(interface))); + cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); + + /* Setup the CLKDLY right in the middle */ + spxx_clk_ctl.u64 = 0; + spxx_clk_ctl.s.seetrn = 0; + spxx_clk_ctl.s.clkdly = 0x10; + spxx_clk_ctl.s.runbist = 0; + spxx_clk_ctl.s.statdrv = 0; + /* This should always be on the opposite edge as statdrv */ + spxx_clk_ctl.s.statrcv = 1; + spxx_clk_ctl.s.sndtrn = 0; + spxx_clk_ctl.s.drptrn = 0; + spxx_clk_ctl.s.rcvtrn = 0; + spxx_clk_ctl.s.srxdlck = 0; + cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); + cvmx_wait(100 * MS); + + /* Reset SRX0 DLL */ + spxx_clk_ctl.s.srxdlck = 1; + cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); + + /* Waiting for Inf0 Spi4 RX DLL to lock */ + cvmx_wait(100 * MS); + + /* Enable dynamic alignment */ + spxx_trn4_ctl.s.trntest = 0; + spxx_trn4_ctl.s.jitter = 1; + spxx_trn4_ctl.s.clr_boot = 1; + spxx_trn4_ctl.s.set_boot = 0; + if (OCTEON_IS_MODEL(OCTEON_CN58XX)) + spxx_trn4_ctl.s.maxdist = 3; + else + spxx_trn4_ctl.s.maxdist = 8; + spxx_trn4_ctl.s.macro_en = 1; + spxx_trn4_ctl.s.mux_en = 1; + cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); + + spxx_dbg_deskew_ctl.u64 = 0; + cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface), + spxx_dbg_deskew_ctl.u64); + + return 0; +} + +/** + * Callback to setup calendar and miscellaneous settings before clock detection + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @num_ports: Number of ports to configure on SPI + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, + int num_ports) +{ + int port; + int index; + if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { + union cvmx_srxx_com_ctl srxx_com_ctl; + union cvmx_srxx_spi4_stat srxx_spi4_stat; + + /* SRX0 number of Ports */ + srxx_com_ctl.u64 = 0; + srxx_com_ctl.s.prts = num_ports - 1; + srxx_com_ctl.s.st_en = 0; + srxx_com_ctl.s.inf_en = 0; + cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); + + /* SRX0 Calendar Table. This round robbins through all ports */ + port = 0; + index = 0; + while (port < num_ports) { + union cvmx_srxx_spi4_calx srxx_spi4_calx; + srxx_spi4_calx.u64 = 0; + srxx_spi4_calx.s.prt0 = port++; + srxx_spi4_calx.s.prt1 = port++; + srxx_spi4_calx.s.prt2 = port++; + srxx_spi4_calx.s.prt3 = port++; + srxx_spi4_calx.s.oddpar = + ~(cvmx_dpop(srxx_spi4_calx.u64) & 1); + cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), + srxx_spi4_calx.u64); + index++; + } + srxx_spi4_stat.u64 = 0; + srxx_spi4_stat.s.len = num_ports; + srxx_spi4_stat.s.m = 1; + cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface), + srxx_spi4_stat.u64); + } + + if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { + union cvmx_stxx_arb_ctl stxx_arb_ctl; + union cvmx_gmxx_tx_spi_max gmxx_tx_spi_max; + union cvmx_gmxx_tx_spi_thresh gmxx_tx_spi_thresh; + union cvmx_gmxx_tx_spi_ctl gmxx_tx_spi_ctl; + union cvmx_stxx_spi4_stat stxx_spi4_stat; + union cvmx_stxx_spi4_dat stxx_spi4_dat; + + /* STX0 Config */ + stxx_arb_ctl.u64 = 0; + stxx_arb_ctl.s.igntpa = 0; + stxx_arb_ctl.s.mintrn = 0; + cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64); + + gmxx_tx_spi_max.u64 = 0; + gmxx_tx_spi_max.s.max1 = 8; + gmxx_tx_spi_max.s.max2 = 4; + gmxx_tx_spi_max.s.slice = 0; + cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface), + gmxx_tx_spi_max.u64); + + gmxx_tx_spi_thresh.u64 = 0; + gmxx_tx_spi_thresh.s.thresh = 4; + cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface), + gmxx_tx_spi_thresh.u64); + + gmxx_tx_spi_ctl.u64 = 0; + gmxx_tx_spi_ctl.s.tpa_clr = 0; + gmxx_tx_spi_ctl.s.cont_pkt = 0; + cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface), + gmxx_tx_spi_ctl.u64); + + /* STX0 Training Control */ + stxx_spi4_dat.u64 = 0; + /*Minimum needed by dynamic alignment */ + stxx_spi4_dat.s.alpha = 32; + stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */ + cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), + stxx_spi4_dat.u64); + + /* STX0 Calendar Table. This round robbins through all ports */ + port = 0; + index = 0; + while (port < num_ports) { + union cvmx_stxx_spi4_calx stxx_spi4_calx; + stxx_spi4_calx.u64 = 0; + stxx_spi4_calx.s.prt0 = port++; + stxx_spi4_calx.s.prt1 = port++; + stxx_spi4_calx.s.prt2 = port++; + stxx_spi4_calx.s.prt3 = port++; + stxx_spi4_calx.s.oddpar = + ~(cvmx_dpop(stxx_spi4_calx.u64) & 1); + cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), + stxx_spi4_calx.u64); + index++; + } + stxx_spi4_stat.u64 = 0; + stxx_spi4_stat.s.len = num_ports; + stxx_spi4_stat.s.m = 1; + cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface), + stxx_spi4_stat.u64); + } + + return 0; +} + +/** + * Callback to perform clock detection + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout) +{ + int clock_transitions; + union cvmx_spxx_clk_stat stat; + uint64_t timeout_time; + uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + + /* + * Regardless of operating mode, both Tx and Rx clocks must be + * present for the SPI interface to operate. + */ + cvmx_dprintf("SPI%d: Waiting to see TsClk...\n", interface); + timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; + /* + * Require 100 clock transitions in order to avoid any noise + * in the beginning. + */ + clock_transitions = 100; + do { + stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); + if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) { + /* + * We've seen a clock transition, so decrement + * the number we still need. + */ + clock_transitions--; + cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); + stat.s.s4clk0 = 0; + stat.s.s4clk1 = 0; + } + if (cvmx_get_cycle() > timeout_time) { + cvmx_dprintf("SPI%d: Timeout\n", interface); + return -1; + } + } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0); + + cvmx_dprintf("SPI%d: Waiting to see RsClk...\n", interface); + timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; + /* + * Require 100 clock transitions in order to avoid any noise in the + * beginning. + */ + clock_transitions = 100; + do { + stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); + if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) { + /* + * We've seen a clock transition, so decrement + * the number we still need + */ + clock_transitions--; + cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); + stat.s.d4clk0 = 0; + stat.s.d4clk1 = 0; + } + if (cvmx_get_cycle() > timeout_time) { + cvmx_dprintf("SPI%d: Timeout\n", interface); + return -1; + } + } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0); + + return 0; +} + +/** + * Callback to perform link training + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for link to be trained (in seconds) + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) +{ + union cvmx_spxx_trn4_ctl spxx_trn4_ctl; + union cvmx_spxx_clk_stat stat; + uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; + int rx_training_needed; + + /* SRX0 & STX0 Inf0 Links are configured - begin training */ + union cvmx_spxx_clk_ctl spxx_clk_ctl; + spxx_clk_ctl.u64 = 0; + spxx_clk_ctl.s.seetrn = 0; + spxx_clk_ctl.s.clkdly = 0x10; + spxx_clk_ctl.s.runbist = 0; + spxx_clk_ctl.s.statdrv = 0; + /* This should always be on the opposite edge as statdrv */ + spxx_clk_ctl.s.statrcv = 1; + spxx_clk_ctl.s.sndtrn = 1; + spxx_clk_ctl.s.drptrn = 1; + spxx_clk_ctl.s.rcvtrn = 1; + spxx_clk_ctl.s.srxdlck = 1; + cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); + cvmx_wait(1000 * MS); + + /* SRX0 clear the boot bit */ + spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface)); + spxx_trn4_ctl.s.clr_boot = 1; + cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); + + /* Wait for the training sequence to complete */ + cvmx_dprintf("SPI%d: Waiting for training\n", interface); + cvmx_wait(1000 * MS); + /* Wait a really long time here */ + timeout_time = cvmx_get_cycle() + 1000ull * MS * 600; + /* + * The HRM says we must wait for 34 + 16 * MAXDIST training sequences. + * We'll be pessimistic and wait for a lot more. + */ + rx_training_needed = 500; + do { + stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); + if (stat.s.srxtrn && rx_training_needed) { + rx_training_needed--; + cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); + stat.s.srxtrn = 0; + } + if (cvmx_get_cycle() > timeout_time) { + cvmx_dprintf("SPI%d: Timeout\n", interface); + return -1; + } + } while (stat.s.srxtrn == 0); + + return 0; +} + +/** + * Callback to perform calendar data synchronization + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for calendar data in seconds + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout) +{ + uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; + if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { + /* SRX0 interface should be good, send calendar data */ + union cvmx_srxx_com_ctl srxx_com_ctl; + cvmx_dprintf + ("SPI%d: Rx is synchronized, start sending calendar data\n", + interface); + srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); + srxx_com_ctl.s.inf_en = 1; + srxx_com_ctl.s.st_en = 1; + cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); + } + + if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { + /* STX0 has achieved sync */ + /* The corespondant board should be sending calendar data */ + /* Enable the STX0 STAT receiver. */ + union cvmx_spxx_clk_stat stat; + uint64_t timeout_time; + union cvmx_stxx_com_ctl stxx_com_ctl; + stxx_com_ctl.u64 = 0; + stxx_com_ctl.s.st_en = 1; + cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); + + /* Waiting for calendar sync on STX0 STAT */ + cvmx_dprintf("SPI%d: Waiting to sync on STX[%d] STAT\n", + interface, interface); + timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; + /* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */ + do { + stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); + if (cvmx_get_cycle() > timeout_time) { + cvmx_dprintf("SPI%d: Timeout\n", interface); + return -1; + } + } while (stat.s.stxcal == 0); + } + + return 0; +} + +/** + * Callback to handle interface up + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode) +{ + union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min; + union cvmx_gmxx_rxx_frm_max gmxx_rxx_frm_max; + union cvmx_gmxx_rxx_jabber gmxx_rxx_jabber; + + if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { + union cvmx_srxx_com_ctl srxx_com_ctl; + srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); + srxx_com_ctl.s.inf_en = 1; + cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); + cvmx_dprintf("SPI%d: Rx is now up\n", interface); + } + + if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { + union cvmx_stxx_com_ctl stxx_com_ctl; + stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface)); + stxx_com_ctl.s.inf_en = 1; + cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); + cvmx_dprintf("SPI%d: Tx is now up\n", interface); + } + + gmxx_rxx_frm_min.u64 = 0; + gmxx_rxx_frm_min.s.len = 64; + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface), + gmxx_rxx_frm_min.u64); + gmxx_rxx_frm_max.u64 = 0; + gmxx_rxx_frm_max.s.len = 64 * 1024 - 4; + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface), + gmxx_rxx_frm_max.u64); + gmxx_rxx_jabber.u64 = 0; + gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4; + cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64); + + return 0; +} diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h new file mode 100644 index 000000000000..3c74d826e2e6 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-address.h @@ -0,0 +1,274 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2009 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * Typedefs and defines for working with Octeon physical addresses. + * + */ +#ifndef __CVMX_ADDRESS_H__ +#define __CVMX_ADDRESS_H__ + +#if 0 +typedef enum { + CVMX_MIPS_SPACE_XKSEG = 3LL, + CVMX_MIPS_SPACE_XKPHYS = 2LL, + CVMX_MIPS_SPACE_XSSEG = 1LL, + CVMX_MIPS_SPACE_XUSEG = 0LL +} cvmx_mips_space_t; +#endif + +typedef enum { + CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, + CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, + CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, + CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL +} cvmx_mips_xkseg_space_t; + +/* decodes <14:13> of a kseg3 window address */ +typedef enum { + CVMX_ADD_WIN_SCR = 0L, + /* see cvmx_add_win_dma_dec_t for further decode */ + CVMX_ADD_WIN_DMA = 1L, + CVMX_ADD_WIN_UNUSED = 2L, + CVMX_ADD_WIN_UNUSED2 = 3L +} cvmx_add_win_dec_t; + +/* decode within DMA space */ +typedef enum { + /* + * Add store data to the write buffer entry, allocating it if + * necessary. + */ + CVMX_ADD_WIN_DMA_ADD = 0L, + /* send out the write buffer entry to DRAM */ + CVMX_ADD_WIN_DMA_SENDMEM = 1L, + /* store data must be normal DRAM memory space address in this case */ + /* send out the write buffer entry as an IOBDMA command */ + CVMX_ADD_WIN_DMA_SENDDMA = 2L, + /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ + /* send out the write buffer entry as an IO write */ + CVMX_ADD_WIN_DMA_SENDIO = 3L, + /* store data must be normal IO space address in this case */ + /* send out a single-tick command on the NCB bus */ + CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, + /* no write buffer data needed/used */ +} cvmx_add_win_dma_dec_t; + +/* + * Physical Address Decode + * + * Octeon-I HW never interprets this X (<39:36> reserved + * for future expansion), software should set to 0. + * + * - 0x0 XXX0 0000 0000 to DRAM Cached + * - 0x0 XXX0 0FFF FFFF + * + * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 + * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) + * + * - 0x0 XXX0 2000 0000 to DRAM Cached + * - 0x0 XXXF FFFF FFFF + * + * - 0x1 00X0 0000 0000 to Boot Bus Uncached + * - 0x1 00XF FFFF FFFF + * + * - 0x1 01X0 0000 0000 to Other NCB Uncached + * - 0x1 FFXF FFFF FFFF devices + * + * Decode of all Octeon addresses + */ +typedef union { + + uint64_t u64; + /* mapped or unmapped virtual address */ + struct { + uint64_t R:2; + uint64_t offset:62; + } sva; + + /* mapped USEG virtual addresses (typically) */ + struct { + uint64_t zeroes:33; + uint64_t offset:31; + } suseg; + + /* mapped or unmapped virtual address */ + struct { + uint64_t ones:33; + uint64_t sp:2; + uint64_t offset:29; + } sxkseg; + + /* + * physical address accessed through xkphys unmapped virtual + * address. + */ + struct { + uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ + uint64_t cca:3; /* ignored by octeon */ + uint64_t mbz:10; + uint64_t pa:49; /* physical address */ + } sxkphys; + + /* physical address */ + struct { + uint64_t mbz:15; + /* if set, the address is uncached and resides on MCB bus */ + uint64_t is_io:1; + /* + * the hardware ignores this field when is_io==0, else + * device ID. + */ + uint64_t did:8; + /* the hardware ignores <39:36> in Octeon I */ + uint64_t unaddr:4; + uint64_t offset:36; + } sphys; + + /* physical mem address */ + struct { + /* techically, <47:40> are dont-cares */ + uint64_t zeroes:24; + /* the hardware ignores <39:36> in Octeon I */ + uint64_t unaddr:4; + uint64_t offset:36; + } smem; + + /* physical IO address */ + struct { + uint64_t mem_region:2; + uint64_t mbz:13; + /* 1 in this case */ + uint64_t is_io:1; + /* + * The hardware ignores this field when is_io==0, else + * device ID. + */ + uint64_t did:8; + /* the hardware ignores <39:36> in Octeon I */ + uint64_t unaddr:4; + uint64_t offset:36; + } sio; + + /* + * Scratchpad virtual address - accessed through a window at + * the end of kseg3 + */ + struct { + uint64_t ones:49; + /* CVMX_ADD_WIN_SCR (0) in this case */ + cvmx_add_win_dec_t csrdec:2; + uint64_t addr:13; + } sscr; + + /* there should only be stores to IOBDMA space, no loads */ + /* + * IOBDMA virtual address - accessed through a window at the + * end of kseg3 + */ + struct { + uint64_t ones:49; + uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */ + uint64_t unused2:3; + uint64_t type:3; + uint64_t addr:7; + } sdma; + + struct { + uint64_t didspace:24; + uint64_t unused:40; + } sfilldidspace; + +} cvmx_addr_t; + +/* These macros for used by 32 bit applications */ + +#define CVMX_MIPS32_SPACE_KSEG0 1l +#define CVMX_ADD_SEG32(segment, add) \ + (((int32_t)segment << 31) | (int32_t)(add)) + +/* + * Currently all IOs are performed using XKPHYS addressing. Linux uses + * the CvmMemCtl register to enable XKPHYS addressing to IO space from + * user mode. Future OSes may need to change the upper bits of IO + * addresses. The following define controls the upper two bits for all + * IO addresses generated by the simple executive library. + */ +#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS + +/* These macros simplify the process of creating common IO addresses */ +#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) +#ifndef CVMX_ADD_IO_SEG +#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) +#endif +#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) +#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) +#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid)) + + /* from include/ncb_rsl_id.v */ +#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ +#define CVMX_OCT_DID_GMX0 1ULL +#define CVMX_OCT_DID_GMX1 2ULL +#define CVMX_OCT_DID_PCI 3ULL +#define CVMX_OCT_DID_KEY 4ULL +#define CVMX_OCT_DID_FPA 5ULL +#define CVMX_OCT_DID_DFA 6ULL +#define CVMX_OCT_DID_ZIP 7ULL +#define CVMX_OCT_DID_RNG 8ULL +#define CVMX_OCT_DID_IPD 9ULL +#define CVMX_OCT_DID_PKT 10ULL +#define CVMX_OCT_DID_TIM 11ULL +#define CVMX_OCT_DID_TAG 12ULL + /* the rest are not on the IO bus */ +#define CVMX_OCT_DID_L2C 16ULL +#define CVMX_OCT_DID_LMC 17ULL +#define CVMX_OCT_DID_SPX0 18ULL +#define CVMX_OCT_DID_SPX1 19ULL +#define CVMX_OCT_DID_PIP 20ULL +#define CVMX_OCT_DID_ASX0 22ULL +#define CVMX_OCT_DID_ASX1 23ULL +#define CVMX_OCT_DID_IOB 30ULL + +#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) +#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) +#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) +#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) +#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) +#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) +#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) +#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) +#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) +#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) +#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) +#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) +#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) +#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) +#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) +#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) +#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) + +#endif /* __CVMX_ADDRESS_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h new file mode 100644 index 000000000000..91415a85e8d2 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h @@ -0,0 +1,475 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_ASXX_DEFS_H__ +#define __CVMX_ASXX_DEFS_H__ + +#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_INT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_PRT_LOOP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_BYPASS(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_COMP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_DATA_DRV(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_SETTING(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_PRT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_MSK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_POWOK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_SIG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_COMP_BYP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_PRT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_asxx_gmii_rx_clk_set { + uint64_t u64; + struct cvmx_asxx_gmii_rx_clk_set_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; + struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; + struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; +}; + +union cvmx_asxx_gmii_rx_dat_set { + uint64_t u64; + struct cvmx_asxx_gmii_rx_dat_set_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; + struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; + struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; +}; + +union cvmx_asxx_int_en { + uint64_t u64; + struct cvmx_asxx_int_en_s { + uint64_t reserved_12_63:52; + uint64_t txpsh:4; + uint64_t txpop:4; + uint64_t ovrflw:4; + } s; + struct cvmx_asxx_int_en_cn30xx { + uint64_t reserved_11_63:53; + uint64_t txpsh:3; + uint64_t reserved_7_7:1; + uint64_t txpop:3; + uint64_t reserved_3_3:1; + uint64_t ovrflw:3; + } cn30xx; + struct cvmx_asxx_int_en_cn30xx cn31xx; + struct cvmx_asxx_int_en_s cn38xx; + struct cvmx_asxx_int_en_s cn38xxp2; + struct cvmx_asxx_int_en_cn30xx cn50xx; + struct cvmx_asxx_int_en_s cn58xx; + struct cvmx_asxx_int_en_s cn58xxp1; +}; + +union cvmx_asxx_int_reg { + uint64_t u64; + struct cvmx_asxx_int_reg_s { + uint64_t reserved_12_63:52; + uint64_t txpsh:4; + uint64_t txpop:4; + uint64_t ovrflw:4; + } s; + struct cvmx_asxx_int_reg_cn30xx { + uint64_t reserved_11_63:53; + uint64_t txpsh:3; + uint64_t reserved_7_7:1; + uint64_t txpop:3; + uint64_t reserved_3_3:1; + uint64_t ovrflw:3; + } cn30xx; + struct cvmx_asxx_int_reg_cn30xx cn31xx; + struct cvmx_asxx_int_reg_s cn38xx; + struct cvmx_asxx_int_reg_s cn38xxp2; + struct cvmx_asxx_int_reg_cn30xx cn50xx; + struct cvmx_asxx_int_reg_s cn58xx; + struct cvmx_asxx_int_reg_s cn58xxp1; +}; + +union cvmx_asxx_mii_rx_dat_set { + uint64_t u64; + struct cvmx_asxx_mii_rx_dat_set_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_mii_rx_dat_set_s cn30xx; + struct cvmx_asxx_mii_rx_dat_set_s cn50xx; +}; + +union cvmx_asxx_prt_loop { + uint64_t u64; + struct cvmx_asxx_prt_loop_s { + uint64_t reserved_8_63:56; + uint64_t ext_loop:4; + uint64_t int_loop:4; + } s; + struct cvmx_asxx_prt_loop_cn30xx { + uint64_t reserved_7_63:57; + uint64_t ext_loop:3; + uint64_t reserved_3_3:1; + uint64_t int_loop:3; + } cn30xx; + struct cvmx_asxx_prt_loop_cn30xx cn31xx; + struct cvmx_asxx_prt_loop_s cn38xx; + struct cvmx_asxx_prt_loop_s cn38xxp2; + struct cvmx_asxx_prt_loop_cn30xx cn50xx; + struct cvmx_asxx_prt_loop_s cn58xx; + struct cvmx_asxx_prt_loop_s cn58xxp1; +}; + +union cvmx_asxx_rld_bypass { + uint64_t u64; + struct cvmx_asxx_rld_bypass_s { + uint64_t reserved_1_63:63; + uint64_t bypass:1; + } s; + struct cvmx_asxx_rld_bypass_s cn38xx; + struct cvmx_asxx_rld_bypass_s cn38xxp2; + struct cvmx_asxx_rld_bypass_s cn58xx; + struct cvmx_asxx_rld_bypass_s cn58xxp1; +}; + +union cvmx_asxx_rld_bypass_setting { + uint64_t u64; + struct cvmx_asxx_rld_bypass_setting_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_rld_bypass_setting_s cn38xx; + struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; + struct cvmx_asxx_rld_bypass_setting_s cn58xx; + struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; +}; + +union cvmx_asxx_rld_comp { + uint64_t u64; + struct cvmx_asxx_rld_comp_s { + uint64_t reserved_9_63:55; + uint64_t pctl:5; + uint64_t nctl:4; + } s; + struct cvmx_asxx_rld_comp_cn38xx { + uint64_t reserved_8_63:56; + uint64_t pctl:4; + uint64_t nctl:4; + } cn38xx; + struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; + struct cvmx_asxx_rld_comp_s cn58xx; + struct cvmx_asxx_rld_comp_s cn58xxp1; +}; + +union cvmx_asxx_rld_data_drv { + uint64_t u64; + struct cvmx_asxx_rld_data_drv_s { + uint64_t reserved_8_63:56; + uint64_t pctl:4; + uint64_t nctl:4; + } s; + struct cvmx_asxx_rld_data_drv_s cn38xx; + struct cvmx_asxx_rld_data_drv_s cn38xxp2; + struct cvmx_asxx_rld_data_drv_s cn58xx; + struct cvmx_asxx_rld_data_drv_s cn58xxp1; +}; + +union cvmx_asxx_rld_fcram_mode { + uint64_t u64; + struct cvmx_asxx_rld_fcram_mode_s { + uint64_t reserved_1_63:63; + uint64_t mode:1; + } s; + struct cvmx_asxx_rld_fcram_mode_s cn38xx; + struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; +}; + +union cvmx_asxx_rld_nctl_strong { + uint64_t u64; + struct cvmx_asxx_rld_nctl_strong_s { + uint64_t reserved_5_63:59; + uint64_t nctl:5; + } s; + struct cvmx_asxx_rld_nctl_strong_s cn38xx; + struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; + struct cvmx_asxx_rld_nctl_strong_s cn58xx; + struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; +}; + +union cvmx_asxx_rld_nctl_weak { + uint64_t u64; + struct cvmx_asxx_rld_nctl_weak_s { + uint64_t reserved_5_63:59; + uint64_t nctl:5; + } s; + struct cvmx_asxx_rld_nctl_weak_s cn38xx; + struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; + struct cvmx_asxx_rld_nctl_weak_s cn58xx; + struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; +}; + +union cvmx_asxx_rld_pctl_strong { + uint64_t u64; + struct cvmx_asxx_rld_pctl_strong_s { + uint64_t reserved_5_63:59; + uint64_t pctl:5; + } s; + struct cvmx_asxx_rld_pctl_strong_s cn38xx; + struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; + struct cvmx_asxx_rld_pctl_strong_s cn58xx; + struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; +}; + +union cvmx_asxx_rld_pctl_weak { + uint64_t u64; + struct cvmx_asxx_rld_pctl_weak_s { + uint64_t reserved_5_63:59; + uint64_t pctl:5; + } s; + struct cvmx_asxx_rld_pctl_weak_s cn38xx; + struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; + struct cvmx_asxx_rld_pctl_weak_s cn58xx; + struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; +}; + +union cvmx_asxx_rld_setting { + uint64_t u64; + struct cvmx_asxx_rld_setting_s { + uint64_t reserved_13_63:51; + uint64_t dfaset:5; + uint64_t dfalag:1; + uint64_t dfalead:1; + uint64_t dfalock:1; + uint64_t setting:5; + } s; + struct cvmx_asxx_rld_setting_cn38xx { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } cn38xx; + struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; + struct cvmx_asxx_rld_setting_s cn58xx; + struct cvmx_asxx_rld_setting_s cn58xxp1; +}; + +union cvmx_asxx_rx_clk_setx { + uint64_t u64; + struct cvmx_asxx_rx_clk_setx_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_rx_clk_setx_s cn30xx; + struct cvmx_asxx_rx_clk_setx_s cn31xx; + struct cvmx_asxx_rx_clk_setx_s cn38xx; + struct cvmx_asxx_rx_clk_setx_s cn38xxp2; + struct cvmx_asxx_rx_clk_setx_s cn50xx; + struct cvmx_asxx_rx_clk_setx_s cn58xx; + struct cvmx_asxx_rx_clk_setx_s cn58xxp1; +}; + +union cvmx_asxx_rx_prt_en { + uint64_t u64; + struct cvmx_asxx_rx_prt_en_s { + uint64_t reserved_4_63:60; + uint64_t prt_en:4; + } s; + struct cvmx_asxx_rx_prt_en_cn30xx { + uint64_t reserved_3_63:61; + uint64_t prt_en:3; + } cn30xx; + struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; + struct cvmx_asxx_rx_prt_en_s cn38xx; + struct cvmx_asxx_rx_prt_en_s cn38xxp2; + struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; + struct cvmx_asxx_rx_prt_en_s cn58xx; + struct cvmx_asxx_rx_prt_en_s cn58xxp1; +}; + +union cvmx_asxx_rx_wol { + uint64_t u64; + struct cvmx_asxx_rx_wol_s { + uint64_t reserved_2_63:62; + uint64_t status:1; + uint64_t enable:1; + } s; + struct cvmx_asxx_rx_wol_s cn38xx; + struct cvmx_asxx_rx_wol_s cn38xxp2; +}; + +union cvmx_asxx_rx_wol_msk { + uint64_t u64; + struct cvmx_asxx_rx_wol_msk_s { + uint64_t msk:64; + } s; + struct cvmx_asxx_rx_wol_msk_s cn38xx; + struct cvmx_asxx_rx_wol_msk_s cn38xxp2; +}; + +union cvmx_asxx_rx_wol_powok { + uint64_t u64; + struct cvmx_asxx_rx_wol_powok_s { + uint64_t reserved_1_63:63; + uint64_t powerok:1; + } s; + struct cvmx_asxx_rx_wol_powok_s cn38xx; + struct cvmx_asxx_rx_wol_powok_s cn38xxp2; +}; + +union cvmx_asxx_rx_wol_sig { + uint64_t u64; + struct cvmx_asxx_rx_wol_sig_s { + uint64_t reserved_32_63:32; + uint64_t sig:32; + } s; + struct cvmx_asxx_rx_wol_sig_s cn38xx; + struct cvmx_asxx_rx_wol_sig_s cn38xxp2; +}; + +union cvmx_asxx_tx_clk_setx { + uint64_t u64; + struct cvmx_asxx_tx_clk_setx_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_tx_clk_setx_s cn30xx; + struct cvmx_asxx_tx_clk_setx_s cn31xx; + struct cvmx_asxx_tx_clk_setx_s cn38xx; + struct cvmx_asxx_tx_clk_setx_s cn38xxp2; + struct cvmx_asxx_tx_clk_setx_s cn50xx; + struct cvmx_asxx_tx_clk_setx_s cn58xx; + struct cvmx_asxx_tx_clk_setx_s cn58xxp1; +}; + +union cvmx_asxx_tx_comp_byp { + uint64_t u64; + struct cvmx_asxx_tx_comp_byp_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_asxx_tx_comp_byp_cn30xx { + uint64_t reserved_9_63:55; + uint64_t bypass:1; + uint64_t pctl:4; + uint64_t nctl:4; + } cn30xx; + struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; + struct cvmx_asxx_tx_comp_byp_cn38xx { + uint64_t reserved_8_63:56; + uint64_t pctl:4; + uint64_t nctl:4; + } cn38xx; + struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; + struct cvmx_asxx_tx_comp_byp_cn50xx { + uint64_t reserved_17_63:47; + uint64_t bypass:1; + uint64_t reserved_13_15:3; + uint64_t pctl:5; + uint64_t reserved_5_7:3; + uint64_t nctl:5; + } cn50xx; + struct cvmx_asxx_tx_comp_byp_cn58xx { + uint64_t reserved_13_63:51; + uint64_t pctl:5; + uint64_t reserved_5_7:3; + uint64_t nctl:5; + } cn58xx; + struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; +}; + +union cvmx_asxx_tx_hi_waterx { + uint64_t u64; + struct cvmx_asxx_tx_hi_waterx_s { + uint64_t reserved_4_63:60; + uint64_t mark:4; + } s; + struct cvmx_asxx_tx_hi_waterx_cn30xx { + uint64_t reserved_3_63:61; + uint64_t mark:3; + } cn30xx; + struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; + struct cvmx_asxx_tx_hi_waterx_s cn38xx; + struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; + struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; + struct cvmx_asxx_tx_hi_waterx_s cn58xx; + struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; +}; + +union cvmx_asxx_tx_prt_en { + uint64_t u64; + struct cvmx_asxx_tx_prt_en_s { + uint64_t reserved_4_63:60; + uint64_t prt_en:4; + } s; + struct cvmx_asxx_tx_prt_en_cn30xx { + uint64_t reserved_3_63:61; + uint64_t prt_en:3; + } cn30xx; + struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; + struct cvmx_asxx_tx_prt_en_s cn38xx; + struct cvmx_asxx_tx_prt_en_s cn38xxp2; + struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; + struct cvmx_asxx_tx_prt_en_s cn58xx; + struct cvmx_asxx_tx_prt_en_s cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h new file mode 100644 index 000000000000..614653b686a0 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h @@ -0,0 +1,617 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Support functions for managing command queues used for + * various hardware blocks. + * + * The common command queue infrastructure abstracts out the + * software necessary for adding to Octeon's chained queue + * structures. These structures are used for commands to the + * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each + * hardware unit takes commands and CSRs of different types, + * they all use basic linked command buffers to store the + * pending request. In general, users of the CVMX API don't + * call cvmx-cmd-queue functions directly. Instead the hardware + * unit specific wrapper should be used. The wrappers perform + * unit specific validation and CSR writes to submit the + * commands. + * + * Even though most software will never directly interact with + * cvmx-cmd-queue, knowledge of its internal working can help + * in diagnosing performance problems and help with debugging. + * + * Command queue pointers are stored in a global named block + * called "cvmx_cmd_queues". Except for the PKO queues, each + * hardware queue is stored in its own cache line to reduce SMP + * contention on spin locks. The PKO queues are stored such that + * every 16th queue is next to each other in memory. This scheme + * allows for queues being in separate cache lines when there + * are low number of queues per port. With 16 queues per port, + * the first queue for each port is in the same cache area. The + * second queues for each port are in another area, etc. This + * allows software to implement very efficient lockless PKO with + * 16 queues per port using a minimum of cache lines per core. + * All queues for a given core will be isolated in the same + * cache area. + * + * In addition to the memory pointer layout, cvmx-cmd-queue + * provides an optimized fair ll/sc locking mechanism for the + * queues. The lock uses a "ticket / now serving" model to + * maintain fair order on contended locks. In addition, it uses + * predicted locking time to limit cache contention. When a core + * know it must wait in line for a lock, it spins on the + * internal cycle counter to completely eliminate any causes of + * bus traffic. + * + */ + +#ifndef __CVMX_CMD_QUEUE_H__ +#define __CVMX_CMD_QUEUE_H__ + +#include + +#include "cvmx-fpa.h" +/** + * By default we disable the max depth support. Most programs + * don't use it and it slows down the command queue processing + * significantly. + */ +#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH +#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0 +#endif + +/** + * Enumeration representing all hardware blocks that use command + * queues. Each hardware block has up to 65536 sub identifiers for + * multiple command queues. Not all chips support all hardware + * units. + */ +typedef enum { + CVMX_CMD_QUEUE_PKO_BASE = 0x00000, + +#define CVMX_CMD_QUEUE_PKO(queue) \ + ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue)))) + + CVMX_CMD_QUEUE_ZIP = 0x10000, + CVMX_CMD_QUEUE_DFA = 0x20000, + CVMX_CMD_QUEUE_RAID = 0x30000, + CVMX_CMD_QUEUE_DMA_BASE = 0x40000, + +#define CVMX_CMD_QUEUE_DMA(queue) \ + ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue)))) + + CVMX_CMD_QUEUE_END = 0x50000, +} cvmx_cmd_queue_id_t; + +/** + * Command write operations can fail if the command queue needs + * a new buffer and the associated FPA pool is empty. It can also + * fail if the number of queued command words reaches the maximum + * set at initialization. + */ +typedef enum { + CVMX_CMD_QUEUE_SUCCESS = 0, + CVMX_CMD_QUEUE_NO_MEMORY = -1, + CVMX_CMD_QUEUE_FULL = -2, + CVMX_CMD_QUEUE_INVALID_PARAM = -3, + CVMX_CMD_QUEUE_ALREADY_SETUP = -4, +} cvmx_cmd_queue_result_t; + +typedef struct { + /* You have lock when this is your ticket */ + uint8_t now_serving; + uint64_t unused1:24; + /* Maximum outstanding command words */ + uint32_t max_depth; + /* FPA pool buffers come from */ + uint64_t fpa_pool:3; + /* Top of command buffer pointer shifted 7 */ + uint64_t base_ptr_div128:29; + uint64_t unused2:6; + /* FPA buffer size in 64bit words minus 1 */ + uint64_t pool_size_m1:13; + /* Number of commands already used in buffer */ + uint64_t index:13; +} __cvmx_cmd_queue_state_t; + +/** + * This structure contains the global state of all command queues. + * It is stored in a bootmem named block and shared by all + * applications running on Octeon. Tickets are stored in a differnet + * cahce line that queue information to reduce the contention on the + * ll/sc used to get a ticket. If this is not the case, the update + * of queue state causes the ll/sc to fail quite often. + */ +typedef struct { + uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256]; + __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256]; +} __cvmx_cmd_queue_all_state_t; + +/** + * Initialize a command queue for use. The initial FPA buffer is + * allocated and the hardware unit is configured to point to the + * new command queue. + * + * @queue_id: Hardware command queue to initialize. + * @max_depth: Maximum outstanding commands that can be queued. + * @fpa_pool: FPA pool the command queues should come from. + * @pool_size: Size of each buffer in the FPA pool (bytes) + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, + int max_depth, int fpa_pool, + int pool_size); + +/** + * Shutdown a queue a free it's command buffers to the FPA. The + * hardware connected to the queue must be stopped before this + * function is called. + * + * @queue_id: Queue to shutdown + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id); + +/** + * Return the number of command words pending in the queue. This + * function may be relatively slow for some hardware units. + * + * @queue_id: Hardware command queue to query + * + * Returns Number of outstanding commands + */ +int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id); + +/** + * Return the command buffer to be written to. The purpose of this + * function is to allow CVMX routine access t othe low level buffer + * for initial hardware setup. User applications should not call this + * function directly. + * + * @queue_id: Command queue to query + * + * Returns Command buffer or NULL on failure + */ +void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id); + +/** + * Get the index into the state arrays for the supplied queue id. + * + * @queue_id: Queue ID to get an index for + * + * Returns Index into the state arrays + */ +static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id) +{ + /* + * Warning: This code currently only works with devices that + * have 256 queues or less. Devices with more than 16 queues + * are laid out in memory to allow cores quick access to + * every 16th queue. This reduces cache thrashing when you are + * running 16 queues per port to support lockless operation. + */ + int unit = queue_id >> 16; + int q = (queue_id >> 4) & 0xf; + int core = queue_id & 0xf; + return unit * 256 + core * 16 + q; +} + +/** + * Lock the supplied queue so nobody else is updating it at the same + * time as us. + * + * @queue_id: Queue ID to lock + * @qptr: Pointer to the queue's global state + */ +static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, + __cvmx_cmd_queue_state_t *qptr) +{ + extern __cvmx_cmd_queue_all_state_t + *__cvmx_cmd_queue_state_ptr; + int tmp; + int my_ticket; + prefetch(qptr); + asm volatile ( + ".set push\n" + ".set noreorder\n" + "1:\n" + /* Atomic add one to ticket_ptr */ + "ll %[my_ticket], %[ticket_ptr]\n" + /* and store the original value */ + "li %[ticket], 1\n" + /* in my_ticket */ + "baddu %[ticket], %[my_ticket]\n" + "sc %[ticket], %[ticket_ptr]\n" + "beqz %[ticket], 1b\n" + " nop\n" + /* Load the current now_serving ticket */ + "lbu %[ticket], %[now_serving]\n" + "2:\n" + /* Jump out if now_serving == my_ticket */ + "beq %[ticket], %[my_ticket], 4f\n" + /* Find out how many tickets are in front of me */ + " subu %[ticket], %[my_ticket], %[ticket]\n" + /* Use tickets in front of me minus one to delay */ + "subu %[ticket], 1\n" + /* Delay will be ((tickets in front)-1)*32 loops */ + "cins %[ticket], %[ticket], 5, 7\n" + "3:\n" + /* Loop here until our ticket might be up */ + "bnez %[ticket], 3b\n" + " subu %[ticket], 1\n" + /* Jump back up to check out ticket again */ + "b 2b\n" + /* Load the current now_serving ticket */ + " lbu %[ticket], %[now_serving]\n" + "4:\n" + ".set pop\n" : + [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), + [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp), + [my_ticket] "=r"(my_ticket) + ); +} + +/** + * Unlock the queue, flushing all writes. + * + * @qptr: Queue to unlock + */ +static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr) +{ + qptr->now_serving++; + CVMX_SYNCWS; +} + +/** + * Get the queue state structure for the given queue id + * + * @queue_id: Queue id to get + * + * Returns Queue structure or NULL on failure + */ +static inline __cvmx_cmd_queue_state_t + *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id) +{ + extern __cvmx_cmd_queue_all_state_t + *__cvmx_cmd_queue_state_ptr; + return &__cvmx_cmd_queue_state_ptr-> + state[__cvmx_cmd_queue_get_index(queue_id)]; +} + +/** + * Write an arbitrary number of command words to a command queue. + * This is a generic function; the fixed number of command word + * functions yield higher performance. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd_count: Number of command words to write + * @cmds: Array of commands to write + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + int cmd_count, + uint64_t *cmds) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) { + uint64_t *ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += cmd_count; + while (cmd_count--) + *ptr++ = *cmds++; + } else { + uint64_t *ptr; + int count; + /* + * We need a new command buffer. Fail if there isn't + * one available. + */ + uint64_t *new_buffer = + (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(new_buffer == NULL)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer. + */ + count = qptr->pool_size_m1 - qptr->index; + ptr += qptr->index; + cmd_count -= count; + while (count--) + *ptr++ = *cmds++; + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = cmd_count; + ptr = new_buffer; + while (cmd_count--) + *ptr++ = *cmds++; + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Simple function to write two command words to a command + * queue. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd1: Command + * @cmd2: Command + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + uint64_t cmd1, + uint64_t cmd2) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + 2 < qptr->pool_size_m1)) { + uint64_t *ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += 2; + ptr[0] = cmd1; + ptr[1] = cmd2; + } else { + uint64_t *ptr; + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer. + */ + int count = qptr->pool_size_m1 - qptr->index; + /* + * We need a new command buffer. Fail if there isn't + * one available. + */ + uint64_t *new_buffer = + (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(new_buffer == NULL)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + count--; + ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + *ptr++ = cmd1; + if (likely(count)) + *ptr++ = cmd2; + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = 0; + if (unlikely(count == 0)) { + qptr->index = 1; + new_buffer[0] = cmd2; + } + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Simple function to write three command words to a command + * queue. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd1: Command + * @cmd2: Command + * @cmd3: Command + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + uint64_t cmd1, + uint64_t cmd2, + uint64_t cmd3) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + 3 < qptr->pool_size_m1)) { + uint64_t *ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += 3; + ptr[0] = cmd1; + ptr[1] = cmd2; + ptr[2] = cmd3; + } else { + uint64_t *ptr; + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer + */ + int count = qptr->pool_size_m1 - qptr->index; + /* + * We need a new command buffer. Fail if there isn't + * one available + */ + uint64_t *new_buffer = + (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(new_buffer == NULL)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + count--; + ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + *ptr++ = cmd1; + if (count) { + *ptr++ = cmd2; + if (count > 1) + *ptr++ = cmd3; + } + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = 0; + ptr = new_buffer; + if (count == 0) { + *ptr++ = cmd2; + qptr->index++; + } + if (count < 2) { + *ptr++ = cmd3; + qptr->index++; + } + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +#endif /* __CVMX_CMD_QUEUE_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h new file mode 100644 index 000000000000..26835d1b43b8 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-config.h @@ -0,0 +1,168 @@ +#ifndef __CVMX_CONFIG_H__ +#define __CVMX_CONFIG_H__ + +/************************* Config Specific Defines ************************/ +#define CVMX_LLM_NUM_PORTS 1 +#define CVMX_NULL_POINTER_PROTECT 1 +#define CVMX_ENABLE_DEBUG_PRINTS 1 +/* PKO queues per port for interface 0 (ports 0-15) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 +/* PKO queues per port for interface 1 (ports 16-31) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 +/* Limit on the number of PKO ports enabled for interface 0 */ +#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 +/* Limit on the number of PKO ports enabled for interface 1 */ +#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 +/* PKO queues per port for PCI (ports 32-35) */ +#define CVMX_PKO_QUEUES_PER_PORT_PCI 1 +/* PKO queues per port for Loop devices (ports 36-39) */ +#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 + +/************************* FPA allocation *********************************/ +/* Pool sizes in bytes, must be multiple of a cache line */ +#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE) + +/* Pools in use */ +/* Packet buffers */ +#define CVMX_FPA_PACKET_POOL (0) +#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE +/* Work queue entrys */ +#define CVMX_FPA_WQE_POOL (1) +#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE +/* PKO queue command buffers */ +#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) +#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE + +/************************* FAU allocation ********************************/ +/* The fetch and add registers are allocated here. They are arranged + * in order of descending size so that all alignment constraints are + * automatically met. The enums are linked so that the following enum + * continues allocating where the previous one left off, so the + * numbering within each enum always starts with zero. The macros + * take care of the address increment size, so the values entered + * always increase by 1. FAU registers are accessed with byte + * addresses. + */ + +#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START) +typedef enum { + CVMX_FAU_REG_64_START = 0, + CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0), +} cvmx_fau_reg_64_t; + +#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START) +typedef enum { + CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END, + CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0), +} cvmx_fau_reg_32_t; + +#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START) +typedef enum { + CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END, + CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0), +} cvmx_fau_reg_16_t; + +#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START) +typedef enum { + CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END, + CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0), +} cvmx_fau_reg_8_t; + +/* + * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first + * available FAU address that is not allocated in cvmx-config.h. This + * is 64 bit aligned. + */ +#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL)) +#define CVMX_FAU_REG_END (2048) + +/********************** scratch memory allocation *************************/ +/* Scratchpad memory allocation. Note that these are byte memory + * addresses. Some uses of scratchpad (IOBDMA for example) require + * the use of 8-byte aligned addresses, so proper alignment needs to + * be taken into account. + */ +/* Generic scratch iobdma area */ +#define CVMX_SCR_SCRATCH (0) +/* First location available after cvmx-config.h allocated region. */ +#define CVMX_SCR_REG_AVAIL_BASE (8) + +/* + * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve + * before the beginning of the packet. If necessary, override the + * default here. See the IPD section of the hardware manual for MBUFF + * SKIP details. + */ +#define CVMX_HELPER_FIRST_MBUFF_SKIP 184 + +/* + * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve + * in each chained packet element. If necessary, override the default + * here. + */ +#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0 + +/* + * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is + * enabled for all input ports. This controls if IPD sends + * backpressure to all ports if Octeon's FPA pools don't have enough + * packet or work queue entries. Even when this is off, it is still + * possible to get backpressure from individual hardware ports. When + * configuring backpressure, also check + * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override + * the default here. + */ +#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1 + +/* + * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper + * function. Once it is enabled the hardware starts accepting + * packets. You might want to skip the IPD enable if configuration + * changes are need from the default helper setup. If necessary, + * override the default here. + */ +#define CVMX_HELPER_ENABLE_IPD 0 + +/* + * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns + * to incoming packets. + */ +#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED + +#define CVMX_ENABLE_PARAMETER_CHECKING 0 + +/* + * The following select which fields are used by the PIP to generate + * the tag on INPUT + * 0: don't include + * 1: include + */ +#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0 +#define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1 + +/* Select skip mode for input ports */ +#define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2 + +/* + * Force backpressure to be disabled. This overrides all other + * backpressure configuration. + */ +#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0 + +#endif /* __CVMX_CONFIG_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h new file mode 100644 index 000000000000..abbf42d05e5a --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h @@ -0,0 +1,72 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_DBG_DEFS_H__ +#define __CVMX_DBG_DEFS_H__ + +#define CVMX_DBG_DATA \ + CVMX_ADD_IO_SEG(0x00011F00000001E8ull) + +union cvmx_dbg_data { + uint64_t u64; + struct cvmx_dbg_data_s { + uint64_t reserved_23_63:41; + uint64_t c_mul:5; + uint64_t dsel_ext:1; + uint64_t data:17; + } s; + struct cvmx_dbg_data_cn30xx { + uint64_t reserved_31_63:33; + uint64_t pll_mul:3; + uint64_t reserved_23_27:5; + uint64_t c_mul:5; + uint64_t dsel_ext:1; + uint64_t data:17; + } cn30xx; + struct cvmx_dbg_data_cn30xx cn31xx; + struct cvmx_dbg_data_cn38xx { + uint64_t reserved_29_63:35; + uint64_t d_mul:4; + uint64_t dclk_mul2:1; + uint64_t cclk_div2:1; + uint64_t c_mul:5; + uint64_t dsel_ext:1; + uint64_t data:17; + } cn38xx; + struct cvmx_dbg_data_cn38xx cn38xxp2; + struct cvmx_dbg_data_cn30xx cn50xx; + struct cvmx_dbg_data_cn58xx { + uint64_t reserved_29_63:35; + uint64_t rem:6; + uint64_t c_mul:5; + uint64_t dsel_ext:1; + uint64_t data:17; + } cn58xx; + struct cvmx_dbg_data_cn58xx cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h new file mode 100644 index 000000000000..a6939fc8ba18 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-fau.h @@ -0,0 +1,597 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Interface to the hardware Fetch and Add Unit. + */ + +#ifndef __CVMX_FAU_H__ +#define __CVMX_FAU_H__ + +/* + * Octeon Fetch and Add Unit (FAU) + */ + +#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) +#define CVMX_FAU_BITS_SCRADDR 63, 56 +#define CVMX_FAU_BITS_LEN 55, 48 +#define CVMX_FAU_BITS_INEVAL 35, 14 +#define CVMX_FAU_BITS_TAGWAIT 13, 13 +#define CVMX_FAU_BITS_NOADD 13, 13 +#define CVMX_FAU_BITS_SIZE 12, 11 +#define CVMX_FAU_BITS_REGISTER 10, 0 + +typedef enum { + CVMX_FAU_OP_SIZE_8 = 0, + CVMX_FAU_OP_SIZE_16 = 1, + CVMX_FAU_OP_SIZE_32 = 2, + CVMX_FAU_OP_SIZE_64 = 3 +} cvmx_fau_op_size_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + uint64_t error:1; + int64_t value:63; +} cvmx_fau_tagwait64_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + uint64_t error:1; + int32_t value:31; +} cvmx_fau_tagwait32_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + uint64_t error:1; + int16_t value:15; +} cvmx_fau_tagwait16_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + uint64_t error:1; + int8_t value:7; +} cvmx_fau_tagwait8_t; + +/** + * Asynchronous tagwait return definition. If a timeout occurs, + * the error bit will be set. Otherwise the value of the + * register before the update will be returned. + */ +typedef union { + uint64_t u64; + struct { + uint64_t invalid:1; + uint64_t data:63; /* unpredictable if invalid is set */ + } s; +} cvmx_fau_async_tagwait_result_t; + +/** + * Builds a store I/O address for writing to the FAU + * + * @noadd: 0 = Store value is atomically added to the current value + * 1 = Store value is atomically written over the current value + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * Returns Address to store for atomic update + */ +static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) +{ + return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | + cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Builds a I/O address for accessing the FAU + * + * @tagwait: Should the atomic add wait for the current tag switch + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. + * Returns Address to read from for atomic update + */ +static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, + int64_t value) +{ + return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | + cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | + cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Perform an atomic 64 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Value of the register before the update + */ +static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, + int64_t value) +{ + return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 32 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Value of the register before the update + */ +static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, + int32_t value) +{ + return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 16 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns Value of the register before the update + */ +static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, + int16_t value) +{ + return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 8 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns Value of the register before the update + */ +static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 64 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait64_t +cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) +{ + union { + uint64_t i64; + cvmx_fau_tagwait64_t t; + } result; + result.i64 = + cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 32 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait32_t +cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) +{ + union { + uint64_t i32; + cvmx_fau_tagwait32_t t; + } result; + result.i32 = + cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 16 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait16_t +cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) +{ + union { + uint64_t i16; + cvmx_fau_tagwait16_t t; + } result; + result.i16 = + cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 8 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait8_t +cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + union { + uint64_t i8; + cvmx_fau_tagwait8_t t; + } result; + result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Builds I/O data for async operations + * + * @scraddr: Scratch pad byte address to write to. Must be 8 byte aligned + * @value: Signed value to add. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. + * @tagwait: Should the atomic add wait for the current tag switch + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete + * @size: The size of the operation: + * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits + * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits + * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits + * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * Returns Data to write using cvmx_send_single + */ +static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, + uint64_t tagwait, + cvmx_fau_op_size_t size, + uint64_t reg) +{ + return CVMX_FAU_LOAD_IO_ADDRESS | + cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) | + cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) | + cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | + cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | + cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Perform an async atomic 64 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, + cvmx_fau_reg_64_t reg, + int64_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); +} + +/** + * Perform an async atomic 32 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, + cvmx_fau_reg_32_t reg, + int32_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); +} + +/** + * Perform an async atomic 16 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, + cvmx_fau_reg_16_t reg, + int16_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); +} + +/** + * Perform an async atomic 8 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, + cvmx_fau_reg_8_t reg, + int8_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); +} + +/** + * Perform an async atomic 64 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, + cvmx_fau_reg_64_t reg, + int64_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); +} + +/** + * Perform an async atomic 32 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, + cvmx_fau_reg_32_t reg, + int32_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); +} + +/** + * Perform an async atomic 16 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, + cvmx_fau_reg_16_t reg, + int16_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); +} + +/** + * Perform an async atomic 8 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, + cvmx_fau_reg_8_t reg, + int8_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); +} + +/** + * Perform an atomic 64 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) +{ + cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 32 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) +{ + cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 16 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) +{ + cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 8 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 64 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) +{ + cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 32 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) +{ + cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 16 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) +{ + cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 8 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) +{ + cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); +} + +#endif /* __CVMX_FAU_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h new file mode 100644 index 000000000000..bf5546b90110 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h @@ -0,0 +1,403 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_FPA_DEFS_H__ +#define __CVMX_FPA_DEFS_H__ + +#define CVMX_FPA_BIST_STATUS \ + CVMX_ADD_IO_SEG(0x00011800280000E8ull) +#define CVMX_FPA_CTL_STATUS \ + CVMX_ADD_IO_SEG(0x0001180028000050ull) +#define CVMX_FPA_FPF0_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000000ull) +#define CVMX_FPA_FPF0_SIZE \ + CVMX_ADD_IO_SEG(0x0001180028000058ull) +#define CVMX_FPA_FPF1_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000008ull) +#define CVMX_FPA_FPF2_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000010ull) +#define CVMX_FPA_FPF3_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000018ull) +#define CVMX_FPA_FPF4_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000020ull) +#define CVMX_FPA_FPF5_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000028ull) +#define CVMX_FPA_FPF6_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000030ull) +#define CVMX_FPA_FPF7_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000038ull) +#define CVMX_FPA_FPFX_MARKS(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1) +#define CVMX_FPA_FPFX_SIZE(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1) +#define CVMX_FPA_INT_ENB \ + CVMX_ADD_IO_SEG(0x0001180028000048ull) +#define CVMX_FPA_INT_SUM \ + CVMX_ADD_IO_SEG(0x0001180028000040ull) +#define CVMX_FPA_QUE0_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x00011800280000F0ull) +#define CVMX_FPA_QUE1_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x00011800280000F8ull) +#define CVMX_FPA_QUE2_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000100ull) +#define CVMX_FPA_QUE3_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000108ull) +#define CVMX_FPA_QUE4_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000110ull) +#define CVMX_FPA_QUE5_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000118ull) +#define CVMX_FPA_QUE6_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000120ull) +#define CVMX_FPA_QUE7_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000128ull) +#define CVMX_FPA_QUEX_AVAILABLE(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8)) +#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \ + CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8)) +#define CVMX_FPA_QUE_ACT \ + CVMX_ADD_IO_SEG(0x0001180028000138ull) +#define CVMX_FPA_QUE_EXP \ + CVMX_ADD_IO_SEG(0x0001180028000130ull) +#define CVMX_FPA_WART_CTL \ + CVMX_ADD_IO_SEG(0x00011800280000D8ull) +#define CVMX_FPA_WART_STATUS \ + CVMX_ADD_IO_SEG(0x00011800280000E0ull) + +union cvmx_fpa_bist_status { + uint64_t u64; + struct cvmx_fpa_bist_status_s { + uint64_t reserved_5_63:59; + uint64_t frd:1; + uint64_t fpf0:1; + uint64_t fpf1:1; + uint64_t ffr:1; + uint64_t fdr:1; + } s; + struct cvmx_fpa_bist_status_s cn30xx; + struct cvmx_fpa_bist_status_s cn31xx; + struct cvmx_fpa_bist_status_s cn38xx; + struct cvmx_fpa_bist_status_s cn38xxp2; + struct cvmx_fpa_bist_status_s cn50xx; + struct cvmx_fpa_bist_status_s cn52xx; + struct cvmx_fpa_bist_status_s cn52xxp1; + struct cvmx_fpa_bist_status_s cn56xx; + struct cvmx_fpa_bist_status_s cn56xxp1; + struct cvmx_fpa_bist_status_s cn58xx; + struct cvmx_fpa_bist_status_s cn58xxp1; +}; + +union cvmx_fpa_ctl_status { + uint64_t u64; + struct cvmx_fpa_ctl_status_s { + uint64_t reserved_18_63:46; + uint64_t reset:1; + uint64_t use_ldt:1; + uint64_t use_stt:1; + uint64_t enb:1; + uint64_t mem1_err:7; + uint64_t mem0_err:7; + } s; + struct cvmx_fpa_ctl_status_s cn30xx; + struct cvmx_fpa_ctl_status_s cn31xx; + struct cvmx_fpa_ctl_status_s cn38xx; + struct cvmx_fpa_ctl_status_s cn38xxp2; + struct cvmx_fpa_ctl_status_s cn50xx; + struct cvmx_fpa_ctl_status_s cn52xx; + struct cvmx_fpa_ctl_status_s cn52xxp1; + struct cvmx_fpa_ctl_status_s cn56xx; + struct cvmx_fpa_ctl_status_s cn56xxp1; + struct cvmx_fpa_ctl_status_s cn58xx; + struct cvmx_fpa_ctl_status_s cn58xxp1; +}; + +union cvmx_fpa_fpfx_marks { + uint64_t u64; + struct cvmx_fpa_fpfx_marks_s { + uint64_t reserved_22_63:42; + uint64_t fpf_wr:11; + uint64_t fpf_rd:11; + } s; + struct cvmx_fpa_fpfx_marks_s cn38xx; + struct cvmx_fpa_fpfx_marks_s cn38xxp2; + struct cvmx_fpa_fpfx_marks_s cn56xx; + struct cvmx_fpa_fpfx_marks_s cn56xxp1; + struct cvmx_fpa_fpfx_marks_s cn58xx; + struct cvmx_fpa_fpfx_marks_s cn58xxp1; +}; + +union cvmx_fpa_fpfx_size { + uint64_t u64; + struct cvmx_fpa_fpfx_size_s { + uint64_t reserved_11_63:53; + uint64_t fpf_siz:11; + } s; + struct cvmx_fpa_fpfx_size_s cn38xx; + struct cvmx_fpa_fpfx_size_s cn38xxp2; + struct cvmx_fpa_fpfx_size_s cn56xx; + struct cvmx_fpa_fpfx_size_s cn56xxp1; + struct cvmx_fpa_fpfx_size_s cn58xx; + struct cvmx_fpa_fpfx_size_s cn58xxp1; +}; + +union cvmx_fpa_fpf0_marks { + uint64_t u64; + struct cvmx_fpa_fpf0_marks_s { + uint64_t reserved_24_63:40; + uint64_t fpf_wr:12; + uint64_t fpf_rd:12; + } s; + struct cvmx_fpa_fpf0_marks_s cn38xx; + struct cvmx_fpa_fpf0_marks_s cn38xxp2; + struct cvmx_fpa_fpf0_marks_s cn56xx; + struct cvmx_fpa_fpf0_marks_s cn56xxp1; + struct cvmx_fpa_fpf0_marks_s cn58xx; + struct cvmx_fpa_fpf0_marks_s cn58xxp1; +}; + +union cvmx_fpa_fpf0_size { + uint64_t u64; + struct cvmx_fpa_fpf0_size_s { + uint64_t reserved_12_63:52; + uint64_t fpf_siz:12; + } s; + struct cvmx_fpa_fpf0_size_s cn38xx; + struct cvmx_fpa_fpf0_size_s cn38xxp2; + struct cvmx_fpa_fpf0_size_s cn56xx; + struct cvmx_fpa_fpf0_size_s cn56xxp1; + struct cvmx_fpa_fpf0_size_s cn58xx; + struct cvmx_fpa_fpf0_size_s cn58xxp1; +}; + +union cvmx_fpa_int_enb { + uint64_t u64; + struct cvmx_fpa_int_enb_s { + uint64_t reserved_28_63:36; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; + } s; + struct cvmx_fpa_int_enb_s cn30xx; + struct cvmx_fpa_int_enb_s cn31xx; + struct cvmx_fpa_int_enb_s cn38xx; + struct cvmx_fpa_int_enb_s cn38xxp2; + struct cvmx_fpa_int_enb_s cn50xx; + struct cvmx_fpa_int_enb_s cn52xx; + struct cvmx_fpa_int_enb_s cn52xxp1; + struct cvmx_fpa_int_enb_s cn56xx; + struct cvmx_fpa_int_enb_s cn56xxp1; + struct cvmx_fpa_int_enb_s cn58xx; + struct cvmx_fpa_int_enb_s cn58xxp1; +}; + +union cvmx_fpa_int_sum { + uint64_t u64; + struct cvmx_fpa_int_sum_s { + uint64_t reserved_28_63:36; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; + } s; + struct cvmx_fpa_int_sum_s cn30xx; + struct cvmx_fpa_int_sum_s cn31xx; + struct cvmx_fpa_int_sum_s cn38xx; + struct cvmx_fpa_int_sum_s cn38xxp2; + struct cvmx_fpa_int_sum_s cn50xx; + struct cvmx_fpa_int_sum_s cn52xx; + struct cvmx_fpa_int_sum_s cn52xxp1; + struct cvmx_fpa_int_sum_s cn56xx; + struct cvmx_fpa_int_sum_s cn56xxp1; + struct cvmx_fpa_int_sum_s cn58xx; + struct cvmx_fpa_int_sum_s cn58xxp1; +}; + +union cvmx_fpa_quex_available { + uint64_t u64; + struct cvmx_fpa_quex_available_s { + uint64_t reserved_29_63:35; + uint64_t que_siz:29; + } s; + struct cvmx_fpa_quex_available_s cn30xx; + struct cvmx_fpa_quex_available_s cn31xx; + struct cvmx_fpa_quex_available_s cn38xx; + struct cvmx_fpa_quex_available_s cn38xxp2; + struct cvmx_fpa_quex_available_s cn50xx; + struct cvmx_fpa_quex_available_s cn52xx; + struct cvmx_fpa_quex_available_s cn52xxp1; + struct cvmx_fpa_quex_available_s cn56xx; + struct cvmx_fpa_quex_available_s cn56xxp1; + struct cvmx_fpa_quex_available_s cn58xx; + struct cvmx_fpa_quex_available_s cn58xxp1; +}; + +union cvmx_fpa_quex_page_index { + uint64_t u64; + struct cvmx_fpa_quex_page_index_s { + uint64_t reserved_25_63:39; + uint64_t pg_num:25; + } s; + struct cvmx_fpa_quex_page_index_s cn30xx; + struct cvmx_fpa_quex_page_index_s cn31xx; + struct cvmx_fpa_quex_page_index_s cn38xx; + struct cvmx_fpa_quex_page_index_s cn38xxp2; + struct cvmx_fpa_quex_page_index_s cn50xx; + struct cvmx_fpa_quex_page_index_s cn52xx; + struct cvmx_fpa_quex_page_index_s cn52xxp1; + struct cvmx_fpa_quex_page_index_s cn56xx; + struct cvmx_fpa_quex_page_index_s cn56xxp1; + struct cvmx_fpa_quex_page_index_s cn58xx; + struct cvmx_fpa_quex_page_index_s cn58xxp1; +}; + +union cvmx_fpa_que_act { + uint64_t u64; + struct cvmx_fpa_que_act_s { + uint64_t reserved_29_63:35; + uint64_t act_que:3; + uint64_t act_indx:26; + } s; + struct cvmx_fpa_que_act_s cn30xx; + struct cvmx_fpa_que_act_s cn31xx; + struct cvmx_fpa_que_act_s cn38xx; + struct cvmx_fpa_que_act_s cn38xxp2; + struct cvmx_fpa_que_act_s cn50xx; + struct cvmx_fpa_que_act_s cn52xx; + struct cvmx_fpa_que_act_s cn52xxp1; + struct cvmx_fpa_que_act_s cn56xx; + struct cvmx_fpa_que_act_s cn56xxp1; + struct cvmx_fpa_que_act_s cn58xx; + struct cvmx_fpa_que_act_s cn58xxp1; +}; + +union cvmx_fpa_que_exp { + uint64_t u64; + struct cvmx_fpa_que_exp_s { + uint64_t reserved_29_63:35; + uint64_t exp_que:3; + uint64_t exp_indx:26; + } s; + struct cvmx_fpa_que_exp_s cn30xx; + struct cvmx_fpa_que_exp_s cn31xx; + struct cvmx_fpa_que_exp_s cn38xx; + struct cvmx_fpa_que_exp_s cn38xxp2; + struct cvmx_fpa_que_exp_s cn50xx; + struct cvmx_fpa_que_exp_s cn52xx; + struct cvmx_fpa_que_exp_s cn52xxp1; + struct cvmx_fpa_que_exp_s cn56xx; + struct cvmx_fpa_que_exp_s cn56xxp1; + struct cvmx_fpa_que_exp_s cn58xx; + struct cvmx_fpa_que_exp_s cn58xxp1; +}; + +union cvmx_fpa_wart_ctl { + uint64_t u64; + struct cvmx_fpa_wart_ctl_s { + uint64_t reserved_16_63:48; + uint64_t ctl:16; + } s; + struct cvmx_fpa_wart_ctl_s cn30xx; + struct cvmx_fpa_wart_ctl_s cn31xx; + struct cvmx_fpa_wart_ctl_s cn38xx; + struct cvmx_fpa_wart_ctl_s cn38xxp2; + struct cvmx_fpa_wart_ctl_s cn50xx; + struct cvmx_fpa_wart_ctl_s cn52xx; + struct cvmx_fpa_wart_ctl_s cn52xxp1; + struct cvmx_fpa_wart_ctl_s cn56xx; + struct cvmx_fpa_wart_ctl_s cn56xxp1; + struct cvmx_fpa_wart_ctl_s cn58xx; + struct cvmx_fpa_wart_ctl_s cn58xxp1; +}; + +union cvmx_fpa_wart_status { + uint64_t u64; + struct cvmx_fpa_wart_status_s { + uint64_t reserved_32_63:32; + uint64_t status:32; + } s; + struct cvmx_fpa_wart_status_s cn30xx; + struct cvmx_fpa_wart_status_s cn31xx; + struct cvmx_fpa_wart_status_s cn38xx; + struct cvmx_fpa_wart_status_s cn38xxp2; + struct cvmx_fpa_wart_status_s cn50xx; + struct cvmx_fpa_wart_status_s cn52xx; + struct cvmx_fpa_wart_status_s cn52xxp1; + struct cvmx_fpa_wart_status_s cn56xx; + struct cvmx_fpa_wart_status_s cn56xxp1; + struct cvmx_fpa_wart_status_s cn58xx; + struct cvmx_fpa_wart_status_s cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h new file mode 100644 index 000000000000..1f04f9658736 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-fpa.h @@ -0,0 +1,299 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Interface to the hardware Free Pool Allocator. + * + * + */ + +#ifndef __CVMX_FPA_H__ +#define __CVMX_FPA_H__ + +#include "cvmx-address.h" +#include "cvmx-fpa-defs.h" + +#define CVMX_FPA_NUM_POOLS 8 +#define CVMX_FPA_MIN_BLOCK_SIZE 128 +#define CVMX_FPA_ALIGNMENT 128 + +/** + * Structure describing the data format used for stores to the FPA. + */ +typedef union { + uint64_t u64; + struct { + /* + * the (64-bit word) location in scratchpad to write + * to (if len != 0) + */ + uint64_t scraddr:8; + /* the number of words in the response (0 => no response) */ + uint64_t len:8; + /* the ID of the device on the non-coherent bus */ + uint64_t did:8; + /* + * the address that will appear in the first tick on + * the NCB bus. + */ + uint64_t addr:40; + } s; +} cvmx_fpa_iobdma_data_t; + +/** + * Structure describing the current state of a FPA pool. + */ +typedef struct { + /* Name it was created under */ + const char *name; + /* Size of each block */ + uint64_t size; + /* The base memory address of whole block */ + void *base; + /* The number of elements in the pool at creation */ + uint64_t starting_element_count; +} cvmx_fpa_pool_info_t; + +/** + * Current state of all the pools. Use access functions + * instead of using it directly. + */ +extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Return the name of the pool + * + * @pool: Pool to get the name of + * Returns The name + */ +static inline const char *cvmx_fpa_get_name(uint64_t pool) +{ + return cvmx_fpa_pool_info[pool].name; +} + +/** + * Return the base of the pool + * + * @pool: Pool to get the base of + * Returns The base + */ +static inline void *cvmx_fpa_get_base(uint64_t pool) +{ + return cvmx_fpa_pool_info[pool].base; +} + +/** + * Check if a pointer belongs to an FPA pool. Return non-zero + * if the supplied pointer is inside the memory controlled by + * an FPA pool. + * + * @pool: Pool to check + * @ptr: Pointer to check + * Returns Non-zero if pointer is in the pool. Zero if not + */ +static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr) +{ + return ((ptr >= cvmx_fpa_pool_info[pool].base) && + ((char *)ptr < + ((char *)(cvmx_fpa_pool_info[pool].base)) + + cvmx_fpa_pool_info[pool].size * + cvmx_fpa_pool_info[pool].starting_element_count)); +} + +/** + * Enable the FPA for use. Must be performed after any CSR + * configuration but before any other FPA functions. + */ +static inline void cvmx_fpa_enable(void) +{ + union cvmx_fpa_ctl_status status; + + status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); + if (status.s.enb) { + cvmx_dprintf + ("Warning: Enabling FPA when FPA already enabled.\n"); + } + + /* + * Do runtime check as we allow pass1 compiled code to run on + * pass2 chips. + */ + if (cvmx_octeon_is_pass1()) { + union cvmx_fpa_fpfx_marks marks; + int i; + for (i = 1; i < 8; i++) { + marks.u64 = + cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull); + marks.s.fpf_wr = 0xe0; + cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull, + marks.u64); + } + + /* Enforce a 10 cycle delay between config and enable */ + cvmx_wait(10); + } + + /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */ + status.u64 = 0; + status.s.enb = 1; + cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64); +} + +/** + * Get a new block from the FPA + * + * @pool: Pool to get the block from + * Returns Pointer to the block or NULL on failure + */ +static inline void *cvmx_fpa_alloc(uint64_t pool) +{ + uint64_t address = + cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool))); + if (address) + return cvmx_phys_to_ptr(address); + else + return NULL; +} + +/** + * Asynchronously get a new block from the FPA + * + * @scr_addr: Local scratch address to put response in. This is a byte address, + * but must be 8 byte aligned. + * @pool: Pool to get the block from + */ +static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool) +{ + cvmx_fpa_iobdma_data_t data; + + /* + * Hardware only uses 64 bit aligned locations, so convert + * from byte address to 64-bit index + */ + data.s.scraddr = scr_addr >> 3; + data.s.len = 1; + data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool); + data.s.addr = 0; + cvmx_send_single(data.u64); +} + +/** + * Free a block allocated with a FPA pool. Does NOT provide memory + * ordering in cases where the memory block was modified by the core. + * + * @ptr: Block to free + * @pool: Pool to put it in + * @num_cache_lines: + * Cache lines to invalidate + */ +static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, + uint64_t num_cache_lines) +{ + cvmx_addr_t newptr; + newptr.u64 = cvmx_ptr_to_phys(ptr); + newptr.sfilldidspace.didspace = + CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); + /* Prevent GCC from reordering around free */ + barrier(); + /* value written is number of cache lines not written back */ + cvmx_write_io(newptr.u64, num_cache_lines); +} + +/** + * Free a block allocated with a FPA pool. Provides required memory + * ordering in cases where memory block was modified by core. + * + * @ptr: Block to free + * @pool: Pool to put it in + * @num_cache_lines: + * Cache lines to invalidate + */ +static inline void cvmx_fpa_free(void *ptr, uint64_t pool, + uint64_t num_cache_lines) +{ + cvmx_addr_t newptr; + newptr.u64 = cvmx_ptr_to_phys(ptr); + newptr.sfilldidspace.didspace = + CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); + /* + * Make sure that any previous writes to memory go out before + * we free this buffer. This also serves as a barrier to + * prevent GCC from reordering operations to after the + * free. + */ + CVMX_SYNCWS; + /* value written is number of cache lines not written back */ + cvmx_write_io(newptr.u64, num_cache_lines); +} + +/** + * Setup a FPA pool to control a new block of memory. + * This can only be called once per pool. Make sure proper + * locking enforces this. + * + * @pool: Pool to initialize + * 0 <= pool < 8 + * @name: Constant character string to name this pool. + * String is not copied. + * @buffer: Pointer to the block of memory to use. This must be + * accessible by all processors and external hardware. + * @block_size: Size for each block controlled by the FPA + * @num_blocks: Number of blocks + * + * Returns 0 on Success, + * -1 on failure + */ +extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, + uint64_t block_size, uint64_t num_blocks); + +/** + * Shutdown a Memory pool and validate that it had all of + * the buffers originally placed in it. This should only be + * called by one processor after all hardware has finished + * using the pool. + * + * @pool: Pool to shutdown + * Returns Zero on success + * - Positive is count of missing buffers + * - Negative is too many buffers or corrupted pointers + */ +extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool); + +/** + * Get the size of blocks controlled by the pool + * This is resolved to a constant at compile time. + * + * @pool: Pool to access + * Returns Size of the block in bytes + */ +uint64_t cvmx_fpa_get_block_size(uint64_t pool); + +#endif /* __CVM_FPA_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h new file mode 100644 index 000000000000..946a43a73fd7 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h @@ -0,0 +1,2529 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_GMXX_DEFS_H__ +#define __CVMX_GMXX_DEFS_H__ + +#define CVMX_GMXX_BAD_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_BIST(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_CLK_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_HG2_CONTROL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_INF_MODE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_NXA_ADR(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_PRTX_CFG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_DECISION(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_IFG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_JABBER(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_HG2_STATUS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PASS_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PRTS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PRT_INFO(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_TX_STATUS(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_XAUI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_SMACX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_STAT_BP(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_APPEND(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_BURST(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CLK(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SLOT(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT0(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT1(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT2(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT3(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT4(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT5(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT6(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT7(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT8(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT9(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_THRESH(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_BP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull)) +#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_CORRUPT(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_HG2_REG1(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_HG2_REG2(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_IFG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_INT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_JAM(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_LFSR(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_OVR_BP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PRTS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_MAX(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_THRESH(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_XAUI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_gmxx_bad_reg { + uint64_t u64; + struct cvmx_gmxx_bad_reg_s { + uint64_t reserved_31_63:33; + uint64_t inb_nxa:4; + uint64_t statovr:1; + uint64_t loststat:4; + uint64_t reserved_18_21:4; + uint64_t out_ovr:16; + uint64_t ncb_ovr:1; + uint64_t out_col:1; + } s; + struct cvmx_gmxx_bad_reg_cn30xx { + uint64_t reserved_31_63:33; + uint64_t inb_nxa:4; + uint64_t statovr:1; + uint64_t reserved_25_25:1; + uint64_t loststat:3; + uint64_t reserved_5_21:17; + uint64_t out_ovr:3; + uint64_t reserved_0_1:2; + } cn30xx; + struct cvmx_gmxx_bad_reg_cn30xx cn31xx; + struct cvmx_gmxx_bad_reg_s cn38xx; + struct cvmx_gmxx_bad_reg_s cn38xxp2; + struct cvmx_gmxx_bad_reg_cn30xx cn50xx; + struct cvmx_gmxx_bad_reg_cn52xx { + uint64_t reserved_31_63:33; + uint64_t inb_nxa:4; + uint64_t statovr:1; + uint64_t loststat:4; + uint64_t reserved_6_21:16; + uint64_t out_ovr:4; + uint64_t reserved_0_1:2; + } cn52xx; + struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; + struct cvmx_gmxx_bad_reg_cn52xx cn56xx; + struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; + struct cvmx_gmxx_bad_reg_s cn58xx; + struct cvmx_gmxx_bad_reg_s cn58xxp1; +}; + +union cvmx_gmxx_bist { + uint64_t u64; + struct cvmx_gmxx_bist_s { + uint64_t reserved_17_63:47; + uint64_t status:17; + } s; + struct cvmx_gmxx_bist_cn30xx { + uint64_t reserved_10_63:54; + uint64_t status:10; + } cn30xx; + struct cvmx_gmxx_bist_cn30xx cn31xx; + struct cvmx_gmxx_bist_cn30xx cn38xx; + struct cvmx_gmxx_bist_cn30xx cn38xxp2; + struct cvmx_gmxx_bist_cn50xx { + uint64_t reserved_12_63:52; + uint64_t status:12; + } cn50xx; + struct cvmx_gmxx_bist_cn52xx { + uint64_t reserved_16_63:48; + uint64_t status:16; + } cn52xx; + struct cvmx_gmxx_bist_cn52xx cn52xxp1; + struct cvmx_gmxx_bist_cn52xx cn56xx; + struct cvmx_gmxx_bist_cn52xx cn56xxp1; + struct cvmx_gmxx_bist_s cn58xx; + struct cvmx_gmxx_bist_s cn58xxp1; +}; + +union cvmx_gmxx_clk_en { + uint64_t u64; + struct cvmx_gmxx_clk_en_s { + uint64_t reserved_1_63:63; + uint64_t clk_en:1; + } s; + struct cvmx_gmxx_clk_en_s cn52xx; + struct cvmx_gmxx_clk_en_s cn52xxp1; + struct cvmx_gmxx_clk_en_s cn56xx; + struct cvmx_gmxx_clk_en_s cn56xxp1; +}; + +union cvmx_gmxx_hg2_control { + uint64_t u64; + struct cvmx_gmxx_hg2_control_s { + uint64_t reserved_19_63:45; + uint64_t hg2tx_en:1; + uint64_t hg2rx_en:1; + uint64_t phys_en:1; + uint64_t logl_en:16; + } s; + struct cvmx_gmxx_hg2_control_s cn52xx; + struct cvmx_gmxx_hg2_control_s cn52xxp1; + struct cvmx_gmxx_hg2_control_s cn56xx; +}; + +union cvmx_gmxx_inf_mode { + uint64_t u64; + struct cvmx_gmxx_inf_mode_s { + uint64_t reserved_10_63:54; + uint64_t speed:2; + uint64_t reserved_6_7:2; + uint64_t mode:2; + uint64_t reserved_3_3:1; + uint64_t p0mii:1; + uint64_t en:1; + uint64_t type:1; + } s; + struct cvmx_gmxx_inf_mode_cn30xx { + uint64_t reserved_3_63:61; + uint64_t p0mii:1; + uint64_t en:1; + uint64_t type:1; + } cn30xx; + struct cvmx_gmxx_inf_mode_cn31xx { + uint64_t reserved_2_63:62; + uint64_t en:1; + uint64_t type:1; + } cn31xx; + struct cvmx_gmxx_inf_mode_cn31xx cn38xx; + struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; + struct cvmx_gmxx_inf_mode_cn30xx cn50xx; + struct cvmx_gmxx_inf_mode_cn52xx { + uint64_t reserved_10_63:54; + uint64_t speed:2; + uint64_t reserved_6_7:2; + uint64_t mode:2; + uint64_t reserved_2_3:2; + uint64_t en:1; + uint64_t type:1; + } cn52xx; + struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; + struct cvmx_gmxx_inf_mode_cn52xx cn56xx; + struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; + struct cvmx_gmxx_inf_mode_cn31xx cn58xx; + struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; +}; + +union cvmx_gmxx_nxa_adr { + uint64_t u64; + struct cvmx_gmxx_nxa_adr_s { + uint64_t reserved_6_63:58; + uint64_t prt:6; + } s; + struct cvmx_gmxx_nxa_adr_s cn30xx; + struct cvmx_gmxx_nxa_adr_s cn31xx; + struct cvmx_gmxx_nxa_adr_s cn38xx; + struct cvmx_gmxx_nxa_adr_s cn38xxp2; + struct cvmx_gmxx_nxa_adr_s cn50xx; + struct cvmx_gmxx_nxa_adr_s cn52xx; + struct cvmx_gmxx_nxa_adr_s cn52xxp1; + struct cvmx_gmxx_nxa_adr_s cn56xx; + struct cvmx_gmxx_nxa_adr_s cn56xxp1; + struct cvmx_gmxx_nxa_adr_s cn58xx; + struct cvmx_gmxx_nxa_adr_s cn58xxp1; +}; + +union cvmx_gmxx_prtx_cbfc_ctl { + uint64_t u64; + struct cvmx_gmxx_prtx_cbfc_ctl_s { + uint64_t phys_en:16; + uint64_t logl_en:16; + uint64_t phys_bp:16; + uint64_t reserved_4_15:12; + uint64_t bck_en:1; + uint64_t drp_en:1; + uint64_t tx_en:1; + uint64_t rx_en:1; + } s; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; +}; + +union cvmx_gmxx_prtx_cfg { + uint64_t u64; + struct cvmx_gmxx_prtx_cfg_s { + uint64_t reserved_14_63:50; + uint64_t tx_idle:1; + uint64_t rx_idle:1; + uint64_t reserved_9_11:3; + uint64_t speed_msb:1; + uint64_t reserved_4_7:4; + uint64_t slottime:1; + uint64_t duplex:1; + uint64_t speed:1; + uint64_t en:1; + } s; + struct cvmx_gmxx_prtx_cfg_cn30xx { + uint64_t reserved_4_63:60; + uint64_t slottime:1; + uint64_t duplex:1; + uint64_t speed:1; + uint64_t en:1; + } cn30xx; + struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; + struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; + struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; + struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; + struct cvmx_gmxx_prtx_cfg_s cn52xx; + struct cvmx_gmxx_prtx_cfg_s cn52xxp1; + struct cvmx_gmxx_prtx_cfg_s cn56xx; + struct cvmx_gmxx_prtx_cfg_s cn56xxp1; + struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; + struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam0 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam0_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam0_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam1 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam1_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam1_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam2 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam2_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam2_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam3 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam3_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam3_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam4 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam4_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam4_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam5 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam5_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam5_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam_en { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam_en_s { + uint64_t reserved_8_63:56; + uint64_t en:8; + } s; + struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_ctl_s { + uint64_t reserved_4_63:60; + uint64_t cam_mode:1; + uint64_t mcst:2; + uint64_t bcst:1; + } s; + struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn38xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_ctl_s cn50xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn52xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cn56xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_decision { + uint64_t u64; + struct cvmx_gmxx_rxx_decision_s { + uint64_t reserved_5_63:59; + uint64_t cnt:5; + } s; + struct cvmx_gmxx_rxx_decision_s cn30xx; + struct cvmx_gmxx_rxx_decision_s cn31xx; + struct cvmx_gmxx_rxx_decision_s cn38xx; + struct cvmx_gmxx_rxx_decision_s cn38xxp2; + struct cvmx_gmxx_rxx_decision_s cn50xx; + struct cvmx_gmxx_rxx_decision_s cn52xx; + struct cvmx_gmxx_rxx_decision_s cn52xxp1; + struct cvmx_gmxx_rxx_decision_s cn56xx; + struct cvmx_gmxx_rxx_decision_s cn56xxp1; + struct cvmx_gmxx_rxx_decision_s cn58xx; + struct cvmx_gmxx_rxx_decision_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_frm_chk { + uint64_t u64; + struct cvmx_gmxx_rxx_frm_chk_s { + uint64_t reserved_10_63:54; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } s; + struct cvmx_gmxx_rxx_frm_chk_s cn30xx; + struct cvmx_gmxx_rxx_frm_chk_s cn31xx; + struct cvmx_gmxx_rxx_frm_chk_s cn38xx; + struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; + struct cvmx_gmxx_rxx_frm_chk_cn50xx { + uint64_t reserved_10_63:54; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_6_6:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn50xx; + struct cvmx_gmxx_rxx_frm_chk_cn52xx { + uint64_t reserved_9_63:55; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn52xx; + struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; + struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; + struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; + struct cvmx_gmxx_rxx_frm_chk_s cn58xx; + struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_frm_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_frm_ctl_s { + uint64_t reserved_11_63:53; + uint64_t null_dis:1; + uint64_t pre_align:1; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } s; + struct cvmx_gmxx_rxx_frm_ctl_cn30xx { + uint64_t reserved_9_63:55; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } cn30xx; + struct cvmx_gmxx_rxx_frm_ctl_cn31xx { + uint64_t reserved_8_63:56; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } cn31xx; + struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; + struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx { + uint64_t reserved_11_63:53; + uint64_t null_dis:1; + uint64_t pre_align:1; + uint64_t reserved_7_8:2; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } cn50xx; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; + struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { + uint64_t reserved_10_63:54; + uint64_t pre_align:1; + uint64_t reserved_7_8:2; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } cn56xxp1; + struct cvmx_gmxx_rxx_frm_ctl_s cn58xx; + struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; +}; + +union cvmx_gmxx_rxx_frm_max { + uint64_t u64; + struct cvmx_gmxx_rxx_frm_max_s { + uint64_t reserved_16_63:48; + uint64_t len:16; + } s; + struct cvmx_gmxx_rxx_frm_max_s cn30xx; + struct cvmx_gmxx_rxx_frm_max_s cn31xx; + struct cvmx_gmxx_rxx_frm_max_s cn38xx; + struct cvmx_gmxx_rxx_frm_max_s cn38xxp2; + struct cvmx_gmxx_rxx_frm_max_s cn58xx; + struct cvmx_gmxx_rxx_frm_max_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_frm_min { + uint64_t u64; + struct cvmx_gmxx_rxx_frm_min_s { + uint64_t reserved_16_63:48; + uint64_t len:16; + } s; + struct cvmx_gmxx_rxx_frm_min_s cn30xx; + struct cvmx_gmxx_rxx_frm_min_s cn31xx; + struct cvmx_gmxx_rxx_frm_min_s cn38xx; + struct cvmx_gmxx_rxx_frm_min_s cn38xxp2; + struct cvmx_gmxx_rxx_frm_min_s cn58xx; + struct cvmx_gmxx_rxx_frm_min_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_ifg { + uint64_t u64; + struct cvmx_gmxx_rxx_ifg_s { + uint64_t reserved_4_63:60; + uint64_t ifg:4; + } s; + struct cvmx_gmxx_rxx_ifg_s cn30xx; + struct cvmx_gmxx_rxx_ifg_s cn31xx; + struct cvmx_gmxx_rxx_ifg_s cn38xx; + struct cvmx_gmxx_rxx_ifg_s cn38xxp2; + struct cvmx_gmxx_rxx_ifg_s cn50xx; + struct cvmx_gmxx_rxx_ifg_s cn52xx; + struct cvmx_gmxx_rxx_ifg_s cn52xxp1; + struct cvmx_gmxx_rxx_ifg_s cn56xx; + struct cvmx_gmxx_rxx_ifg_s cn56xxp1; + struct cvmx_gmxx_rxx_ifg_s cn58xx; + struct cvmx_gmxx_rxx_ifg_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_int_en { + uint64_t u64; + struct cvmx_gmxx_rxx_int_en_s { + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } s; + struct cvmx_gmxx_rxx_int_en_cn30xx { + uint64_t reserved_19_63:45; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } cn30xx; + struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; + struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; + struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; + struct cvmx_gmxx_rxx_int_en_cn50xx { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_6_6:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn50xx; + struct cvmx_gmxx_rxx_int_en_cn52xx { + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn52xx; + struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; + struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; + struct cvmx_gmxx_rxx_int_en_cn56xxp1 { + uint64_t reserved_27_63:37; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn56xxp1; + struct cvmx_gmxx_rxx_int_en_cn58xx { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } cn58xx; + struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; +}; + +union cvmx_gmxx_rxx_int_reg { + uint64_t u64; + struct cvmx_gmxx_rxx_int_reg_s { + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } s; + struct cvmx_gmxx_rxx_int_reg_cn30xx { + uint64_t reserved_19_63:45; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } cn30xx; + struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; + struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; + struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; + struct cvmx_gmxx_rxx_int_reg_cn50xx { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_6_6:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn50xx; + struct cvmx_gmxx_rxx_int_reg_cn52xx { + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn52xx; + struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; + struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; + struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { + uint64_t reserved_27_63:37; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn56xxp1; + struct cvmx_gmxx_rxx_int_reg_cn58xx { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } cn58xx; + struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; +}; + +union cvmx_gmxx_rxx_jabber { + uint64_t u64; + struct cvmx_gmxx_rxx_jabber_s { + uint64_t reserved_16_63:48; + uint64_t cnt:16; + } s; + struct cvmx_gmxx_rxx_jabber_s cn30xx; + struct cvmx_gmxx_rxx_jabber_s cn31xx; + struct cvmx_gmxx_rxx_jabber_s cn38xx; + struct cvmx_gmxx_rxx_jabber_s cn38xxp2; + struct cvmx_gmxx_rxx_jabber_s cn50xx; + struct cvmx_gmxx_rxx_jabber_s cn52xx; + struct cvmx_gmxx_rxx_jabber_s cn52xxp1; + struct cvmx_gmxx_rxx_jabber_s cn56xx; + struct cvmx_gmxx_rxx_jabber_s cn56xxp1; + struct cvmx_gmxx_rxx_jabber_s cn58xx; + struct cvmx_gmxx_rxx_jabber_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_pause_drop_time { + uint64_t u64; + struct cvmx_gmxx_rxx_pause_drop_time_s { + uint64_t reserved_16_63:48; + uint64_t status:16; + } s; + struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_rx_inbnd { + uint64_t u64; + struct cvmx_gmxx_rxx_rx_inbnd_s { + uint64_t reserved_4_63:60; + uint64_t duplex:1; + uint64_t speed:2; + uint64_t status:1; + } s; + struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2; + struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_ctl_s { + uint64_t reserved_1_63:63; + uint64_t rd_clr:1; + } s; + struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn38xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_ctl_s cn50xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn52xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cn56xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_octs { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_octs_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_gmxx_rxx_stats_octs_s cn30xx; + struct cvmx_gmxx_rxx_stats_octs_s cn31xx; + struct cvmx_gmxx_rxx_stats_octs_s cn38xx; + struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_octs_s cn50xx; + struct cvmx_gmxx_rxx_stats_octs_s cn52xx; + struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cn56xx; + struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cn58xx; + struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_octs_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_octs_ctl_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_octs_dmac { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_octs_dmac_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_octs_drp { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_octs_drp_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts_bad { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_bad_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts_dmac { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts_drp { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_drp_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_udd_skp { + uint64_t u64; + struct cvmx_gmxx_rxx_udd_skp_s { + uint64_t reserved_9_63:55; + uint64_t fcssel:1; + uint64_t reserved_7_7:1; + uint64_t len:7; + } s; + struct cvmx_gmxx_rxx_udd_skp_s cn30xx; + struct cvmx_gmxx_rxx_udd_skp_s cn31xx; + struct cvmx_gmxx_rxx_udd_skp_s cn38xx; + struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2; + struct cvmx_gmxx_rxx_udd_skp_s cn50xx; + struct cvmx_gmxx_rxx_udd_skp_s cn52xx; + struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cn56xx; + struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cn58xx; + struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; +}; + +union cvmx_gmxx_rx_bp_dropx { + uint64_t u64; + struct cvmx_gmxx_rx_bp_dropx_s { + uint64_t reserved_6_63:58; + uint64_t mark:6; + } s; + struct cvmx_gmxx_rx_bp_dropx_s cn30xx; + struct cvmx_gmxx_rx_bp_dropx_s cn31xx; + struct cvmx_gmxx_rx_bp_dropx_s cn38xx; + struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2; + struct cvmx_gmxx_rx_bp_dropx_s cn50xx; + struct cvmx_gmxx_rx_bp_dropx_s cn52xx; + struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cn56xx; + struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cn58xx; + struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; +}; + +union cvmx_gmxx_rx_bp_offx { + uint64_t u64; + struct cvmx_gmxx_rx_bp_offx_s { + uint64_t reserved_6_63:58; + uint64_t mark:6; + } s; + struct cvmx_gmxx_rx_bp_offx_s cn30xx; + struct cvmx_gmxx_rx_bp_offx_s cn31xx; + struct cvmx_gmxx_rx_bp_offx_s cn38xx; + struct cvmx_gmxx_rx_bp_offx_s cn38xxp2; + struct cvmx_gmxx_rx_bp_offx_s cn50xx; + struct cvmx_gmxx_rx_bp_offx_s cn52xx; + struct cvmx_gmxx_rx_bp_offx_s cn52xxp1; + struct cvmx_gmxx_rx_bp_offx_s cn56xx; + struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; + struct cvmx_gmxx_rx_bp_offx_s cn58xx; + struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; +}; + +union cvmx_gmxx_rx_bp_onx { + uint64_t u64; + struct cvmx_gmxx_rx_bp_onx_s { + uint64_t reserved_9_63:55; + uint64_t mark:9; + } s; + struct cvmx_gmxx_rx_bp_onx_s cn30xx; + struct cvmx_gmxx_rx_bp_onx_s cn31xx; + struct cvmx_gmxx_rx_bp_onx_s cn38xx; + struct cvmx_gmxx_rx_bp_onx_s cn38xxp2; + struct cvmx_gmxx_rx_bp_onx_s cn50xx; + struct cvmx_gmxx_rx_bp_onx_s cn52xx; + struct cvmx_gmxx_rx_bp_onx_s cn52xxp1; + struct cvmx_gmxx_rx_bp_onx_s cn56xx; + struct cvmx_gmxx_rx_bp_onx_s cn56xxp1; + struct cvmx_gmxx_rx_bp_onx_s cn58xx; + struct cvmx_gmxx_rx_bp_onx_s cn58xxp1; +}; + +union cvmx_gmxx_rx_hg2_status { + uint64_t u64; + struct cvmx_gmxx_rx_hg2_status_s { + uint64_t reserved_48_63:16; + uint64_t phtim2go:16; + uint64_t xof:16; + uint64_t lgtim2go:16; + } s; + struct cvmx_gmxx_rx_hg2_status_s cn52xx; + struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; + struct cvmx_gmxx_rx_hg2_status_s cn56xx; +}; + +union cvmx_gmxx_rx_pass_en { + uint64_t u64; + struct cvmx_gmxx_rx_pass_en_s { + uint64_t reserved_16_63:48; + uint64_t en:16; + } s; + struct cvmx_gmxx_rx_pass_en_s cn38xx; + struct cvmx_gmxx_rx_pass_en_s cn38xxp2; + struct cvmx_gmxx_rx_pass_en_s cn58xx; + struct cvmx_gmxx_rx_pass_en_s cn58xxp1; +}; + +union cvmx_gmxx_rx_pass_mapx { + uint64_t u64; + struct cvmx_gmxx_rx_pass_mapx_s { + uint64_t reserved_4_63:60; + uint64_t dprt:4; + } s; + struct cvmx_gmxx_rx_pass_mapx_s cn38xx; + struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; + struct cvmx_gmxx_rx_pass_mapx_s cn58xx; + struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1; +}; + +union cvmx_gmxx_rx_prt_info { + uint64_t u64; + struct cvmx_gmxx_rx_prt_info_s { + uint64_t reserved_32_63:32; + uint64_t drop:16; + uint64_t commit:16; + } s; + struct cvmx_gmxx_rx_prt_info_cn30xx { + uint64_t reserved_19_63:45; + uint64_t drop:3; + uint64_t reserved_3_15:13; + uint64_t commit:3; + } cn30xx; + struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; + struct cvmx_gmxx_rx_prt_info_s cn38xx; + struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; + struct cvmx_gmxx_rx_prt_info_cn52xx { + uint64_t reserved_20_63:44; + uint64_t drop:4; + uint64_t reserved_4_15:12; + uint64_t commit:4; + } cn52xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; + struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; + struct cvmx_gmxx_rx_prt_info_s cn58xx; + struct cvmx_gmxx_rx_prt_info_s cn58xxp1; +}; + +union cvmx_gmxx_rx_prts { + uint64_t u64; + struct cvmx_gmxx_rx_prts_s { + uint64_t reserved_3_63:61; + uint64_t prts:3; + } s; + struct cvmx_gmxx_rx_prts_s cn30xx; + struct cvmx_gmxx_rx_prts_s cn31xx; + struct cvmx_gmxx_rx_prts_s cn38xx; + struct cvmx_gmxx_rx_prts_s cn38xxp2; + struct cvmx_gmxx_rx_prts_s cn50xx; + struct cvmx_gmxx_rx_prts_s cn52xx; + struct cvmx_gmxx_rx_prts_s cn52xxp1; + struct cvmx_gmxx_rx_prts_s cn56xx; + struct cvmx_gmxx_rx_prts_s cn56xxp1; + struct cvmx_gmxx_rx_prts_s cn58xx; + struct cvmx_gmxx_rx_prts_s cn58xxp1; +}; + +union cvmx_gmxx_rx_tx_status { + uint64_t u64; + struct cvmx_gmxx_rx_tx_status_s { + uint64_t reserved_7_63:57; + uint64_t tx:3; + uint64_t reserved_3_3:1; + uint64_t rx:3; + } s; + struct cvmx_gmxx_rx_tx_status_s cn30xx; + struct cvmx_gmxx_rx_tx_status_s cn31xx; + struct cvmx_gmxx_rx_tx_status_s cn50xx; +}; + +union cvmx_gmxx_rx_xaui_bad_col { + uint64_t u64; + struct cvmx_gmxx_rx_xaui_bad_col_s { + uint64_t reserved_40_63:24; + uint64_t val:1; + uint64_t state:3; + uint64_t lane_rxc:4; + uint64_t lane_rxd:32; + } s; + struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; + struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; +}; + +union cvmx_gmxx_rx_xaui_ctl { + uint64_t u64; + struct cvmx_gmxx_rx_xaui_ctl_s { + uint64_t reserved_2_63:62; + uint64_t status:2; + } s; + struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; + struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; +}; + +union cvmx_gmxx_smacx { + uint64_t u64; + struct cvmx_gmxx_smacx_s { + uint64_t reserved_48_63:16; + uint64_t smac:48; + } s; + struct cvmx_gmxx_smacx_s cn30xx; + struct cvmx_gmxx_smacx_s cn31xx; + struct cvmx_gmxx_smacx_s cn38xx; + struct cvmx_gmxx_smacx_s cn38xxp2; + struct cvmx_gmxx_smacx_s cn50xx; + struct cvmx_gmxx_smacx_s cn52xx; + struct cvmx_gmxx_smacx_s cn52xxp1; + struct cvmx_gmxx_smacx_s cn56xx; + struct cvmx_gmxx_smacx_s cn56xxp1; + struct cvmx_gmxx_smacx_s cn58xx; + struct cvmx_gmxx_smacx_s cn58xxp1; +}; + +union cvmx_gmxx_stat_bp { + uint64_t u64; + struct cvmx_gmxx_stat_bp_s { + uint64_t reserved_17_63:47; + uint64_t bp:1; + uint64_t cnt:16; + } s; + struct cvmx_gmxx_stat_bp_s cn30xx; + struct cvmx_gmxx_stat_bp_s cn31xx; + struct cvmx_gmxx_stat_bp_s cn38xx; + struct cvmx_gmxx_stat_bp_s cn38xxp2; + struct cvmx_gmxx_stat_bp_s cn50xx; + struct cvmx_gmxx_stat_bp_s cn52xx; + struct cvmx_gmxx_stat_bp_s cn52xxp1; + struct cvmx_gmxx_stat_bp_s cn56xx; + struct cvmx_gmxx_stat_bp_s cn56xxp1; + struct cvmx_gmxx_stat_bp_s cn58xx; + struct cvmx_gmxx_stat_bp_s cn58xxp1; +}; + +union cvmx_gmxx_txx_append { + uint64_t u64; + struct cvmx_gmxx_txx_append_s { + uint64_t reserved_4_63:60; + uint64_t force_fcs:1; + uint64_t fcs:1; + uint64_t pad:1; + uint64_t preamble:1; + } s; + struct cvmx_gmxx_txx_append_s cn30xx; + struct cvmx_gmxx_txx_append_s cn31xx; + struct cvmx_gmxx_txx_append_s cn38xx; + struct cvmx_gmxx_txx_append_s cn38xxp2; + struct cvmx_gmxx_txx_append_s cn50xx; + struct cvmx_gmxx_txx_append_s cn52xx; + struct cvmx_gmxx_txx_append_s cn52xxp1; + struct cvmx_gmxx_txx_append_s cn56xx; + struct cvmx_gmxx_txx_append_s cn56xxp1; + struct cvmx_gmxx_txx_append_s cn58xx; + struct cvmx_gmxx_txx_append_s cn58xxp1; +}; + +union cvmx_gmxx_txx_burst { + uint64_t u64; + struct cvmx_gmxx_txx_burst_s { + uint64_t reserved_16_63:48; + uint64_t burst:16; + } s; + struct cvmx_gmxx_txx_burst_s cn30xx; + struct cvmx_gmxx_txx_burst_s cn31xx; + struct cvmx_gmxx_txx_burst_s cn38xx; + struct cvmx_gmxx_txx_burst_s cn38xxp2; + struct cvmx_gmxx_txx_burst_s cn50xx; + struct cvmx_gmxx_txx_burst_s cn52xx; + struct cvmx_gmxx_txx_burst_s cn52xxp1; + struct cvmx_gmxx_txx_burst_s cn56xx; + struct cvmx_gmxx_txx_burst_s cn56xxp1; + struct cvmx_gmxx_txx_burst_s cn58xx; + struct cvmx_gmxx_txx_burst_s cn58xxp1; +}; + +union cvmx_gmxx_txx_cbfc_xoff { + uint64_t u64; + struct cvmx_gmxx_txx_cbfc_xoff_s { + uint64_t reserved_16_63:48; + uint64_t xoff:16; + } s; + struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; +}; + +union cvmx_gmxx_txx_cbfc_xon { + uint64_t u64; + struct cvmx_gmxx_txx_cbfc_xon_s { + uint64_t reserved_16_63:48; + uint64_t xon:16; + } s; + struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; +}; + +union cvmx_gmxx_txx_clk { + uint64_t u64; + struct cvmx_gmxx_txx_clk_s { + uint64_t reserved_6_63:58; + uint64_t clk_cnt:6; + } s; + struct cvmx_gmxx_txx_clk_s cn30xx; + struct cvmx_gmxx_txx_clk_s cn31xx; + struct cvmx_gmxx_txx_clk_s cn38xx; + struct cvmx_gmxx_txx_clk_s cn38xxp2; + struct cvmx_gmxx_txx_clk_s cn50xx; + struct cvmx_gmxx_txx_clk_s cn58xx; + struct cvmx_gmxx_txx_clk_s cn58xxp1; +}; + +union cvmx_gmxx_txx_ctl { + uint64_t u64; + struct cvmx_gmxx_txx_ctl_s { + uint64_t reserved_2_63:62; + uint64_t xsdef_en:1; + uint64_t xscol_en:1; + } s; + struct cvmx_gmxx_txx_ctl_s cn30xx; + struct cvmx_gmxx_txx_ctl_s cn31xx; + struct cvmx_gmxx_txx_ctl_s cn38xx; + struct cvmx_gmxx_txx_ctl_s cn38xxp2; + struct cvmx_gmxx_txx_ctl_s cn50xx; + struct cvmx_gmxx_txx_ctl_s cn52xx; + struct cvmx_gmxx_txx_ctl_s cn52xxp1; + struct cvmx_gmxx_txx_ctl_s cn56xx; + struct cvmx_gmxx_txx_ctl_s cn56xxp1; + struct cvmx_gmxx_txx_ctl_s cn58xx; + struct cvmx_gmxx_txx_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_txx_min_pkt { + uint64_t u64; + struct cvmx_gmxx_txx_min_pkt_s { + uint64_t reserved_8_63:56; + uint64_t min_size:8; + } s; + struct cvmx_gmxx_txx_min_pkt_s cn30xx; + struct cvmx_gmxx_txx_min_pkt_s cn31xx; + struct cvmx_gmxx_txx_min_pkt_s cn38xx; + struct cvmx_gmxx_txx_min_pkt_s cn38xxp2; + struct cvmx_gmxx_txx_min_pkt_s cn50xx; + struct cvmx_gmxx_txx_min_pkt_s cn52xx; + struct cvmx_gmxx_txx_min_pkt_s cn52xxp1; + struct cvmx_gmxx_txx_min_pkt_s cn56xx; + struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; + struct cvmx_gmxx_txx_min_pkt_s cn58xx; + struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; +}; + +union cvmx_gmxx_txx_pause_pkt_interval { + uint64_t u64; + struct cvmx_gmxx_txx_pause_pkt_interval_s { + uint64_t reserved_16_63:48; + uint64_t interval:16; + } s; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; +}; + +union cvmx_gmxx_txx_pause_pkt_time { + uint64_t u64; + struct cvmx_gmxx_txx_pause_pkt_time_s { + uint64_t reserved_16_63:48; + uint64_t time:16; + } s; + struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2; + struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; +}; + +union cvmx_gmxx_txx_pause_togo { + uint64_t u64; + struct cvmx_gmxx_txx_pause_togo_s { + uint64_t reserved_32_63:32; + uint64_t msg_time:16; + uint64_t time:16; + } s; + struct cvmx_gmxx_txx_pause_togo_cn30xx { + uint64_t reserved_16_63:48; + uint64_t time:16; + } cn30xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx; + struct cvmx_gmxx_txx_pause_togo_s cn52xx; + struct cvmx_gmxx_txx_pause_togo_s cn52xxp1; + struct cvmx_gmxx_txx_pause_togo_s cn56xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; +}; + +union cvmx_gmxx_txx_pause_zero { + uint64_t u64; + struct cvmx_gmxx_txx_pause_zero_s { + uint64_t reserved_1_63:63; + uint64_t send:1; + } s; + struct cvmx_gmxx_txx_pause_zero_s cn30xx; + struct cvmx_gmxx_txx_pause_zero_s cn31xx; + struct cvmx_gmxx_txx_pause_zero_s cn38xx; + struct cvmx_gmxx_txx_pause_zero_s cn38xxp2; + struct cvmx_gmxx_txx_pause_zero_s cn50xx; + struct cvmx_gmxx_txx_pause_zero_s cn52xx; + struct cvmx_gmxx_txx_pause_zero_s cn52xxp1; + struct cvmx_gmxx_txx_pause_zero_s cn56xx; + struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; + struct cvmx_gmxx_txx_pause_zero_s cn58xx; + struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; +}; + +union cvmx_gmxx_txx_sgmii_ctl { + uint64_t u64; + struct cvmx_gmxx_txx_sgmii_ctl_s { + uint64_t reserved_1_63:63; + uint64_t align:1; + } s; + struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; + struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; +}; + +union cvmx_gmxx_txx_slot { + uint64_t u64; + struct cvmx_gmxx_txx_slot_s { + uint64_t reserved_10_63:54; + uint64_t slot:10; + } s; + struct cvmx_gmxx_txx_slot_s cn30xx; + struct cvmx_gmxx_txx_slot_s cn31xx; + struct cvmx_gmxx_txx_slot_s cn38xx; + struct cvmx_gmxx_txx_slot_s cn38xxp2; + struct cvmx_gmxx_txx_slot_s cn50xx; + struct cvmx_gmxx_txx_slot_s cn52xx; + struct cvmx_gmxx_txx_slot_s cn52xxp1; + struct cvmx_gmxx_txx_slot_s cn56xx; + struct cvmx_gmxx_txx_slot_s cn56xxp1; + struct cvmx_gmxx_txx_slot_s cn58xx; + struct cvmx_gmxx_txx_slot_s cn58xxp1; +}; + +union cvmx_gmxx_txx_soft_pause { + uint64_t u64; + struct cvmx_gmxx_txx_soft_pause_s { + uint64_t reserved_16_63:48; + uint64_t time:16; + } s; + struct cvmx_gmxx_txx_soft_pause_s cn30xx; + struct cvmx_gmxx_txx_soft_pause_s cn31xx; + struct cvmx_gmxx_txx_soft_pause_s cn38xx; + struct cvmx_gmxx_txx_soft_pause_s cn38xxp2; + struct cvmx_gmxx_txx_soft_pause_s cn50xx; + struct cvmx_gmxx_txx_soft_pause_s cn52xx; + struct cvmx_gmxx_txx_soft_pause_s cn52xxp1; + struct cvmx_gmxx_txx_soft_pause_s cn56xx; + struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; + struct cvmx_gmxx_txx_soft_pause_s cn58xx; + struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat0 { + uint64_t u64; + struct cvmx_gmxx_txx_stat0_s { + uint64_t xsdef:32; + uint64_t xscol:32; + } s; + struct cvmx_gmxx_txx_stat0_s cn30xx; + struct cvmx_gmxx_txx_stat0_s cn31xx; + struct cvmx_gmxx_txx_stat0_s cn38xx; + struct cvmx_gmxx_txx_stat0_s cn38xxp2; + struct cvmx_gmxx_txx_stat0_s cn50xx; + struct cvmx_gmxx_txx_stat0_s cn52xx; + struct cvmx_gmxx_txx_stat0_s cn52xxp1; + struct cvmx_gmxx_txx_stat0_s cn56xx; + struct cvmx_gmxx_txx_stat0_s cn56xxp1; + struct cvmx_gmxx_txx_stat0_s cn58xx; + struct cvmx_gmxx_txx_stat0_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat1 { + uint64_t u64; + struct cvmx_gmxx_txx_stat1_s { + uint64_t scol:32; + uint64_t mcol:32; + } s; + struct cvmx_gmxx_txx_stat1_s cn30xx; + struct cvmx_gmxx_txx_stat1_s cn31xx; + struct cvmx_gmxx_txx_stat1_s cn38xx; + struct cvmx_gmxx_txx_stat1_s cn38xxp2; + struct cvmx_gmxx_txx_stat1_s cn50xx; + struct cvmx_gmxx_txx_stat1_s cn52xx; + struct cvmx_gmxx_txx_stat1_s cn52xxp1; + struct cvmx_gmxx_txx_stat1_s cn56xx; + struct cvmx_gmxx_txx_stat1_s cn56xxp1; + struct cvmx_gmxx_txx_stat1_s cn58xx; + struct cvmx_gmxx_txx_stat1_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat2 { + uint64_t u64; + struct cvmx_gmxx_txx_stat2_s { + uint64_t reserved_48_63:16; + uint64_t octs:48; + } s; + struct cvmx_gmxx_txx_stat2_s cn30xx; + struct cvmx_gmxx_txx_stat2_s cn31xx; + struct cvmx_gmxx_txx_stat2_s cn38xx; + struct cvmx_gmxx_txx_stat2_s cn38xxp2; + struct cvmx_gmxx_txx_stat2_s cn50xx; + struct cvmx_gmxx_txx_stat2_s cn52xx; + struct cvmx_gmxx_txx_stat2_s cn52xxp1; + struct cvmx_gmxx_txx_stat2_s cn56xx; + struct cvmx_gmxx_txx_stat2_s cn56xxp1; + struct cvmx_gmxx_txx_stat2_s cn58xx; + struct cvmx_gmxx_txx_stat2_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat3 { + uint64_t u64; + struct cvmx_gmxx_txx_stat3_s { + uint64_t reserved_32_63:32; + uint64_t pkts:32; + } s; + struct cvmx_gmxx_txx_stat3_s cn30xx; + struct cvmx_gmxx_txx_stat3_s cn31xx; + struct cvmx_gmxx_txx_stat3_s cn38xx; + struct cvmx_gmxx_txx_stat3_s cn38xxp2; + struct cvmx_gmxx_txx_stat3_s cn50xx; + struct cvmx_gmxx_txx_stat3_s cn52xx; + struct cvmx_gmxx_txx_stat3_s cn52xxp1; + struct cvmx_gmxx_txx_stat3_s cn56xx; + struct cvmx_gmxx_txx_stat3_s cn56xxp1; + struct cvmx_gmxx_txx_stat3_s cn58xx; + struct cvmx_gmxx_txx_stat3_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat4 { + uint64_t u64; + struct cvmx_gmxx_txx_stat4_s { + uint64_t hist1:32; + uint64_t hist0:32; + } s; + struct cvmx_gmxx_txx_stat4_s cn30xx; + struct cvmx_gmxx_txx_stat4_s cn31xx; + struct cvmx_gmxx_txx_stat4_s cn38xx; + struct cvmx_gmxx_txx_stat4_s cn38xxp2; + struct cvmx_gmxx_txx_stat4_s cn50xx; + struct cvmx_gmxx_txx_stat4_s cn52xx; + struct cvmx_gmxx_txx_stat4_s cn52xxp1; + struct cvmx_gmxx_txx_stat4_s cn56xx; + struct cvmx_gmxx_txx_stat4_s cn56xxp1; + struct cvmx_gmxx_txx_stat4_s cn58xx; + struct cvmx_gmxx_txx_stat4_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat5 { + uint64_t u64; + struct cvmx_gmxx_txx_stat5_s { + uint64_t hist3:32; + uint64_t hist2:32; + } s; + struct cvmx_gmxx_txx_stat5_s cn30xx; + struct cvmx_gmxx_txx_stat5_s cn31xx; + struct cvmx_gmxx_txx_stat5_s cn38xx; + struct cvmx_gmxx_txx_stat5_s cn38xxp2; + struct cvmx_gmxx_txx_stat5_s cn50xx; + struct cvmx_gmxx_txx_stat5_s cn52xx; + struct cvmx_gmxx_txx_stat5_s cn52xxp1; + struct cvmx_gmxx_txx_stat5_s cn56xx; + struct cvmx_gmxx_txx_stat5_s cn56xxp1; + struct cvmx_gmxx_txx_stat5_s cn58xx; + struct cvmx_gmxx_txx_stat5_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat6 { + uint64_t u64; + struct cvmx_gmxx_txx_stat6_s { + uint64_t hist5:32; + uint64_t hist4:32; + } s; + struct cvmx_gmxx_txx_stat6_s cn30xx; + struct cvmx_gmxx_txx_stat6_s cn31xx; + struct cvmx_gmxx_txx_stat6_s cn38xx; + struct cvmx_gmxx_txx_stat6_s cn38xxp2; + struct cvmx_gmxx_txx_stat6_s cn50xx; + struct cvmx_gmxx_txx_stat6_s cn52xx; + struct cvmx_gmxx_txx_stat6_s cn52xxp1; + struct cvmx_gmxx_txx_stat6_s cn56xx; + struct cvmx_gmxx_txx_stat6_s cn56xxp1; + struct cvmx_gmxx_txx_stat6_s cn58xx; + struct cvmx_gmxx_txx_stat6_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat7 { + uint64_t u64; + struct cvmx_gmxx_txx_stat7_s { + uint64_t hist7:32; + uint64_t hist6:32; + } s; + struct cvmx_gmxx_txx_stat7_s cn30xx; + struct cvmx_gmxx_txx_stat7_s cn31xx; + struct cvmx_gmxx_txx_stat7_s cn38xx; + struct cvmx_gmxx_txx_stat7_s cn38xxp2; + struct cvmx_gmxx_txx_stat7_s cn50xx; + struct cvmx_gmxx_txx_stat7_s cn52xx; + struct cvmx_gmxx_txx_stat7_s cn52xxp1; + struct cvmx_gmxx_txx_stat7_s cn56xx; + struct cvmx_gmxx_txx_stat7_s cn56xxp1; + struct cvmx_gmxx_txx_stat7_s cn58xx; + struct cvmx_gmxx_txx_stat7_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat8 { + uint64_t u64; + struct cvmx_gmxx_txx_stat8_s { + uint64_t mcst:32; + uint64_t bcst:32; + } s; + struct cvmx_gmxx_txx_stat8_s cn30xx; + struct cvmx_gmxx_txx_stat8_s cn31xx; + struct cvmx_gmxx_txx_stat8_s cn38xx; + struct cvmx_gmxx_txx_stat8_s cn38xxp2; + struct cvmx_gmxx_txx_stat8_s cn50xx; + struct cvmx_gmxx_txx_stat8_s cn52xx; + struct cvmx_gmxx_txx_stat8_s cn52xxp1; + struct cvmx_gmxx_txx_stat8_s cn56xx; + struct cvmx_gmxx_txx_stat8_s cn56xxp1; + struct cvmx_gmxx_txx_stat8_s cn58xx; + struct cvmx_gmxx_txx_stat8_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat9 { + uint64_t u64; + struct cvmx_gmxx_txx_stat9_s { + uint64_t undflw:32; + uint64_t ctl:32; + } s; + struct cvmx_gmxx_txx_stat9_s cn30xx; + struct cvmx_gmxx_txx_stat9_s cn31xx; + struct cvmx_gmxx_txx_stat9_s cn38xx; + struct cvmx_gmxx_txx_stat9_s cn38xxp2; + struct cvmx_gmxx_txx_stat9_s cn50xx; + struct cvmx_gmxx_txx_stat9_s cn52xx; + struct cvmx_gmxx_txx_stat9_s cn52xxp1; + struct cvmx_gmxx_txx_stat9_s cn56xx; + struct cvmx_gmxx_txx_stat9_s cn56xxp1; + struct cvmx_gmxx_txx_stat9_s cn58xx; + struct cvmx_gmxx_txx_stat9_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stats_ctl { + uint64_t u64; + struct cvmx_gmxx_txx_stats_ctl_s { + uint64_t reserved_1_63:63; + uint64_t rd_clr:1; + } s; + struct cvmx_gmxx_txx_stats_ctl_s cn30xx; + struct cvmx_gmxx_txx_stats_ctl_s cn31xx; + struct cvmx_gmxx_txx_stats_ctl_s cn38xx; + struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2; + struct cvmx_gmxx_txx_stats_ctl_s cn50xx; + struct cvmx_gmxx_txx_stats_ctl_s cn52xx; + struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cn56xx; + struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cn58xx; + struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_txx_thresh { + uint64_t u64; + struct cvmx_gmxx_txx_thresh_s { + uint64_t reserved_9_63:55; + uint64_t cnt:9; + } s; + struct cvmx_gmxx_txx_thresh_cn30xx { + uint64_t reserved_7_63:57; + uint64_t cnt:7; + } cn30xx; + struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; + struct cvmx_gmxx_txx_thresh_s cn38xx; + struct cvmx_gmxx_txx_thresh_s cn38xxp2; + struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; + struct cvmx_gmxx_txx_thresh_s cn52xx; + struct cvmx_gmxx_txx_thresh_s cn52xxp1; + struct cvmx_gmxx_txx_thresh_s cn56xx; + struct cvmx_gmxx_txx_thresh_s cn56xxp1; + struct cvmx_gmxx_txx_thresh_s cn58xx; + struct cvmx_gmxx_txx_thresh_s cn58xxp1; +}; + +union cvmx_gmxx_tx_bp { + uint64_t u64; + struct cvmx_gmxx_tx_bp_s { + uint64_t reserved_4_63:60; + uint64_t bp:4; + } s; + struct cvmx_gmxx_tx_bp_cn30xx { + uint64_t reserved_3_63:61; + uint64_t bp:3; + } cn30xx; + struct cvmx_gmxx_tx_bp_cn30xx cn31xx; + struct cvmx_gmxx_tx_bp_s cn38xx; + struct cvmx_gmxx_tx_bp_s cn38xxp2; + struct cvmx_gmxx_tx_bp_cn30xx cn50xx; + struct cvmx_gmxx_tx_bp_s cn52xx; + struct cvmx_gmxx_tx_bp_s cn52xxp1; + struct cvmx_gmxx_tx_bp_s cn56xx; + struct cvmx_gmxx_tx_bp_s cn56xxp1; + struct cvmx_gmxx_tx_bp_s cn58xx; + struct cvmx_gmxx_tx_bp_s cn58xxp1; +}; + +union cvmx_gmxx_tx_clk_mskx { + uint64_t u64; + struct cvmx_gmxx_tx_clk_mskx_s { + uint64_t reserved_1_63:63; + uint64_t msk:1; + } s; + struct cvmx_gmxx_tx_clk_mskx_s cn30xx; + struct cvmx_gmxx_tx_clk_mskx_s cn50xx; +}; + +union cvmx_gmxx_tx_col_attempt { + uint64_t u64; + struct cvmx_gmxx_tx_col_attempt_s { + uint64_t reserved_5_63:59; + uint64_t limit:5; + } s; + struct cvmx_gmxx_tx_col_attempt_s cn30xx; + struct cvmx_gmxx_tx_col_attempt_s cn31xx; + struct cvmx_gmxx_tx_col_attempt_s cn38xx; + struct cvmx_gmxx_tx_col_attempt_s cn38xxp2; + struct cvmx_gmxx_tx_col_attempt_s cn50xx; + struct cvmx_gmxx_tx_col_attempt_s cn52xx; + struct cvmx_gmxx_tx_col_attempt_s cn52xxp1; + struct cvmx_gmxx_tx_col_attempt_s cn56xx; + struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; + struct cvmx_gmxx_tx_col_attempt_s cn58xx; + struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; +}; + +union cvmx_gmxx_tx_corrupt { + uint64_t u64; + struct cvmx_gmxx_tx_corrupt_s { + uint64_t reserved_4_63:60; + uint64_t corrupt:4; + } s; + struct cvmx_gmxx_tx_corrupt_cn30xx { + uint64_t reserved_3_63:61; + uint64_t corrupt:3; + } cn30xx; + struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; + struct cvmx_gmxx_tx_corrupt_s cn38xx; + struct cvmx_gmxx_tx_corrupt_s cn38xxp2; + struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx; + struct cvmx_gmxx_tx_corrupt_s cn52xx; + struct cvmx_gmxx_tx_corrupt_s cn52xxp1; + struct cvmx_gmxx_tx_corrupt_s cn56xx; + struct cvmx_gmxx_tx_corrupt_s cn56xxp1; + struct cvmx_gmxx_tx_corrupt_s cn58xx; + struct cvmx_gmxx_tx_corrupt_s cn58xxp1; +}; + +union cvmx_gmxx_tx_hg2_reg1 { + uint64_t u64; + struct cvmx_gmxx_tx_hg2_reg1_s { + uint64_t reserved_16_63:48; + uint64_t tx_xof:16; + } s; + struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; + struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; +}; + +union cvmx_gmxx_tx_hg2_reg2 { + uint64_t u64; + struct cvmx_gmxx_tx_hg2_reg2_s { + uint64_t reserved_16_63:48; + uint64_t tx_xon:16; + } s; + struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; + struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; +}; + +union cvmx_gmxx_tx_ifg { + uint64_t u64; + struct cvmx_gmxx_tx_ifg_s { + uint64_t reserved_8_63:56; + uint64_t ifg2:4; + uint64_t ifg1:4; + } s; + struct cvmx_gmxx_tx_ifg_s cn30xx; + struct cvmx_gmxx_tx_ifg_s cn31xx; + struct cvmx_gmxx_tx_ifg_s cn38xx; + struct cvmx_gmxx_tx_ifg_s cn38xxp2; + struct cvmx_gmxx_tx_ifg_s cn50xx; + struct cvmx_gmxx_tx_ifg_s cn52xx; + struct cvmx_gmxx_tx_ifg_s cn52xxp1; + struct cvmx_gmxx_tx_ifg_s cn56xx; + struct cvmx_gmxx_tx_ifg_s cn56xxp1; + struct cvmx_gmxx_tx_ifg_s cn58xx; + struct cvmx_gmxx_tx_ifg_s cn58xxp1; +}; + +union cvmx_gmxx_tx_int_en { + uint64_t u64; + struct cvmx_gmxx_tx_int_en_s { + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; + } s; + struct cvmx_gmxx_tx_int_en_cn30xx { + uint64_t reserved_19_63:45; + uint64_t late_col:3; + uint64_t reserved_15_15:1; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn30xx; + struct cvmx_gmxx_tx_int_en_cn31xx { + uint64_t reserved_15_63:49; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn31xx; + struct cvmx_gmxx_tx_int_en_s cn38xx; + struct cvmx_gmxx_tx_int_en_cn38xxp2 { + uint64_t reserved_16_63:48; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; + } cn38xxp2; + struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; + struct cvmx_gmxx_tx_int_en_cn52xx { + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn52xx; + struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; + struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; + struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; + struct cvmx_gmxx_tx_int_en_s cn58xx; + struct cvmx_gmxx_tx_int_en_s cn58xxp1; +}; + +union cvmx_gmxx_tx_int_reg { + uint64_t u64; + struct cvmx_gmxx_tx_int_reg_s { + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; + } s; + struct cvmx_gmxx_tx_int_reg_cn30xx { + uint64_t reserved_19_63:45; + uint64_t late_col:3; + uint64_t reserved_15_15:1; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn30xx; + struct cvmx_gmxx_tx_int_reg_cn31xx { + uint64_t reserved_15_63:49; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn31xx; + struct cvmx_gmxx_tx_int_reg_s cn38xx; + struct cvmx_gmxx_tx_int_reg_cn38xxp2 { + uint64_t reserved_16_63:48; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; + } cn38xxp2; + struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; + struct cvmx_gmxx_tx_int_reg_cn52xx { + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn52xx; + struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; + struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; + struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; + struct cvmx_gmxx_tx_int_reg_s cn58xx; + struct cvmx_gmxx_tx_int_reg_s cn58xxp1; +}; + +union cvmx_gmxx_tx_jam { + uint64_t u64; + struct cvmx_gmxx_tx_jam_s { + uint64_t reserved_8_63:56; + uint64_t jam:8; + } s; + struct cvmx_gmxx_tx_jam_s cn30xx; + struct cvmx_gmxx_tx_jam_s cn31xx; + struct cvmx_gmxx_tx_jam_s cn38xx; + struct cvmx_gmxx_tx_jam_s cn38xxp2; + struct cvmx_gmxx_tx_jam_s cn50xx; + struct cvmx_gmxx_tx_jam_s cn52xx; + struct cvmx_gmxx_tx_jam_s cn52xxp1; + struct cvmx_gmxx_tx_jam_s cn56xx; + struct cvmx_gmxx_tx_jam_s cn56xxp1; + struct cvmx_gmxx_tx_jam_s cn58xx; + struct cvmx_gmxx_tx_jam_s cn58xxp1; +}; + +union cvmx_gmxx_tx_lfsr { + uint64_t u64; + struct cvmx_gmxx_tx_lfsr_s { + uint64_t reserved_16_63:48; + uint64_t lfsr:16; + } s; + struct cvmx_gmxx_tx_lfsr_s cn30xx; + struct cvmx_gmxx_tx_lfsr_s cn31xx; + struct cvmx_gmxx_tx_lfsr_s cn38xx; + struct cvmx_gmxx_tx_lfsr_s cn38xxp2; + struct cvmx_gmxx_tx_lfsr_s cn50xx; + struct cvmx_gmxx_tx_lfsr_s cn52xx; + struct cvmx_gmxx_tx_lfsr_s cn52xxp1; + struct cvmx_gmxx_tx_lfsr_s cn56xx; + struct cvmx_gmxx_tx_lfsr_s cn56xxp1; + struct cvmx_gmxx_tx_lfsr_s cn58xx; + struct cvmx_gmxx_tx_lfsr_s cn58xxp1; +}; + +union cvmx_gmxx_tx_ovr_bp { + uint64_t u64; + struct cvmx_gmxx_tx_ovr_bp_s { + uint64_t reserved_48_63:16; + uint64_t tx_prt_bp:16; + uint64_t reserved_12_31:20; + uint64_t en:4; + uint64_t bp:4; + uint64_t ign_full:4; + } s; + struct cvmx_gmxx_tx_ovr_bp_cn30xx { + uint64_t reserved_11_63:53; + uint64_t en:3; + uint64_t reserved_7_7:1; + uint64_t bp:3; + uint64_t reserved_3_3:1; + uint64_t ign_full:3; + } cn30xx; + struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; + struct cvmx_gmxx_tx_ovr_bp_cn38xx { + uint64_t reserved_12_63:52; + uint64_t en:4; + uint64_t bp:4; + uint64_t ign_full:4; + } cn38xx; + struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; + struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; + struct cvmx_gmxx_tx_ovr_bp_s cn52xx; + struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1; + struct cvmx_gmxx_tx_ovr_bp_s cn56xx; + struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; + struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; + struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; +}; + +union cvmx_gmxx_tx_pause_pkt_dmac { + uint64_t u64; + struct cvmx_gmxx_tx_pause_pkt_dmac_s { + uint64_t reserved_48_63:16; + uint64_t dmac:48; + } s; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; +}; + +union cvmx_gmxx_tx_pause_pkt_type { + uint64_t u64; + struct cvmx_gmxx_tx_pause_pkt_type_s { + uint64_t reserved_16_63:48; + uint64_t type:16; + } s; + struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2; + struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; +}; + +union cvmx_gmxx_tx_prts { + uint64_t u64; + struct cvmx_gmxx_tx_prts_s { + uint64_t reserved_5_63:59; + uint64_t prts:5; + } s; + struct cvmx_gmxx_tx_prts_s cn30xx; + struct cvmx_gmxx_tx_prts_s cn31xx; + struct cvmx_gmxx_tx_prts_s cn38xx; + struct cvmx_gmxx_tx_prts_s cn38xxp2; + struct cvmx_gmxx_tx_prts_s cn50xx; + struct cvmx_gmxx_tx_prts_s cn52xx; + struct cvmx_gmxx_tx_prts_s cn52xxp1; + struct cvmx_gmxx_tx_prts_s cn56xx; + struct cvmx_gmxx_tx_prts_s cn56xxp1; + struct cvmx_gmxx_tx_prts_s cn58xx; + struct cvmx_gmxx_tx_prts_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_ctl { + uint64_t u64; + struct cvmx_gmxx_tx_spi_ctl_s { + uint64_t reserved_2_63:62; + uint64_t tpa_clr:1; + uint64_t cont_pkt:1; + } s; + struct cvmx_gmxx_tx_spi_ctl_s cn38xx; + struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; + struct cvmx_gmxx_tx_spi_ctl_s cn58xx; + struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_drain { + uint64_t u64; + struct cvmx_gmxx_tx_spi_drain_s { + uint64_t reserved_16_63:48; + uint64_t drain:16; + } s; + struct cvmx_gmxx_tx_spi_drain_s cn38xx; + struct cvmx_gmxx_tx_spi_drain_s cn58xx; + struct cvmx_gmxx_tx_spi_drain_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_max { + uint64_t u64; + struct cvmx_gmxx_tx_spi_max_s { + uint64_t reserved_23_63:41; + uint64_t slice:7; + uint64_t max2:8; + uint64_t max1:8; + } s; + struct cvmx_gmxx_tx_spi_max_cn38xx { + uint64_t reserved_16_63:48; + uint64_t max2:8; + uint64_t max1:8; + } cn38xx; + struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; + struct cvmx_gmxx_tx_spi_max_s cn58xx; + struct cvmx_gmxx_tx_spi_max_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_roundx { + uint64_t u64; + struct cvmx_gmxx_tx_spi_roundx_s { + uint64_t reserved_16_63:48; + uint64_t round:16; + } s; + struct cvmx_gmxx_tx_spi_roundx_s cn58xx; + struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_thresh { + uint64_t u64; + struct cvmx_gmxx_tx_spi_thresh_s { + uint64_t reserved_6_63:58; + uint64_t thresh:6; + } s; + struct cvmx_gmxx_tx_spi_thresh_s cn38xx; + struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; + struct cvmx_gmxx_tx_spi_thresh_s cn58xx; + struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1; +}; + +union cvmx_gmxx_tx_xaui_ctl { + uint64_t u64; + struct cvmx_gmxx_tx_xaui_ctl_s { + uint64_t reserved_11_63:53; + uint64_t hg_pause_hgi:2; + uint64_t hg_en:1; + uint64_t reserved_7_7:1; + uint64_t ls_byp:1; + uint64_t ls:2; + uint64_t reserved_2_3:2; + uint64_t uni_en:1; + uint64_t dic_en:1; + } s; + struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; + struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; +}; + +union cvmx_gmxx_xaui_ext_loopback { + uint64_t u64; + struct cvmx_gmxx_xaui_ext_loopback_s { + uint64_t reserved_5_63:59; + uint64_t en:1; + uint64_t thresh:4; + } s; + struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; + struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h new file mode 100644 index 000000000000..b465bec43553 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h @@ -0,0 +1,151 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Helper functions to abstract board specific data about + * network ports from the rest of the cvmx-helper files. + * + */ +#ifndef __CVMX_HELPER_BOARD_H__ +#define __CVMX_HELPER_BOARD_H__ + +#include "cvmx-helper.h" + +typedef enum { + set_phy_link_flags_autoneg = 0x1, + set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, + set_phy_link_flags_flow_control_enable = 0x1 << 1, + set_phy_link_flags_flow_control_disable = 0x2 << 1, + set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */ +} cvmx_helper_board_set_phy_link_flags_types_t; + +/** + * cvmx_override_board_link_get(int ipd_port) is a function + * pointer. It is meant to allow customization of the process of + * talking to a PHY to determine link speed. It is called every + * time a PHY must be polled for link status. Users should set + * this pointer to a function before calling any cvmx-helper + * operations. + */ +extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port); + +/** + * Return the MII PHY address associated with the given IPD + * port. A result of -1 means there isn't a MII capable PHY + * connected to this port. On chips supporting multiple MII + * busses the bus number is encoded in bits <15:8>. + * + * This function must be modifed for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relys on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: Octeon IPD port to get the MII address for. + * + * Returns MII PHY address and bus number or -1. + */ +extern int cvmx_helper_board_get_mii_address(int ipd_port); + +/** + * This function as a board specific method of changing the PHY + * speed, duplex, and autonegotiation. This programs the PHY and + * not Octeon. This can be used to force Octeon's links to + * specific settings. + * + * @phy_addr: The address of the PHY to program + * @link_flags: + * Flags to control autonegotiation. Bit 0 is autonegotiation + * enable/disable to maintain backware compatibility. + * @link_info: Link speed to program. If the speed is zero and autonegotiation + * is enabled, all possible negotiation speeds are advertised. + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_board_link_set_phy(int phy_addr, + cvmx_helper_board_set_phy_link_flags_types_t + link_flags, + cvmx_helper_link_info_t link_info); + +/** + * This function is the board specific method of determining an + * ethernet ports link speed. Most Octeon boards have Marvell PHYs + * and are handled by the fall through case. This function must be + * updated for boards that don't have the normal Marvell PHYs. + * + * This function must be modifed for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relys on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: IPD input port associated with the port we want to get link + * status for. + * + * Returns The ports link status. If the link isn't fully resolved, this must + * return zero. + */ +extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); + +/** + * This function is called by cvmx_helper_interface_probe() after it + * determines the number of ports Octeon can support on a specific + * interface. This function is the per board location to override + * this value. It is called with the number of ports Octeon might + * support and should return the number of actual ports on the + * board. + * + * This function must be modifed for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relys on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @interface: Interface to probe + * @supported_ports: + * Number of ports Octeon supports. + * + * Returns Number of ports the actual board supports. Many times this will + * simple be "support_ports". + */ +extern int __cvmx_helper_board_interface_probe(int interface, + int supported_ports); + +/** + * Enable packet input/output from the hardware. This function is + * called after by cvmx_helper_packet_hardware_enable() to + * perform board specific initialization. For most boards + * nothing is needed. + * + * @interface: Interface to enable + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_board_hardware_enable(int interface); + +#endif /* __CVMX_HELPER_BOARD_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h new file mode 100644 index 000000000000..5ff8c93198de --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h @@ -0,0 +1,64 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Helper functions for FPA setup. + * + */ +#ifndef __CVMX_HELPER_H_FPA__ +#define __CVMX_HELPER_H_FPA__ + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Sizes of each element in the pools is + * controlled by the cvmx-config.h header file. Specifying + * zero for any parameter will cause that FPA pool to not be + * setup. This is useful if you aren't using some of the + * hardware and want to save memory. + * + * @packet_buffers: + * Number of packet buffers to allocate + * @work_queue_entries: + * Number of work queue entries + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +extern int cvmx_helper_initialize_fpa(int packet_buffers, + int work_queue_entries, int pko_buffers, + int tim_buffers, int dfa_buffers); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h new file mode 100644 index 000000000000..e646a6ccce75 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h @@ -0,0 +1,59 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as published by + * the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for LOOP initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_LOOP_H__ +#define __CVMX_HELPER_LOOP_H__ + +/** + * Probe a LOOP interface and determine the number of ports + * connected to it. The LOOP interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_loop_probe(int interface); + +/** + * Bringup and enable a LOOP interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_loop_enable(int interface); + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h new file mode 100644 index 000000000000..908e7b08c214 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h @@ -0,0 +1,60 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for NPI initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_NPI_H__ +#define __CVMX_HELPER_NPI_H__ + +/** + * Probe a NPI interface and determine the number of ports + * connected to it. The NPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_npi_probe(int interface); + +/** + * Bringup and enable a NPI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_npi_enable(int interface); + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h new file mode 100644 index 000000000000..ea2652604a57 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h @@ -0,0 +1,110 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for RGMII/GMII/MII initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_RGMII_H__ +#define __CVMX_HELPER_RGMII_H__ + +/** + * Probe RGMII ports and determine the number present + * + * @interface: Interface to probe + * + * Returns Number of RGMII/GMII/MII ports (0-4). + */ +extern int __cvmx_helper_rgmii_probe(int interface); + +/** + * Put an RGMII interface in loopback mode. Internal packets sent + * out will be received back again on the same port. Externally + * received packets will echo back out. + * + * @port: IPD port number to loop. + */ +extern void cvmx_helper_rgmii_internal_loopback(int port); + +/** + * Configure all of the ASX, GMX, and PKO regsiters required + * to get RGMII to function on the supplied interface. + * + * @interface: PKO Interface to configure (0 or 1) + * + * Returns Zero on success + */ +extern int __cvmx_helper_rgmii_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_rgmii_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port, + int enable_internal, + int enable_external); + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h new file mode 100644 index 000000000000..19b48d60857f --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h @@ -0,0 +1,104 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for SGMII initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_SGMII_H__ +#define __CVMX_HELPER_SGMII_H__ + +/** + * Probe a SGMII interface and determine the number of ports + * connected to it. The SGMII interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_sgmii_probe(int interface); + +/** + * Bringup and enable a SGMII interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_sgmii_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_sgmii_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port, + int enable_internal, + int enable_external); + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h new file mode 100644 index 000000000000..69bac036d10e --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h @@ -0,0 +1,84 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for SPI initialization, configuration, + * and monitoring. + */ +#ifndef __CVMX_HELPER_SPI_H__ +#define __CVMX_HELPER_SPI_H__ + +/** + * Probe a SPI interface and determine the number of ports + * connected to it. The SPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_spi_probe(int interface); + +/** + * Bringup and enable a SPI interface. After this call packet I/O + * should be fully functional. This is called with IPD enabled but + * PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_spi_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_spi_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h new file mode 100644 index 000000000000..6a6e52fc22c1 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h @@ -0,0 +1,215 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Small helper utilities. + * + */ + +#ifndef __CVMX_HELPER_UTIL_H__ +#define __CVMX_HELPER_UTIL_H__ + +/** + * Convert a interface mode into a human readable string + * + * @mode: Mode to convert + * + * Returns String + */ +extern const char + *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode); + +/** + * Debug routine to dump the packet structure to the console + * + * @work: Work queue entry containing the packet to dump + * Returns + */ +extern int cvmx_helper_dump_packet(cvmx_wqe_t *work); + +/** + * Setup Random Early Drop on a specific input queue + * + * @queue: Input queue to setup RED on (0-7) + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incomming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, + int drop_thresh); + +/** + * Setup Random Early Drop to automatically begin dropping packets. + * + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incomming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); + +/** + * Get the version of the CVMX libraries. + * + * Returns Version string. Note this buffer is allocated statically + * and will be shared by all callers. + */ +extern const char *cvmx_helper_get_version(void); + +/** + * Setup the common GMX settings that determine the number of + * ports. These setting apply to almost all configurations of all + * chips. + * + * @interface: Interface to configure + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_setup_gmx(int interface, int num_ports); + +/** + * Returns the IPD/PKO port number for a port on the given + * interface. + * + * @interface: Interface to use + * @port: Port on the interface + * + * Returns IPD/PKO port number + */ +extern int cvmx_helper_get_ipd_port(int interface, int port); + +/** + * Returns the IPD/PKO port number for the first port on the given + * interface. + * + * @interface: Interface to use + * + * Returns IPD/PKO port number + */ +static inline int cvmx_helper_get_first_ipd_port(int interface) +{ + return cvmx_helper_get_ipd_port(interface, 0); +} + +/** + * Returns the IPD/PKO port number for the last port on the given + * interface. + * + * @interface: Interface to use + * + * Returns IPD/PKO port number + */ +static inline int cvmx_helper_get_last_ipd_port(int interface) +{ + extern int cvmx_helper_ports_on_interface(int interface); + + return cvmx_helper_get_first_ipd_port(interface) + + cvmx_helper_ports_on_interface(interface) - 1; +} + +/** + * Free the packet buffers contained in a work queue entry. + * The work queue entry is not freed. + * + * @work: Work queue entry with packet to free + */ +static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work) +{ + uint64_t number_buffers; + union cvmx_buf_ptr buffer_ptr; + union cvmx_buf_ptr next_buffer_ptr; + uint64_t start_of_buffer; + + number_buffers = work->word2.s.bufs; + if (number_buffers == 0) + return; + buffer_ptr = work->packet_ptr; + + /* + * Since the number of buffers is not zero, we know this is + * not a dynamic short packet. We need to check if it is a + * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is + * true, we need to free all buffers except for the first + * one. The caller doesn't expect their WQE pointer to be + * freed + */ + start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; + if (cvmx_ptr_to_phys(work) == start_of_buffer) { + next_buffer_ptr = + *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); + buffer_ptr = next_buffer_ptr; + number_buffers--; + } + + while (number_buffers--) { + /* + * Remember the back pointer is in cache lines, not + * 64bit words + */ + start_of_buffer = + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; + /* + * Read pointer to next buffer before we free the + * current buffer. + */ + next_buffer_ptr = + *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); + cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer), + buffer_ptr.s.pool, 0); + buffer_ptr = next_buffer_ptr; + } +} + +/** + * Returns the interface number for an IPD/PKO port number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface number + */ +extern int cvmx_helper_get_interface_num(int ipd_port); + +/** + * Returns the interface index number for an IPD/PKO port + * number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface index number + */ +extern int cvmx_helper_get_interface_index_num(int ipd_port); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h new file mode 100644 index 000000000000..4b4db2f93cd4 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h @@ -0,0 +1,103 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for XAUI initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_XAUI_H__ +#define __CVMX_HELPER_XAUI_H__ + +/** + * Probe a XAUI interface and determine the number of ports + * connected to it. The XAUI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_xaui_probe(int interface); + +/** + * Bringup and enable a XAUI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_xaui_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_xaui_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, + int enable_internal, + int enable_external); +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h new file mode 100644 index 000000000000..51916f3cc40c --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-helper.h @@ -0,0 +1,227 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Helper functions for common, but complicated tasks. + * + */ + +#ifndef __CVMX_HELPER_H__ +#define __CVMX_HELPER_H__ + +#include "cvmx-config.h" +#include "cvmx-fpa.h" +#include "cvmx-wqe.h" + +typedef enum { + CVMX_HELPER_INTERFACE_MODE_DISABLED, + CVMX_HELPER_INTERFACE_MODE_RGMII, + CVMX_HELPER_INTERFACE_MODE_GMII, + CVMX_HELPER_INTERFACE_MODE_SPI, + CVMX_HELPER_INTERFACE_MODE_PCIE, + CVMX_HELPER_INTERFACE_MODE_XAUI, + CVMX_HELPER_INTERFACE_MODE_SGMII, + CVMX_HELPER_INTERFACE_MODE_PICMG, + CVMX_HELPER_INTERFACE_MODE_NPI, + CVMX_HELPER_INTERFACE_MODE_LOOP, +} cvmx_helper_interface_mode_t; + +typedef union { + uint64_t u64; + struct { + uint64_t reserved_20_63:44; + uint64_t link_up:1; /**< Is the physical link up? */ + uint64_t full_duplex:1; /**< 1 if the link is full duplex */ + uint64_t speed:18; /**< Speed of the link in Mbps */ + } s; +} cvmx_helper_link_info_t; + +#include "cvmx-helper-fpa.h" + +#include +#include "cvmx-helper-loop.h" +#include "cvmx-helper-npi.h" +#include "cvmx-helper-rgmii.h" +#include "cvmx-helper-sgmii.h" +#include "cvmx-helper-spi.h" +#include "cvmx-helper-util.h" +#include "cvmx-helper-xaui.h" + +/** + * cvmx_override_pko_queue_priority(int ipd_port, uint64_t + * priorities[16]) is a function pointer. It is meant to allow + * customization of the PKO queue priorities based on the port + * number. Users should set this pointer to a function before + * calling any cvmx-helper operations. + */ +extern void (*cvmx_override_pko_queue_priority) (int pko_port, + uint64_t priorities[16]); + +/** + * cvmx_override_ipd_port_setup(int ipd_port) is a function + * pointer. It is meant to allow customization of the IPD port + * setup before packet input/output comes online. It is called + * after cvmx-helper does the default IPD configuration, but + * before IPD is enabled. Users should set this pointer to a + * function before calling any cvmx-helper operations. + */ +extern void (*cvmx_override_ipd_port_setup) (int ipd_port); + +/** + * This function enables the IPD and also enables the packet interfaces. + * The packet interfaces (RGMII and SPI) must be enabled after the + * IPD. This should be called by the user program after any additional + * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD + * is not set in the executive-config.h file. + * + * Returns 0 on success + * -1 on failure + */ +extern int cvmx_helper_ipd_and_packet_input_enable(void); + +/** + * Initialize the PIP, IPD, and PKO hardware to support + * simple priority based queues for the ethernet ports. Each + * port is configured with a number of priority queues based + * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower + * priority than the previous. + * + * Returns Zero on success, non-zero on failure + */ +extern int cvmx_helper_initialize_packet_io_global(void); + +/** + * Does core local initialization for packet io + * + * Returns Zero on success, non-zero on failure + */ +extern int cvmx_helper_initialize_packet_io_local(void); + +/** + * Returns the number of ports on the given interface. + * The interface must be initialized before the port count + * can be returned. + * + * @interface: Which interface to return port count for. + * + * Returns Port count for interface + * -1 for uninitialized interface + */ +extern int cvmx_helper_ports_on_interface(int interface); + +/** + * Return the number of interfaces the chip has. Each interface + * may have multiple ports. Most chips support two interfaces, + * but the CNX0XX and CNX1XX are exceptions. These only support + * one interface. + * + * Returns Number of interfaces on chip + */ +extern int cvmx_helper_get_number_of_interfaces(void); + +/** + * Get the operating mode of an interface. Depending on the Octeon + * chip and configuration, this function returns an enumeration + * of the type of packet I/O supported by an interface. + * + * @interface: Interface to probe + * + * Returns Mode of the interface. Unknown or unsupported interfaces return + * DISABLED. + */ +extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int + interface); + +/** + * Auto configure an IPD/PKO port link state and speed. This + * function basically does the equivalent of: + * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); + * + * @ipd_port: IPD/PKO port to auto configure + * + * Returns Link state after configure + */ +extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int cvmx_helper_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +/** + * This function probes an interface to determine the actual + * number of hardware ports connected to it. It doesn't setup the + * ports or enable them. The main goal here is to set the global + * interface_port_count[interface] correctly. Hardware setup of the + * ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ +extern int cvmx_helper_interface_probe(int interface); + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, + int enable_external); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h new file mode 100644 index 000000000000..115a552c5c7f --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-ipd.h @@ -0,0 +1,338 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Interface to the hardware Input Packet Data unit. + */ + +#ifndef __CVMX_IPD_H__ +#define __CVMX_IPD_H__ + +#include + +#include + +enum cvmx_ipd_mode { + CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ + CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ + CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ + CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ +}; + +#ifndef CVMX_ENABLE_LEN_M8_FIX +#define CVMX_ENABLE_LEN_M8_FIX 0 +#endif + +/* CSR typedefs have been moved to cvmx-csr-*.h */ +typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t; +typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t; + +typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t; +typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t; + +/** + * Configure IPD + * + * @mbuff_size: Packets buffer size in 8 byte words + * @first_mbuff_skip: + * Number of 8 byte words to skip in the first buffer + * @not_first_mbuff_skip: + * Number of 8 byte words to skip in each following buffer + * @first_back: Must be same as first_mbuff_skip / 128 + * @second_back: + * Must be same as not_first_mbuff_skip / 128 + * @wqe_fpa_pool: + * FPA pool to get work entries from + * @cache_mode: + * @back_pres_enable_flag: + * Enable or disable port back pressure + */ +static inline void cvmx_ipd_config(uint64_t mbuff_size, + uint64_t first_mbuff_skip, + uint64_t not_first_mbuff_skip, + uint64_t first_back, + uint64_t second_back, + uint64_t wqe_fpa_pool, + enum cvmx_ipd_mode cache_mode, + uint64_t back_pres_enable_flag) +{ + cvmx_ipd_mbuff_first_skip_t first_skip; + cvmx_ipd_mbuff_not_first_skip_t not_first_skip; + union cvmx_ipd_packet_mbuff_size size; + cvmx_ipd_first_next_ptr_back_t first_back_struct; + cvmx_ipd_second_next_ptr_back_t second_back_struct; + union cvmx_ipd_wqe_fpa_queue wqe_pool; + union cvmx_ipd_ctl_status ipd_ctl_reg; + + first_skip.u64 = 0; + first_skip.s.skip_sz = first_mbuff_skip; + cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); + + not_first_skip.u64 = 0; + not_first_skip.s.skip_sz = not_first_mbuff_skip; + cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); + + size.u64 = 0; + size.s.mb_size = mbuff_size; + cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); + + first_back_struct.u64 = 0; + first_back_struct.s.back = first_back; + cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); + + second_back_struct.u64 = 0; + second_back_struct.s.back = second_back; + cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); + + wqe_pool.u64 = 0; + wqe_pool.s.wqe_pool = wqe_fpa_pool; + cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); + + ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_ctl_reg.s.opc_mode = cache_mode; + ipd_ctl_reg.s.pbp_en = back_pres_enable_flag; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); + + /* Note: the example RED code that used to be here has been moved to + cvmx_helper_setup_red */ +} + +/** + * Enable IPD + */ +static inline void cvmx_ipd_enable(void) +{ + union cvmx_ipd_ctl_status ipd_reg; + ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + if (ipd_reg.s.ipd_en) { + cvmx_dprintf + ("Warning: Enabling IPD when IPD already enabled.\n"); + } + ipd_reg.s.ipd_en = 1; +#if CVMX_ENABLE_LEN_M8_FIX + if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) + ipd_reg.s.len_m8 = TRUE; +#endif + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); +} + +/** + * Disable IPD + */ +static inline void cvmx_ipd_disable(void) +{ + union cvmx_ipd_ctl_status ipd_reg; + ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_reg.s.ipd_en = 0; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); +} + +/** + * Supportive function for cvmx_fpa_shutdown_pool. + */ +static inline void cvmx_ipd_free_ptr(void) +{ + /* Only CN38XXp{1,2} cannot read pointer out of the IPD */ + if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) + && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) { + int no_wptr = 0; + union cvmx_ipd_ptr_count ipd_ptr_count; + ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); + + /* Handle Work Queue Entry in cn56xx and cn52xx */ + if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) { + union cvmx_ipd_ctl_status ipd_ctl_status; + ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + if (ipd_ctl_status.s.no_wptr) + no_wptr = 1; + } + + /* Free the prefetched WQE */ + if (ipd_ptr_count.s.wqev_cnt) { + union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid; + ipd_wqe_ptr_valid.u64 = + cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); + if (no_wptr) + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) ipd_wqe_ptr_valid.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + else + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) ipd_wqe_ptr_valid.s. + ptr << 7), CVMX_FPA_WQE_POOL, 0); + } + + /* Free all WQE in the fifo */ + if (ipd_ptr_count.s.wqe_pcnt) { + int i; + union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) { + ipd_pwp_ptr_fifo_ctl.s.cena = 0; + ipd_pwp_ptr_fifo_ctl.s.raddr = + ipd_pwp_ptr_fifo_ctl.s.max_cnts + + (ipd_pwp_ptr_fifo_ctl.s.wraddr + + i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + if (no_wptr) + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) + ipd_pwp_ptr_fifo_ctl.s. + ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + else + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) + ipd_pwp_ptr_fifo_ctl.s. + ptr << 7), + CVMX_FPA_WQE_POOL, 0); + } + ipd_pwp_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + } + + /* Free the prefetched packet */ + if (ipd_ptr_count.s.pktv_cnt) { + union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid; + ipd_pkt_ptr_valid.u64 = + cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); + cvmx_fpa_free(cvmx_phys_to_ptr + (ipd_pkt_ptr_valid.s.ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + } + + /* Free the per port prefetched packets */ + if (1) { + int i; + union cvmx_ipd_prc_port_ptr_fifo_ctl + ipd_prc_port_ptr_fifo_ctl; + ipd_prc_port_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); + + for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; + i++) { + ipd_prc_port_ptr_fifo_ctl.s.cena = 0; + ipd_prc_port_ptr_fifo_ctl.s.raddr = + i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt; + cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, + ipd_prc_port_ptr_fifo_ctl.u64); + ipd_prc_port_ptr_fifo_ctl.u64 = + cvmx_read_csr + (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) + ipd_prc_port_ptr_fifo_ctl.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + } + ipd_prc_port_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, + ipd_prc_port_ptr_fifo_ctl.u64); + } + + /* Free all packets in the holding fifo */ + if (ipd_ptr_count.s.pfif_cnt) { + int i; + union cvmx_ipd_prc_hold_ptr_fifo_ctl + ipd_prc_hold_ptr_fifo_ctl; + + ipd_prc_hold_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); + + for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) { + ipd_prc_hold_ptr_fifo_ctl.s.cena = 0; + ipd_prc_hold_ptr_fifo_ctl.s.raddr = + (ipd_prc_hold_ptr_fifo_ctl.s.praddr + + i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt; + cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, + ipd_prc_hold_ptr_fifo_ctl.u64); + ipd_prc_hold_ptr_fifo_ctl.u64 = + cvmx_read_csr + (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) + ipd_prc_hold_ptr_fifo_ctl.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + } + ipd_prc_hold_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, + ipd_prc_hold_ptr_fifo_ctl.u64); + } + + /* Free all packets in the fifo */ + if (ipd_ptr_count.s.pkt_pcnt) { + int i; + union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + + for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) { + ipd_pwp_ptr_fifo_ctl.s.cena = 0; + ipd_pwp_ptr_fifo_ctl.s.raddr = + (ipd_pwp_ptr_fifo_ctl.s.praddr + + i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) ipd_pwp_ptr_fifo_ctl. + s.ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + } + ipd_pwp_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + } + + /* Reset the IPD to get all buffers out of it */ + { + union cvmx_ipd_ctl_status ipd_ctl_status; + ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_ctl_status.s.reset = 1; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); + } + + /* Reset the PIP */ + { + union cvmx_pip_sft_rst pip_sft_rst; + pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST); + pip_sft_rst.s.rst = 1; + cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64); + } + } +} + +#endif /* __CVMX_IPD_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h new file mode 100644 index 000000000000..d88ab8d8e37d --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-mdio.h @@ -0,0 +1,506 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3 + * clause 22 and clause 45 operations. + * + */ + +#ifndef __CVMX_MIO_H__ +#define __CVMX_MIO_H__ + +#include "cvmx-smix-defs.h" + +/** + * PHY register 0 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_CONTROL 0 +typedef union { + uint16_t u16; + struct { + uint16_t reset:1; + uint16_t loopback:1; + uint16_t speed_lsb:1; + uint16_t autoneg_enable:1; + uint16_t power_down:1; + uint16_t isolate:1; + uint16_t restart_autoneg:1; + uint16_t duplex:1; + uint16_t collision_test:1; + uint16_t speed_msb:1; + uint16_t unidirectional_enable:1; + uint16_t reserved_0_4:5; + } s; +} cvmx_mdio_phy_reg_control_t; + +/** + * PHY register 1 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_STATUS 1 +typedef union { + uint16_t u16; + struct { + uint16_t capable_100base_t4:1; + uint16_t capable_100base_x_full:1; + uint16_t capable_100base_x_half:1; + uint16_t capable_10_full:1; + uint16_t capable_10_half:1; + uint16_t capable_100base_t2_full:1; + uint16_t capable_100base_t2_half:1; + uint16_t capable_extended_status:1; + uint16_t capable_unidirectional:1; + uint16_t capable_mf_preamble_suppression:1; + uint16_t autoneg_complete:1; + uint16_t remote_fault:1; + uint16_t capable_autoneg:1; + uint16_t link_status:1; + uint16_t jabber_detect:1; + uint16_t capable_extended_registers:1; + + } s; +} cvmx_mdio_phy_reg_status_t; + +/** + * PHY register 2 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_ID1 2 +typedef union { + uint16_t u16; + struct { + uint16_t oui_bits_3_18; + } s; +} cvmx_mdio_phy_reg_id1_t; + +/** + * PHY register 3 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_ID2 3 +typedef union { + uint16_t u16; + struct { + uint16_t oui_bits_19_24:6; + uint16_t model:6; + uint16_t revision:4; + } s; +} cvmx_mdio_phy_reg_id2_t; + +/** + * PHY register 4 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4 +typedef union { + uint16_t u16; + struct { + uint16_t next_page:1; + uint16_t reserved_14:1; + uint16_t remote_fault:1; + uint16_t reserved_12:1; + uint16_t asymmetric_pause:1; + uint16_t pause:1; + uint16_t advert_100base_t4:1; + uint16_t advert_100base_tx_full:1; + uint16_t advert_100base_tx_half:1; + uint16_t advert_10base_tx_full:1; + uint16_t advert_10base_tx_half:1; + uint16_t selector:5; + } s; +} cvmx_mdio_phy_reg_autoneg_adver_t; + +/** + * PHY register 5 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5 +typedef union { + uint16_t u16; + struct { + uint16_t next_page:1; + uint16_t ack:1; + uint16_t remote_fault:1; + uint16_t reserved_12:1; + uint16_t asymmetric_pause:1; + uint16_t pause:1; + uint16_t advert_100base_t4:1; + uint16_t advert_100base_tx_full:1; + uint16_t advert_100base_tx_half:1; + uint16_t advert_10base_tx_full:1; + uint16_t advert_10base_tx_half:1; + uint16_t selector:5; + } s; +} cvmx_mdio_phy_reg_link_partner_ability_t; + +/** + * PHY register 6 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6 +typedef union { + uint16_t u16; + struct { + uint16_t reserved_5_15:11; + uint16_t parallel_detection_fault:1; + uint16_t link_partner_next_page_capable:1; + uint16_t local_next_page_capable:1; + uint16_t page_received:1; + uint16_t link_partner_autoneg_capable:1; + + } s; +} cvmx_mdio_phy_reg_autoneg_expansion_t; + +/** + * PHY register 9 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_CONTROL_1000 9 +typedef union { + uint16_t u16; + struct { + uint16_t test_mode:3; + uint16_t manual_master_slave:1; + uint16_t master:1; + uint16_t port_type:1; + uint16_t advert_1000base_t_full:1; + uint16_t advert_1000base_t_half:1; + uint16_t reserved_0_7:8; + } s; +} cvmx_mdio_phy_reg_control_1000_t; + +/** + * PHY register 10 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_STATUS_1000 10 +typedef union { + uint16_t u16; + struct { + uint16_t master_slave_fault:1; + uint16_t is_master:1; + uint16_t local_receiver_ok:1; + uint16_t remote_receiver_ok:1; + uint16_t remote_capable_1000base_t_full:1; + uint16_t remote_capable_1000base_t_half:1; + uint16_t reserved_8_9:2; + uint16_t idle_error_count:8; + } s; +} cvmx_mdio_phy_reg_status_1000_t; + +/** + * PHY register 15 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15 +typedef union { + uint16_t u16; + struct { + uint16_t capable_1000base_x_full:1; + uint16_t capable_1000base_x_half:1; + uint16_t capable_1000base_t_full:1; + uint16_t capable_1000base_t_half:1; + uint16_t reserved_0_11:12; + } s; +} cvmx_mdio_phy_reg_extended_status_t; + +/** + * PHY register 13 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13 +typedef union { + uint16_t u16; + struct { + uint16_t function:2; + uint16_t reserved_5_13:9; + uint16_t devad:5; + } s; +} cvmx_mdio_phy_reg_mmd_control_t; + +/** + * PHY register 14 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14 +typedef union { + uint16_t u16; + struct { + uint16_t address_data:16; + } s; +} cvmx_mdio_phy_reg_mmd_address_data_t; + +/* Operating request encodings. */ +#define MDIO_CLAUSE_22_WRITE 0 +#define MDIO_CLAUSE_22_READ 1 + +#define MDIO_CLAUSE_45_ADDRESS 0 +#define MDIO_CLAUSE_45_WRITE 1 +#define MDIO_CLAUSE_45_READ_INC 2 +#define MDIO_CLAUSE_45_READ 3 + +/* MMD identifiers, mostly for accessing devices within XENPAK modules. */ +#define CVMX_MMD_DEVICE_PMA_PMD 1 +#define CVMX_MMD_DEVICE_WIS 2 +#define CVMX_MMD_DEVICE_PCS 3 +#define CVMX_MMD_DEVICE_PHY_XS 4 +#define CVMX_MMD_DEVICE_DTS_XS 5 +#define CVMX_MMD_DEVICE_TC 6 +#define CVMX_MMD_DEVICE_CL22_EXT 29 +#define CVMX_MMD_DEVICE_VENDOR_1 30 +#define CVMX_MMD_DEVICE_VENDOR_2 31 + +/* Helper function to put MDIO interface into clause 45 mode */ +static inline void __cvmx_mdio_set_clause45_mode(int bus_id) +{ + union cvmx_smix_clk smi_clk; + /* Put bus into clause 45 mode */ + smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); + smi_clk.s.mode = 1; + smi_clk.s.preamble = 1; + cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); +} + +/* Helper function to put MDIO interface into clause 22 mode */ +static inline void __cvmx_mdio_set_clause22_mode(int bus_id) +{ + union cvmx_smix_clk smi_clk; + /* Put bus into clause 22 mode */ + smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); + smi_clk.s.mode = 0; + cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); +} + +/** + * Perform an MII read. This function is used to read PHY + * registers controlling auto negotiation. + * + * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) + * support multiple busses. + * @phy_id: The MII phy id + * @location: Register location to read + * + * Returns Result from the read or -1 on failure + */ +static inline int cvmx_mdio_read(int bus_id, int phy_id, int location) +{ + union cvmx_smix_cmd smi_cmd; + union cvmx_smix_rd_dat smi_rd; + int timeout = 1000; + + if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) + __cvmx_mdio_set_clause22_mode(bus_id); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = location; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); + } while (smi_rd.s.pending && timeout--); + + if (smi_rd.s.val) + return smi_rd.s.dat; + else + return -1; +} + +/** + * Perform an MII write. This function is used to write PHY + * registers controlling auto negotiation. + * + * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) + * support multiple busses. + * @phy_id: The MII phy id + * @location: Register location to write + * @val: Value to write + * + * Returns -1 on error + * 0 on success + */ +static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val) +{ + union cvmx_smix_cmd smi_cmd; + union cvmx_smix_wr_dat smi_wr; + int timeout = 1000; + + if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) + __cvmx_mdio_set_clause22_mode(bus_id); + + smi_wr.u64 = 0; + smi_wr.s.dat = val; + cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = location; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); + } while (smi_wr.s.pending && --timeout); + if (timeout <= 0) + return -1; + + return 0; +} + +/** + * Perform an IEEE 802.3 clause 45 MII read. This function is used to + * read PHY registers controlling auto negotiation. + * + * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) + * support multiple busses. + * @phy_id: The MII phy id + * @device: MDIO Managable Device (MMD) id + * @location: Register location to read + * + * Returns Result from the read or -1 on failure + */ + +static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, + int location) +{ + union cvmx_smix_cmd smi_cmd; + union cvmx_smix_rd_dat smi_rd; + union cvmx_smix_wr_dat smi_wr; + int timeout = 1000; + + if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) + return -1; + + __cvmx_mdio_set_clause45_mode(bus_id); + + smi_wr.u64 = 0; + smi_wr.s.dat = location; + cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = device; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); + } while (smi_wr.s.pending && --timeout); + if (timeout <= 0) { + cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " + "device %2d register %2d TIME OUT(address)\n", + bus_id, phy_id, device, location); + return -1; + } + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = device; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); + } while (smi_rd.s.pending && --timeout); + + if (timeout <= 0) { + cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " + "device %2d register %2d TIME OUT(data)\n", + bus_id, phy_id, device, location); + return -1; + } + + if (smi_rd.s.val) + return smi_rd.s.dat; + else { + cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " + "device %2d register %2d INVALID READ\n", + bus_id, phy_id, device, location); + return -1; + } +} + +/** + * Perform an IEEE 802.3 clause 45 MII write. This function is used to + * write PHY registers controlling auto negotiation. + * + * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) + * support multiple busses. + * @phy_id: The MII phy id + * @device: MDIO Managable Device (MMD) id + * @location: Register location to write + * @val: Value to write + * + * Returns -1 on error + * 0 on success + */ +static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, + int location, int val) +{ + union cvmx_smix_cmd smi_cmd; + union cvmx_smix_wr_dat smi_wr; + int timeout = 1000; + + if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) + return -1; + + __cvmx_mdio_set_clause45_mode(bus_id); + + smi_wr.u64 = 0; + smi_wr.s.dat = location; + cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = device; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); + } while (smi_wr.s.pending && --timeout); + if (timeout <= 0) + return -1; + + smi_wr.u64 = 0; + smi_wr.s.dat = val; + cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = device; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); + } while (smi_wr.s.pending && --timeout); + if (timeout <= 0) + return -1; + + return 0; +} + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h new file mode 100644 index 000000000000..d45952df5f5b --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h @@ -0,0 +1,370 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PCSX_DEFS_H__ +#define __CVMX_PCSX_DEFS_H__ + +#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_INTX_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_pcsx_anx_adv_reg { + uint64_t u64; + struct cvmx_pcsx_anx_adv_reg_s { + uint64_t reserved_16_63:48; + uint64_t np:1; + uint64_t reserved_14_14:1; + uint64_t rem_flt:2; + uint64_t reserved_9_11:3; + uint64_t pause:2; + uint64_t hfd:1; + uint64_t fd:1; + uint64_t reserved_0_4:5; + } s; + struct cvmx_pcsx_anx_adv_reg_s cn52xx; + struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; + struct cvmx_pcsx_anx_adv_reg_s cn56xx; + struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; +}; + +union cvmx_pcsx_anx_ext_st_reg { + uint64_t u64; + struct cvmx_pcsx_anx_ext_st_reg_s { + uint64_t reserved_16_63:48; + uint64_t thou_xfd:1; + uint64_t thou_xhd:1; + uint64_t thou_tfd:1; + uint64_t thou_thd:1; + uint64_t reserved_0_11:12; + } s; + struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; + struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; +}; + +union cvmx_pcsx_anx_lp_abil_reg { + uint64_t u64; + struct cvmx_pcsx_anx_lp_abil_reg_s { + uint64_t reserved_16_63:48; + uint64_t np:1; + uint64_t ack:1; + uint64_t rem_flt:2; + uint64_t reserved_9_11:3; + uint64_t pause:2; + uint64_t hfd:1; + uint64_t fd:1; + uint64_t reserved_0_4:5; + } s; + struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; + struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; +}; + +union cvmx_pcsx_anx_results_reg { + uint64_t u64; + struct cvmx_pcsx_anx_results_reg_s { + uint64_t reserved_7_63:57; + uint64_t pause:2; + uint64_t spd:2; + uint64_t an_cpt:1; + uint64_t dup:1; + uint64_t link_ok:1; + } s; + struct cvmx_pcsx_anx_results_reg_s cn52xx; + struct cvmx_pcsx_anx_results_reg_s cn52xxp1; + struct cvmx_pcsx_anx_results_reg_s cn56xx; + struct cvmx_pcsx_anx_results_reg_s cn56xxp1; +}; + +union cvmx_pcsx_intx_en_reg { + uint64_t u64; + struct cvmx_pcsx_intx_en_reg_s { + uint64_t reserved_12_63:52; + uint64_t dup:1; + uint64_t sync_bad_en:1; + uint64_t an_bad_en:1; + uint64_t rxlock_en:1; + uint64_t rxbad_en:1; + uint64_t rxerr_en:1; + uint64_t txbad_en:1; + uint64_t txfifo_en:1; + uint64_t txfifu_en:1; + uint64_t an_err_en:1; + uint64_t xmit_en:1; + uint64_t lnkspd_en:1; + } s; + struct cvmx_pcsx_intx_en_reg_s cn52xx; + struct cvmx_pcsx_intx_en_reg_s cn52xxp1; + struct cvmx_pcsx_intx_en_reg_s cn56xx; + struct cvmx_pcsx_intx_en_reg_s cn56xxp1; +}; + +union cvmx_pcsx_intx_reg { + uint64_t u64; + struct cvmx_pcsx_intx_reg_s { + uint64_t reserved_12_63:52; + uint64_t dup:1; + uint64_t sync_bad:1; + uint64_t an_bad:1; + uint64_t rxlock:1; + uint64_t rxbad:1; + uint64_t rxerr:1; + uint64_t txbad:1; + uint64_t txfifo:1; + uint64_t txfifu:1; + uint64_t an_err:1; + uint64_t xmit:1; + uint64_t lnkspd:1; + } s; + struct cvmx_pcsx_intx_reg_s cn52xx; + struct cvmx_pcsx_intx_reg_s cn52xxp1; + struct cvmx_pcsx_intx_reg_s cn56xx; + struct cvmx_pcsx_intx_reg_s cn56xxp1; +}; + +union cvmx_pcsx_linkx_timer_count_reg { + uint64_t u64; + struct cvmx_pcsx_linkx_timer_count_reg_s { + uint64_t reserved_16_63:48; + uint64_t count:16; + } s; + struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; + struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; +}; + +union cvmx_pcsx_log_anlx_reg { + uint64_t u64; + struct cvmx_pcsx_log_anlx_reg_s { + uint64_t reserved_4_63:60; + uint64_t lafifovfl:1; + uint64_t la_en:1; + uint64_t pkt_sz:2; + } s; + struct cvmx_pcsx_log_anlx_reg_s cn52xx; + struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; + struct cvmx_pcsx_log_anlx_reg_s cn56xx; + struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; +}; + +union cvmx_pcsx_miscx_ctl_reg { + uint64_t u64; + struct cvmx_pcsx_miscx_ctl_reg_s { + uint64_t reserved_13_63:51; + uint64_t sgmii:1; + uint64_t gmxeno:1; + uint64_t loopbck2:1; + uint64_t mac_phy:1; + uint64_t mode:1; + uint64_t an_ovrd:1; + uint64_t samp_pt:7; + } s; + struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; + struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; +}; + +union cvmx_pcsx_mrx_control_reg { + uint64_t u64; + struct cvmx_pcsx_mrx_control_reg_s { + uint64_t reserved_16_63:48; + uint64_t reset:1; + uint64_t loopbck1:1; + uint64_t spdlsb:1; + uint64_t an_en:1; + uint64_t pwr_dn:1; + uint64_t reserved_10_10:1; + uint64_t rst_an:1; + uint64_t dup:1; + uint64_t coltst:1; + uint64_t spdmsb:1; + uint64_t uni:1; + uint64_t reserved_0_4:5; + } s; + struct cvmx_pcsx_mrx_control_reg_s cn52xx; + struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; + struct cvmx_pcsx_mrx_control_reg_s cn56xx; + struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; +}; + +union cvmx_pcsx_mrx_status_reg { + uint64_t u64; + struct cvmx_pcsx_mrx_status_reg_s { + uint64_t reserved_16_63:48; + uint64_t hun_t4:1; + uint64_t hun_xfd:1; + uint64_t hun_xhd:1; + uint64_t ten_fd:1; + uint64_t ten_hd:1; + uint64_t hun_t2fd:1; + uint64_t hun_t2hd:1; + uint64_t ext_st:1; + uint64_t reserved_7_7:1; + uint64_t prb_sup:1; + uint64_t an_cpt:1; + uint64_t rm_flt:1; + uint64_t an_abil:1; + uint64_t lnk_st:1; + uint64_t reserved_1_1:1; + uint64_t extnd:1; + } s; + struct cvmx_pcsx_mrx_status_reg_s cn52xx; + struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; + struct cvmx_pcsx_mrx_status_reg_s cn56xx; + struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; +}; + +union cvmx_pcsx_rxx_states_reg { + uint64_t u64; + struct cvmx_pcsx_rxx_states_reg_s { + uint64_t reserved_16_63:48; + uint64_t rx_bad:1; + uint64_t rx_st:5; + uint64_t sync_bad:1; + uint64_t sync:4; + uint64_t an_bad:1; + uint64_t an_st:4; + } s; + struct cvmx_pcsx_rxx_states_reg_s cn52xx; + struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; + struct cvmx_pcsx_rxx_states_reg_s cn56xx; + struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; +}; + +union cvmx_pcsx_rxx_sync_reg { + uint64_t u64; + struct cvmx_pcsx_rxx_sync_reg_s { + uint64_t reserved_2_63:62; + uint64_t sync:1; + uint64_t bit_lock:1; + } s; + struct cvmx_pcsx_rxx_sync_reg_s cn52xx; + struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; + struct cvmx_pcsx_rxx_sync_reg_s cn56xx; + struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; +}; + +union cvmx_pcsx_sgmx_an_adv_reg { + uint64_t u64; + struct cvmx_pcsx_sgmx_an_adv_reg_s { + uint64_t reserved_16_63:48; + uint64_t link:1; + uint64_t ack:1; + uint64_t reserved_13_13:1; + uint64_t dup:1; + uint64_t speed:2; + uint64_t reserved_1_9:9; + uint64_t one:1; + } s; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; +}; + +union cvmx_pcsx_sgmx_lp_adv_reg { + uint64_t u64; + struct cvmx_pcsx_sgmx_lp_adv_reg_s { + uint64_t reserved_16_63:48; + uint64_t link:1; + uint64_t reserved_13_14:2; + uint64_t dup:1; + uint64_t speed:2; + uint64_t reserved_1_9:9; + uint64_t one:1; + } s; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; +}; + +union cvmx_pcsx_txx_states_reg { + uint64_t u64; + struct cvmx_pcsx_txx_states_reg_s { + uint64_t reserved_7_63:57; + uint64_t xmit:2; + uint64_t tx_bad:1; + uint64_t ord_st:4; + } s; + struct cvmx_pcsx_txx_states_reg_s cn52xx; + struct cvmx_pcsx_txx_states_reg_s cn52xxp1; + struct cvmx_pcsx_txx_states_reg_s cn56xx; + struct cvmx_pcsx_txx_states_reg_s cn56xxp1; +}; + +union cvmx_pcsx_tx_rxx_polarity_reg { + uint64_t u64; + struct cvmx_pcsx_tx_rxx_polarity_reg_s { + uint64_t reserved_4_63:60; + uint64_t rxovrd:1; + uint64_t autorxpl:1; + uint64_t rxplrt:1; + uint64_t txplrt:1; + } s; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h new file mode 100644 index 000000000000..55d120fe8aed --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h @@ -0,0 +1,316 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PCSXX_DEFS_H__ +#define __CVMX_PCSXX_DEFS_H__ + +#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_CONTROL1_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_CONTROL2_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_INT_EN_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_LOG_ANL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_MISC_CTL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_STATUS1_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_STATUS2_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_pcsxx_10gbx_status_reg { + uint64_t u64; + struct cvmx_pcsxx_10gbx_status_reg_s { + uint64_t reserved_13_63:51; + uint64_t alignd:1; + uint64_t pattst:1; + uint64_t reserved_4_10:7; + uint64_t l3sync:1; + uint64_t l2sync:1; + uint64_t l1sync:1; + uint64_t l0sync:1; + } s; + struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; + struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_bist_status_reg { + uint64_t u64; + struct cvmx_pcsxx_bist_status_reg_s { + uint64_t reserved_1_63:63; + uint64_t bist_status:1; + } s; + struct cvmx_pcsxx_bist_status_reg_s cn52xx; + struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; + struct cvmx_pcsxx_bist_status_reg_s cn56xx; + struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_bit_lock_status_reg { + uint64_t u64; + struct cvmx_pcsxx_bit_lock_status_reg_s { + uint64_t reserved_4_63:60; + uint64_t bitlck3:1; + uint64_t bitlck2:1; + uint64_t bitlck1:1; + uint64_t bitlck0:1; + } s; + struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; + struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_control1_reg { + uint64_t u64; + struct cvmx_pcsxx_control1_reg_s { + uint64_t reserved_16_63:48; + uint64_t reset:1; + uint64_t loopbck1:1; + uint64_t spdsel1:1; + uint64_t reserved_12_12:1; + uint64_t lo_pwr:1; + uint64_t reserved_7_10:4; + uint64_t spdsel0:1; + uint64_t spd:4; + uint64_t reserved_0_1:2; + } s; + struct cvmx_pcsxx_control1_reg_s cn52xx; + struct cvmx_pcsxx_control1_reg_s cn52xxp1; + struct cvmx_pcsxx_control1_reg_s cn56xx; + struct cvmx_pcsxx_control1_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_control2_reg { + uint64_t u64; + struct cvmx_pcsxx_control2_reg_s { + uint64_t reserved_2_63:62; + uint64_t type:2; + } s; + struct cvmx_pcsxx_control2_reg_s cn52xx; + struct cvmx_pcsxx_control2_reg_s cn52xxp1; + struct cvmx_pcsxx_control2_reg_s cn56xx; + struct cvmx_pcsxx_control2_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_int_en_reg { + uint64_t u64; + struct cvmx_pcsxx_int_en_reg_s { + uint64_t reserved_6_63:58; + uint64_t algnlos_en:1; + uint64_t synlos_en:1; + uint64_t bitlckls_en:1; + uint64_t rxsynbad_en:1; + uint64_t rxbad_en:1; + uint64_t txflt_en:1; + } s; + struct cvmx_pcsxx_int_en_reg_s cn52xx; + struct cvmx_pcsxx_int_en_reg_s cn52xxp1; + struct cvmx_pcsxx_int_en_reg_s cn56xx; + struct cvmx_pcsxx_int_en_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_int_reg { + uint64_t u64; + struct cvmx_pcsxx_int_reg_s { + uint64_t reserved_6_63:58; + uint64_t algnlos:1; + uint64_t synlos:1; + uint64_t bitlckls:1; + uint64_t rxsynbad:1; + uint64_t rxbad:1; + uint64_t txflt:1; + } s; + struct cvmx_pcsxx_int_reg_s cn52xx; + struct cvmx_pcsxx_int_reg_s cn52xxp1; + struct cvmx_pcsxx_int_reg_s cn56xx; + struct cvmx_pcsxx_int_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_log_anl_reg { + uint64_t u64; + struct cvmx_pcsxx_log_anl_reg_s { + uint64_t reserved_7_63:57; + uint64_t enc_mode:1; + uint64_t drop_ln:2; + uint64_t lafifovfl:1; + uint64_t la_en:1; + uint64_t pkt_sz:2; + } s; + struct cvmx_pcsxx_log_anl_reg_s cn52xx; + struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; + struct cvmx_pcsxx_log_anl_reg_s cn56xx; + struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_misc_ctl_reg { + uint64_t u64; + struct cvmx_pcsxx_misc_ctl_reg_s { + uint64_t reserved_4_63:60; + uint64_t tx_swap:1; + uint64_t rx_swap:1; + uint64_t xaui:1; + uint64_t gmxeno:1; + } s; + struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; + struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_rx_sync_states_reg { + uint64_t u64; + struct cvmx_pcsxx_rx_sync_states_reg_s { + uint64_t reserved_16_63:48; + uint64_t sync3st:4; + uint64_t sync2st:4; + uint64_t sync1st:4; + uint64_t sync0st:4; + } s; + struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; + struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_spd_abil_reg { + uint64_t u64; + struct cvmx_pcsxx_spd_abil_reg_s { + uint64_t reserved_2_63:62; + uint64_t tenpasst:1; + uint64_t tengb:1; + } s; + struct cvmx_pcsxx_spd_abil_reg_s cn52xx; + struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; + struct cvmx_pcsxx_spd_abil_reg_s cn56xx; + struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_status1_reg { + uint64_t u64; + struct cvmx_pcsxx_status1_reg_s { + uint64_t reserved_8_63:56; + uint64_t flt:1; + uint64_t reserved_3_6:4; + uint64_t rcv_lnk:1; + uint64_t lpable:1; + uint64_t reserved_0_0:1; + } s; + struct cvmx_pcsxx_status1_reg_s cn52xx; + struct cvmx_pcsxx_status1_reg_s cn52xxp1; + struct cvmx_pcsxx_status1_reg_s cn56xx; + struct cvmx_pcsxx_status1_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_status2_reg { + uint64_t u64; + struct cvmx_pcsxx_status2_reg_s { + uint64_t reserved_16_63:48; + uint64_t dev:2; + uint64_t reserved_12_13:2; + uint64_t xmtflt:1; + uint64_t rcvflt:1; + uint64_t reserved_3_9:7; + uint64_t tengb_w:1; + uint64_t tengb_x:1; + uint64_t tengb_r:1; + } s; + struct cvmx_pcsxx_status2_reg_s cn52xx; + struct cvmx_pcsxx_status2_reg_s cn52xxp1; + struct cvmx_pcsxx_status2_reg_s cn56xx; + struct cvmx_pcsxx_status2_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_tx_rx_polarity_reg { + uint64_t u64; + struct cvmx_pcsxx_tx_rx_polarity_reg_s { + uint64_t reserved_10_63:54; + uint64_t xor_rxplrt:4; + uint64_t xor_txplrt:4; + uint64_t rxplrt:1; + uint64_t txplrt:1; + } s; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { + uint64_t reserved_2_63:62; + uint64_t rxplrt:1; + uint64_t txplrt:1; + } cn52xxp1; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; +}; + +union cvmx_pcsxx_tx_rx_states_reg { + uint64_t u64; + struct cvmx_pcsxx_tx_rx_states_reg_s { + uint64_t reserved_14_63:50; + uint64_t term_err:1; + uint64_t syn3bad:1; + uint64_t syn2bad:1; + uint64_t syn1bad:1; + uint64_t syn0bad:1; + uint64_t rxbad:1; + uint64_t algn_st:3; + uint64_t rx_st:2; + uint64_t tx_st:3; + } s; + struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; + struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { + uint64_t reserved_13_63:51; + uint64_t syn3bad:1; + uint64_t syn2bad:1; + uint64_t syn1bad:1; + uint64_t syn0bad:1; + uint64_t rxbad:1; + uint64_t algn_st:3; + uint64_t rx_st:2; + uint64_t tx_st:3; + } cn52xxp1; + struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; + struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h new file mode 100644 index 000000000000..5a369100ca68 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h @@ -0,0 +1,1267 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PIP_DEFS_H__ +#define __CVMX_PIP_DEFS_H__ + +/* + * Enumeration representing the amount of packet processing + * and validation performed by the input hardware. + */ +enum cvmx_pip_port_parse_mode { + /* + * Packet input doesn't perform any processing of the input + * packet. + */ + CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, + /* + * Full packet processing is performed with pointer starting + * at the L2 (ethernet MAC) header. + */ + CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, + /* + * Input packets are assumed to be IP. Results from non IP + * packets is undefined. Pointers reference the beginning of + * the IP header. + */ + CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull +}; + +#define CVMX_PIP_BCK_PRS \ + CVMX_ADD_IO_SEG(0x00011800A0000038ull) +#define CVMX_PIP_BIST_STATUS \ + CVMX_ADD_IO_SEG(0x00011800A0000000ull) +#define CVMX_PIP_CRC_CTLX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8)) +#define CVMX_PIP_CRC_IVX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8)) +#define CVMX_PIP_DEC_IPSECX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8)) +#define CVMX_PIP_DSA_SRC_GRP \ + CVMX_ADD_IO_SEG(0x00011800A0000190ull) +#define CVMX_PIP_DSA_VID_GRP \ + CVMX_ADD_IO_SEG(0x00011800A0000198ull) +#define CVMX_PIP_FRM_LEN_CHKX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8)) +#define CVMX_PIP_GBL_CFG \ + CVMX_ADD_IO_SEG(0x00011800A0000028ull) +#define CVMX_PIP_GBL_CTL \ + CVMX_ADD_IO_SEG(0x00011800A0000020ull) +#define CVMX_PIP_HG_PRI_QOS \ + CVMX_ADD_IO_SEG(0x00011800A00001A0ull) +#define CVMX_PIP_INT_EN \ + CVMX_ADD_IO_SEG(0x00011800A0000010ull) +#define CVMX_PIP_INT_REG \ + CVMX_ADD_IO_SEG(0x00011800A0000008ull) +#define CVMX_PIP_IP_OFFSET \ + CVMX_ADD_IO_SEG(0x00011800A0000060ull) +#define CVMX_PIP_PRT_CFGX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8)) +#define CVMX_PIP_PRT_TAGX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8)) +#define CVMX_PIP_QOS_DIFFX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8)) +#define CVMX_PIP_QOS_VLANX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8)) +#define CVMX_PIP_QOS_WATCHX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8)) +#define CVMX_PIP_RAW_WORD \ + CVMX_ADD_IO_SEG(0x00011800A00000B0ull) +#define CVMX_PIP_SFT_RST \ + CVMX_ADD_IO_SEG(0x00011800A0000030ull) +#define CVMX_PIP_STAT0_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT1_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT2_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT3_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT4_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT5_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT6_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT7_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT8_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT9_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT_CTL \ + CVMX_ADD_IO_SEG(0x00011800A0000018ull) +#define CVMX_PIP_STAT_INB_ERRSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32)) +#define CVMX_PIP_STAT_INB_OCTSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32)) +#define CVMX_PIP_STAT_INB_PKTSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32)) +#define CVMX_PIP_TAG_INCX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8)) +#define CVMX_PIP_TAG_MASK \ + CVMX_ADD_IO_SEG(0x00011800A0000070ull) +#define CVMX_PIP_TAG_SECRET \ + CVMX_ADD_IO_SEG(0x00011800A0000068ull) +#define CVMX_PIP_TODO_ENTRY \ + CVMX_ADD_IO_SEG(0x00011800A0000078ull) + +union cvmx_pip_bck_prs { + uint64_t u64; + struct cvmx_pip_bck_prs_s { + uint64_t bckprs:1; + uint64_t reserved_13_62:50; + uint64_t hiwater:5; + uint64_t reserved_5_7:3; + uint64_t lowater:5; + } s; + struct cvmx_pip_bck_prs_s cn38xx; + struct cvmx_pip_bck_prs_s cn38xxp2; + struct cvmx_pip_bck_prs_s cn56xx; + struct cvmx_pip_bck_prs_s cn56xxp1; + struct cvmx_pip_bck_prs_s cn58xx; + struct cvmx_pip_bck_prs_s cn58xxp1; +}; + +union cvmx_pip_bist_status { + uint64_t u64; + struct cvmx_pip_bist_status_s { + uint64_t reserved_18_63:46; + uint64_t bist:18; + } s; + struct cvmx_pip_bist_status_s cn30xx; + struct cvmx_pip_bist_status_s cn31xx; + struct cvmx_pip_bist_status_s cn38xx; + struct cvmx_pip_bist_status_s cn38xxp2; + struct cvmx_pip_bist_status_cn50xx { + uint64_t reserved_17_63:47; + uint64_t bist:17; + } cn50xx; + struct cvmx_pip_bist_status_s cn52xx; + struct cvmx_pip_bist_status_s cn52xxp1; + struct cvmx_pip_bist_status_s cn56xx; + struct cvmx_pip_bist_status_s cn56xxp1; + struct cvmx_pip_bist_status_s cn58xx; + struct cvmx_pip_bist_status_s cn58xxp1; +}; + +union cvmx_pip_crc_ctlx { + uint64_t u64; + struct cvmx_pip_crc_ctlx_s { + uint64_t reserved_2_63:62; + uint64_t invres:1; + uint64_t reflect:1; + } s; + struct cvmx_pip_crc_ctlx_s cn38xx; + struct cvmx_pip_crc_ctlx_s cn38xxp2; + struct cvmx_pip_crc_ctlx_s cn58xx; + struct cvmx_pip_crc_ctlx_s cn58xxp1; +}; + +union cvmx_pip_crc_ivx { + uint64_t u64; + struct cvmx_pip_crc_ivx_s { + uint64_t reserved_32_63:32; + uint64_t iv:32; + } s; + struct cvmx_pip_crc_ivx_s cn38xx; + struct cvmx_pip_crc_ivx_s cn38xxp2; + struct cvmx_pip_crc_ivx_s cn58xx; + struct cvmx_pip_crc_ivx_s cn58xxp1; +}; + +union cvmx_pip_dec_ipsecx { + uint64_t u64; + struct cvmx_pip_dec_ipsecx_s { + uint64_t reserved_18_63:46; + uint64_t tcp:1; + uint64_t udp:1; + uint64_t dprt:16; + } s; + struct cvmx_pip_dec_ipsecx_s cn30xx; + struct cvmx_pip_dec_ipsecx_s cn31xx; + struct cvmx_pip_dec_ipsecx_s cn38xx; + struct cvmx_pip_dec_ipsecx_s cn38xxp2; + struct cvmx_pip_dec_ipsecx_s cn50xx; + struct cvmx_pip_dec_ipsecx_s cn52xx; + struct cvmx_pip_dec_ipsecx_s cn52xxp1; + struct cvmx_pip_dec_ipsecx_s cn56xx; + struct cvmx_pip_dec_ipsecx_s cn56xxp1; + struct cvmx_pip_dec_ipsecx_s cn58xx; + struct cvmx_pip_dec_ipsecx_s cn58xxp1; +}; + +union cvmx_pip_dsa_src_grp { + uint64_t u64; + struct cvmx_pip_dsa_src_grp_s { + uint64_t map15:4; + uint64_t map14:4; + uint64_t map13:4; + uint64_t map12:4; + uint64_t map11:4; + uint64_t map10:4; + uint64_t map9:4; + uint64_t map8:4; + uint64_t map7:4; + uint64_t map6:4; + uint64_t map5:4; + uint64_t map4:4; + uint64_t map3:4; + uint64_t map2:4; + uint64_t map1:4; + uint64_t map0:4; + } s; + struct cvmx_pip_dsa_src_grp_s cn52xx; + struct cvmx_pip_dsa_src_grp_s cn52xxp1; + struct cvmx_pip_dsa_src_grp_s cn56xx; +}; + +union cvmx_pip_dsa_vid_grp { + uint64_t u64; + struct cvmx_pip_dsa_vid_grp_s { + uint64_t map15:4; + uint64_t map14:4; + uint64_t map13:4; + uint64_t map12:4; + uint64_t map11:4; + uint64_t map10:4; + uint64_t map9:4; + uint64_t map8:4; + uint64_t map7:4; + uint64_t map6:4; + uint64_t map5:4; + uint64_t map4:4; + uint64_t map3:4; + uint64_t map2:4; + uint64_t map1:4; + uint64_t map0:4; + } s; + struct cvmx_pip_dsa_vid_grp_s cn52xx; + struct cvmx_pip_dsa_vid_grp_s cn52xxp1; + struct cvmx_pip_dsa_vid_grp_s cn56xx; +}; + +union cvmx_pip_frm_len_chkx { + uint64_t u64; + struct cvmx_pip_frm_len_chkx_s { + uint64_t reserved_32_63:32; + uint64_t maxlen:16; + uint64_t minlen:16; + } s; + struct cvmx_pip_frm_len_chkx_s cn50xx; + struct cvmx_pip_frm_len_chkx_s cn52xx; + struct cvmx_pip_frm_len_chkx_s cn52xxp1; + struct cvmx_pip_frm_len_chkx_s cn56xx; + struct cvmx_pip_frm_len_chkx_s cn56xxp1; +}; + +union cvmx_pip_gbl_cfg { + uint64_t u64; + struct cvmx_pip_gbl_cfg_s { + uint64_t reserved_19_63:45; + uint64_t tag_syn:1; + uint64_t ip6_udp:1; + uint64_t max_l2:1; + uint64_t reserved_11_15:5; + uint64_t raw_shf:3; + uint64_t reserved_3_7:5; + uint64_t nip_shf:3; + } s; + struct cvmx_pip_gbl_cfg_s cn30xx; + struct cvmx_pip_gbl_cfg_s cn31xx; + struct cvmx_pip_gbl_cfg_s cn38xx; + struct cvmx_pip_gbl_cfg_s cn38xxp2; + struct cvmx_pip_gbl_cfg_s cn50xx; + struct cvmx_pip_gbl_cfg_s cn52xx; + struct cvmx_pip_gbl_cfg_s cn52xxp1; + struct cvmx_pip_gbl_cfg_s cn56xx; + struct cvmx_pip_gbl_cfg_s cn56xxp1; + struct cvmx_pip_gbl_cfg_s cn58xx; + struct cvmx_pip_gbl_cfg_s cn58xxp1; +}; + +union cvmx_pip_gbl_ctl { + uint64_t u64; + struct cvmx_pip_gbl_ctl_s { + uint64_t reserved_27_63:37; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_21_23:3; + uint64_t ring_en:1; + uint64_t reserved_17_19:3; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; + } s; + struct cvmx_pip_gbl_ctl_cn30xx { + uint64_t reserved_17_63:47; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; + } cn30xx; + struct cvmx_pip_gbl_ctl_cn30xx cn31xx; + struct cvmx_pip_gbl_ctl_cn30xx cn38xx; + struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; + struct cvmx_pip_gbl_ctl_cn30xx cn50xx; + struct cvmx_pip_gbl_ctl_s cn52xx; + struct cvmx_pip_gbl_ctl_s cn52xxp1; + struct cvmx_pip_gbl_ctl_s cn56xx; + struct cvmx_pip_gbl_ctl_cn56xxp1 { + uint64_t reserved_21_63:43; + uint64_t ring_en:1; + uint64_t reserved_17_19:3; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; + } cn56xxp1; + struct cvmx_pip_gbl_ctl_cn30xx cn58xx; + struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; +}; + +union cvmx_pip_hg_pri_qos { + uint64_t u64; + struct cvmx_pip_hg_pri_qos_s { + uint64_t reserved_11_63:53; + uint64_t qos:3; + uint64_t reserved_6_7:2; + uint64_t pri:6; + } s; + struct cvmx_pip_hg_pri_qos_s cn52xx; + struct cvmx_pip_hg_pri_qos_s cn52xxp1; + struct cvmx_pip_hg_pri_qos_s cn56xx; +}; + +union cvmx_pip_int_en { + uint64_t u64; + struct cvmx_pip_int_en_s { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } s; + struct cvmx_pip_int_en_cn30xx { + uint64_t reserved_9_63:55; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn30xx; + struct cvmx_pip_int_en_cn30xx cn31xx; + struct cvmx_pip_int_en_cn30xx cn38xx; + struct cvmx_pip_int_en_cn30xx cn38xxp2; + struct cvmx_pip_int_en_cn50xx { + uint64_t reserved_12_63:52; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t reserved_1_1:1; + uint64_t pktdrp:1; + } cn50xx; + struct cvmx_pip_int_en_cn52xx { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t reserved_1_1:1; + uint64_t pktdrp:1; + } cn52xx; + struct cvmx_pip_int_en_cn52xx cn52xxp1; + struct cvmx_pip_int_en_s cn56xx; + struct cvmx_pip_int_en_cn56xxp1 { + uint64_t reserved_12_63:52; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn56xxp1; + struct cvmx_pip_int_en_cn58xx { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t reserved_9_11:3; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn58xx; + struct cvmx_pip_int_en_cn30xx cn58xxp1; +}; + +union cvmx_pip_int_reg { + uint64_t u64; + struct cvmx_pip_int_reg_s { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } s; + struct cvmx_pip_int_reg_cn30xx { + uint64_t reserved_9_63:55; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn30xx; + struct cvmx_pip_int_reg_cn30xx cn31xx; + struct cvmx_pip_int_reg_cn30xx cn38xx; + struct cvmx_pip_int_reg_cn30xx cn38xxp2; + struct cvmx_pip_int_reg_cn50xx { + uint64_t reserved_12_63:52; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t reserved_1_1:1; + uint64_t pktdrp:1; + } cn50xx; + struct cvmx_pip_int_reg_cn52xx { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t reserved_1_1:1; + uint64_t pktdrp:1; + } cn52xx; + struct cvmx_pip_int_reg_cn52xx cn52xxp1; + struct cvmx_pip_int_reg_s cn56xx; + struct cvmx_pip_int_reg_cn56xxp1 { + uint64_t reserved_12_63:52; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn56xxp1; + struct cvmx_pip_int_reg_cn58xx { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t reserved_9_11:3; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn58xx; + struct cvmx_pip_int_reg_cn30xx cn58xxp1; +}; + +union cvmx_pip_ip_offset { + uint64_t u64; + struct cvmx_pip_ip_offset_s { + uint64_t reserved_3_63:61; + uint64_t offset:3; + } s; + struct cvmx_pip_ip_offset_s cn30xx; + struct cvmx_pip_ip_offset_s cn31xx; + struct cvmx_pip_ip_offset_s cn38xx; + struct cvmx_pip_ip_offset_s cn38xxp2; + struct cvmx_pip_ip_offset_s cn50xx; + struct cvmx_pip_ip_offset_s cn52xx; + struct cvmx_pip_ip_offset_s cn52xxp1; + struct cvmx_pip_ip_offset_s cn56xx; + struct cvmx_pip_ip_offset_s cn56xxp1; + struct cvmx_pip_ip_offset_s cn58xx; + struct cvmx_pip_ip_offset_s cn58xxp1; +}; + +union cvmx_pip_prt_cfgx { + uint64_t u64; + struct cvmx_pip_prt_cfgx_s { + uint64_t reserved_53_63:11; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t lenerr_en:1; + uint64_t maxerr_en:1; + uint64_t minerr_en:1; + uint64_t grp_wat_47:4; + uint64_t qos_wat_47:4; + uint64_t reserved_37_39:3; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t hg_qos:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t qos_vsel:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t higig_en:1; + uint64_t dsa_en:1; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } s; + struct cvmx_pip_prt_cfgx_cn30xx { + uint64_t reserved_37_63:27; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t reserved_27_27:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_18_19:2; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_10_15:6; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } cn30xx; + struct cvmx_pip_prt_cfgx_cn30xx cn31xx; + struct cvmx_pip_prt_cfgx_cn38xx { + uint64_t reserved_37_63:27; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t reserved_27_27:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_18_19:2; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t reserved_10_11:2; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } cn38xx; + struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; + struct cvmx_pip_prt_cfgx_cn50xx { + uint64_t reserved_53_63:11; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t lenerr_en:1; + uint64_t maxerr_en:1; + uint64_t minerr_en:1; + uint64_t grp_wat_47:4; + uint64_t qos_wat_47:4; + uint64_t reserved_37_39:3; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t reserved_27_27:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_19_19:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t reserved_10_11:2; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } cn50xx; + struct cvmx_pip_prt_cfgx_s cn52xx; + struct cvmx_pip_prt_cfgx_s cn52xxp1; + struct cvmx_pip_prt_cfgx_s cn56xx; + struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; + struct cvmx_pip_prt_cfgx_cn58xx { + uint64_t reserved_37_63:27; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t reserved_27_27:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_19_19:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t reserved_10_11:2; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } cn58xx; + struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; +}; + +union cvmx_pip_prt_tagx { + uint64_t u64; + struct cvmx_pip_prt_tagx_s { + uint64_t reserved_40_63:24; + uint64_t grptagbase:4; + uint64_t grptagmask:4; + uint64_t grptag:1; + uint64_t grptag_mskip:1; + uint64_t tag_mode:2; + uint64_t inc_vs:2; + uint64_t inc_vlan:1; + uint64_t inc_prt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_src_flag:1; + uint64_t tcp6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t non_tag_type:2; + uint64_t grp:4; + } s; + struct cvmx_pip_prt_tagx_cn30xx { + uint64_t reserved_40_63:24; + uint64_t grptagbase:4; + uint64_t grptagmask:4; + uint64_t grptag:1; + uint64_t reserved_30_30:1; + uint64_t tag_mode:2; + uint64_t inc_vs:2; + uint64_t inc_vlan:1; + uint64_t inc_prt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_src_flag:1; + uint64_t tcp6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t non_tag_type:2; + uint64_t grp:4; + } cn30xx; + struct cvmx_pip_prt_tagx_cn30xx cn31xx; + struct cvmx_pip_prt_tagx_cn30xx cn38xx; + struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; + struct cvmx_pip_prt_tagx_s cn50xx; + struct cvmx_pip_prt_tagx_s cn52xx; + struct cvmx_pip_prt_tagx_s cn52xxp1; + struct cvmx_pip_prt_tagx_s cn56xx; + struct cvmx_pip_prt_tagx_s cn56xxp1; + struct cvmx_pip_prt_tagx_cn30xx cn58xx; + struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; +}; + +union cvmx_pip_qos_diffx { + uint64_t u64; + struct cvmx_pip_qos_diffx_s { + uint64_t reserved_3_63:61; + uint64_t qos:3; + } s; + struct cvmx_pip_qos_diffx_s cn30xx; + struct cvmx_pip_qos_diffx_s cn31xx; + struct cvmx_pip_qos_diffx_s cn38xx; + struct cvmx_pip_qos_diffx_s cn38xxp2; + struct cvmx_pip_qos_diffx_s cn50xx; + struct cvmx_pip_qos_diffx_s cn52xx; + struct cvmx_pip_qos_diffx_s cn52xxp1; + struct cvmx_pip_qos_diffx_s cn56xx; + struct cvmx_pip_qos_diffx_s cn56xxp1; + struct cvmx_pip_qos_diffx_s cn58xx; + struct cvmx_pip_qos_diffx_s cn58xxp1; +}; + +union cvmx_pip_qos_vlanx { + uint64_t u64; + struct cvmx_pip_qos_vlanx_s { + uint64_t reserved_7_63:57; + uint64_t qos1:3; + uint64_t reserved_3_3:1; + uint64_t qos:3; + } s; + struct cvmx_pip_qos_vlanx_cn30xx { + uint64_t reserved_3_63:61; + uint64_t qos:3; + } cn30xx; + struct cvmx_pip_qos_vlanx_cn30xx cn31xx; + struct cvmx_pip_qos_vlanx_cn30xx cn38xx; + struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2; + struct cvmx_pip_qos_vlanx_cn30xx cn50xx; + struct cvmx_pip_qos_vlanx_s cn52xx; + struct cvmx_pip_qos_vlanx_s cn52xxp1; + struct cvmx_pip_qos_vlanx_s cn56xx; + struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; + struct cvmx_pip_qos_vlanx_cn30xx cn58xx; + struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; +}; + +union cvmx_pip_qos_watchx { + uint64_t u64; + struct cvmx_pip_qos_watchx_s { + uint64_t reserved_48_63:16; + uint64_t mask:16; + uint64_t reserved_28_31:4; + uint64_t grp:4; + uint64_t reserved_23_23:1; + uint64_t qos:3; + uint64_t reserved_19_19:1; + uint64_t match_type:3; + uint64_t match_value:16; + } s; + struct cvmx_pip_qos_watchx_cn30xx { + uint64_t reserved_48_63:16; + uint64_t mask:16; + uint64_t reserved_28_31:4; + uint64_t grp:4; + uint64_t reserved_23_23:1; + uint64_t qos:3; + uint64_t reserved_18_19:2; + uint64_t match_type:2; + uint64_t match_value:16; + } cn30xx; + struct cvmx_pip_qos_watchx_cn30xx cn31xx; + struct cvmx_pip_qos_watchx_cn30xx cn38xx; + struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; + struct cvmx_pip_qos_watchx_s cn50xx; + struct cvmx_pip_qos_watchx_s cn52xx; + struct cvmx_pip_qos_watchx_s cn52xxp1; + struct cvmx_pip_qos_watchx_s cn56xx; + struct cvmx_pip_qos_watchx_s cn56xxp1; + struct cvmx_pip_qos_watchx_cn30xx cn58xx; + struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; +}; + +union cvmx_pip_raw_word { + uint64_t u64; + struct cvmx_pip_raw_word_s { + uint64_t reserved_56_63:8; + uint64_t word:56; + } s; + struct cvmx_pip_raw_word_s cn30xx; + struct cvmx_pip_raw_word_s cn31xx; + struct cvmx_pip_raw_word_s cn38xx; + struct cvmx_pip_raw_word_s cn38xxp2; + struct cvmx_pip_raw_word_s cn50xx; + struct cvmx_pip_raw_word_s cn52xx; + struct cvmx_pip_raw_word_s cn52xxp1; + struct cvmx_pip_raw_word_s cn56xx; + struct cvmx_pip_raw_word_s cn56xxp1; + struct cvmx_pip_raw_word_s cn58xx; + struct cvmx_pip_raw_word_s cn58xxp1; +}; + +union cvmx_pip_sft_rst { + uint64_t u64; + struct cvmx_pip_sft_rst_s { + uint64_t reserved_1_63:63; + uint64_t rst:1; + } s; + struct cvmx_pip_sft_rst_s cn30xx; + struct cvmx_pip_sft_rst_s cn31xx; + struct cvmx_pip_sft_rst_s cn38xx; + struct cvmx_pip_sft_rst_s cn50xx; + struct cvmx_pip_sft_rst_s cn52xx; + struct cvmx_pip_sft_rst_s cn52xxp1; + struct cvmx_pip_sft_rst_s cn56xx; + struct cvmx_pip_sft_rst_s cn56xxp1; + struct cvmx_pip_sft_rst_s cn58xx; + struct cvmx_pip_sft_rst_s cn58xxp1; +}; + +union cvmx_pip_stat0_prtx { + uint64_t u64; + struct cvmx_pip_stat0_prtx_s { + uint64_t drp_pkts:32; + uint64_t drp_octs:32; + } s; + struct cvmx_pip_stat0_prtx_s cn30xx; + struct cvmx_pip_stat0_prtx_s cn31xx; + struct cvmx_pip_stat0_prtx_s cn38xx; + struct cvmx_pip_stat0_prtx_s cn38xxp2; + struct cvmx_pip_stat0_prtx_s cn50xx; + struct cvmx_pip_stat0_prtx_s cn52xx; + struct cvmx_pip_stat0_prtx_s cn52xxp1; + struct cvmx_pip_stat0_prtx_s cn56xx; + struct cvmx_pip_stat0_prtx_s cn56xxp1; + struct cvmx_pip_stat0_prtx_s cn58xx; + struct cvmx_pip_stat0_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat1_prtx { + uint64_t u64; + struct cvmx_pip_stat1_prtx_s { + uint64_t reserved_48_63:16; + uint64_t octs:48; + } s; + struct cvmx_pip_stat1_prtx_s cn30xx; + struct cvmx_pip_stat1_prtx_s cn31xx; + struct cvmx_pip_stat1_prtx_s cn38xx; + struct cvmx_pip_stat1_prtx_s cn38xxp2; + struct cvmx_pip_stat1_prtx_s cn50xx; + struct cvmx_pip_stat1_prtx_s cn52xx; + struct cvmx_pip_stat1_prtx_s cn52xxp1; + struct cvmx_pip_stat1_prtx_s cn56xx; + struct cvmx_pip_stat1_prtx_s cn56xxp1; + struct cvmx_pip_stat1_prtx_s cn58xx; + struct cvmx_pip_stat1_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat2_prtx { + uint64_t u64; + struct cvmx_pip_stat2_prtx_s { + uint64_t pkts:32; + uint64_t raw:32; + } s; + struct cvmx_pip_stat2_prtx_s cn30xx; + struct cvmx_pip_stat2_prtx_s cn31xx; + struct cvmx_pip_stat2_prtx_s cn38xx; + struct cvmx_pip_stat2_prtx_s cn38xxp2; + struct cvmx_pip_stat2_prtx_s cn50xx; + struct cvmx_pip_stat2_prtx_s cn52xx; + struct cvmx_pip_stat2_prtx_s cn52xxp1; + struct cvmx_pip_stat2_prtx_s cn56xx; + struct cvmx_pip_stat2_prtx_s cn56xxp1; + struct cvmx_pip_stat2_prtx_s cn58xx; + struct cvmx_pip_stat2_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat3_prtx { + uint64_t u64; + struct cvmx_pip_stat3_prtx_s { + uint64_t bcst:32; + uint64_t mcst:32; + } s; + struct cvmx_pip_stat3_prtx_s cn30xx; + struct cvmx_pip_stat3_prtx_s cn31xx; + struct cvmx_pip_stat3_prtx_s cn38xx; + struct cvmx_pip_stat3_prtx_s cn38xxp2; + struct cvmx_pip_stat3_prtx_s cn50xx; + struct cvmx_pip_stat3_prtx_s cn52xx; + struct cvmx_pip_stat3_prtx_s cn52xxp1; + struct cvmx_pip_stat3_prtx_s cn56xx; + struct cvmx_pip_stat3_prtx_s cn56xxp1; + struct cvmx_pip_stat3_prtx_s cn58xx; + struct cvmx_pip_stat3_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat4_prtx { + uint64_t u64; + struct cvmx_pip_stat4_prtx_s { + uint64_t h65to127:32; + uint64_t h64:32; + } s; + struct cvmx_pip_stat4_prtx_s cn30xx; + struct cvmx_pip_stat4_prtx_s cn31xx; + struct cvmx_pip_stat4_prtx_s cn38xx; + struct cvmx_pip_stat4_prtx_s cn38xxp2; + struct cvmx_pip_stat4_prtx_s cn50xx; + struct cvmx_pip_stat4_prtx_s cn52xx; + struct cvmx_pip_stat4_prtx_s cn52xxp1; + struct cvmx_pip_stat4_prtx_s cn56xx; + struct cvmx_pip_stat4_prtx_s cn56xxp1; + struct cvmx_pip_stat4_prtx_s cn58xx; + struct cvmx_pip_stat4_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat5_prtx { + uint64_t u64; + struct cvmx_pip_stat5_prtx_s { + uint64_t h256to511:32; + uint64_t h128to255:32; + } s; + struct cvmx_pip_stat5_prtx_s cn30xx; + struct cvmx_pip_stat5_prtx_s cn31xx; + struct cvmx_pip_stat5_prtx_s cn38xx; + struct cvmx_pip_stat5_prtx_s cn38xxp2; + struct cvmx_pip_stat5_prtx_s cn50xx; + struct cvmx_pip_stat5_prtx_s cn52xx; + struct cvmx_pip_stat5_prtx_s cn52xxp1; + struct cvmx_pip_stat5_prtx_s cn56xx; + struct cvmx_pip_stat5_prtx_s cn56xxp1; + struct cvmx_pip_stat5_prtx_s cn58xx; + struct cvmx_pip_stat5_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat6_prtx { + uint64_t u64; + struct cvmx_pip_stat6_prtx_s { + uint64_t h1024to1518:32; + uint64_t h512to1023:32; + } s; + struct cvmx_pip_stat6_prtx_s cn30xx; + struct cvmx_pip_stat6_prtx_s cn31xx; + struct cvmx_pip_stat6_prtx_s cn38xx; + struct cvmx_pip_stat6_prtx_s cn38xxp2; + struct cvmx_pip_stat6_prtx_s cn50xx; + struct cvmx_pip_stat6_prtx_s cn52xx; + struct cvmx_pip_stat6_prtx_s cn52xxp1; + struct cvmx_pip_stat6_prtx_s cn56xx; + struct cvmx_pip_stat6_prtx_s cn56xxp1; + struct cvmx_pip_stat6_prtx_s cn58xx; + struct cvmx_pip_stat6_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat7_prtx { + uint64_t u64; + struct cvmx_pip_stat7_prtx_s { + uint64_t fcs:32; + uint64_t h1519:32; + } s; + struct cvmx_pip_stat7_prtx_s cn30xx; + struct cvmx_pip_stat7_prtx_s cn31xx; + struct cvmx_pip_stat7_prtx_s cn38xx; + struct cvmx_pip_stat7_prtx_s cn38xxp2; + struct cvmx_pip_stat7_prtx_s cn50xx; + struct cvmx_pip_stat7_prtx_s cn52xx; + struct cvmx_pip_stat7_prtx_s cn52xxp1; + struct cvmx_pip_stat7_prtx_s cn56xx; + struct cvmx_pip_stat7_prtx_s cn56xxp1; + struct cvmx_pip_stat7_prtx_s cn58xx; + struct cvmx_pip_stat7_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat8_prtx { + uint64_t u64; + struct cvmx_pip_stat8_prtx_s { + uint64_t frag:32; + uint64_t undersz:32; + } s; + struct cvmx_pip_stat8_prtx_s cn30xx; + struct cvmx_pip_stat8_prtx_s cn31xx; + struct cvmx_pip_stat8_prtx_s cn38xx; + struct cvmx_pip_stat8_prtx_s cn38xxp2; + struct cvmx_pip_stat8_prtx_s cn50xx; + struct cvmx_pip_stat8_prtx_s cn52xx; + struct cvmx_pip_stat8_prtx_s cn52xxp1; + struct cvmx_pip_stat8_prtx_s cn56xx; + struct cvmx_pip_stat8_prtx_s cn56xxp1; + struct cvmx_pip_stat8_prtx_s cn58xx; + struct cvmx_pip_stat8_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat9_prtx { + uint64_t u64; + struct cvmx_pip_stat9_prtx_s { + uint64_t jabber:32; + uint64_t oversz:32; + } s; + struct cvmx_pip_stat9_prtx_s cn30xx; + struct cvmx_pip_stat9_prtx_s cn31xx; + struct cvmx_pip_stat9_prtx_s cn38xx; + struct cvmx_pip_stat9_prtx_s cn38xxp2; + struct cvmx_pip_stat9_prtx_s cn50xx; + struct cvmx_pip_stat9_prtx_s cn52xx; + struct cvmx_pip_stat9_prtx_s cn52xxp1; + struct cvmx_pip_stat9_prtx_s cn56xx; + struct cvmx_pip_stat9_prtx_s cn56xxp1; + struct cvmx_pip_stat9_prtx_s cn58xx; + struct cvmx_pip_stat9_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat_ctl { + uint64_t u64; + struct cvmx_pip_stat_ctl_s { + uint64_t reserved_1_63:63; + uint64_t rdclr:1; + } s; + struct cvmx_pip_stat_ctl_s cn30xx; + struct cvmx_pip_stat_ctl_s cn31xx; + struct cvmx_pip_stat_ctl_s cn38xx; + struct cvmx_pip_stat_ctl_s cn38xxp2; + struct cvmx_pip_stat_ctl_s cn50xx; + struct cvmx_pip_stat_ctl_s cn52xx; + struct cvmx_pip_stat_ctl_s cn52xxp1; + struct cvmx_pip_stat_ctl_s cn56xx; + struct cvmx_pip_stat_ctl_s cn56xxp1; + struct cvmx_pip_stat_ctl_s cn58xx; + struct cvmx_pip_stat_ctl_s cn58xxp1; +}; + +union cvmx_pip_stat_inb_errsx { + uint64_t u64; + struct cvmx_pip_stat_inb_errsx_s { + uint64_t reserved_16_63:48; + uint64_t errs:16; + } s; + struct cvmx_pip_stat_inb_errsx_s cn30xx; + struct cvmx_pip_stat_inb_errsx_s cn31xx; + struct cvmx_pip_stat_inb_errsx_s cn38xx; + struct cvmx_pip_stat_inb_errsx_s cn38xxp2; + struct cvmx_pip_stat_inb_errsx_s cn50xx; + struct cvmx_pip_stat_inb_errsx_s cn52xx; + struct cvmx_pip_stat_inb_errsx_s cn52xxp1; + struct cvmx_pip_stat_inb_errsx_s cn56xx; + struct cvmx_pip_stat_inb_errsx_s cn56xxp1; + struct cvmx_pip_stat_inb_errsx_s cn58xx; + struct cvmx_pip_stat_inb_errsx_s cn58xxp1; +}; + +union cvmx_pip_stat_inb_octsx { + uint64_t u64; + struct cvmx_pip_stat_inb_octsx_s { + uint64_t reserved_48_63:16; + uint64_t octs:48; + } s; + struct cvmx_pip_stat_inb_octsx_s cn30xx; + struct cvmx_pip_stat_inb_octsx_s cn31xx; + struct cvmx_pip_stat_inb_octsx_s cn38xx; + struct cvmx_pip_stat_inb_octsx_s cn38xxp2; + struct cvmx_pip_stat_inb_octsx_s cn50xx; + struct cvmx_pip_stat_inb_octsx_s cn52xx; + struct cvmx_pip_stat_inb_octsx_s cn52xxp1; + struct cvmx_pip_stat_inb_octsx_s cn56xx; + struct cvmx_pip_stat_inb_octsx_s cn56xxp1; + struct cvmx_pip_stat_inb_octsx_s cn58xx; + struct cvmx_pip_stat_inb_octsx_s cn58xxp1; +}; + +union cvmx_pip_stat_inb_pktsx { + uint64_t u64; + struct cvmx_pip_stat_inb_pktsx_s { + uint64_t reserved_32_63:32; + uint64_t pkts:32; + } s; + struct cvmx_pip_stat_inb_pktsx_s cn30xx; + struct cvmx_pip_stat_inb_pktsx_s cn31xx; + struct cvmx_pip_stat_inb_pktsx_s cn38xx; + struct cvmx_pip_stat_inb_pktsx_s cn38xxp2; + struct cvmx_pip_stat_inb_pktsx_s cn50xx; + struct cvmx_pip_stat_inb_pktsx_s cn52xx; + struct cvmx_pip_stat_inb_pktsx_s cn52xxp1; + struct cvmx_pip_stat_inb_pktsx_s cn56xx; + struct cvmx_pip_stat_inb_pktsx_s cn56xxp1; + struct cvmx_pip_stat_inb_pktsx_s cn58xx; + struct cvmx_pip_stat_inb_pktsx_s cn58xxp1; +}; + +union cvmx_pip_tag_incx { + uint64_t u64; + struct cvmx_pip_tag_incx_s { + uint64_t reserved_8_63:56; + uint64_t en:8; + } s; + struct cvmx_pip_tag_incx_s cn30xx; + struct cvmx_pip_tag_incx_s cn31xx; + struct cvmx_pip_tag_incx_s cn38xx; + struct cvmx_pip_tag_incx_s cn38xxp2; + struct cvmx_pip_tag_incx_s cn50xx; + struct cvmx_pip_tag_incx_s cn52xx; + struct cvmx_pip_tag_incx_s cn52xxp1; + struct cvmx_pip_tag_incx_s cn56xx; + struct cvmx_pip_tag_incx_s cn56xxp1; + struct cvmx_pip_tag_incx_s cn58xx; + struct cvmx_pip_tag_incx_s cn58xxp1; +}; + +union cvmx_pip_tag_mask { + uint64_t u64; + struct cvmx_pip_tag_mask_s { + uint64_t reserved_16_63:48; + uint64_t mask:16; + } s; + struct cvmx_pip_tag_mask_s cn30xx; + struct cvmx_pip_tag_mask_s cn31xx; + struct cvmx_pip_tag_mask_s cn38xx; + struct cvmx_pip_tag_mask_s cn38xxp2; + struct cvmx_pip_tag_mask_s cn50xx; + struct cvmx_pip_tag_mask_s cn52xx; + struct cvmx_pip_tag_mask_s cn52xxp1; + struct cvmx_pip_tag_mask_s cn56xx; + struct cvmx_pip_tag_mask_s cn56xxp1; + struct cvmx_pip_tag_mask_s cn58xx; + struct cvmx_pip_tag_mask_s cn58xxp1; +}; + +union cvmx_pip_tag_secret { + uint64_t u64; + struct cvmx_pip_tag_secret_s { + uint64_t reserved_32_63:32; + uint64_t dst:16; + uint64_t src:16; + } s; + struct cvmx_pip_tag_secret_s cn30xx; + struct cvmx_pip_tag_secret_s cn31xx; + struct cvmx_pip_tag_secret_s cn38xx; + struct cvmx_pip_tag_secret_s cn38xxp2; + struct cvmx_pip_tag_secret_s cn50xx; + struct cvmx_pip_tag_secret_s cn52xx; + struct cvmx_pip_tag_secret_s cn52xxp1; + struct cvmx_pip_tag_secret_s cn56xx; + struct cvmx_pip_tag_secret_s cn56xxp1; + struct cvmx_pip_tag_secret_s cn58xx; + struct cvmx_pip_tag_secret_s cn58xxp1; +}; + +union cvmx_pip_todo_entry { + uint64_t u64; + struct cvmx_pip_todo_entry_s { + uint64_t val:1; + uint64_t reserved_62_62:1; + uint64_t entry:62; + } s; + struct cvmx_pip_todo_entry_s cn30xx; + struct cvmx_pip_todo_entry_s cn31xx; + struct cvmx_pip_todo_entry_s cn38xx; + struct cvmx_pip_todo_entry_s cn38xxp2; + struct cvmx_pip_todo_entry_s cn50xx; + struct cvmx_pip_todo_entry_s cn52xx; + struct cvmx_pip_todo_entry_s cn52xxp1; + struct cvmx_pip_todo_entry_s cn56xx; + struct cvmx_pip_todo_entry_s cn56xxp1; + struct cvmx_pip_todo_entry_s cn58xx; + struct cvmx_pip_todo_entry_s cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h new file mode 100644 index 000000000000..78dbce8f2c5e --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pip.h @@ -0,0 +1,524 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Interface to the hardware Packet Input Processing unit. + * + */ + +#ifndef __CVMX_PIP_H__ +#define __CVMX_PIP_H__ + +#include "cvmx-wqe.h" +#include "cvmx-fpa.h" +#include "cvmx-pip-defs.h" + +#define CVMX_PIP_NUM_INPUT_PORTS 40 +#define CVMX_PIP_NUM_WATCHERS 4 + +/* + * Encodes the different error and exception codes + */ +typedef enum { + CVMX_PIP_L4_NO_ERR = 0ull, + /* + * 1 = TCP (UDP) packet not long enough to cover TCP (UDP) + * header + */ + CVMX_PIP_L4_MAL_ERR = 1ull, + /* 2 = TCP/UDP checksum failure */ + CVMX_PIP_CHK_ERR = 2ull, + /* + * 3 = TCP/UDP length check (TCP/UDP length does not match IP + * length). + */ + CVMX_PIP_L4_LENGTH_ERR = 3ull, + /* 4 = illegal TCP/UDP port (either source or dest port is zero) */ + CVMX_PIP_BAD_PRT_ERR = 4ull, + /* 8 = TCP flags = FIN only */ + CVMX_PIP_TCP_FLG8_ERR = 8ull, + /* 9 = TCP flags = 0 */ + CVMX_PIP_TCP_FLG9_ERR = 9ull, + /* 10 = TCP flags = FIN+RST+* */ + CVMX_PIP_TCP_FLG10_ERR = 10ull, + /* 11 = TCP flags = SYN+URG+* */ + CVMX_PIP_TCP_FLG11_ERR = 11ull, + /* 12 = TCP flags = SYN+RST+* */ + CVMX_PIP_TCP_FLG12_ERR = 12ull, + /* 13 = TCP flags = SYN+FIN+* */ + CVMX_PIP_TCP_FLG13_ERR = 13ull +} cvmx_pip_l4_err_t; + +typedef enum { + + CVMX_PIP_IP_NO_ERR = 0ull, + /* 1 = not IPv4 or IPv6 */ + CVMX_PIP_NOT_IP = 1ull, + /* 2 = IPv4 header checksum violation */ + CVMX_PIP_IPV4_HDR_CHK = 2ull, + /* 3 = malformed (packet not long enough to cover IP hdr) */ + CVMX_PIP_IP_MAL_HDR = 3ull, + /* 4 = malformed (packet not long enough to cover len in IP hdr) */ + CVMX_PIP_IP_MAL_PKT = 4ull, + /* 5 = TTL / hop count equal zero */ + CVMX_PIP_TTL_HOP = 5ull, + /* 6 = IPv4 options / IPv6 early extension headers */ + CVMX_PIP_OPTS = 6ull +} cvmx_pip_ip_exc_t; + +/** + * NOTES + * late collision (data received before collision) + * late collisions cannot be detected by the receiver + * they would appear as JAM bits which would appear as bad FCS + * or carrier extend error which is CVMX_PIP_EXTEND_ERR + */ +typedef enum { + /* No error */ + CVMX_PIP_RX_NO_ERR = 0ull, + /* RGM+SPI 1 = partially received packet (buffering/bandwidth + * not adequate) */ + CVMX_PIP_PARTIAL_ERR = 1ull, + /* RGM+SPI 2 = receive packet too large and truncated */ + CVMX_PIP_JABBER_ERR = 2ull, + /* + * RGM 3 = max frame error (pkt len > max frame len) (with FCS + * error) + */ + CVMX_PIP_OVER_FCS_ERR = 3ull, + /* RGM+SPI 4 = max frame error (pkt len > max frame len) */ + CVMX_PIP_OVER_ERR = 4ull, + /* + * RGM 5 = nibble error (data not byte multiple - 100M and 10M + * only) + */ + CVMX_PIP_ALIGN_ERR = 5ull, + /* + * RGM 6 = min frame error (pkt len < min frame len) (with FCS + * error) + */ + CVMX_PIP_UNDER_FCS_ERR = 6ull, + /* RGM 7 = FCS error */ + CVMX_PIP_GMX_FCS_ERR = 7ull, + /* RGM+SPI 8 = min frame error (pkt len < min frame len) */ + CVMX_PIP_UNDER_ERR = 8ull, + /* RGM 9 = Frame carrier extend error */ + CVMX_PIP_EXTEND_ERR = 9ull, + /* + * RGM 10 = length mismatch (len did not match len in L2 + * length/type) + */ + CVMX_PIP_LENGTH_ERR = 10ull, + /* RGM 11 = Frame error (some or all data bits marked err) */ + CVMX_PIP_DAT_ERR = 11ull, + /* SPI 11 = DIP4 error */ + CVMX_PIP_DIP_ERR = 11ull, + /* + * RGM 12 = packet was not large enough to pass the skipper - + * no inspection could occur. + */ + CVMX_PIP_SKIP_ERR = 12ull, + /* + * RGM 13 = studder error (data not repeated - 100M and 10M + * only) + */ + CVMX_PIP_NIBBLE_ERR = 13ull, + /* RGM+SPI 16 = FCS error */ + CVMX_PIP_PIP_FCS = 16L, + /* + * RGM+SPI+PCI 17 = packet was not large enough to pass the + * skipper - no inspection could occur. + */ + CVMX_PIP_PIP_SKIP_ERR = 17L, + /* + * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to + * cover L2 hdr). + */ + CVMX_PIP_PIP_L2_MAL_HDR = 18L + /* + * NOTES: xx = late collision (data received before collision) + * late collisions cannot be detected by the receiver + * they would appear as JAM bits which would appear as + * bad FCS or carrier extend error which is + * CVMX_PIP_EXTEND_ERR + */ +} cvmx_pip_rcv_err_t; + +/** + * This defines the err_code field errors in the work Q entry + */ +typedef union { + cvmx_pip_l4_err_t l4_err; + cvmx_pip_ip_exc_t ip_exc; + cvmx_pip_rcv_err_t rcv_err; +} cvmx_pip_err_t; + +/** + * Status statistics for a port + */ +typedef struct { + /* Inbound octets marked to be dropped by the IPD */ + uint32_t dropped_octets; + /* Inbound packets marked to be dropped by the IPD */ + uint32_t dropped_packets; + /* RAW PCI Packets received by PIP per port */ + uint32_t pci_raw_packets; + /* Number of octets processed by PIP */ + uint32_t octets; + /* Number of packets processed by PIP */ + uint32_t packets; + /* + * Number of indentified L2 multicast packets. Does not + * include broadcast packets. Only includes packets whose + * parse mode is SKIP_TO_L2 + */ + uint32_t multicast_packets; + /* + * Number of indentified L2 broadcast packets. Does not + * include multicast packets. Only includes packets whose + * parse mode is SKIP_TO_L2 + */ + uint32_t broadcast_packets; + /* Number of 64B packets */ + uint32_t len_64_packets; + /* Number of 65-127B packets */ + uint32_t len_65_127_packets; + /* Number of 128-255B packets */ + uint32_t len_128_255_packets; + /* Number of 256-511B packets */ + uint32_t len_256_511_packets; + /* Number of 512-1023B packets */ + uint32_t len_512_1023_packets; + /* Number of 1024-1518B packets */ + uint32_t len_1024_1518_packets; + /* Number of 1519-max packets */ + uint32_t len_1519_max_packets; + /* Number of packets with FCS or Align opcode errors */ + uint32_t fcs_align_err_packets; + /* Number of packets with length < min */ + uint32_t runt_packets; + /* Number of packets with length < min and FCS error */ + uint32_t runt_crc_packets; + /* Number of packets with length > max */ + uint32_t oversize_packets; + /* Number of packets with length > max and FCS error */ + uint32_t oversize_crc_packets; + /* Number of packets without GMX/SPX/PCI errors received by PIP */ + uint32_t inb_packets; + /* + * Total number of octets from all packets received by PIP, + * including CRC + */ + uint64_t inb_octets; + /* Number of packets with GMX/SPX/PCI errors received by PIP */ + uint16_t inb_errors; +} cvmx_pip_port_status_t; + +/** + * Definition of the PIP custom header that can be prepended + * to a packet by external hardware. + */ +typedef union { + uint64_t u64; + struct { + /* + * Documented as R - Set if the Packet is RAWFULL. If + * set, this header must be the full 8 bytes. + */ + uint64_t rawfull:1; + /* Must be zero */ + uint64_t reserved0:5; + /* PIP parse mode for this packet */ + uint64_t parse_mode:2; + /* Must be zero */ + uint64_t reserved1:1; + /* + * Skip amount, including this header, to the + * beginning of the packet + */ + uint64_t skip_len:7; + /* Must be zero */ + uint64_t reserved2:6; + /* POW input queue for this packet */ + uint64_t qos:3; + /* POW input group for this packet */ + uint64_t grp:4; + /* + * Flag to store this packet in the work queue entry, + * if possible + */ + uint64_t rs:1; + /* POW input tag type */ + uint64_t tag_type:2; + /* POW input tag */ + uint64_t tag:32; + } s; +} cvmx_pip_pkt_inst_hdr_t; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Configure an ethernet input port + * + * @port_num: Port number to configure + * @port_cfg: Port hardware configuration + * @port_tag_cfg: + * Port POW tagging configuration + */ +static inline void cvmx_pip_config_port(uint64_t port_num, + union cvmx_pip_prt_cfgx port_cfg, + union cvmx_pip_prt_tagx port_tag_cfg) +{ + cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); + cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); +} +#if 0 +/** + * @deprecated This function is a thin wrapper around the Pass1 version + * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for + * setting the group that is incompatible with this function, + * the preferred upgrade path is to use the CSR directly. + * + * Configure the global QoS packet watchers. Each watcher is + * capable of matching a field in a packet to determine the + * QoS queue for scheduling. + * + * @watcher: Watcher number to configure (0 - 3). + * @match_type: Watcher match type + * @match_value: + * Value the watcher will match against + * @qos: QoS queue for packets matching this watcher + */ +static inline void cvmx_pip_config_watcher(uint64_t watcher, + cvmx_pip_qos_watch_types match_type, + uint64_t match_value, uint64_t qos) +{ + cvmx_pip_port_watcher_cfg_t watcher_config; + + watcher_config.u64 = 0; + watcher_config.s.match_type = match_type; + watcher_config.s.match_value = match_value; + watcher_config.s.qos = qos; + + cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64); +} +#endif +/** + * Configure the VLAN priority to QoS queue mapping. + * + * @vlan_priority: + * VLAN priority (0-7) + * @qos: QoS queue for packets matching this watcher + */ +static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, + uint64_t qos) +{ + union cvmx_pip_qos_vlanx pip_qos_vlanx; + pip_qos_vlanx.u64 = 0; + pip_qos_vlanx.s.qos = qos; + cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); +} + +/** + * Configure the Diffserv to QoS queue mapping. + * + * @diffserv: Diffserv field value (0-63) + * @qos: QoS queue for packets matching this watcher + */ +static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos) +{ + union cvmx_pip_qos_diffx pip_qos_diffx; + pip_qos_diffx.u64 = 0; + pip_qos_diffx.s.qos = qos; + cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); +} + +/** + * Get the status counters for a port. + * + * @port_num: Port number to get statistics for. + * @clear: Set to 1 to clear the counters after they are read + * @status: Where to put the results. + */ +static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, + cvmx_pip_port_status_t *status) +{ + union cvmx_pip_stat_ctl pip_stat_ctl; + union cvmx_pip_stat0_prtx stat0; + union cvmx_pip_stat1_prtx stat1; + union cvmx_pip_stat2_prtx stat2; + union cvmx_pip_stat3_prtx stat3; + union cvmx_pip_stat4_prtx stat4; + union cvmx_pip_stat5_prtx stat5; + union cvmx_pip_stat6_prtx stat6; + union cvmx_pip_stat7_prtx stat7; + union cvmx_pip_stat8_prtx stat8; + union cvmx_pip_stat9_prtx stat9; + union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx; + union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx; + union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx; + + pip_stat_ctl.u64 = 0; + pip_stat_ctl.s.rdclr = clear; + cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); + + stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num)); + stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num)); + stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num)); + stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num)); + stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num)); + stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num)); + stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num)); + stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num)); + stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num)); + stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num)); + pip_stat_inb_pktsx.u64 = + cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num)); + pip_stat_inb_octsx.u64 = + cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num)); + pip_stat_inb_errsx.u64 = + cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num)); + + status->dropped_octets = stat0.s.drp_octs; + status->dropped_packets = stat0.s.drp_pkts; + status->octets = stat1.s.octs; + status->pci_raw_packets = stat2.s.raw; + status->packets = stat2.s.pkts; + status->multicast_packets = stat3.s.mcst; + status->broadcast_packets = stat3.s.bcst; + status->len_64_packets = stat4.s.h64; + status->len_65_127_packets = stat4.s.h65to127; + status->len_128_255_packets = stat5.s.h128to255; + status->len_256_511_packets = stat5.s.h256to511; + status->len_512_1023_packets = stat6.s.h512to1023; + status->len_1024_1518_packets = stat6.s.h1024to1518; + status->len_1519_max_packets = stat7.s.h1519; + status->fcs_align_err_packets = stat7.s.fcs; + status->runt_packets = stat8.s.undersz; + status->runt_crc_packets = stat8.s.frag; + status->oversize_packets = stat9.s.oversz; + status->oversize_crc_packets = stat9.s.jabber; + status->inb_packets = pip_stat_inb_pktsx.s.pkts; + status->inb_octets = pip_stat_inb_octsx.s.octs; + status->inb_errors = pip_stat_inb_errsx.s.errs; + + if (cvmx_octeon_is_pass1()) { + /* + * Kludge to fix Octeon Pass 1 errata - Drop counts + * don't work. + */ + if (status->inb_packets > status->packets) + status->dropped_packets = + status->inb_packets - status->packets; + else + status->dropped_packets = 0; + if (status->inb_octets - status->inb_packets * 4 > + status->octets) + status->dropped_octets = + status->inb_octets - status->inb_packets * 4 - + status->octets; + else + status->dropped_octets = 0; + } +} + +/** + * Configure the hardware CRC engine + * + * @interface: Interface to configure (0 or 1) + * @invert_result: + * Invert the result of the CRC + * @reflect: Reflect + * @initialization_vector: + * CRC initialization vector + */ +static inline void cvmx_pip_config_crc(uint64_t interface, + uint64_t invert_result, uint64_t reflect, + uint32_t initialization_vector) +{ + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + union cvmx_pip_crc_ctlx config; + union cvmx_pip_crc_ivx pip_crc_ivx; + + config.u64 = 0; + config.s.invres = invert_result; + config.s.reflect = reflect; + cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); + + pip_crc_ivx.u64 = 0; + pip_crc_ivx.s.iv = initialization_vector; + cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); + } +} + +/** + * Clear all bits in a tag mask. This should be called on + * startup before any calls to cvmx_pip_tag_mask_set. Each bit + * set in the final mask represent a byte used in the packet for + * tag generation. + * + * @mask_index: Which tag mask to clear (0..3) + */ +static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index) +{ + uint64_t index; + union cvmx_pip_tag_incx pip_tag_incx; + pip_tag_incx.u64 = 0; + pip_tag_incx.s.en = 0; + for (index = mask_index * 16; index < (mask_index + 1) * 16; index++) + cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); +} + +/** + * Sets a range of bits in the tag mask. The tag mask is used + * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero. + * There are four separate masks that can be configured. + * + * @mask_index: Which tag mask to modify (0..3) + * @offset: Offset into the bitmask to set bits at. Use the GCC macro + * offsetof() to determine the offsets into packet headers. + * For example, offsetof(ethhdr, protocol) returns the offset + * of the ethernet protocol field. The bitmask selects which + * bytes to include the the tag, with bit offset X selecting + * byte at offset X from the beginning of the packet data. + * @len: Number of bytes to include. Usually this is the sizeof() + * the field. + */ +static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, + uint64_t len) +{ + while (len--) { + union cvmx_pip_tag_incx pip_tag_incx; + uint64_t index = mask_index * 16 + offset / 8; + pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index)); + pip_tag_incx.s.en |= 0x80 >> (offset & 0x7); + cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); + offset++; + } +} + +#endif /* __CVMX_PIP_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h new file mode 100644 index 000000000000..50e779cf1ad8 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h @@ -0,0 +1,1133 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PKO_DEFS_H__ +#define __CVMX_PKO_DEFS_H__ + +#define CVMX_PKO_MEM_COUNT0 \ + CVMX_ADD_IO_SEG(0x0001180050001080ull) +#define CVMX_PKO_MEM_COUNT1 \ + CVMX_ADD_IO_SEG(0x0001180050001088ull) +#define CVMX_PKO_MEM_DEBUG0 \ + CVMX_ADD_IO_SEG(0x0001180050001100ull) +#define CVMX_PKO_MEM_DEBUG1 \ + CVMX_ADD_IO_SEG(0x0001180050001108ull) +#define CVMX_PKO_MEM_DEBUG10 \ + CVMX_ADD_IO_SEG(0x0001180050001150ull) +#define CVMX_PKO_MEM_DEBUG11 \ + CVMX_ADD_IO_SEG(0x0001180050001158ull) +#define CVMX_PKO_MEM_DEBUG12 \ + CVMX_ADD_IO_SEG(0x0001180050001160ull) +#define CVMX_PKO_MEM_DEBUG13 \ + CVMX_ADD_IO_SEG(0x0001180050001168ull) +#define CVMX_PKO_MEM_DEBUG14 \ + CVMX_ADD_IO_SEG(0x0001180050001170ull) +#define CVMX_PKO_MEM_DEBUG2 \ + CVMX_ADD_IO_SEG(0x0001180050001110ull) +#define CVMX_PKO_MEM_DEBUG3 \ + CVMX_ADD_IO_SEG(0x0001180050001118ull) +#define CVMX_PKO_MEM_DEBUG4 \ + CVMX_ADD_IO_SEG(0x0001180050001120ull) +#define CVMX_PKO_MEM_DEBUG5 \ + CVMX_ADD_IO_SEG(0x0001180050001128ull) +#define CVMX_PKO_MEM_DEBUG6 \ + CVMX_ADD_IO_SEG(0x0001180050001130ull) +#define CVMX_PKO_MEM_DEBUG7 \ + CVMX_ADD_IO_SEG(0x0001180050001138ull) +#define CVMX_PKO_MEM_DEBUG8 \ + CVMX_ADD_IO_SEG(0x0001180050001140ull) +#define CVMX_PKO_MEM_DEBUG9 \ + CVMX_ADD_IO_SEG(0x0001180050001148ull) +#define CVMX_PKO_MEM_PORT_PTRS \ + CVMX_ADD_IO_SEG(0x0001180050001010ull) +#define CVMX_PKO_MEM_PORT_QOS \ + CVMX_ADD_IO_SEG(0x0001180050001018ull) +#define CVMX_PKO_MEM_PORT_RATE0 \ + CVMX_ADD_IO_SEG(0x0001180050001020ull) +#define CVMX_PKO_MEM_PORT_RATE1 \ + CVMX_ADD_IO_SEG(0x0001180050001028ull) +#define CVMX_PKO_MEM_QUEUE_PTRS \ + CVMX_ADD_IO_SEG(0x0001180050001000ull) +#define CVMX_PKO_MEM_QUEUE_QOS \ + CVMX_ADD_IO_SEG(0x0001180050001008ull) +#define CVMX_PKO_REG_BIST_RESULT \ + CVMX_ADD_IO_SEG(0x0001180050000080ull) +#define CVMX_PKO_REG_CMD_BUF \ + CVMX_ADD_IO_SEG(0x0001180050000010ull) +#define CVMX_PKO_REG_CRC_CTLX(offset) \ + CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8)) +#define CVMX_PKO_REG_CRC_ENABLE \ + CVMX_ADD_IO_SEG(0x0001180050000020ull) +#define CVMX_PKO_REG_CRC_IVX(offset) \ + CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8)) +#define CVMX_PKO_REG_DEBUG0 \ + CVMX_ADD_IO_SEG(0x0001180050000098ull) +#define CVMX_PKO_REG_DEBUG1 \ + CVMX_ADD_IO_SEG(0x00011800500000A0ull) +#define CVMX_PKO_REG_DEBUG2 \ + CVMX_ADD_IO_SEG(0x00011800500000A8ull) +#define CVMX_PKO_REG_DEBUG3 \ + CVMX_ADD_IO_SEG(0x00011800500000B0ull) +#define CVMX_PKO_REG_ENGINE_INFLIGHT \ + CVMX_ADD_IO_SEG(0x0001180050000050ull) +#define CVMX_PKO_REG_ENGINE_THRESH \ + CVMX_ADD_IO_SEG(0x0001180050000058ull) +#define CVMX_PKO_REG_ERROR \ + CVMX_ADD_IO_SEG(0x0001180050000088ull) +#define CVMX_PKO_REG_FLAGS \ + CVMX_ADD_IO_SEG(0x0001180050000000ull) +#define CVMX_PKO_REG_GMX_PORT_MODE \ + CVMX_ADD_IO_SEG(0x0001180050000018ull) +#define CVMX_PKO_REG_INT_MASK \ + CVMX_ADD_IO_SEG(0x0001180050000090ull) +#define CVMX_PKO_REG_QUEUE_MODE \ + CVMX_ADD_IO_SEG(0x0001180050000048ull) +#define CVMX_PKO_REG_QUEUE_PTRS1 \ + CVMX_ADD_IO_SEG(0x0001180050000100ull) +#define CVMX_PKO_REG_READ_IDX \ + CVMX_ADD_IO_SEG(0x0001180050000008ull) + +union cvmx_pko_mem_count0 { + uint64_t u64; + struct cvmx_pko_mem_count0_s { + uint64_t reserved_32_63:32; + uint64_t count:32; + } s; + struct cvmx_pko_mem_count0_s cn30xx; + struct cvmx_pko_mem_count0_s cn31xx; + struct cvmx_pko_mem_count0_s cn38xx; + struct cvmx_pko_mem_count0_s cn38xxp2; + struct cvmx_pko_mem_count0_s cn50xx; + struct cvmx_pko_mem_count0_s cn52xx; + struct cvmx_pko_mem_count0_s cn52xxp1; + struct cvmx_pko_mem_count0_s cn56xx; + struct cvmx_pko_mem_count0_s cn56xxp1; + struct cvmx_pko_mem_count0_s cn58xx; + struct cvmx_pko_mem_count0_s cn58xxp1; +}; + +union cvmx_pko_mem_count1 { + uint64_t u64; + struct cvmx_pko_mem_count1_s { + uint64_t reserved_48_63:16; + uint64_t count:48; + } s; + struct cvmx_pko_mem_count1_s cn30xx; + struct cvmx_pko_mem_count1_s cn31xx; + struct cvmx_pko_mem_count1_s cn38xx; + struct cvmx_pko_mem_count1_s cn38xxp2; + struct cvmx_pko_mem_count1_s cn50xx; + struct cvmx_pko_mem_count1_s cn52xx; + struct cvmx_pko_mem_count1_s cn52xxp1; + struct cvmx_pko_mem_count1_s cn56xx; + struct cvmx_pko_mem_count1_s cn56xxp1; + struct cvmx_pko_mem_count1_s cn58xx; + struct cvmx_pko_mem_count1_s cn58xxp1; +}; + +union cvmx_pko_mem_debug0 { + uint64_t u64; + struct cvmx_pko_mem_debug0_s { + uint64_t fau:28; + uint64_t cmd:14; + uint64_t segs:6; + uint64_t size:16; + } s; + struct cvmx_pko_mem_debug0_s cn30xx; + struct cvmx_pko_mem_debug0_s cn31xx; + struct cvmx_pko_mem_debug0_s cn38xx; + struct cvmx_pko_mem_debug0_s cn38xxp2; + struct cvmx_pko_mem_debug0_s cn50xx; + struct cvmx_pko_mem_debug0_s cn52xx; + struct cvmx_pko_mem_debug0_s cn52xxp1; + struct cvmx_pko_mem_debug0_s cn56xx; + struct cvmx_pko_mem_debug0_s cn56xxp1; + struct cvmx_pko_mem_debug0_s cn58xx; + struct cvmx_pko_mem_debug0_s cn58xxp1; +}; + +union cvmx_pko_mem_debug1 { + uint64_t u64; + struct cvmx_pko_mem_debug1_s { + uint64_t i:1; + uint64_t back:4; + uint64_t pool:3; + uint64_t size:16; + uint64_t ptr:40; + } s; + struct cvmx_pko_mem_debug1_s cn30xx; + struct cvmx_pko_mem_debug1_s cn31xx; + struct cvmx_pko_mem_debug1_s cn38xx; + struct cvmx_pko_mem_debug1_s cn38xxp2; + struct cvmx_pko_mem_debug1_s cn50xx; + struct cvmx_pko_mem_debug1_s cn52xx; + struct cvmx_pko_mem_debug1_s cn52xxp1; + struct cvmx_pko_mem_debug1_s cn56xx; + struct cvmx_pko_mem_debug1_s cn56xxp1; + struct cvmx_pko_mem_debug1_s cn58xx; + struct cvmx_pko_mem_debug1_s cn58xxp1; +}; + +union cvmx_pko_mem_debug10 { + uint64_t u64; + struct cvmx_pko_mem_debug10_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_pko_mem_debug10_cn30xx { + uint64_t fau:28; + uint64_t cmd:14; + uint64_t segs:6; + uint64_t size:16; + } cn30xx; + struct cvmx_pko_mem_debug10_cn30xx cn31xx; + struct cvmx_pko_mem_debug10_cn30xx cn38xx; + struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug10_cn50xx { + uint64_t reserved_49_63:15; + uint64_t ptrs1:17; + uint64_t reserved_17_31:15; + uint64_t ptrs2:17; + } cn50xx; + struct cvmx_pko_mem_debug10_cn50xx cn52xx; + struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; + struct cvmx_pko_mem_debug10_cn50xx cn56xx; + struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; + struct cvmx_pko_mem_debug10_cn50xx cn58xx; + struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug11 { + uint64_t u64; + struct cvmx_pko_mem_debug11_s { + uint64_t i:1; + uint64_t back:4; + uint64_t pool:3; + uint64_t size:16; + uint64_t reserved_0_39:40; + } s; + struct cvmx_pko_mem_debug11_cn30xx { + uint64_t i:1; + uint64_t back:4; + uint64_t pool:3; + uint64_t size:16; + uint64_t ptr:40; + } cn30xx; + struct cvmx_pko_mem_debug11_cn30xx cn31xx; + struct cvmx_pko_mem_debug11_cn30xx cn38xx; + struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug11_cn50xx { + uint64_t reserved_23_63:41; + uint64_t maj:1; + uint64_t uid:3; + uint64_t sop:1; + uint64_t len:1; + uint64_t chk:1; + uint64_t cnt:13; + uint64_t mod:3; + } cn50xx; + struct cvmx_pko_mem_debug11_cn50xx cn52xx; + struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; + struct cvmx_pko_mem_debug11_cn50xx cn56xx; + struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; + struct cvmx_pko_mem_debug11_cn50xx cn58xx; + struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug12 { + uint64_t u64; + struct cvmx_pko_mem_debug12_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_pko_mem_debug12_cn30xx { + uint64_t data:64; + } cn30xx; + struct cvmx_pko_mem_debug12_cn30xx cn31xx; + struct cvmx_pko_mem_debug12_cn30xx cn38xx; + struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug12_cn50xx { + uint64_t fau:28; + uint64_t cmd:14; + uint64_t segs:6; + uint64_t size:16; + } cn50xx; + struct cvmx_pko_mem_debug12_cn50xx cn52xx; + struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; + struct cvmx_pko_mem_debug12_cn50xx cn56xx; + struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; + struct cvmx_pko_mem_debug12_cn50xx cn58xx; + struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug13 { + uint64_t u64; + struct cvmx_pko_mem_debug13_s { + uint64_t i:1; + uint64_t back:4; + uint64_t pool:3; + uint64_t reserved_0_55:56; + } s; + struct cvmx_pko_mem_debug13_cn30xx { + uint64_t reserved_51_63:13; + uint64_t widx:17; + uint64_t ridx2:17; + uint64_t widx2:17; + } cn30xx; + struct cvmx_pko_mem_debug13_cn30xx cn31xx; + struct cvmx_pko_mem_debug13_cn30xx cn38xx; + struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug13_cn50xx { + uint64_t i:1; + uint64_t back:4; + uint64_t pool:3; + uint64_t size:16; + uint64_t ptr:40; + } cn50xx; + struct cvmx_pko_mem_debug13_cn50xx cn52xx; + struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; + struct cvmx_pko_mem_debug13_cn50xx cn56xx; + struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; + struct cvmx_pko_mem_debug13_cn50xx cn58xx; + struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug14 { + uint64_t u64; + struct cvmx_pko_mem_debug14_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_pko_mem_debug14_cn30xx { + uint64_t reserved_17_63:47; + uint64_t ridx:17; + } cn30xx; + struct cvmx_pko_mem_debug14_cn30xx cn31xx; + struct cvmx_pko_mem_debug14_cn30xx cn38xx; + struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug14_cn52xx { + uint64_t data:64; + } cn52xx; + struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; + struct cvmx_pko_mem_debug14_cn52xx cn56xx; + struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; +}; + +union cvmx_pko_mem_debug2 { + uint64_t u64; + struct cvmx_pko_mem_debug2_s { + uint64_t i:1; + uint64_t back:4; + uint64_t pool:3; + uint64_t size:16; + uint64_t ptr:40; + } s; + struct cvmx_pko_mem_debug2_s cn30xx; + struct cvmx_pko_mem_debug2_s cn31xx; + struct cvmx_pko_mem_debug2_s cn38xx; + struct cvmx_pko_mem_debug2_s cn38xxp2; + struct cvmx_pko_mem_debug2_s cn50xx; + struct cvmx_pko_mem_debug2_s cn52xx; + struct cvmx_pko_mem_debug2_s cn52xxp1; + struct cvmx_pko_mem_debug2_s cn56xx; + struct cvmx_pko_mem_debug2_s cn56xxp1; + struct cvmx_pko_mem_debug2_s cn58xx; + struct cvmx_pko_mem_debug2_s cn58xxp1; +}; + +union cvmx_pko_mem_debug3 { + uint64_t u64; + struct cvmx_pko_mem_debug3_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_pko_mem_debug3_cn30xx { + uint64_t i:1; + uint64_t back:4; + uint64_t pool:3; + uint64_t size:16; + uint64_t ptr:40; + } cn30xx; + struct cvmx_pko_mem_debug3_cn30xx cn31xx; + struct cvmx_pko_mem_debug3_cn30xx cn38xx; + struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug3_cn50xx { + uint64_t data:64; + } cn50xx; + struct cvmx_pko_mem_debug3_cn50xx cn52xx; + struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; + struct cvmx_pko_mem_debug3_cn50xx cn56xx; + struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; + struct cvmx_pko_mem_debug3_cn50xx cn58xx; + struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug4 { + uint64_t u64; + struct cvmx_pko_mem_debug4_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_pko_mem_debug4_cn30xx { + uint64_t data:64; + } cn30xx; + struct cvmx_pko_mem_debug4_cn30xx cn31xx; + struct cvmx_pko_mem_debug4_cn30xx cn38xx; + struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug4_cn50xx { + uint64_t cmnd_segs:3; + uint64_t cmnd_siz:16; + uint64_t cmnd_off:6; + uint64_t uid:3; + uint64_t dread_sop:1; + uint64_t init_dwrite:1; + uint64_t chk_once:1; + uint64_t chk_mode:1; + uint64_t active:1; + uint64_t static_p:1; + uint64_t qos:3; + uint64_t qcb_ridx:5; + uint64_t qid_off_max:4; + uint64_t qid_off:4; + uint64_t qid_base:8; + uint64_t wait:1; + uint64_t minor:2; + uint64_t major:3; + } cn50xx; + struct cvmx_pko_mem_debug4_cn52xx { + uint64_t curr_siz:8; + uint64_t curr_off:16; + uint64_t cmnd_segs:6; + uint64_t cmnd_siz:16; + uint64_t cmnd_off:6; + uint64_t uid:2; + uint64_t dread_sop:1; + uint64_t init_dwrite:1; + uint64_t chk_once:1; + uint64_t chk_mode:1; + uint64_t wait:1; + uint64_t minor:2; + uint64_t major:3; + } cn52xx; + struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; + struct cvmx_pko_mem_debug4_cn52xx cn56xx; + struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; + struct cvmx_pko_mem_debug4_cn50xx cn58xx; + struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug5 { + uint64_t u64; + struct cvmx_pko_mem_debug5_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_pko_mem_debug5_cn30xx { + uint64_t dwri_mod:1; + uint64_t dwri_sop:1; + uint64_t dwri_len:1; + uint64_t dwri_cnt:13; + uint64_t cmnd_siz:16; + uint64_t uid:1; + uint64_t xfer_wor:1; + uint64_t xfer_dwr:1; + uint64_t cbuf_fre:1; + uint64_t reserved_27_27:1; + uint64_t chk_mode:1; + uint64_t active:1; + uint64_t qos:3; + uint64_t qcb_ridx:5; + uint64_t qid_off:3; + uint64_t qid_base:7; + uint64_t wait:1; + uint64_t minor:2; + uint64_t major:4; + } cn30xx; + struct cvmx_pko_mem_debug5_cn30xx cn31xx; + struct cvmx_pko_mem_debug5_cn30xx cn38xx; + struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug5_cn50xx { + uint64_t curr_ptr:29; + uint64_t curr_siz:16; + uint64_t curr_off:16; + uint64_t cmnd_segs:3; + } cn50xx; + struct cvmx_pko_mem_debug5_cn52xx { + uint64_t reserved_54_63:10; + uint64_t nxt_inflt:6; + uint64_t curr_ptr:40; + uint64_t curr_siz:8; + } cn52xx; + struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; + struct cvmx_pko_mem_debug5_cn52xx cn56xx; + struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; + struct cvmx_pko_mem_debug5_cn50xx cn58xx; + struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug6 { + uint64_t u64; + struct cvmx_pko_mem_debug6_s { + uint64_t reserved_37_63:27; + uint64_t qid_offres:4; + uint64_t qid_offths:4; + uint64_t preempter:1; + uint64_t preemptee:1; + uint64_t preempted:1; + uint64_t active:1; + uint64_t statc:1; + uint64_t qos:3; + uint64_t qcb_ridx:5; + uint64_t qid_offmax:4; + uint64_t reserved_0_11:12; + } s; + struct cvmx_pko_mem_debug6_cn30xx { + uint64_t reserved_11_63:53; + uint64_t qid_offm:3; + uint64_t static_p:1; + uint64_t work_min:3; + uint64_t dwri_chk:1; + uint64_t dwri_uid:1; + uint64_t dwri_mod:2; + } cn30xx; + struct cvmx_pko_mem_debug6_cn30xx cn31xx; + struct cvmx_pko_mem_debug6_cn30xx cn38xx; + struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug6_cn50xx { + uint64_t reserved_11_63:53; + uint64_t curr_ptr:11; + } cn50xx; + struct cvmx_pko_mem_debug6_cn52xx { + uint64_t reserved_37_63:27; + uint64_t qid_offres:4; + uint64_t qid_offths:4; + uint64_t preempter:1; + uint64_t preemptee:1; + uint64_t preempted:1; + uint64_t active:1; + uint64_t statc:1; + uint64_t qos:3; + uint64_t qcb_ridx:5; + uint64_t qid_offmax:4; + uint64_t qid_off:4; + uint64_t qid_base:8; + } cn52xx; + struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; + struct cvmx_pko_mem_debug6_cn52xx cn56xx; + struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; + struct cvmx_pko_mem_debug6_cn50xx cn58xx; + struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug7 { + uint64_t u64; + struct cvmx_pko_mem_debug7_s { + uint64_t qos:5; + uint64_t tail:1; + uint64_t reserved_0_57:58; + } s; + struct cvmx_pko_mem_debug7_cn30xx { + uint64_t reserved_58_63:6; + uint64_t dwb:9; + uint64_t start:33; + uint64_t size:16; + } cn30xx; + struct cvmx_pko_mem_debug7_cn30xx cn31xx; + struct cvmx_pko_mem_debug7_cn30xx cn38xx; + struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug7_cn50xx { + uint64_t qos:5; + uint64_t tail:1; + uint64_t buf_siz:13; + uint64_t buf_ptr:33; + uint64_t qcb_widx:6; + uint64_t qcb_ridx:6; + } cn50xx; + struct cvmx_pko_mem_debug7_cn50xx cn52xx; + struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; + struct cvmx_pko_mem_debug7_cn50xx cn56xx; + struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; + struct cvmx_pko_mem_debug7_cn50xx cn58xx; + struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug8 { + uint64_t u64; + struct cvmx_pko_mem_debug8_s { + uint64_t reserved_59_63:5; + uint64_t tail:1; + uint64_t buf_siz:13; + uint64_t reserved_0_44:45; + } s; + struct cvmx_pko_mem_debug8_cn30xx { + uint64_t qos:5; + uint64_t tail:1; + uint64_t buf_siz:13; + uint64_t buf_ptr:33; + uint64_t qcb_widx:6; + uint64_t qcb_ridx:6; + } cn30xx; + struct cvmx_pko_mem_debug8_cn30xx cn31xx; + struct cvmx_pko_mem_debug8_cn30xx cn38xx; + struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; + struct cvmx_pko_mem_debug8_cn50xx { + uint64_t reserved_28_63:36; + uint64_t doorbell:20; + uint64_t reserved_6_7:2; + uint64_t static_p:1; + uint64_t s_tail:1; + uint64_t static_q:1; + uint64_t qos:3; + } cn50xx; + struct cvmx_pko_mem_debug8_cn52xx { + uint64_t reserved_29_63:35; + uint64_t preempter:1; + uint64_t doorbell:20; + uint64_t reserved_7_7:1; + uint64_t preemptee:1; + uint64_t static_p:1; + uint64_t s_tail:1; + uint64_t static_q:1; + uint64_t qos:3; + } cn52xx; + struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; + struct cvmx_pko_mem_debug8_cn52xx cn56xx; + struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; + struct cvmx_pko_mem_debug8_cn50xx cn58xx; + struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_debug9 { + uint64_t u64; + struct cvmx_pko_mem_debug9_s { + uint64_t reserved_49_63:15; + uint64_t ptrs0:17; + uint64_t reserved_0_31:32; + } s; + struct cvmx_pko_mem_debug9_cn30xx { + uint64_t reserved_28_63:36; + uint64_t doorbell:20; + uint64_t reserved_5_7:3; + uint64_t s_tail:1; + uint64_t static_q:1; + uint64_t qos:3; + } cn30xx; + struct cvmx_pko_mem_debug9_cn30xx cn31xx; + struct cvmx_pko_mem_debug9_cn38xx { + uint64_t reserved_28_63:36; + uint64_t doorbell:20; + uint64_t reserved_6_7:2; + uint64_t static_p:1; + uint64_t s_tail:1; + uint64_t static_q:1; + uint64_t qos:3; + } cn38xx; + struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; + struct cvmx_pko_mem_debug9_cn50xx { + uint64_t reserved_49_63:15; + uint64_t ptrs0:17; + uint64_t reserved_17_31:15; + uint64_t ptrs3:17; + } cn50xx; + struct cvmx_pko_mem_debug9_cn50xx cn52xx; + struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; + struct cvmx_pko_mem_debug9_cn50xx cn56xx; + struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; + struct cvmx_pko_mem_debug9_cn50xx cn58xx; + struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; +}; + +union cvmx_pko_mem_port_ptrs { + uint64_t u64; + struct cvmx_pko_mem_port_ptrs_s { + uint64_t reserved_62_63:2; + uint64_t static_p:1; + uint64_t qos_mask:8; + uint64_t reserved_16_52:37; + uint64_t bp_port:6; + uint64_t eid:4; + uint64_t pid:6; + } s; + struct cvmx_pko_mem_port_ptrs_s cn52xx; + struct cvmx_pko_mem_port_ptrs_s cn52xxp1; + struct cvmx_pko_mem_port_ptrs_s cn56xx; + struct cvmx_pko_mem_port_ptrs_s cn56xxp1; +}; + +union cvmx_pko_mem_port_qos { + uint64_t u64; + struct cvmx_pko_mem_port_qos_s { + uint64_t reserved_61_63:3; + uint64_t qos_mask:8; + uint64_t reserved_10_52:43; + uint64_t eid:4; + uint64_t pid:6; + } s; + struct cvmx_pko_mem_port_qos_s cn52xx; + struct cvmx_pko_mem_port_qos_s cn52xxp1; + struct cvmx_pko_mem_port_qos_s cn56xx; + struct cvmx_pko_mem_port_qos_s cn56xxp1; +}; + +union cvmx_pko_mem_port_rate0 { + uint64_t u64; + struct cvmx_pko_mem_port_rate0_s { + uint64_t reserved_51_63:13; + uint64_t rate_word:19; + uint64_t rate_pkt:24; + uint64_t reserved_6_7:2; + uint64_t pid:6; + } s; + struct cvmx_pko_mem_port_rate0_s cn52xx; + struct cvmx_pko_mem_port_rate0_s cn52xxp1; + struct cvmx_pko_mem_port_rate0_s cn56xx; + struct cvmx_pko_mem_port_rate0_s cn56xxp1; +}; + +union cvmx_pko_mem_port_rate1 { + uint64_t u64; + struct cvmx_pko_mem_port_rate1_s { + uint64_t reserved_32_63:32; + uint64_t rate_lim:24; + uint64_t reserved_6_7:2; + uint64_t pid:6; + } s; + struct cvmx_pko_mem_port_rate1_s cn52xx; + struct cvmx_pko_mem_port_rate1_s cn52xxp1; + struct cvmx_pko_mem_port_rate1_s cn56xx; + struct cvmx_pko_mem_port_rate1_s cn56xxp1; +}; + +union cvmx_pko_mem_queue_ptrs { + uint64_t u64; + struct cvmx_pko_mem_queue_ptrs_s { + uint64_t s_tail:1; + uint64_t static_p:1; + uint64_t static_q:1; + uint64_t qos_mask:8; + uint64_t buf_ptr:36; + uint64_t tail:1; + uint64_t index:3; + uint64_t port:6; + uint64_t queue:7; + } s; + struct cvmx_pko_mem_queue_ptrs_s cn30xx; + struct cvmx_pko_mem_queue_ptrs_s cn31xx; + struct cvmx_pko_mem_queue_ptrs_s cn38xx; + struct cvmx_pko_mem_queue_ptrs_s cn38xxp2; + struct cvmx_pko_mem_queue_ptrs_s cn50xx; + struct cvmx_pko_mem_queue_ptrs_s cn52xx; + struct cvmx_pko_mem_queue_ptrs_s cn52xxp1; + struct cvmx_pko_mem_queue_ptrs_s cn56xx; + struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; + struct cvmx_pko_mem_queue_ptrs_s cn58xx; + struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; +}; + +union cvmx_pko_mem_queue_qos { + uint64_t u64; + struct cvmx_pko_mem_queue_qos_s { + uint64_t reserved_61_63:3; + uint64_t qos_mask:8; + uint64_t reserved_13_52:40; + uint64_t pid:6; + uint64_t qid:7; + } s; + struct cvmx_pko_mem_queue_qos_s cn30xx; + struct cvmx_pko_mem_queue_qos_s cn31xx; + struct cvmx_pko_mem_queue_qos_s cn38xx; + struct cvmx_pko_mem_queue_qos_s cn38xxp2; + struct cvmx_pko_mem_queue_qos_s cn50xx; + struct cvmx_pko_mem_queue_qos_s cn52xx; + struct cvmx_pko_mem_queue_qos_s cn52xxp1; + struct cvmx_pko_mem_queue_qos_s cn56xx; + struct cvmx_pko_mem_queue_qos_s cn56xxp1; + struct cvmx_pko_mem_queue_qos_s cn58xx; + struct cvmx_pko_mem_queue_qos_s cn58xxp1; +}; + +union cvmx_pko_reg_bist_result { + uint64_t u64; + struct cvmx_pko_reg_bist_result_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_pko_reg_bist_result_cn30xx { + uint64_t reserved_27_63:37; + uint64_t psb2:5; + uint64_t count:1; + uint64_t rif:1; + uint64_t wif:1; + uint64_t ncb:1; + uint64_t out:1; + uint64_t crc:1; + uint64_t chk:1; + uint64_t qsb:2; + uint64_t qcb:2; + uint64_t pdb:4; + uint64_t psb:7; + } cn30xx; + struct cvmx_pko_reg_bist_result_cn30xx cn31xx; + struct cvmx_pko_reg_bist_result_cn30xx cn38xx; + struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; + struct cvmx_pko_reg_bist_result_cn50xx { + uint64_t reserved_33_63:31; + uint64_t csr:1; + uint64_t iob:1; + uint64_t out_crc:1; + uint64_t out_ctl:3; + uint64_t out_sta:1; + uint64_t out_wif:1; + uint64_t prt_chk:3; + uint64_t prt_nxt:1; + uint64_t prt_psb:6; + uint64_t ncb_inb:2; + uint64_t prt_qcb:2; + uint64_t prt_qsb:3; + uint64_t dat_dat:4; + uint64_t dat_ptr:4; + } cn50xx; + struct cvmx_pko_reg_bist_result_cn52xx { + uint64_t reserved_35_63:29; + uint64_t csr:1; + uint64_t iob:1; + uint64_t out_dat:1; + uint64_t out_ctl:3; + uint64_t out_sta:1; + uint64_t out_wif:1; + uint64_t prt_chk:3; + uint64_t prt_nxt:1; + uint64_t prt_psb:8; + uint64_t ncb_inb:2; + uint64_t prt_qcb:2; + uint64_t prt_qsb:3; + uint64_t prt_ctl:2; + uint64_t dat_dat:2; + uint64_t dat_ptr:4; + } cn52xx; + struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; + struct cvmx_pko_reg_bist_result_cn52xx cn56xx; + struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; + struct cvmx_pko_reg_bist_result_cn50xx cn58xx; + struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; +}; + +union cvmx_pko_reg_cmd_buf { + uint64_t u64; + struct cvmx_pko_reg_cmd_buf_s { + uint64_t reserved_23_63:41; + uint64_t pool:3; + uint64_t reserved_13_19:7; + uint64_t size:13; + } s; + struct cvmx_pko_reg_cmd_buf_s cn30xx; + struct cvmx_pko_reg_cmd_buf_s cn31xx; + struct cvmx_pko_reg_cmd_buf_s cn38xx; + struct cvmx_pko_reg_cmd_buf_s cn38xxp2; + struct cvmx_pko_reg_cmd_buf_s cn50xx; + struct cvmx_pko_reg_cmd_buf_s cn52xx; + struct cvmx_pko_reg_cmd_buf_s cn52xxp1; + struct cvmx_pko_reg_cmd_buf_s cn56xx; + struct cvmx_pko_reg_cmd_buf_s cn56xxp1; + struct cvmx_pko_reg_cmd_buf_s cn58xx; + struct cvmx_pko_reg_cmd_buf_s cn58xxp1; +}; + +union cvmx_pko_reg_crc_ctlx { + uint64_t u64; + struct cvmx_pko_reg_crc_ctlx_s { + uint64_t reserved_2_63:62; + uint64_t invres:1; + uint64_t refin:1; + } s; + struct cvmx_pko_reg_crc_ctlx_s cn38xx; + struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; + struct cvmx_pko_reg_crc_ctlx_s cn58xx; + struct cvmx_pko_reg_crc_ctlx_s cn58xxp1; +}; + +union cvmx_pko_reg_crc_enable { + uint64_t u64; + struct cvmx_pko_reg_crc_enable_s { + uint64_t reserved_32_63:32; + uint64_t enable:32; + } s; + struct cvmx_pko_reg_crc_enable_s cn38xx; + struct cvmx_pko_reg_crc_enable_s cn38xxp2; + struct cvmx_pko_reg_crc_enable_s cn58xx; + struct cvmx_pko_reg_crc_enable_s cn58xxp1; +}; + +union cvmx_pko_reg_crc_ivx { + uint64_t u64; + struct cvmx_pko_reg_crc_ivx_s { + uint64_t reserved_32_63:32; + uint64_t iv:32; + } s; + struct cvmx_pko_reg_crc_ivx_s cn38xx; + struct cvmx_pko_reg_crc_ivx_s cn38xxp2; + struct cvmx_pko_reg_crc_ivx_s cn58xx; + struct cvmx_pko_reg_crc_ivx_s cn58xxp1; +}; + +union cvmx_pko_reg_debug0 { + uint64_t u64; + struct cvmx_pko_reg_debug0_s { + uint64_t asserts:64; + } s; + struct cvmx_pko_reg_debug0_cn30xx { + uint64_t reserved_17_63:47; + uint64_t asserts:17; + } cn30xx; + struct cvmx_pko_reg_debug0_cn30xx cn31xx; + struct cvmx_pko_reg_debug0_cn30xx cn38xx; + struct cvmx_pko_reg_debug0_cn30xx cn38xxp2; + struct cvmx_pko_reg_debug0_s cn50xx; + struct cvmx_pko_reg_debug0_s cn52xx; + struct cvmx_pko_reg_debug0_s cn52xxp1; + struct cvmx_pko_reg_debug0_s cn56xx; + struct cvmx_pko_reg_debug0_s cn56xxp1; + struct cvmx_pko_reg_debug0_s cn58xx; + struct cvmx_pko_reg_debug0_s cn58xxp1; +}; + +union cvmx_pko_reg_debug1 { + uint64_t u64; + struct cvmx_pko_reg_debug1_s { + uint64_t asserts:64; + } s; + struct cvmx_pko_reg_debug1_s cn50xx; + struct cvmx_pko_reg_debug1_s cn52xx; + struct cvmx_pko_reg_debug1_s cn52xxp1; + struct cvmx_pko_reg_debug1_s cn56xx; + struct cvmx_pko_reg_debug1_s cn56xxp1; + struct cvmx_pko_reg_debug1_s cn58xx; + struct cvmx_pko_reg_debug1_s cn58xxp1; +}; + +union cvmx_pko_reg_debug2 { + uint64_t u64; + struct cvmx_pko_reg_debug2_s { + uint64_t asserts:64; + } s; + struct cvmx_pko_reg_debug2_s cn50xx; + struct cvmx_pko_reg_debug2_s cn52xx; + struct cvmx_pko_reg_debug2_s cn52xxp1; + struct cvmx_pko_reg_debug2_s cn56xx; + struct cvmx_pko_reg_debug2_s cn56xxp1; + struct cvmx_pko_reg_debug2_s cn58xx; + struct cvmx_pko_reg_debug2_s cn58xxp1; +}; + +union cvmx_pko_reg_debug3 { + uint64_t u64; + struct cvmx_pko_reg_debug3_s { + uint64_t asserts:64; + } s; + struct cvmx_pko_reg_debug3_s cn50xx; + struct cvmx_pko_reg_debug3_s cn52xx; + struct cvmx_pko_reg_debug3_s cn52xxp1; + struct cvmx_pko_reg_debug3_s cn56xx; + struct cvmx_pko_reg_debug3_s cn56xxp1; + struct cvmx_pko_reg_debug3_s cn58xx; + struct cvmx_pko_reg_debug3_s cn58xxp1; +}; + +union cvmx_pko_reg_engine_inflight { + uint64_t u64; + struct cvmx_pko_reg_engine_inflight_s { + uint64_t reserved_40_63:24; + uint64_t engine9:4; + uint64_t engine8:4; + uint64_t engine7:4; + uint64_t engine6:4; + uint64_t engine5:4; + uint64_t engine4:4; + uint64_t engine3:4; + uint64_t engine2:4; + uint64_t engine1:4; + uint64_t engine0:4; + } s; + struct cvmx_pko_reg_engine_inflight_s cn52xx; + struct cvmx_pko_reg_engine_inflight_s cn52xxp1; + struct cvmx_pko_reg_engine_inflight_s cn56xx; + struct cvmx_pko_reg_engine_inflight_s cn56xxp1; +}; + +union cvmx_pko_reg_engine_thresh { + uint64_t u64; + struct cvmx_pko_reg_engine_thresh_s { + uint64_t reserved_10_63:54; + uint64_t mask:10; + } s; + struct cvmx_pko_reg_engine_thresh_s cn52xx; + struct cvmx_pko_reg_engine_thresh_s cn52xxp1; + struct cvmx_pko_reg_engine_thresh_s cn56xx; + struct cvmx_pko_reg_engine_thresh_s cn56xxp1; +}; + +union cvmx_pko_reg_error { + uint64_t u64; + struct cvmx_pko_reg_error_s { + uint64_t reserved_3_63:61; + uint64_t currzero:1; + uint64_t doorbell:1; + uint64_t parity:1; + } s; + struct cvmx_pko_reg_error_cn30xx { + uint64_t reserved_2_63:62; + uint64_t doorbell:1; + uint64_t parity:1; + } cn30xx; + struct cvmx_pko_reg_error_cn30xx cn31xx; + struct cvmx_pko_reg_error_cn30xx cn38xx; + struct cvmx_pko_reg_error_cn30xx cn38xxp2; + struct cvmx_pko_reg_error_s cn50xx; + struct cvmx_pko_reg_error_s cn52xx; + struct cvmx_pko_reg_error_s cn52xxp1; + struct cvmx_pko_reg_error_s cn56xx; + struct cvmx_pko_reg_error_s cn56xxp1; + struct cvmx_pko_reg_error_s cn58xx; + struct cvmx_pko_reg_error_s cn58xxp1; +}; + +union cvmx_pko_reg_flags { + uint64_t u64; + struct cvmx_pko_reg_flags_s { + uint64_t reserved_4_63:60; + uint64_t reset:1; + uint64_t store_be:1; + uint64_t ena_dwb:1; + uint64_t ena_pko:1; + } s; + struct cvmx_pko_reg_flags_s cn30xx; + struct cvmx_pko_reg_flags_s cn31xx; + struct cvmx_pko_reg_flags_s cn38xx; + struct cvmx_pko_reg_flags_s cn38xxp2; + struct cvmx_pko_reg_flags_s cn50xx; + struct cvmx_pko_reg_flags_s cn52xx; + struct cvmx_pko_reg_flags_s cn52xxp1; + struct cvmx_pko_reg_flags_s cn56xx; + struct cvmx_pko_reg_flags_s cn56xxp1; + struct cvmx_pko_reg_flags_s cn58xx; + struct cvmx_pko_reg_flags_s cn58xxp1; +}; + +union cvmx_pko_reg_gmx_port_mode { + uint64_t u64; + struct cvmx_pko_reg_gmx_port_mode_s { + uint64_t reserved_6_63:58; + uint64_t mode1:3; + uint64_t mode0:3; + } s; + struct cvmx_pko_reg_gmx_port_mode_s cn30xx; + struct cvmx_pko_reg_gmx_port_mode_s cn31xx; + struct cvmx_pko_reg_gmx_port_mode_s cn38xx; + struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2; + struct cvmx_pko_reg_gmx_port_mode_s cn50xx; + struct cvmx_pko_reg_gmx_port_mode_s cn52xx; + struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1; + struct cvmx_pko_reg_gmx_port_mode_s cn56xx; + struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; + struct cvmx_pko_reg_gmx_port_mode_s cn58xx; + struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; +}; + +union cvmx_pko_reg_int_mask { + uint64_t u64; + struct cvmx_pko_reg_int_mask_s { + uint64_t reserved_3_63:61; + uint64_t currzero:1; + uint64_t doorbell:1; + uint64_t parity:1; + } s; + struct cvmx_pko_reg_int_mask_cn30xx { + uint64_t reserved_2_63:62; + uint64_t doorbell:1; + uint64_t parity:1; + } cn30xx; + struct cvmx_pko_reg_int_mask_cn30xx cn31xx; + struct cvmx_pko_reg_int_mask_cn30xx cn38xx; + struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; + struct cvmx_pko_reg_int_mask_s cn50xx; + struct cvmx_pko_reg_int_mask_s cn52xx; + struct cvmx_pko_reg_int_mask_s cn52xxp1; + struct cvmx_pko_reg_int_mask_s cn56xx; + struct cvmx_pko_reg_int_mask_s cn56xxp1; + struct cvmx_pko_reg_int_mask_s cn58xx; + struct cvmx_pko_reg_int_mask_s cn58xxp1; +}; + +union cvmx_pko_reg_queue_mode { + uint64_t u64; + struct cvmx_pko_reg_queue_mode_s { + uint64_t reserved_2_63:62; + uint64_t mode:2; + } s; + struct cvmx_pko_reg_queue_mode_s cn30xx; + struct cvmx_pko_reg_queue_mode_s cn31xx; + struct cvmx_pko_reg_queue_mode_s cn38xx; + struct cvmx_pko_reg_queue_mode_s cn38xxp2; + struct cvmx_pko_reg_queue_mode_s cn50xx; + struct cvmx_pko_reg_queue_mode_s cn52xx; + struct cvmx_pko_reg_queue_mode_s cn52xxp1; + struct cvmx_pko_reg_queue_mode_s cn56xx; + struct cvmx_pko_reg_queue_mode_s cn56xxp1; + struct cvmx_pko_reg_queue_mode_s cn58xx; + struct cvmx_pko_reg_queue_mode_s cn58xxp1; +}; + +union cvmx_pko_reg_queue_ptrs1 { + uint64_t u64; + struct cvmx_pko_reg_queue_ptrs1_s { + uint64_t reserved_2_63:62; + uint64_t idx3:1; + uint64_t qid7:1; + } s; + struct cvmx_pko_reg_queue_ptrs1_s cn50xx; + struct cvmx_pko_reg_queue_ptrs1_s cn52xx; + struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1; + struct cvmx_pko_reg_queue_ptrs1_s cn56xx; + struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; + struct cvmx_pko_reg_queue_ptrs1_s cn58xx; + struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; +}; + +union cvmx_pko_reg_read_idx { + uint64_t u64; + struct cvmx_pko_reg_read_idx_s { + uint64_t reserved_16_63:48; + uint64_t inc:8; + uint64_t index:8; + } s; + struct cvmx_pko_reg_read_idx_s cn30xx; + struct cvmx_pko_reg_read_idx_s cn31xx; + struct cvmx_pko_reg_read_idx_s cn38xx; + struct cvmx_pko_reg_read_idx_s cn38xxp2; + struct cvmx_pko_reg_read_idx_s cn50xx; + struct cvmx_pko_reg_read_idx_s cn52xx; + struct cvmx_pko_reg_read_idx_s cn52xxp1; + struct cvmx_pko_reg_read_idx_s cn56xx; + struct cvmx_pko_reg_read_idx_s cn56xxp1; + struct cvmx_pko_reg_read_idx_s cn58xx; + struct cvmx_pko_reg_read_idx_s cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h new file mode 100644 index 000000000000..de3412aada5d --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pko.h @@ -0,0 +1,610 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Interface to the hardware Packet Output unit. + * + * Starting with SDK 1.7.0, the PKO output functions now support + * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to + * function similarly to previous SDKs by using POW atomic tags + * to preserve ordering and exclusivity. As a new option, you + * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc + * memory based locking instead. This locking has the advantage + * of not affecting the tag state but doesn't preserve packet + * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most + * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used + * with hand tuned fast path code. + * + * Some of other SDK differences visible to the command command + * queuing: + * - PKO indexes are no longer stored in the FAU. A large + * percentage of the FAU register block used to be tied up + * maintaining PKO queue pointers. These are now stored in a + * global named block. + * - The PKO use_locking parameter can now have a global + * effect. Since all application use the same named block, + * queue locking correctly applies across all operating + * systems when using CVMX_PKO_LOCK_CMD_QUEUE. + * - PKO 3 word commands are now supported. Use + * cvmx_pko_send_packet_finish3(). + * + */ + +#ifndef __CVMX_PKO_H__ +#define __CVMX_PKO_H__ + +#include "cvmx-fpa.h" +#include "cvmx-pow.h" +#include "cvmx-cmd-queue.h" +#include "cvmx-pko-defs.h" + +/* Adjust the command buffer size by 1 word so that in the case of using only + * two word PKO commands no command words stradle buffers. The useful values + * for this are 0 and 1. */ +#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1) + +#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256 +#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ + OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \ + OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \ + (OCTEON_IS_MODEL(OCTEON_CN58XX) || \ + OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128) +#define CVMX_PKO_NUM_OUTPUT_PORTS 40 +/* use this for queues that are not used */ +#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 +#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 +#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF +#define CVMX_PKO_MAX_QUEUE_DEPTH 0 + +typedef enum { + CVMX_PKO_SUCCESS, + CVMX_PKO_INVALID_PORT, + CVMX_PKO_INVALID_QUEUE, + CVMX_PKO_INVALID_PRIORITY, + CVMX_PKO_NO_MEMORY, + CVMX_PKO_PORT_ALREADY_SETUP, + CVMX_PKO_CMD_QUEUE_INIT_ERROR +} cvmx_pko_status_t; + +/** + * This enumeration represents the differnet locking modes supported by PKO. + */ +typedef enum { + /* + * PKO doesn't do any locking. It is the responsibility of the + * application to make sure that no other core is accessing + * the same queue at the same time + */ + CVMX_PKO_LOCK_NONE = 0, + /* + * PKO performs an atomic tagswitch to insure exclusive access + * to the output queue. This will maintain packet ordering on + * output. + */ + CVMX_PKO_LOCK_ATOMIC_TAG = 1, + /* + * PKO uses the common command queue locks to insure exclusive + * access to the output queue. This is a memory based + * ll/sc. This is the most portable locking mechanism. + */ + CVMX_PKO_LOCK_CMD_QUEUE = 2, +} cvmx_pko_lock_t; + +typedef struct { + uint32_t packets; + uint64_t octets; + uint64_t doorbell; +} cvmx_pko_port_status_t; + +/** + * This structure defines the address to use on a packet enqueue + */ +typedef union { + uint64_t u64; + struct { + /* Must CVMX_IO_SEG */ + uint64_t mem_space:2; + /* Must be zero */ + uint64_t reserved:13; + /* Must be one */ + uint64_t is_io:1; + /* The ID of the device on the non-coherent bus */ + uint64_t did:8; + /* Must be zero */ + uint64_t reserved2:4; + /* Must be zero */ + uint64_t reserved3:18; + /* + * The hardware likes to have the output port in + * addition to the output queue, + */ + uint64_t port:6; + /* + * The output queue to send the packet to (0-127 are + * legal) + */ + uint64_t queue:9; + /* Must be zero */ + uint64_t reserved4:3; + } s; +} cvmx_pko_doorbell_address_t; + +/** + * Structure of the first packet output command word. + */ +typedef union { + uint64_t u64; + struct { + /* + * The size of the reg1 operation - could be 8, 16, + * 32, or 64 bits. + */ + uint64_t size1:2; + /* + * The size of the reg0 operation - could be 8, 16, + * 32, or 64 bits. + */ + uint64_t size0:2; + /* + * If set, subtract 1, if clear, subtract packet + * size. + */ + uint64_t subone1:1; + /* + * The register, subtract will be done if reg1 is + * non-zero. + */ + uint64_t reg1:11; + /* If set, subtract 1, if clear, subtract packet size */ + uint64_t subone0:1; + /* The register, subtract will be done if reg0 is non-zero */ + uint64_t reg0:11; + /* + * When set, interpret segment pointer and segment + * bytes in little endian order. + */ + uint64_t le:1; + /* + * When set, packet data not allocated in L2 cache by + * PKO. + */ + uint64_t n2:1; + /* + * If set and rsp is set, word3 contains a pointer to + * a work queue entry. + */ + uint64_t wqp:1; + /* If set, the hardware will send a response when done */ + uint64_t rsp:1; + /* + * If set, the supplied pkt_ptr is really a pointer to + * a list of pkt_ptr's. + */ + uint64_t gather:1; + /* + * If ipoffp1 is non zero, (ipoffp1-1) is the number + * of bytes to IP header, and the hardware will + * calculate and insert the UDP/TCP checksum. + */ + uint64_t ipoffp1:7; + /* + * If set, ignore the I bit (force to zero) from all + * pointer structures. + */ + uint64_t ignore_i:1; + /* + * If clear, the hardware will attempt to free the + * buffers containing the packet. + */ + uint64_t dontfree:1; + /* + * The total number of segs in the packet, if gather + * set, also gather list length. + */ + uint64_t segs:6; + /* Including L2, but no trailing CRC */ + uint64_t total_bytes:16; + } s; +} cvmx_pko_command_word0_t; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Definition of internal state for Packet output processing + */ +typedef struct { + /* ptr to start of buffer, offset kept in FAU reg */ + uint64_t *start_ptr; +} cvmx_pko_state_elem_t; + +/** + * Call before any other calls to initialize the packet + * output system. + */ +extern void cvmx_pko_initialize_global(void); +extern int cvmx_pko_initialize_local(void); + +/** + * Enables the packet output hardware. It must already be + * configured. + */ +extern void cvmx_pko_enable(void); + +/** + * Disables the packet output. Does not affect any configuration. + */ +extern void cvmx_pko_disable(void); + +/** + * Shutdown and free resources required by packet output. + */ + +extern void cvmx_pko_shutdown(void); + +/** + * Configure a output port and the associated queues for use. + * + * @port: Port to configure. + * @base_queue: First queue number to associate with this port. + * @num_queues: Number of queues t oassociate with this port + * @priority: Array of priority levels for each queue. Values are + * allowed to be 1-8. A value of 8 get 8 times the traffic + * of a value of 1. There must be num_queues elements in the + * array. + */ +extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, + uint64_t base_queue, + uint64_t num_queues, + const uint64_t priority[]); + +/** + * Ring the packet output doorbell. This tells the packet + * output hardware that "len" command words have been added + * to its pending list. This command includes the required + * CVMX_SYNCWS before the doorbell ring. + * + * @port: Port the packet is for + * @queue: Queue the packet is for + * @len: Length of the command in 64 bit words + */ +static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, + uint64_t len) +{ + cvmx_pko_doorbell_address_t ptr; + + ptr.u64 = 0; + ptr.s.mem_space = CVMX_IO_SEG; + ptr.s.did = CVMX_OCT_DID_PKT_SEND; + ptr.s.is_io = 1; + ptr.s.port = port; + ptr.s.queue = queue; + /* + * Need to make sure output queue data is in DRAM before + * doorbell write. + */ + CVMX_SYNCWS; + cvmx_write_io(ptr.u64, len); +} + +/** + * Prepare to send a packet. This may initiate a tag switch to + * get exclusive access to the output queue structure, and + * performs other prep work for the packet send operation. + * + * cvmx_pko_send_packet_finish() MUST be called after this function is called, + * and must be called with the same port/queue/use_locking arguments. + * + * The use_locking parameter allows the caller to use three + * possible locking modes. + * - CVMX_PKO_LOCK_NONE + * - PKO doesn't do any locking. It is the responsibility + * of the application to make sure that no other core + * is accessing the same queue at the same time. + * - CVMX_PKO_LOCK_ATOMIC_TAG + * - PKO performs an atomic tagswitch to insure exclusive + * access to the output queue. This will maintain + * packet ordering on output. + * - CVMX_PKO_LOCK_CMD_QUEUE + * - PKO uses the common command queue locks to insure + * exclusive access to the output queue. This is a + * memory based ll/sc. This is the most portable + * locking mechanism. + * + * NOTE: If atomic locking is used, the POW entry CANNOT be + * descheduled, as it does not contain a valid WQE pointer. + * + * @port: Port to send it on + * @queue: Queue to use + * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or + * CVMX_PKO_LOCK_CMD_QUEUE + */ + +static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, + cvmx_pko_lock_t use_locking) +{ + if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) { + /* + * Must do a full switch here to handle all cases. We + * use a fake WQE pointer, as the POW does not access + * this memory. The WQE pointer and group are only + * used if this work is descheduled, which is not + * supported by the + * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish + * combination. Note that this is a special case in + * which these fake values can be used - this is not a + * general technique. + */ + uint32_t tag = + CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT | + CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT | + (CVMX_TAG_SUBGROUP_MASK & queue); + cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag, + CVMX_POW_TAG_TYPE_ATOMIC, 0); + } +} + +/** + * Complete packet output. cvmx_pko_send_packet_prepare() must be + * called exactly once before this, and the same parameters must be + * passed to both cvmx_pko_send_packet_prepare() and + * cvmx_pko_send_packet_finish(). + * + * @port: Port to send it on + * @queue: Queue to use + * @pko_command: + * PKO HW command word + * @packet: Packet to send + * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or + * CVMX_PKO_LOCK_CMD_QUEUE + * + * Returns returns CVMX_PKO_SUCCESS on success, or error code on + * failure of output + */ +static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( + uint64_t port, + uint64_t queue, + cvmx_pko_command_word0_t pko_command, + union cvmx_buf_ptr packet, + cvmx_pko_lock_t use_locking) +{ + cvmx_cmd_queue_result_t result; + if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) + cvmx_pow_tag_sw_wait(); + result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue), + (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), + pko_command.u64, packet.u64); + if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { + cvmx_pko_doorbell(port, queue, 2); + return CVMX_PKO_SUCCESS; + } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) + || (result == CVMX_CMD_QUEUE_FULL)) { + return CVMX_PKO_NO_MEMORY; + } else { + return CVMX_PKO_INVALID_QUEUE; + } +} + +/** + * Complete packet output. cvmx_pko_send_packet_prepare() must be + * called exactly once before this, and the same parameters must be + * passed to both cvmx_pko_send_packet_prepare() and + * cvmx_pko_send_packet_finish(). + * + * @port: Port to send it on + * @queue: Queue to use + * @pko_command: + * PKO HW command word + * @packet: Packet to send + * @addr: Plysical address of a work queue entry or physical address + * to zero on complete. + * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or + * CVMX_PKO_LOCK_CMD_QUEUE + * + * Returns returns CVMX_PKO_SUCCESS on success, or error code on + * failure of output + */ +static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3( + uint64_t port, + uint64_t queue, + cvmx_pko_command_word0_t pko_command, + union cvmx_buf_ptr packet, + uint64_t addr, + cvmx_pko_lock_t use_locking) +{ + cvmx_cmd_queue_result_t result; + if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) + cvmx_pow_tag_sw_wait(); + result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue), + (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), + pko_command.u64, packet.u64, addr); + if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { + cvmx_pko_doorbell(port, queue, 3); + return CVMX_PKO_SUCCESS; + } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) + || (result == CVMX_CMD_QUEUE_FULL)) { + return CVMX_PKO_NO_MEMORY; + } else { + return CVMX_PKO_INVALID_QUEUE; + } +} + +/** + * Return the pko output queue associated with a port and a specific core. + * In normal mode (PKO lockless operation is disabled), the value returned + * is the base queue. + * + * @port: Port number + * @core: Core to get queue for + * + * Returns Core-specific output queue + */ +static inline int cvmx_pko_get_base_queue_per_core(int port, int core) +{ +#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 +#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16 +#endif +#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 +#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16 +#endif + + if (port < CVMX_PKO_MAX_PORTS_INTERFACE0) + return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core; + else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1) + return CVMX_PKO_MAX_PORTS_INTERFACE0 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port - + 16) * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core; + else if ((port >= 32) && (port < 36)) + return CVMX_PKO_MAX_PORTS_INTERFACE0 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + + CVMX_PKO_MAX_PORTS_INTERFACE1 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port - + 32) * + CVMX_PKO_QUEUES_PER_PORT_PCI; + else if ((port >= 36) && (port < 40)) + return CVMX_PKO_MAX_PORTS_INTERFACE0 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + + CVMX_PKO_MAX_PORTS_INTERFACE1 * + CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + + 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port - + 36) * + CVMX_PKO_QUEUES_PER_PORT_LOOP; + else + /* Given the limit on the number of ports we can map to + * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256, + * divided among all cores), the remaining unmapped ports + * are assigned an illegal queue number */ + return CVMX_PKO_ILLEGAL_QUEUE; +} + +/** + * For a given port number, return the base pko output queue + * for the port. + * + * @port: Port number + * Returns Base output queue + */ +static inline int cvmx_pko_get_base_queue(int port) +{ + return cvmx_pko_get_base_queue_per_core(port, 0); +} + +/** + * For a given port number, return the number of pko output queues. + * + * @port: Port number + * Returns Number of output queues + */ +static inline int cvmx_pko_get_num_queues(int port) +{ + if (port < 16) + return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0; + else if (port < 32) + return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1; + else if (port < 36) + return CVMX_PKO_QUEUES_PER_PORT_PCI; + else if (port < 40) + return CVMX_PKO_QUEUES_PER_PORT_LOOP; + else + return 0; +} + +/** + * Get the status counters for a port. + * + * @port_num: Port number to get statistics for. + * @clear: Set to 1 to clear the counters after they are read + * @status: Where to put the results. + */ +static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, + cvmx_pko_port_status_t *status) +{ + union cvmx_pko_reg_read_idx pko_reg_read_idx; + union cvmx_pko_mem_count0 pko_mem_count0; + union cvmx_pko_mem_count1 pko_mem_count1; + + pko_reg_read_idx.u64 = 0; + pko_reg_read_idx.s.index = port_num; + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); + + pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0); + status->packets = pko_mem_count0.s.count; + if (clear) { + pko_mem_count0.s.count = port_num; + cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64); + } + + pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1); + status->octets = pko_mem_count1.s.count; + if (clear) { + pko_mem_count1.s.count = port_num; + cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64); + } + + if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { + union cvmx_pko_mem_debug9 debug9; + pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); + debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); + status->doorbell = debug9.cn38xx.doorbell; + } else { + union cvmx_pko_mem_debug8 debug8; + pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); + debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); + status->doorbell = debug8.cn58xx.doorbell; + } +} + +/** + * Rate limit a PKO port to a max packets/sec. This function is only + * supported on CN57XX, CN56XX, CN55XX, and CN54XX. + * + * @port: Port to rate limit + * @packets_s: Maximum packet/sec + * @burst: Maximum number of packets to burst in a row before rate + * limiting cuts in. + * + * Returns Zero on success, negative on failure + */ +extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst); + +/** + * Rate limit a PKO port to a max bits/sec. This function is only + * supported on CN57XX, CN56XX, CN55XX, and CN54XX. + * + * @port: Port to rate limit + * @bits_s: PKO rate limit in bits/sec + * @burst: Maximum number of bits to burst before rate + * limiting cuts in. + * + * Returns Zero on success, negative on failure + */ +extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst); + +#endif /* __CVMX_PKO_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h new file mode 100644 index 000000000000..999aefe3274c --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-pow.h @@ -0,0 +1,1982 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * Interface to the hardware Packet Order / Work unit. + * + * New, starting with SDK 1.7.0, cvmx-pow supports a number of + * extended consistency checks. The define + * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW + * internal state checks to find common programming errors. If + * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default + * enabled. For example, cvmx-pow will check for the following + * program errors or POW state inconsistency. + * - Requesting a POW operation with an active tag switch in + * progress. + * - Waiting for a tag switch to complete for an excessively + * long period. This is normally a sign of an error in locking + * causing deadlock. + * - Illegal tag switches from NULL_NULL. + * - Illegal tag switches from NULL. + * - Illegal deschedule request. + * - WQE pointer not matching the one attached to the core by + * the POW. + * + */ + +#ifndef __CVMX_POW_H__ +#define __CVMX_POW_H__ + +#include + +#include "cvmx-scratch.h" +#include "cvmx-wqe.h" + +/* Default to having all POW constancy checks turned on */ +#ifndef CVMX_ENABLE_POW_CHECKS +#define CVMX_ENABLE_POW_CHECKS 1 +#endif + +enum cvmx_pow_tag_type { + /* Tag ordering is maintained */ + CVMX_POW_TAG_TYPE_ORDERED = 0L, + /* Tag ordering is maintained, and at most one PP has the tag */ + CVMX_POW_TAG_TYPE_ATOMIC = 1L, + /* + * The work queue entry from the order - NEVER tag switch from + * NULL to NULL + */ + CVMX_POW_TAG_TYPE_NULL = 2L, + /* A tag switch to NULL, and there is no space reserved in POW + * - NEVER tag switch to NULL_NULL + * - NEVER tag switch from NULL_NULL + * - NULL_NULL is entered at the beginning of time and on a deschedule. + * - NULL_NULL can be exited by a new work request. A NULL_SWITCH + * load can also switch the state to NULL + */ + CVMX_POW_TAG_TYPE_NULL_NULL = 3L +}; + +/** + * Wait flag values for pow functions. + */ +typedef enum { + CVMX_POW_WAIT = 1, + CVMX_POW_NO_WAIT = 0, +} cvmx_pow_wait_t; + +/** + * POW tag operations. These are used in the data stored to the POW. + */ +typedef enum { + /* + * switch the tag (only) for this PP + * - the previous tag should be non-NULL in this case + * - tag switch response required + * - fields used: op, type, tag + */ + CVMX_POW_TAG_OP_SWTAG = 0L, + /* + * switch the tag for this PP, with full information + * - this should be used when the previous tag is NULL + * - tag switch response required + * - fields used: address, op, grp, type, tag + */ + CVMX_POW_TAG_OP_SWTAG_FULL = 1L, + /* + * switch the tag (and/or group) for this PP and de-schedule + * - OK to keep the tag the same and only change the group + * - fields used: op, no_sched, grp, type, tag + */ + CVMX_POW_TAG_OP_SWTAG_DESCH = 2L, + /* + * just de-schedule + * - fields used: op, no_sched + */ + CVMX_POW_TAG_OP_DESCH = 3L, + /* + * create an entirely new work queue entry + * - fields used: address, op, qos, grp, type, tag + */ + CVMX_POW_TAG_OP_ADDWQ = 4L, + /* + * just update the work queue pointer and grp for this PP + * - fields used: address, op, grp + */ + CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L, + /* + * set the no_sched bit on the de-schedule list + * + * - does nothing if the selected entry is not on the + * de-schedule list + * + * - does nothing if the stored work queue pointer does not + * match the address field + * + * - fields used: address, index, op + * + * Before issuing a *_NSCHED operation, SW must guarantee + * that all prior deschedules and set/clr NSCHED operations + * are complete and all prior switches are complete. The + * hardware provides the opsdone bit and swdone bit for SW + * polling. After issuing a *_NSCHED operation, SW must + * guarantee that the set/clr NSCHED is complete before any + * subsequent operations. + */ + CVMX_POW_TAG_OP_SET_NSCHED = 6L, + /* + * clears the no_sched bit on the de-schedule list + * + * - does nothing if the selected entry is not on the + * de-schedule list + * + * - does nothing if the stored work queue pointer does not + * match the address field + * + * - fields used: address, index, op + * + * Before issuing a *_NSCHED operation, SW must guarantee that + * all prior deschedules and set/clr NSCHED operations are + * complete and all prior switches are complete. The hardware + * provides the opsdone bit and swdone bit for SW + * polling. After issuing a *_NSCHED operation, SW must + * guarantee that the set/clr NSCHED is complete before any + * subsequent operations. + */ + CVMX_POW_TAG_OP_CLR_NSCHED = 7L, + /* do nothing */ + CVMX_POW_TAG_OP_NOP = 15L +} cvmx_pow_tag_op_t; + +/** + * This structure defines the store data on a store to POW + */ +typedef union { + uint64_t u64; + struct { + /* + * Don't reschedule this entry. no_sched is used for + * CVMX_POW_TAG_OP_SWTAG_DESCH and + * CVMX_POW_TAG_OP_DESCH + */ + uint64_t no_sched:1; + uint64_t unused:2; + /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */ + uint64_t index:13; + /* The operation to perform */ + cvmx_pow_tag_op_t op:4; + uint64_t unused2:2; + /* + * The QOS level for the packet. qos is only used for + * CVMX_POW_TAG_OP_ADDWQ + */ + uint64_t qos:3; + /* + * The group that the work queue entry will be + * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ, + * CVMX_POW_TAG_OP_SWTAG_FULL, + * CVMX_POW_TAG_OP_SWTAG_DESCH, and + * CVMX_POW_TAG_OP_UPDATE_WQP_GRP + */ + uint64_t grp:4; + /* + * The type of the tag. type is used for everything + * except CVMX_POW_TAG_OP_DESCH, + * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and + * CVMX_POW_TAG_OP_*_NSCHED + */ + uint64_t type:3; + /* + * The actual tag. tag is used for everything except + * CVMX_POW_TAG_OP_DESCH, + * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and + * CVMX_POW_TAG_OP_*_NSCHED + */ + uint64_t tag:32; + } s; +} cvmx_pow_tag_req_t; + +/** + * This structure describes the address to load stuff from POW + */ +typedef union { + uint64_t u64; + + /** + * Address for new work request loads (did<2:0> == 0) + */ + struct { + /* Mips64 address region. Should be CVMX_IO_SEG */ + uint64_t mem_region:2; + /* Must be zero */ + uint64_t reserved_49_61:13; + /* Must be one */ + uint64_t is_io:1; + /* the ID of POW -- did<2:0> == 0 in this case */ + uint64_t did:8; + /* Must be zero */ + uint64_t reserved_4_39:36; + /* + * If set, don't return load response until work is + * available. + */ + uint64_t wait:1; + /* Must be zero */ + uint64_t reserved_0_2:3; + } swork; + + /** + * Address for loads to get POW internal status + */ + struct { + /* Mips64 address region. Should be CVMX_IO_SEG */ + uint64_t mem_region:2; + /* Must be zero */ + uint64_t reserved_49_61:13; + /* Must be one */ + uint64_t is_io:1; + /* the ID of POW -- did<2:0> == 1 in this case */ + uint64_t did:8; + /* Must be zero */ + uint64_t reserved_10_39:30; + /* The core id to get status for */ + uint64_t coreid:4; + /* + * If set and get_cur is set, return reverse tag-list + * pointer rather than forward tag-list pointer. + */ + uint64_t get_rev:1; + /* + * If set, return current status rather than pending + * status. + */ + uint64_t get_cur:1; + /* + * If set, get the work-queue pointer rather than + * tag/type. + */ + uint64_t get_wqp:1; + /* Must be zero */ + uint64_t reserved_0_2:3; + } sstatus; + + /** + * Address for memory loads to get POW internal state + */ + struct { + /* Mips64 address region. Should be CVMX_IO_SEG */ + uint64_t mem_region:2; + /* Must be zero */ + uint64_t reserved_49_61:13; + /* Must be one */ + uint64_t is_io:1; + /* the ID of POW -- did<2:0> == 2 in this case */ + uint64_t did:8; + /* Must be zero */ + uint64_t reserved_16_39:24; + /* POW memory index */ + uint64_t index:11; + /* + * If set, return deschedule information rather than + * the standard response for work-queue index (invalid + * if the work-queue entry is not on the deschedule + * list). + */ + uint64_t get_des:1; + /* + * If set, get the work-queue pointer rather than + * tag/type (no effect when get_des set). + */ + uint64_t get_wqp:1; + /* Must be zero */ + uint64_t reserved_0_2:3; + } smemload; + + /** + * Address for index/pointer loads + */ + struct { + /* Mips64 address region. Should be CVMX_IO_SEG */ + uint64_t mem_region:2; + /* Must be zero */ + uint64_t reserved_49_61:13; + /* Must be one */ + uint64_t is_io:1; + /* the ID of POW -- did<2:0> == 3 in this case */ + uint64_t did:8; + /* Must be zero */ + uint64_t reserved_9_39:31; + /* + * when {get_rmt ==0 AND get_des_get_tail == 0}, this + * field selects one of eight POW internal-input + * queues (0-7), one per QOS level; values 8-15 are + * illegal in this case; when {get_rmt ==0 AND + * get_des_get_tail == 1}, this field selects one of + * 16 deschedule lists (per group); when get_rmt ==1, + * this field selects one of 16 memory-input queue + * lists. The two memory-input queue lists associated + * with each QOS level are: + * + * - qosgrp = 0, qosgrp = 8: QOS0 + * - qosgrp = 1, qosgrp = 9: QOS1 + * - qosgrp = 2, qosgrp = 10: QOS2 + * - qosgrp = 3, qosgrp = 11: QOS3 + * - qosgrp = 4, qosgrp = 12: QOS4 + * - qosgrp = 5, qosgrp = 13: QOS5 + * - qosgrp = 6, qosgrp = 14: QOS6 + * - qosgrp = 7, qosgrp = 15: QOS7 + */ + uint64_t qosgrp:4; + /* + * If set and get_rmt is clear, return deschedule list + * indexes rather than indexes for the specified qos + * level; if set and get_rmt is set, return the tail + * pointer rather than the head pointer for the + * specified qos level. + */ + uint64_t get_des_get_tail:1; + /* + * If set, return remote pointers rather than the + * local indexes for the specified qos level. + */ + uint64_t get_rmt:1; + /* Must be zero */ + uint64_t reserved_0_2:3; + } sindexload; + + /** + * address for NULL_RD request (did<2:0> == 4) when this is read, + * HW attempts to change the state to NULL if it is NULL_NULL (the + * hardware cannot switch from NULL_NULL to NULL if a POW entry is + * not available - software may need to recover by finishing + * another piece of work before a POW entry can ever become + * available.) + */ + struct { + /* Mips64 address region. Should be CVMX_IO_SEG */ + uint64_t mem_region:2; + /* Must be zero */ + uint64_t reserved_49_61:13; + /* Must be one */ + uint64_t is_io:1; + /* the ID of POW -- did<2:0> == 4 in this case */ + uint64_t did:8; + /* Must be zero */ + uint64_t reserved_0_39:40; + } snull_rd; +} cvmx_pow_load_addr_t; + +/** + * This structure defines the response to a load/SENDSINGLE to POW + * (except CSR reads) + */ +typedef union { + uint64_t u64; + + /** + * Response to new work request loads + */ + struct { + /* + * Set when no new work queue entry was returned. * + * If there was de-scheduled work, the HW will + * definitely return it. When this bit is set, it + * could mean either mean: + * + * - There was no work, or + * + * - There was no work that the HW could find. This + * case can happen, regardless of the wait bit value + * in the original request, when there is work in + * the IQ's that is too deep down the list. + */ + uint64_t no_work:1; + /* Must be zero */ + uint64_t reserved_40_62:23; + /* 36 in O1 -- the work queue pointer */ + uint64_t addr:40; + } s_work; + + /** + * Result for a POW Status Load (when get_cur==0 and get_wqp==0) + */ + struct { + uint64_t reserved_62_63:2; + /* Set when there is a pending non-NULL SWTAG or + * SWTAG_FULL, and the POW entry has not left the list + * for the original tag. */ + uint64_t pend_switch:1; + /* Set when SWTAG_FULL and pend_switch is set. */ + uint64_t pend_switch_full:1; + /* + * Set when there is a pending NULL SWTAG, or an + * implicit switch to NULL. + */ + uint64_t pend_switch_null:1; + /* Set when there is a pending DESCHED or SWTAG_DESCHED. */ + uint64_t pend_desched:1; + /* + * Set when there is a pending SWTAG_DESCHED and + * pend_desched is set. + */ + uint64_t pend_desched_switch:1; + /* Set when nosched is desired and pend_desched is set. */ + uint64_t pend_nosched:1; + /* Set when there is a pending GET_WORK. */ + uint64_t pend_new_work:1; + /* + * When pend_new_work is set, this bit indicates that + * the wait bit was set. + */ + uint64_t pend_new_work_wait:1; + /* Set when there is a pending NULL_RD. */ + uint64_t pend_null_rd:1; + /* Set when there is a pending CLR_NSCHED. */ + uint64_t pend_nosched_clr:1; + uint64_t reserved_51:1; + /* This is the index when pend_nosched_clr is set. */ + uint64_t pend_index:11; + /* + * This is the new_grp when (pend_desched AND + * pend_desched_switch) is set. + */ + uint64_t pend_grp:4; + uint64_t reserved_34_35:2; + /* + * This is the tag type when pend_switch or + * (pend_desched AND pend_desched_switch) are set. + */ + uint64_t pend_type:2; + /* + * - this is the tag when pend_switch or (pend_desched + * AND pend_desched_switch) are set. + */ + uint64_t pend_tag:32; + } s_sstatus0; + + /** + * Result for a POW Status Load (when get_cur==0 and get_wqp==1) + */ + struct { + uint64_t reserved_62_63:2; + /* + * Set when there is a pending non-NULL SWTAG or + * SWTAG_FULL, and the POW entry has not left the list + * for the original tag. + */ + uint64_t pend_switch:1; + /* Set when SWTAG_FULL and pend_switch is set. */ + uint64_t pend_switch_full:1; + /* + * Set when there is a pending NULL SWTAG, or an + * implicit switch to NULL. + */ + uint64_t pend_switch_null:1; + /* + * Set when there is a pending DESCHED or + * SWTAG_DESCHED. + */ + uint64_t pend_desched:1; + /* + * Set when there is a pending SWTAG_DESCHED and + * pend_desched is set. + */ + uint64_t pend_desched_switch:1; + /* Set when nosched is desired and pend_desched is set. */ + uint64_t pend_nosched:1; + /* Set when there is a pending GET_WORK. */ + uint64_t pend_new_work:1; + /* + * When pend_new_work is set, this bit indicates that + * the wait bit was set. + */ + uint64_t pend_new_work_wait:1; + /* Set when there is a pending NULL_RD. */ + uint64_t pend_null_rd:1; + /* Set when there is a pending CLR_NSCHED. */ + uint64_t pend_nosched_clr:1; + uint64_t reserved_51:1; + /* This is the index when pend_nosched_clr is set. */ + uint64_t pend_index:11; + /* + * This is the new_grp when (pend_desched AND + * pend_desched_switch) is set. + */ + uint64_t pend_grp:4; + /* This is the wqp when pend_nosched_clr is set. */ + uint64_t pend_wqp:36; + } s_sstatus1; + + /** + * Result for a POW Status Load (when get_cur==1, get_wqp==0, and + * get_rev==0) + */ + struct { + uint64_t reserved_62_63:2; + /* + * Points to the next POW entry in the tag list when + * tail == 0 (and tag_type is not NULL or NULL_NULL). + */ + uint64_t link_index:11; + /* The POW entry attached to the core. */ + uint64_t index:11; + /* + * The group attached to the core (updated when new + * tag list entered on SWTAG_FULL). + */ + uint64_t grp:4; + /* + * Set when this POW entry is at the head of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + uint64_t head:1; + /* + * Set when this POW entry is at the tail of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + uint64_t tail:1; + /* + * The tag type attached to the core (updated when new + * tag list entered on SWTAG, SWTAG_FULL, or + * SWTAG_DESCHED). + */ + uint64_t tag_type:2; + /* + * The tag attached to the core (updated when new tag + * list entered on SWTAG, SWTAG_FULL, or + * SWTAG_DESCHED). + */ + uint64_t tag:32; + } s_sstatus2; + + /** + * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1) + */ + struct { + uint64_t reserved_62_63:2; + /* + * Points to the prior POW entry in the tag list when + * head == 0 (and tag_type is not NULL or + * NULL_NULL). This field is unpredictable when the + * core's state is NULL or NULL_NULL. + */ + uint64_t revlink_index:11; + /* The POW entry attached to the core. */ + uint64_t index:11; + /* + * The group attached to the core (updated when new + * tag list entered on SWTAG_FULL). + */ + uint64_t grp:4; + /* Set when this POW entry is at the head of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + uint64_t head:1; + /* + * Set when this POW entry is at the tail of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + uint64_t tail:1; + /* + * The tag type attached to the core (updated when new + * tag list entered on SWTAG, SWTAG_FULL, or + * SWTAG_DESCHED). + */ + uint64_t tag_type:2; + /* + * The tag attached to the core (updated when new tag + * list entered on SWTAG, SWTAG_FULL, or + * SWTAG_DESCHED). + */ + uint64_t tag:32; + } s_sstatus3; + + /** + * Result for a POW Status Load (when get_cur==1, get_wqp==1, and + * get_rev==0) + */ + struct { + uint64_t reserved_62_63:2; + /* + * Points to the next POW entry in the tag list when + * tail == 0 (and tag_type is not NULL or NULL_NULL). + */ + uint64_t link_index:11; + /* The POW entry attached to the core. */ + uint64_t index:11; + /* + * The group attached to the core (updated when new + * tag list entered on SWTAG_FULL). + */ + uint64_t grp:4; + /* + * The wqp attached to the core (updated when new tag + * list entered on SWTAG_FULL). + */ + uint64_t wqp:36; + } s_sstatus4; + + /** + * Result for a POW Status Load (when get_cur==1, get_wqp==1, and + * get_rev==1) + */ + struct { + uint64_t reserved_62_63:2; + /* + * Points to the prior POW entry in the tag list when + * head == 0 (and tag_type is not NULL or + * NULL_NULL). This field is unpredictable when the + * core's state is NULL or NULL_NULL. + */ + uint64_t revlink_index:11; + /* The POW entry attached to the core. */ + uint64_t index:11; + /* + * The group attached to the core (updated when new + * tag list entered on SWTAG_FULL). + */ + uint64_t grp:4; + /* + * The wqp attached to the core (updated when new tag + * list entered on SWTAG_FULL). + */ + uint64_t wqp:36; + } s_sstatus5; + + /** + * Result For POW Memory Load (get_des == 0 and get_wqp == 0) + */ + struct { + uint64_t reserved_51_63:13; + /* + * The next entry in the input, free, descheduled_head + * list (unpredictable if entry is the tail of the + * list). + */ + uint64_t next_index:11; + /* The group of the POW entry. */ + uint64_t grp:4; + uint64_t reserved_35:1; + /* + * Set when this POW entry is at the tail of its tag + * list (also set when in the NULL or NULL_NULL + * state). + */ + uint64_t tail:1; + /* The tag type of the POW entry. */ + uint64_t tag_type:2; + /* The tag of the POW entry. */ + uint64_t tag:32; + } s_smemload0; + + /** + * Result For POW Memory Load (get_des == 0 and get_wqp == 1) + */ + struct { + uint64_t reserved_51_63:13; + /* + * The next entry in the input, free, descheduled_head + * list (unpredictable if entry is the tail of the + * list). + */ + uint64_t next_index:11; + /* The group of the POW entry. */ + uint64_t grp:4; + /* The WQP held in the POW entry. */ + uint64_t wqp:36; + } s_smemload1; + + /** + * Result For POW Memory Load (get_des == 1) + */ + struct { + uint64_t reserved_51_63:13; + /* + * The next entry in the tag list connected to the + * descheduled head. + */ + uint64_t fwd_index:11; + /* The group of the POW entry. */ + uint64_t grp:4; + /* The nosched bit for the POW entry. */ + uint64_t nosched:1; + /* There is a pending tag switch */ + uint64_t pend_switch:1; + /* + * The next tag type for the new tag list when + * pend_switch is set. + */ + uint64_t pend_type:2; + /* + * The next tag for the new tag list when pend_switch + * is set. + */ + uint64_t pend_tag:32; + } s_smemload2; + + /** + * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0) + */ + struct { + uint64_t reserved_52_63:12; + /* + * set when there is one or more POW entries on the + * free list. + */ + uint64_t free_val:1; + /* + * set when there is exactly one POW entry on the free + * list. + */ + uint64_t free_one:1; + uint64_t reserved_49:1; + /* + * when free_val is set, indicates the first entry on + * the free list. + */ + uint64_t free_head:11; + uint64_t reserved_37:1; + /* + * when free_val is set, indicates the last entry on + * the free list. + */ + uint64_t free_tail:11; + /* + * set when there is one or more POW entries on the + * input Q list selected by qosgrp. + */ + uint64_t loc_val:1; + /* + * set when there is exactly one POW entry on the + * input Q list selected by qosgrp. + */ + uint64_t loc_one:1; + uint64_t reserved_23:1; + /* + * when loc_val is set, indicates the first entry on + * the input Q list selected by qosgrp. + */ + uint64_t loc_head:11; + uint64_t reserved_11:1; + /* + * when loc_val is set, indicates the last entry on + * the input Q list selected by qosgrp. + */ + uint64_t loc_tail:11; + } sindexload0; + + /** + * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1) + */ + struct { + uint64_t reserved_52_63:12; + /* + * set when there is one or more POW entries on the + * nosched list. + */ + uint64_t nosched_val:1; + /* + * set when there is exactly one POW entry on the + * nosched list. + */ + uint64_t nosched_one:1; + uint64_t reserved_49:1; + /* + * when nosched_val is set, indicates the first entry + * on the nosched list. + */ + uint64_t nosched_head:11; + uint64_t reserved_37:1; + /* + * when nosched_val is set, indicates the last entry + * on the nosched list. + */ + uint64_t nosched_tail:11; + /* + * set when there is one or more descheduled heads on + * the descheduled list selected by qosgrp. + */ + uint64_t des_val:1; + /* + * set when there is exactly one descheduled head on + * the descheduled list selected by qosgrp. + */ + uint64_t des_one:1; + uint64_t reserved_23:1; + /* + * when des_val is set, indicates the first + * descheduled head on the descheduled list selected + * by qosgrp. + */ + uint64_t des_head:11; + uint64_t reserved_11:1; + /* + * when des_val is set, indicates the last descheduled + * head on the descheduled list selected by qosgrp. + */ + uint64_t des_tail:11; + } sindexload1; + + /** + * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0) + */ + struct { + uint64_t reserved_39_63:25; + /* + * Set when this DRAM list is the current head + * (i.e. is the next to be reloaded when the POW + * hardware reloads a POW entry from DRAM). The POW + * hardware alternates between the two DRAM lists + * associated with a QOS level when it reloads work + * from DRAM into the POW unit. + */ + uint64_t rmt_is_head:1; + /* + * Set when the DRAM portion of the input Q list + * selected by qosgrp contains one or more pieces of + * work. + */ + uint64_t rmt_val:1; + /* + * Set when the DRAM portion of the input Q list + * selected by qosgrp contains exactly one piece of + * work. + */ + uint64_t rmt_one:1; + /* + * When rmt_val is set, indicates the first piece of + * work on the DRAM input Q list selected by + * qosgrp. + */ + uint64_t rmt_head:36; + } sindexload2; + + /** + * Result For POW Index/Pointer Load (get_rmt == + * 1/get_des_get_tail == 1) + */ + struct { + uint64_t reserved_39_63:25; + /* + * set when this DRAM list is the current head + * (i.e. is the next to be reloaded when the POW + * hardware reloads a POW entry from DRAM). The POW + * hardware alternates between the two DRAM lists + * associated with a QOS level when it reloads work + * from DRAM into the POW unit. + */ + uint64_t rmt_is_head:1; + /* + * set when the DRAM portion of the input Q list + * selected by qosgrp contains one or more pieces of + * work. + */ + uint64_t rmt_val:1; + /* + * set when the DRAM portion of the input Q list + * selected by qosgrp contains exactly one piece of + * work. + */ + uint64_t rmt_one:1; + /* + * when rmt_val is set, indicates the last piece of + * work on the DRAM input Q list selected by + * qosgrp. + */ + uint64_t rmt_tail:36; + } sindexload3; + + /** + * Response to NULL_RD request loads + */ + struct { + uint64_t unused:62; + /* of type cvmx_pow_tag_type_t. state is one of the + * following: + * + * - CVMX_POW_TAG_TYPE_ORDERED + * - CVMX_POW_TAG_TYPE_ATOMIC + * - CVMX_POW_TAG_TYPE_NULL + * - CVMX_POW_TAG_TYPE_NULL_NULL + */ + uint64_t state:2; + } s_null_rd; + +} cvmx_pow_tag_load_resp_t; + +/** + * This structure describes the address used for stores to the POW. + * The store address is meaningful on stores to the POW. The + * hardware assumes that an aligned 64-bit store was used for all + * these stores. Note the assumption that the work queue entry is + * aligned on an 8-byte boundary (since the low-order 3 address bits + * must be zero). Note that not all fields are used by all + * operations. + * + * NOTE: The following is the behavior of the pending switch bit at the PP + * for POW stores (i.e. when did<7:3> == 0xc) + * - did<2:0> == 0 => pending switch bit is set + * - did<2:0> == 1 => no affect on the pending switch bit + * - did<2:0> == 3 => pending switch bit is cleared + * - did<2:0> == 7 => no affect on the pending switch bit + * - did<2:0> == others => must not be used + * - No other loads/stores have an affect on the pending switch bit + * - The switch bus from POW can clear the pending switch bit + * + * NOTE: did<2:0> == 2 is used by the HW for a special single-cycle + * ADDWQ command that only contains the pointer). SW must never use + * did<2:0> == 2. + */ +typedef union { + /** + * Unsigned 64 bit integer representation of store address + */ + uint64_t u64; + + struct { + /* Memory region. Should be CVMX_IO_SEG in most cases */ + uint64_t mem_reg:2; + uint64_t reserved_49_61:13; /* Must be zero */ + uint64_t is_io:1; /* Must be one */ + /* Device ID of POW. Note that different sub-dids are used. */ + uint64_t did:8; + uint64_t reserved_36_39:4; /* Must be zero */ + /* Address field. addr<2:0> must be zero */ + uint64_t addr:36; + } stag; +} cvmx_pow_tag_store_addr_t; + +/** + * decode of the store data when an IOBDMA SENDSINGLE is sent to POW + */ +typedef union { + uint64_t u64; + + struct { + /* + * the (64-bit word) location in scratchpad to write + * to (if len != 0) + */ + uint64_t scraddr:8; + /* the number of words in the response (0 => no response) */ + uint64_t len:8; + /* the ID of the device on the non-coherent bus */ + uint64_t did:8; + uint64_t unused:36; + /* if set, don't return load response until work is available */ + uint64_t wait:1; + uint64_t unused2:3; + } s; + +} cvmx_pow_iobdma_store_t; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Get the POW tag for this core. This returns the current + * tag type, tag, group, and POW entry index associated with + * this core. Index is only valid if the tag type isn't NULL_NULL. + * If a tag switch is pending this routine returns the tag before + * the tag switch, not after. + * + * Returns Current tag + */ +static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void) +{ + cvmx_pow_load_addr_t load_addr; + cvmx_pow_tag_load_resp_t load_resp; + cvmx_pow_tag_req_t result; + + load_addr.u64 = 0; + load_addr.sstatus.mem_region = CVMX_IO_SEG; + load_addr.sstatus.is_io = 1; + load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1; + load_addr.sstatus.coreid = cvmx_get_core_num(); + load_addr.sstatus.get_cur = 1; + load_resp.u64 = cvmx_read_csr(load_addr.u64); + result.u64 = 0; + result.s.grp = load_resp.s_sstatus2.grp; + result.s.index = load_resp.s_sstatus2.index; + result.s.type = load_resp.s_sstatus2.tag_type; + result.s.tag = load_resp.s_sstatus2.tag; + return result; +} + +/** + * Get the POW WQE for this core. This returns the work queue + * entry currently associated with this core. + * + * Returns WQE pointer + */ +static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void) +{ + cvmx_pow_load_addr_t load_addr; + cvmx_pow_tag_load_resp_t load_resp; + + load_addr.u64 = 0; + load_addr.sstatus.mem_region = CVMX_IO_SEG; + load_addr.sstatus.is_io = 1; + load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1; + load_addr.sstatus.coreid = cvmx_get_core_num(); + load_addr.sstatus.get_cur = 1; + load_addr.sstatus.get_wqp = 1; + load_resp.u64 = cvmx_read_csr(load_addr.u64); + return (cvmx_wqe_t *) cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp); +} + +#ifndef CVMX_MF_CHORD +#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) +#endif + +/** + * Print a warning if a tag switch is pending for this core + * + * @function: Function name checking for a pending tag switch + */ +static inline void __cvmx_pow_warn_if_pending_switch(const char *function) +{ + uint64_t switch_complete; + CVMX_MF_CHORD(switch_complete); + if (!switch_complete) + pr_warning("%s called with tag switch in progress\n", function); +} + +/** + * Waits for a tag switch to complete by polling the completion bit. + * Note that switches to NULL complete immediately and do not need + * to be waited for. + */ +static inline void cvmx_pow_tag_sw_wait(void) +{ + const uint64_t MAX_CYCLES = 1ull << 31; + uint64_t switch_complete; + uint64_t start_cycle = cvmx_get_cycle(); + while (1) { + CVMX_MF_CHORD(switch_complete); + if (unlikely(switch_complete)) + break; + if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) { + pr_warning("Tag switch is taking a long time, " + "possible deadlock\n"); + start_cycle = -MAX_CYCLES - 1; + } + } +} + +/** + * Synchronous work request. Requests work from the POW. + * This function does NOT wait for previous tag switches to complete, + * so the caller must ensure that there is not a pending tag switch. + * + * @wait: When set, call stalls until work becomes avaiable, or times out. + * If not set, returns immediately. + * + * Returns Returns the WQE pointer from POW. Returns NULL if no work + * was available. + */ +static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t + wait) +{ + cvmx_pow_load_addr_t ptr; + cvmx_pow_tag_load_resp_t result; + + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + ptr.u64 = 0; + ptr.swork.mem_region = CVMX_IO_SEG; + ptr.swork.is_io = 1; + ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG; + ptr.swork.wait = wait; + + result.u64 = cvmx_read_csr(ptr.u64); + + if (result.s_work.no_work) + return NULL; + else + return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr); +} + +/** + * Synchronous work request. Requests work from the POW. + * This function waits for any previous tag switch to complete before + * requesting the new work. + * + * @wait: When set, call stalls until work becomes avaiable, or times out. + * If not set, returns immediately. + * + * Returns Returns the WQE pointer from POW. Returns NULL if no work + * was available. + */ +static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* Must not have a switch pending when requesting work */ + cvmx_pow_tag_sw_wait(); + return cvmx_pow_work_request_sync_nocheck(wait); + +} + +/** + * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state. + * This function waits for any previous tag switch to complete before + * requesting the null_rd. + * + * Returns Returns the POW state of type cvmx_pow_tag_type_t. + */ +static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void) +{ + cvmx_pow_load_addr_t ptr; + cvmx_pow_tag_load_resp_t result; + + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* Must not have a switch pending when requesting work */ + cvmx_pow_tag_sw_wait(); + + ptr.u64 = 0; + ptr.snull_rd.mem_region = CVMX_IO_SEG; + ptr.snull_rd.is_io = 1; + ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD; + + result.u64 = cvmx_read_csr(ptr.u64); + + return (enum cvmx_pow_tag_type) result.s_null_rd.state; +} + +/** + * Asynchronous work request. Work is requested from the POW unit, + * and should later be checked with function + * cvmx_pow_work_response_async. This function does NOT wait for + * previous tag switches to complete, so the caller must ensure that + * there is not a pending tag switch. + * + * @scr_addr: Scratch memory address that response will be returned + * to, which is either a valid WQE, or a response with the + * invalid bit set. Byte address, must be 8 byte aligned. + * + * @wait: 1 to cause response to wait for work to become available (or + * timeout), 0 to cause response to return immediately + */ +static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, + cvmx_pow_wait_t wait) +{ + cvmx_pow_iobdma_store_t data; + + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* scr_addr must be 8 byte aligned */ + data.s.scraddr = scr_addr >> 3; + data.s.len = 1; + data.s.did = CVMX_OCT_DID_TAG_SWTAG; + data.s.wait = wait; + cvmx_send_single(data.u64); +} + +/** + * Asynchronous work request. Work is requested from the POW unit, + * and should later be checked with function + * cvmx_pow_work_response_async. This function waits for any previous + * tag switch to complete before requesting the new work. + * + * @scr_addr: Scratch memory address that response will be returned + * to, which is either a valid WQE, or a response with the + * invalid bit set. Byte address, must be 8 byte aligned. + * + * @wait: 1 to cause response to wait for work to become available (or + * timeout), 0 to cause response to return immediately + */ +static inline void cvmx_pow_work_request_async(int scr_addr, + cvmx_pow_wait_t wait) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* Must not have a switch pending when requesting work */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_work_request_async_nocheck(scr_addr, wait); +} + +/** + * Gets result of asynchronous work request. Performs a IOBDMA sync + * to wait for the response. + * + * @scr_addr: Scratch memory address to get result from Byte address, + * must be 8 byte aligned. + * + * Returns Returns the WQE from the scratch register, or NULL if no + * work was available. + */ +static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr) +{ + cvmx_pow_tag_load_resp_t result; + + CVMX_SYNCIOBDMA; + result.u64 = cvmx_scratch_read64(scr_addr); + + if (result.s_work.no_work) + return NULL; + else + return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr); +} + +/** + * Checks if a work queue entry pointer returned by a work + * request is valid. It may be invalid due to no work + * being available or due to a timeout. + * + * @wqe_ptr: pointer to a work queue entry returned by the POW + * + * Returns 0 if pointer is valid + * 1 if invalid (no work was returned) + */ +static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr) +{ + return wqe_ptr == NULL; +} + +/** + * Starts a tag switch to the provided tag value and tag type. + * Completion for the tag switch must be checked for separately. This + * function does NOT update the work queue entry in dram to match tag + * value and type, so the application must keep track of these if they + * are important to the application. This tag switch command must not + * be used for switches to NULL, as the tag switch pending bit will be + * set by the switch request, but never cleared by the hardware. + * + * NOTE: This should not be used when switching from a NULL tag. Use + * cvmx_pow_tag_sw_full() instead. + * + * This function does no checks, so the caller must ensure that any + * previous tag switch has completed. + * + * @tag: new tag value + * @tag_type: new tag type (ordered or atomic) + */ +static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, + enum cvmx_pow_tag_type tag_type) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warning("%s called with NULL_NULL tag\n", + __func__); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) + pr_warning("%s called with NULL tag\n", __func__); + if ((current_tag.s.type == tag_type) + && (current_tag.s.tag == tag)) + pr_warning("%s called to perform a tag switch to the " + "same tag\n", + __func__); + if (tag_type == CVMX_POW_TAG_TYPE_NULL) + pr_warning("%s called to perform a tag switch to " + "NULL. Use cvmx_pow_tag_sw_null() instead\n", + __func__); + } + + /* + * Note that WQE in DRAM is not updated here, as the POW does + * not read from DRAM once the WQE is in flight. See hardware + * manual for complete details. It is the application's + * responsibility to keep track of the current tag value if + * that is important. + */ + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_SWTAG; + tag_req.s.tag = tag; + tag_req.s.type = tag_type; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; + + /* once this store arrives at POW, it will attempt the switch + software must wait for the switch to complete separately */ + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/** + * Starts a tag switch to the provided tag value and tag type. + * Completion for the tag switch must be checked for separately. This + * function does NOT update the work queue entry in dram to match tag + * value and type, so the application must keep track of these if they + * are important to the application. This tag switch command must not + * be used for switches to NULL, as the tag switch pending bit will be + * set by the switch request, but never cleared by the hardware. + * + * NOTE: This should not be used when switching from a NULL tag. Use + * cvmx_pow_tag_sw_full() instead. + * + * This function waits for any previous tag switch to complete, and also + * displays an error on tag switches to NULL. + * + * @tag: new tag value + * @tag_type: new tag type (ordered or atomic) + */ +static inline void cvmx_pow_tag_sw(uint32_t tag, + enum cvmx_pow_tag_type tag_type) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* + * Note that WQE in DRAM is not updated here, as the POW does + * not read from DRAM once the WQE is in flight. See hardware + * manual for complete details. It is the application's + * responsibility to keep track of the current tag value if + * that is important. + */ + + /* + * Ensure that there is not a pending tag switch, as a tag + * switch cannot be started if a previous switch is still + * pending. + */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_tag_sw_nocheck(tag, tag_type); +} + +/** + * Starts a tag switch to the provided tag value and tag type. + * Completion for the tag switch must be checked for separately. This + * function does NOT update the work queue entry in dram to match tag + * value and type, so the application must keep track of these if they + * are important to the application. This tag switch command must not + * be used for switches to NULL, as the tag switch pending bit will be + * set by the switch request, but never cleared by the hardware. + * + * This function must be used for tag switches from NULL. + * + * This function does no checks, so the caller must ensure that any + * previous tag switch has completed. + * + * @wqp: pointer to work queue entry to submit. This entry is + * updated to match the other parameters + * @tag: tag value to be assigned to work queue entry + * @tag_type: type of tag + * @group: group value for the work queue entry. + */ +static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, + enum cvmx_pow_tag_type tag_type, + uint64_t group) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warning("%s called with NULL_NULL tag\n", + __func__); + if ((current_tag.s.type == tag_type) + && (current_tag.s.tag == tag)) + pr_warning("%s called to perform a tag switch to " + "the same tag\n", + __func__); + if (tag_type == CVMX_POW_TAG_TYPE_NULL) + pr_warning("%s called to perform a tag switch to " + "NULL. Use cvmx_pow_tag_sw_null() instead\n", + __func__); + if (wqp != cvmx_phys_to_ptr(0x80)) + if (wqp != cvmx_pow_get_current_wqp()) + pr_warning("%s passed WQE(%p) doesn't match " + "the address in the POW(%p)\n", + __func__, wqp, + cvmx_pow_get_current_wqp()); + } + + /* + * Note that WQE in DRAM is not updated here, as the POW does + * not read from DRAM once the WQE is in flight. See hardware + * manual for complete details. It is the application's + * responsibility to keep track of the current tag value if + * that is important. + */ + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL; + tag_req.s.tag = tag; + tag_req.s.type = tag_type; + tag_req.s.grp = group; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; + ptr.sio.offset = CAST64(wqp); + + /* + * once this store arrives at POW, it will attempt the switch + * software must wait for the switch to complete separately. + */ + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/** + * Starts a tag switch to the provided tag value and tag type. + * Completion for the tag switch must be checked for separately. This + * function does NOT update the work queue entry in dram to match tag + * value and type, so the application must keep track of these if they + * are important to the application. This tag switch command must not + * be used for switches to NULL, as the tag switch pending bit will be + * set by the switch request, but never cleared by the hardware. + * + * This function must be used for tag switches from NULL. + * + * This function waits for any pending tag switches to complete + * before requesting the tag switch. + * + * @wqp: pointer to work queue entry to submit. This entry is updated + * to match the other parameters + * @tag: tag value to be assigned to work queue entry + * @tag_type: type of tag + * @group: group value for the work queue entry. + */ +static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag, + enum cvmx_pow_tag_type tag_type, + uint64_t group) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* + * Ensure that there is not a pending tag switch, as a tag + * switch cannot be started if a previous switch is still + * pending. + */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group); +} + +/** + * Switch to a NULL tag, which ends any ordering or + * synchronization provided by the POW for the current + * work queue entry. This operation completes immediately, + * so completion should not be waited for. + * This function does NOT wait for previous tag switches to complete, + * so the caller must ensure that any previous tag switches have completed. + */ +static inline void cvmx_pow_tag_sw_null_nocheck(void) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warning("%s called with NULL_NULL tag\n", + __func__); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) + pr_warning("%s called when we already have a " + "NULL tag\n", + __func__); + } + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_SWTAG; + tag_req.s.type = CVMX_POW_TAG_TYPE_NULL; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; + + cvmx_write_io(ptr.u64, tag_req.u64); + + /* switch to NULL completes immediately */ +} + +/** + * Switch to a NULL tag, which ends any ordering or + * synchronization provided by the POW for the current + * work queue entry. This operation completes immediately, + * so completion should not be waited for. + * This function waits for any pending tag switches to complete + * before requesting the switch to NULL. + */ +static inline void cvmx_pow_tag_sw_null(void) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* + * Ensure that there is not a pending tag switch, as a tag + * switch cannot be started if a previous switch is still + * pending. + */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_tag_sw_null_nocheck(); + + /* switch to NULL completes immediately */ +} + +/** + * Submits work to an input queue. This function updates the work + * queue entry in DRAM to match the arguments given. Note that the + * tag provided is for the work queue entry submitted, and is + * unrelated to the tag that the core currently holds. + * + * @wqp: pointer to work queue entry to submit. This entry is + * updated to match the other parameters + * @tag: tag value to be assigned to work queue entry + * @tag_type: type of tag + * @qos: Input queue to add to. + * @grp: group value for the work queue entry. + */ +static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, + enum cvmx_pow_tag_type tag_type, + uint64_t qos, uint64_t grp) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + wqp->qos = qos; + wqp->tag = tag; + wqp->tag_type = tag_type; + wqp->grp = grp; + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ; + tag_req.s.type = tag_type; + tag_req.s.tag = tag; + tag_req.s.qos = qos; + tag_req.s.grp = grp; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; + ptr.sio.offset = cvmx_ptr_to_phys(wqp); + + /* + * SYNC write to memory before the work submit. This is + * necessary as POW may read values from DRAM at this time. + */ + CVMX_SYNCWS; + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/** + * This function sets the group mask for a core. The group mask + * indicates which groups each core will accept work from. There are + * 16 groups. + * + * @core_num: core to apply mask to + * @mask: Group mask. There are 16 groups, so only bits 0-15 are valid, + * representing groups 0-15. + * Each 1 bit in the mask enables the core to accept work from + * the corresponding group. + */ +static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask) +{ + union cvmx_pow_pp_grp_mskx grp_msk; + + grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); + grp_msk.s.grp_msk = mask; + cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); +} + +/** + * This function sets POW static priorities for a core. Each input queue has + * an associated priority value. + * + * @core_num: core to apply priorities to + * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). + * Highest priority is 0 and lowest is 7. A priority value + * of 0xF instructs POW to skip the Input Queue when + * scheduling to this specific core. + * NOTE: priorities should not have gaps in values, meaning + * {0,1,1,1,1,1,1,1} is a valid configuration while + * {0,2,2,2,2,2,2,2} is not. + */ +static inline void cvmx_pow_set_priority(uint64_t core_num, + const uint8_t priority[]) +{ + /* POW priorities are supported on CN5xxx and later */ + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { + union cvmx_pow_pp_grp_mskx grp_msk; + + grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); + grp_msk.s.qos0_pri = priority[0]; + grp_msk.s.qos1_pri = priority[1]; + grp_msk.s.qos2_pri = priority[2]; + grp_msk.s.qos3_pri = priority[3]; + grp_msk.s.qos4_pri = priority[4]; + grp_msk.s.qos5_pri = priority[5]; + grp_msk.s.qos6_pri = priority[6]; + grp_msk.s.qos7_pri = priority[7]; + + /* Detect gaps between priorities and flag error */ + { + int i; + uint32_t prio_mask = 0; + + for (i = 0; i < 8; i++) + if (priority[i] != 0xF) + prio_mask |= 1 << priority[i]; + + if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) { + pr_err("POW static priorities should be " + "contiguous (0x%llx)\n", + (unsigned long long)prio_mask); + return; + } + } + + cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); + } +} + +/** + * Performs a tag switch and then an immediate deschedule. This completes + * immediately, so completion must not be waited for. This function does NOT + * update the wqe in DRAM to match arguments. + * + * This function does NOT wait for any prior tag switches to complete, so the + * calling code must do this. + * + * Note the following CAVEAT of the Octeon HW behavior when + * re-scheduling DE-SCHEDULEd items whose (next) state is + * ORDERED: + * - If there are no switches pending at the time that the + * HW executes the de-schedule, the HW will only re-schedule + * the head of the FIFO associated with the given tag. This + * means that in many respects, the HW treats this ORDERED + * tag as an ATOMIC tag. Note that in the SWTAG_DESCH + * case (to an ORDERED tag), the HW will do the switch + * before the deschedule whenever it is possible to do + * the switch immediately, so it may often look like + * this case. + * - If there is a pending switch to ORDERED at the time + * the HW executes the de-schedule, the HW will perform + * the switch at the time it re-schedules, and will be + * able to reschedule any/all of the entries with the + * same tag. + * Due to this behavior, the RECOMMENDATION to software is + * that they have a (next) state of ATOMIC when they + * DE-SCHEDULE. If an ORDERED tag is what was really desired, + * SW can choose to immediately switch to an ORDERED tag + * after the work (that has an ATOMIC tag) is re-scheduled. + * Note that since there are never any tag switches pending + * when the HW re-schedules, this switch can be IMMEDIATE upon + * the reception of the pointer during the re-schedule. + * + * @tag: New tag value + * @tag_type: New tag type + * @group: New group value + * @no_sched: Control whether this work queue entry will be rescheduled. + * - 1 : don't schedule this work + * - 0 : allow this work to be scheduled. + */ +static inline void cvmx_pow_tag_sw_desched_nocheck( + uint32_t tag, + enum cvmx_pow_tag_type tag_type, + uint64_t group, + uint64_t no_sched) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warning("%s called with NULL_NULL tag\n", + __func__); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) + pr_warning("%s called with NULL tag. Deschedule not " + "allowed from NULL state\n", + __func__); + if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC) + && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC)) + pr_warning("%s called where neither the before or " + "after tag is ATOMIC\n", + __func__); + } + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH; + tag_req.s.tag = tag; + tag_req.s.type = tag_type; + tag_req.s.grp = group; + tag_req.s.no_sched = no_sched; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_TAG3; + /* + * since TAG3 is used, this store will clear the local pending + * switch bit. + */ + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/** + * Performs a tag switch and then an immediate deschedule. This completes + * immediately, so completion must not be waited for. This function does NOT + * update the wqe in DRAM to match arguments. + * + * This function waits for any prior tag switches to complete, so the + * calling code may call this function with a pending tag switch. + * + * Note the following CAVEAT of the Octeon HW behavior when + * re-scheduling DE-SCHEDULEd items whose (next) state is + * ORDERED: + * - If there are no switches pending at the time that the + * HW executes the de-schedule, the HW will only re-schedule + * the head of the FIFO associated with the given tag. This + * means that in many respects, the HW treats this ORDERED + * tag as an ATOMIC tag. Note that in the SWTAG_DESCH + * case (to an ORDERED tag), the HW will do the switch + * before the deschedule whenever it is possible to do + * the switch immediately, so it may often look like + * this case. + * - If there is a pending switch to ORDERED at the time + * the HW executes the de-schedule, the HW will perform + * the switch at the time it re-schedules, and will be + * able to reschedule any/all of the entries with the + * same tag. + * Due to this behavior, the RECOMMENDATION to software is + * that they have a (next) state of ATOMIC when they + * DE-SCHEDULE. If an ORDERED tag is what was really desired, + * SW can choose to immediately switch to an ORDERED tag + * after the work (that has an ATOMIC tag) is re-scheduled. + * Note that since there are never any tag switches pending + * when the HW re-schedules, this switch can be IMMEDIATE upon + * the reception of the pointer during the re-schedule. + * + * @tag: New tag value + * @tag_type: New tag type + * @group: New group value + * @no_sched: Control whether this work queue entry will be rescheduled. + * - 1 : don't schedule this work + * - 0 : allow this work to be scheduled. + */ +static inline void cvmx_pow_tag_sw_desched(uint32_t tag, + enum cvmx_pow_tag_type tag_type, + uint64_t group, uint64_t no_sched) +{ + if (CVMX_ENABLE_POW_CHECKS) + __cvmx_pow_warn_if_pending_switch(__func__); + + /* Need to make sure any writes to the work queue entry are complete */ + CVMX_SYNCWS; + /* + * Ensure that there is not a pending tag switch, as a tag + * switch cannot be started if a previous switch is still + * pending. + */ + cvmx_pow_tag_sw_wait(); + cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched); +} + +/** + * Descchedules the current work queue entry. + * + * @no_sched: no schedule flag value to be set on the work queue + * entry. If this is set the entry will not be + * rescheduled. + */ +static inline void cvmx_pow_desched(uint64_t no_sched) +{ + cvmx_addr_t ptr; + cvmx_pow_tag_req_t tag_req; + + if (CVMX_ENABLE_POW_CHECKS) { + cvmx_pow_tag_req_t current_tag; + __cvmx_pow_warn_if_pending_switch(__func__); + current_tag = cvmx_pow_get_current_tag(); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) + pr_warning("%s called with NULL_NULL tag\n", + __func__); + if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) + pr_warning("%s called with NULL tag. Deschedule not " + "expected from NULL state\n", + __func__); + } + + /* Need to make sure any writes to the work queue entry are complete */ + CVMX_SYNCWS; + + tag_req.u64 = 0; + tag_req.s.op = CVMX_POW_TAG_OP_DESCH; + tag_req.s.no_sched = no_sched; + + ptr.u64 = 0; + ptr.sio.mem_region = CVMX_IO_SEG; + ptr.sio.is_io = 1; + ptr.sio.did = CVMX_OCT_DID_TAG_TAG3; + /* + * since TAG3 is used, this store will clear the local pending + * switch bit. + */ + cvmx_write_io(ptr.u64, tag_req.u64); +} + +/**************************************************** +* Define usage of bits within the 32 bit tag values. +*****************************************************/ + +/* + * Number of bits of the tag used by software. The SW bits are always + * a contiguous block of the high starting at bit 31. The hardware + * bits are always the low bits. By default, the top 8 bits of the + * tag are reserved for software, and the low 24 are set by the IPD + * unit. + */ +#define CVMX_TAG_SW_BITS (8) +#define CVMX_TAG_SW_SHIFT (32 - CVMX_TAG_SW_BITS) + +/* Below is the list of values for the top 8 bits of the tag. */ +/* + * Tag values with top byte of this value are reserved for internal + * executive uses. + */ +#define CVMX_TAG_SW_BITS_INTERNAL 0x1 +/* The executive divides the remaining 24 bits as follows: + * - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup + * + * - the lower 16 bits (bits 15 - 0 of the tag) define are the value + * with the subgroup + * + * Note that this section describes the format of tags generated by + * software - refer to the hardware documentation for a description of + * the tags values generated by the packet input hardware. Subgroups + * are defined here. + */ +/* Mask for the value portion of the tag */ +#define CVMX_TAG_SUBGROUP_MASK 0xFFFF +#define CVMX_TAG_SUBGROUP_SHIFT 16 +#define CVMX_TAG_SUBGROUP_PKO 0x1 + +/* End of executive tag subgroup definitions */ + +/* + * The remaining values software bit values 0x2 - 0xff are available + * for application use. + */ + +/** + * This function creates a 32 bit tag value from the two values provided. + * + * @sw_bits: The upper bits (number depends on configuration) are set + * to this value. The remainder of bits are set by the + * hw_bits parameter. + * + * @hw_bits: The lower bits (number depends on configuration) are set + * to this value. The remainder of bits are set by the + * sw_bits parameter. + * + * Returns 32 bit value of the combined hw and sw bits. + */ +static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits) +{ + return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) << + CVMX_TAG_SW_SHIFT) | + (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS)); +} + +/** + * Extracts the bits allocated for software use from the tag + * + * @tag: 32 bit tag value + * + * Returns N bit software tag value, where N is configurable with the + * CVMX_TAG_SW_BITS define + */ +static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag) +{ + return (tag >> (32 - CVMX_TAG_SW_BITS)) & + cvmx_build_mask(CVMX_TAG_SW_BITS); +} + +/** + * + * Extracts the bits allocated for hardware use from the tag + * + * @tag: 32 bit tag value + * + * Returns (32 - N) bit software tag value, where N is configurable + * with the CVMX_TAG_SW_BITS define + */ +static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag) +{ + return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS); +} + +/** + * Store the current POW internal state into the supplied + * buffer. It is recommended that you pass a buffer of at least + * 128KB. The format of the capture may change based on SDK + * version and Octeon chip. + * + * @buffer: Buffer to store capture into + * @buffer_size: + * The size of the supplied buffer + * + * Returns Zero on success, negative on failure + */ +extern int cvmx_pow_capture(void *buffer, int buffer_size); + +/** + * Dump a POW capture to the console in a human readable format. + * + * @buffer: POW capture from cvmx_pow_capture() + * @buffer_size: + * Size of the buffer + */ +extern void cvmx_pow_display(void *buffer, int buffer_size); + +/** + * Return the number of POW entries supported by this chip + * + * Returns Number of POW entries + */ +extern int cvmx_pow_get_num_entries(void); + +#endif /* __CVMX_POW_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h new file mode 100644 index 000000000000..96b70cfd6245 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-scratch.h @@ -0,0 +1,139 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * This file provides support for the processor local scratch memory. + * Scratch memory is byte addressable - all addresses are byte addresses. + * + */ + +#ifndef __CVMX_SCRATCH_H__ +#define __CVMX_SCRATCH_H__ + +/* + * Note: This define must be a long, not a long long in order to + * compile without warnings for both 32bit and 64bit. + */ +#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */ + +/** + * Reads an 8 bit value from the processor local scratchpad memory. + * + * @address: byte address to read from + * + * Returns value read + */ +static inline uint8_t cvmx_scratch_read8(uint64_t address) +{ + return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address); +} + +/** + * Reads a 16 bit value from the processor local scratchpad memory. + * + * @address: byte address to read from + * + * Returns value read + */ +static inline uint16_t cvmx_scratch_read16(uint64_t address) +{ + return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address); +} + +/** + * Reads a 32 bit value from the processor local scratchpad memory. + * + * @address: byte address to read from + * + * Returns value read + */ +static inline uint32_t cvmx_scratch_read32(uint64_t address) +{ + return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address); +} + +/** + * Reads a 64 bit value from the processor local scratchpad memory. + * + * @address: byte address to read from + * + * Returns value read + */ +static inline uint64_t cvmx_scratch_read64(uint64_t address) +{ + return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address); +} + +/** + * Writes an 8 bit value to the processor local scratchpad memory. + * + * @address: byte address to write to + * @value: value to write + */ +static inline void cvmx_scratch_write8(uint64_t address, uint64_t value) +{ + *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) = + (uint8_t) value; +} + +/** + * Writes a 32 bit value to the processor local scratchpad memory. + * + * @address: byte address to write to + * @value: value to write + */ +static inline void cvmx_scratch_write16(uint64_t address, uint64_t value) +{ + *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) = + (uint16_t) value; +} + +/** + * Writes a 16 bit value to the processor local scratchpad memory. + * + * @address: byte address to write to + * @value: value to write + */ +static inline void cvmx_scratch_write32(uint64_t address, uint64_t value) +{ + *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) = + (uint32_t) value; +} + +/** + * Writes a 64 bit value to the processor local scratchpad memory. + * + * @address: byte address to write to + * @value: value to write + */ +static inline void cvmx_scratch_write64(uint64_t address, uint64_t value) +{ + *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value; +} + +#endif /* __CVMX_SCRATCH_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h new file mode 100644 index 000000000000..e814648953a5 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-spi.h @@ -0,0 +1,269 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * This file contains defines for the SPI interface + */ +#ifndef __CVMX_SPI_H__ +#define __CVMX_SPI_H__ + +#include "cvmx-gmxx-defs.h" + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +typedef enum { + CVMX_SPI_MODE_UNKNOWN = 0, + CVMX_SPI_MODE_TX_HALFPLEX = 1, + CVMX_SPI_MODE_RX_HALFPLEX = 2, + CVMX_SPI_MODE_DUPLEX = 3 +} cvmx_spi_mode_t; + +/** Callbacks structure to customize SPI4 initialization sequence */ +typedef struct { + /** Called to reset SPI4 DLL */ + int (*reset_cb) (int interface, cvmx_spi_mode_t mode); + + /** Called to setup calendar */ + int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode, + int num_ports); + + /** Called for Tx and Rx clock detection */ + int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode, + int timeout); + + /** Called to perform link training */ + int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout); + + /** Called for calendar data synchronization */ + int (*calendar_sync_cb) (int interface, cvmx_spi_mode_t mode, + int timeout); + + /** Called when interface is up */ + int (*interface_up_cb) (int interface, cvmx_spi_mode_t mode); + +} cvmx_spi_callbacks_t; + +/** + * Return true if the supplied interface is configured for SPI + * + * @interface: Interface to check + * Returns True if interface is SPI + */ +static inline int cvmx_spi_is_spi_interface(int interface) +{ + uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + return (gmxState & 0x2) && (gmxState & 0x1); +} + +/** + * Initialize and start the SPI interface. + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * @num_ports: Number of SPI ports to configure + * + * Returns Zero on success, negative of failure. + */ +extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, + int timeout, int num_ports); + +/** + * This routine restarts the SPI interface after it has lost synchronization + * with its corespondant system. + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * Returns Zero on success, negative of failure. + */ +extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, + int timeout); + +/** + * Return non-zero if the SPI interface has a SPI4000 attached + * + * @interface: SPI interface the SPI4000 is connected to + * + * Returns + */ +static inline int cvmx_spi4000_is_present(int interface) +{ + return 0; +} + +/** + * Initialize the SPI4000 for use + * + * @interface: SPI interface the SPI4000 is connected to + */ +static inline int cvmx_spi4000_initialize(int interface) +{ + return 0; +} + +/** + * Poll all the SPI4000 port and check its speed + * + * @interface: Interface the SPI4000 is on + * @port: Port to poll (0-9) + * Returns Status of the port. 0=down. All other values the port is up. + */ +static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed( + int interface, + int port) +{ + union cvmx_gmxx_rxx_rx_inbnd r; + r.u64 = 0; + return r; +} + +/** + * Get current SPI4 initialization callbacks + * + * @callbacks: Pointer to the callbacks structure.to fill + * + * Returns Pointer to cvmx_spi_callbacks_t structure. + */ +extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks); + +/** + * Set new SPI4 initialization callbacks + * + * @new_callbacks: Pointer to an updated callbacks structure. + */ +extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks); + +/** + * Callback to perform SPI4 reset + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode); + +/** + * Callback to setup calendar and miscellaneous settings before clock + * detection + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @num_ports: Number of ports to configure on SPI + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, + int num_ports); + +/** + * Callback to perform clock detection + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for clock synchronization in seconds + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, + int timeout); + +/** + * Callback to perform link training + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for link to be trained (in seconds) + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, + int timeout); + +/** + * Callback to perform calendar data synchronization + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * @timeout: Timeout to wait for calendar data in seconds + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, + int timeout); + +/** + * Callback to handle interface up + * + * @interface: The identifier of the packet interface to configure and + * use as a SPI interface. + * @mode: The operating mode for the SPI interface. The interface + * can operate as a full duplex (both Tx and Rx data paths + * active) or as a halfplex (either the Tx data path is + * active or the Rx data path is active, but not both). + * + * Returns Zero on success, non-zero error code on failure (will cause + * SPI initialization to abort) + */ +extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode); + +#endif /* __CVMX_SPI_H__ */ diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h new file mode 100644 index 000000000000..b16940e32c83 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h @@ -0,0 +1,347 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SPXX_DEFS_H__ +#define __CVMX_SPXX_DEFS_H__ + +#define CVMX_SPXX_BCKPRS_CNT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_BIST_STAT(block_id) \ + CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_CLK_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_CLK_STAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_DRV_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_ERR_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_INT_DAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_INT_MSK(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_INT_SYNC(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_TPA_ACC(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_TPA_MAX(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_TPA_SEL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SPXX_TRN4_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_spxx_bckprs_cnt { + uint64_t u64; + struct cvmx_spxx_bckprs_cnt_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_spxx_bckprs_cnt_s cn38xx; + struct cvmx_spxx_bckprs_cnt_s cn38xxp2; + struct cvmx_spxx_bckprs_cnt_s cn58xx; + struct cvmx_spxx_bckprs_cnt_s cn58xxp1; +}; + +union cvmx_spxx_bist_stat { + uint64_t u64; + struct cvmx_spxx_bist_stat_s { + uint64_t reserved_3_63:61; + uint64_t stat2:1; + uint64_t stat1:1; + uint64_t stat0:1; + } s; + struct cvmx_spxx_bist_stat_s cn38xx; + struct cvmx_spxx_bist_stat_s cn38xxp2; + struct cvmx_spxx_bist_stat_s cn58xx; + struct cvmx_spxx_bist_stat_s cn58xxp1; +}; + +union cvmx_spxx_clk_ctl { + uint64_t u64; + struct cvmx_spxx_clk_ctl_s { + uint64_t reserved_17_63:47; + uint64_t seetrn:1; + uint64_t reserved_12_15:4; + uint64_t clkdly:5; + uint64_t runbist:1; + uint64_t statdrv:1; + uint64_t statrcv:1; + uint64_t sndtrn:1; + uint64_t drptrn:1; + uint64_t rcvtrn:1; + uint64_t srxdlck:1; + } s; + struct cvmx_spxx_clk_ctl_s cn38xx; + struct cvmx_spxx_clk_ctl_s cn38xxp2; + struct cvmx_spxx_clk_ctl_s cn58xx; + struct cvmx_spxx_clk_ctl_s cn58xxp1; +}; + +union cvmx_spxx_clk_stat { + uint64_t u64; + struct cvmx_spxx_clk_stat_s { + uint64_t reserved_11_63:53; + uint64_t stxcal:1; + uint64_t reserved_9_9:1; + uint64_t srxtrn:1; + uint64_t s4clk1:1; + uint64_t s4clk0:1; + uint64_t d4clk1:1; + uint64_t d4clk0:1; + uint64_t reserved_0_3:4; + } s; + struct cvmx_spxx_clk_stat_s cn38xx; + struct cvmx_spxx_clk_stat_s cn38xxp2; + struct cvmx_spxx_clk_stat_s cn58xx; + struct cvmx_spxx_clk_stat_s cn58xxp1; +}; + +union cvmx_spxx_dbg_deskew_ctl { + uint64_t u64; + struct cvmx_spxx_dbg_deskew_ctl_s { + uint64_t reserved_30_63:34; + uint64_t fallnop:1; + uint64_t fall8:1; + uint64_t reserved_26_27:2; + uint64_t sstep_go:1; + uint64_t sstep:1; + uint64_t reserved_22_23:2; + uint64_t clrdly:1; + uint64_t dec:1; + uint64_t inc:1; + uint64_t mux:1; + uint64_t offset:5; + uint64_t bitsel:5; + uint64_t offdly:6; + uint64_t dllfrc:1; + uint64_t dlldis:1; + } s; + struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; + struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; + struct cvmx_spxx_dbg_deskew_ctl_s cn58xx; + struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1; +}; + +union cvmx_spxx_dbg_deskew_state { + uint64_t u64; + struct cvmx_spxx_dbg_deskew_state_s { + uint64_t reserved_9_63:55; + uint64_t testres:1; + uint64_t unxterm:1; + uint64_t muxsel:2; + uint64_t offset:5; + } s; + struct cvmx_spxx_dbg_deskew_state_s cn38xx; + struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; + struct cvmx_spxx_dbg_deskew_state_s cn58xx; + struct cvmx_spxx_dbg_deskew_state_s cn58xxp1; +}; + +union cvmx_spxx_drv_ctl { + uint64_t u64; + struct cvmx_spxx_drv_ctl_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_spxx_drv_ctl_cn38xx { + uint64_t reserved_16_63:48; + uint64_t stx4ncmp:4; + uint64_t stx4pcmp:4; + uint64_t srx4cmp:8; + } cn38xx; + struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; + struct cvmx_spxx_drv_ctl_cn58xx { + uint64_t reserved_24_63:40; + uint64_t stx4ncmp:4; + uint64_t stx4pcmp:4; + uint64_t reserved_10_15:6; + uint64_t srx4cmp:10; + } cn58xx; + struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; +}; + +union cvmx_spxx_err_ctl { + uint64_t u64; + struct cvmx_spxx_err_ctl_s { + uint64_t reserved_9_63:55; + uint64_t prtnxa:1; + uint64_t dipcls:1; + uint64_t dippay:1; + uint64_t reserved_4_5:2; + uint64_t errcnt:4; + } s; + struct cvmx_spxx_err_ctl_s cn38xx; + struct cvmx_spxx_err_ctl_s cn38xxp2; + struct cvmx_spxx_err_ctl_s cn58xx; + struct cvmx_spxx_err_ctl_s cn58xxp1; +}; + +union cvmx_spxx_int_dat { + uint64_t u64; + struct cvmx_spxx_int_dat_s { + uint64_t reserved_32_63:32; + uint64_t mul:1; + uint64_t reserved_14_30:17; + uint64_t calbnk:2; + uint64_t rsvop:4; + uint64_t prt:8; + } s; + struct cvmx_spxx_int_dat_s cn38xx; + struct cvmx_spxx_int_dat_s cn38xxp2; + struct cvmx_spxx_int_dat_s cn58xx; + struct cvmx_spxx_int_dat_s cn58xxp1; +}; + +union cvmx_spxx_int_msk { + uint64_t u64; + struct cvmx_spxx_int_msk_s { + uint64_t reserved_12_63:52; + uint64_t calerr:1; + uint64_t syncerr:1; + uint64_t diperr:1; + uint64_t tpaovr:1; + uint64_t rsverr:1; + uint64_t drwnng:1; + uint64_t clserr:1; + uint64_t spiovr:1; + uint64_t reserved_2_3:2; + uint64_t abnorm:1; + uint64_t prtnxa:1; + } s; + struct cvmx_spxx_int_msk_s cn38xx; + struct cvmx_spxx_int_msk_s cn38xxp2; + struct cvmx_spxx_int_msk_s cn58xx; + struct cvmx_spxx_int_msk_s cn58xxp1; +}; + +union cvmx_spxx_int_reg { + uint64_t u64; + struct cvmx_spxx_int_reg_s { + uint64_t reserved_32_63:32; + uint64_t spf:1; + uint64_t reserved_12_30:19; + uint64_t calerr:1; + uint64_t syncerr:1; + uint64_t diperr:1; + uint64_t tpaovr:1; + uint64_t rsverr:1; + uint64_t drwnng:1; + uint64_t clserr:1; + uint64_t spiovr:1; + uint64_t reserved_2_3:2; + uint64_t abnorm:1; + uint64_t prtnxa:1; + } s; + struct cvmx_spxx_int_reg_s cn38xx; + struct cvmx_spxx_int_reg_s cn38xxp2; + struct cvmx_spxx_int_reg_s cn58xx; + struct cvmx_spxx_int_reg_s cn58xxp1; +}; + +union cvmx_spxx_int_sync { + uint64_t u64; + struct cvmx_spxx_int_sync_s { + uint64_t reserved_12_63:52; + uint64_t calerr:1; + uint64_t syncerr:1; + uint64_t diperr:1; + uint64_t tpaovr:1; + uint64_t rsverr:1; + uint64_t drwnng:1; + uint64_t clserr:1; + uint64_t spiovr:1; + uint64_t reserved_2_3:2; + uint64_t abnorm:1; + uint64_t prtnxa:1; + } s; + struct cvmx_spxx_int_sync_s cn38xx; + struct cvmx_spxx_int_sync_s cn38xxp2; + struct cvmx_spxx_int_sync_s cn58xx; + struct cvmx_spxx_int_sync_s cn58xxp1; +}; + +union cvmx_spxx_tpa_acc { + uint64_t u64; + struct cvmx_spxx_tpa_acc_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_spxx_tpa_acc_s cn38xx; + struct cvmx_spxx_tpa_acc_s cn38xxp2; + struct cvmx_spxx_tpa_acc_s cn58xx; + struct cvmx_spxx_tpa_acc_s cn58xxp1; +}; + +union cvmx_spxx_tpa_max { + uint64_t u64; + struct cvmx_spxx_tpa_max_s { + uint64_t reserved_32_63:32; + uint64_t max:32; + } s; + struct cvmx_spxx_tpa_max_s cn38xx; + struct cvmx_spxx_tpa_max_s cn38xxp2; + struct cvmx_spxx_tpa_max_s cn58xx; + struct cvmx_spxx_tpa_max_s cn58xxp1; +}; + +union cvmx_spxx_tpa_sel { + uint64_t u64; + struct cvmx_spxx_tpa_sel_s { + uint64_t reserved_4_63:60; + uint64_t prtsel:4; + } s; + struct cvmx_spxx_tpa_sel_s cn38xx; + struct cvmx_spxx_tpa_sel_s cn38xxp2; + struct cvmx_spxx_tpa_sel_s cn58xx; + struct cvmx_spxx_tpa_sel_s cn58xxp1; +}; + +union cvmx_spxx_trn4_ctl { + uint64_t u64; + struct cvmx_spxx_trn4_ctl_s { + uint64_t reserved_13_63:51; + uint64_t trntest:1; + uint64_t jitter:3; + uint64_t clr_boot:1; + uint64_t set_boot:1; + uint64_t maxdist:5; + uint64_t macro_en:1; + uint64_t mux_en:1; + } s; + struct cvmx_spxx_trn4_ctl_s cn38xx; + struct cvmx_spxx_trn4_ctl_s cn38xxp2; + struct cvmx_spxx_trn4_ctl_s cn58xx; + struct cvmx_spxx_trn4_ctl_s cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h new file mode 100644 index 000000000000..d82b366c279f --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h @@ -0,0 +1,126 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_SRXX_DEFS_H__ +#define __CVMX_SRXX_DEFS_H__ + +#define CVMX_SRXX_COM_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_IGN_RX_FULL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_SPI4_CALX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_SPI4_STAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_SW_TICK_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_SRXX_SW_TICK_DAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_srxx_com_ctl { + uint64_t u64; + struct cvmx_srxx_com_ctl_s { + uint64_t reserved_8_63:56; + uint64_t prts:4; + uint64_t st_en:1; + uint64_t reserved_1_2:2; + uint64_t inf_en:1; + } s; + struct cvmx_srxx_com_ctl_s cn38xx; + struct cvmx_srxx_com_ctl_s cn38xxp2; + struct cvmx_srxx_com_ctl_s cn58xx; + struct cvmx_srxx_com_ctl_s cn58xxp1; +}; + +union cvmx_srxx_ign_rx_full { + uint64_t u64; + struct cvmx_srxx_ign_rx_full_s { + uint64_t reserved_16_63:48; + uint64_t ignore:16; + } s; + struct cvmx_srxx_ign_rx_full_s cn38xx; + struct cvmx_srxx_ign_rx_full_s cn38xxp2; + struct cvmx_srxx_ign_rx_full_s cn58xx; + struct cvmx_srxx_ign_rx_full_s cn58xxp1; +}; + +union cvmx_srxx_spi4_calx { + uint64_t u64; + struct cvmx_srxx_spi4_calx_s { + uint64_t reserved_17_63:47; + uint64_t oddpar:1; + uint64_t prt3:4; + uint64_t prt2:4; + uint64_t prt1:4; + uint64_t prt0:4; + } s; + struct cvmx_srxx_spi4_calx_s cn38xx; + struct cvmx_srxx_spi4_calx_s cn38xxp2; + struct cvmx_srxx_spi4_calx_s cn58xx; + struct cvmx_srxx_spi4_calx_s cn58xxp1; +}; + +union cvmx_srxx_spi4_stat { + uint64_t u64; + struct cvmx_srxx_spi4_stat_s { + uint64_t reserved_16_63:48; + uint64_t m:8; + uint64_t reserved_7_7:1; + uint64_t len:7; + } s; + struct cvmx_srxx_spi4_stat_s cn38xx; + struct cvmx_srxx_spi4_stat_s cn38xxp2; + struct cvmx_srxx_spi4_stat_s cn58xx; + struct cvmx_srxx_spi4_stat_s cn58xxp1; +}; + +union cvmx_srxx_sw_tick_ctl { + uint64_t u64; + struct cvmx_srxx_sw_tick_ctl_s { + uint64_t reserved_14_63:50; + uint64_t eop:1; + uint64_t sop:1; + uint64_t mod:4; + uint64_t opc:4; + uint64_t adr:4; + } s; + struct cvmx_srxx_sw_tick_ctl_s cn38xx; + struct cvmx_srxx_sw_tick_ctl_s cn58xx; + struct cvmx_srxx_sw_tick_ctl_s cn58xxp1; +}; + +union cvmx_srxx_sw_tick_dat { + uint64_t u64; + struct cvmx_srxx_sw_tick_dat_s { + uint64_t dat:64; + } s; + struct cvmx_srxx_sw_tick_dat_s cn38xx; + struct cvmx_srxx_sw_tick_dat_s cn58xx; + struct cvmx_srxx_sw_tick_dat_s cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h new file mode 100644 index 000000000000..4f209b62cae1 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h @@ -0,0 +1,292 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_STXX_DEFS_H__ +#define __CVMX_STXX_DEFS_H__ + +#define CVMX_STXX_ARB_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_BCKPRS_CNT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_COM_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_DIP_CNT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_IGN_CAL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_INT_MSK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_INT_SYNC(block_id) \ + CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_MIN_BST(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_SPI4_CALX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_SPI4_DAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_SPI4_STAT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_STAT_BYTES_HI(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_STAT_BYTES_LO(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_STAT_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_STXX_STAT_PKT_XMT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_stxx_arb_ctl { + uint64_t u64; + struct cvmx_stxx_arb_ctl_s { + uint64_t reserved_6_63:58; + uint64_t mintrn:1; + uint64_t reserved_4_4:1; + uint64_t igntpa:1; + uint64_t reserved_0_2:3; + } s; + struct cvmx_stxx_arb_ctl_s cn38xx; + struct cvmx_stxx_arb_ctl_s cn38xxp2; + struct cvmx_stxx_arb_ctl_s cn58xx; + struct cvmx_stxx_arb_ctl_s cn58xxp1; +}; + +union cvmx_stxx_bckprs_cnt { + uint64_t u64; + struct cvmx_stxx_bckprs_cnt_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_stxx_bckprs_cnt_s cn38xx; + struct cvmx_stxx_bckprs_cnt_s cn38xxp2; + struct cvmx_stxx_bckprs_cnt_s cn58xx; + struct cvmx_stxx_bckprs_cnt_s cn58xxp1; +}; + +union cvmx_stxx_com_ctl { + uint64_t u64; + struct cvmx_stxx_com_ctl_s { + uint64_t reserved_4_63:60; + uint64_t st_en:1; + uint64_t reserved_1_2:2; + uint64_t inf_en:1; + } s; + struct cvmx_stxx_com_ctl_s cn38xx; + struct cvmx_stxx_com_ctl_s cn38xxp2; + struct cvmx_stxx_com_ctl_s cn58xx; + struct cvmx_stxx_com_ctl_s cn58xxp1; +}; + +union cvmx_stxx_dip_cnt { + uint64_t u64; + struct cvmx_stxx_dip_cnt_s { + uint64_t reserved_8_63:56; + uint64_t frmmax:4; + uint64_t dipmax:4; + } s; + struct cvmx_stxx_dip_cnt_s cn38xx; + struct cvmx_stxx_dip_cnt_s cn38xxp2; + struct cvmx_stxx_dip_cnt_s cn58xx; + struct cvmx_stxx_dip_cnt_s cn58xxp1; +}; + +union cvmx_stxx_ign_cal { + uint64_t u64; + struct cvmx_stxx_ign_cal_s { + uint64_t reserved_16_63:48; + uint64_t igntpa:16; + } s; + struct cvmx_stxx_ign_cal_s cn38xx; + struct cvmx_stxx_ign_cal_s cn38xxp2; + struct cvmx_stxx_ign_cal_s cn58xx; + struct cvmx_stxx_ign_cal_s cn58xxp1; +}; + +union cvmx_stxx_int_msk { + uint64_t u64; + struct cvmx_stxx_int_msk_s { + uint64_t reserved_8_63:56; + uint64_t frmerr:1; + uint64_t unxfrm:1; + uint64_t nosync:1; + uint64_t diperr:1; + uint64_t datovr:1; + uint64_t ovrbst:1; + uint64_t calpar1:1; + uint64_t calpar0:1; + } s; + struct cvmx_stxx_int_msk_s cn38xx; + struct cvmx_stxx_int_msk_s cn38xxp2; + struct cvmx_stxx_int_msk_s cn58xx; + struct cvmx_stxx_int_msk_s cn58xxp1; +}; + +union cvmx_stxx_int_reg { + uint64_t u64; + struct cvmx_stxx_int_reg_s { + uint64_t reserved_9_63:55; + uint64_t syncerr:1; + uint64_t frmerr:1; + uint64_t unxfrm:1; + uint64_t nosync:1; + uint64_t diperr:1; + uint64_t datovr:1; + uint64_t ovrbst:1; + uint64_t calpar1:1; + uint64_t calpar0:1; + } s; + struct cvmx_stxx_int_reg_s cn38xx; + struct cvmx_stxx_int_reg_s cn38xxp2; + struct cvmx_stxx_int_reg_s cn58xx; + struct cvmx_stxx_int_reg_s cn58xxp1; +}; + +union cvmx_stxx_int_sync { + uint64_t u64; + struct cvmx_stxx_int_sync_s { + uint64_t reserved_8_63:56; + uint64_t frmerr:1; + uint64_t unxfrm:1; + uint64_t nosync:1; + uint64_t diperr:1; + uint64_t datovr:1; + uint64_t ovrbst:1; + uint64_t calpar1:1; + uint64_t calpar0:1; + } s; + struct cvmx_stxx_int_sync_s cn38xx; + struct cvmx_stxx_int_sync_s cn38xxp2; + struct cvmx_stxx_int_sync_s cn58xx; + struct cvmx_stxx_int_sync_s cn58xxp1; +}; + +union cvmx_stxx_min_bst { + uint64_t u64; + struct cvmx_stxx_min_bst_s { + uint64_t reserved_9_63:55; + uint64_t minb:9; + } s; + struct cvmx_stxx_min_bst_s cn38xx; + struct cvmx_stxx_min_bst_s cn38xxp2; + struct cvmx_stxx_min_bst_s cn58xx; + struct cvmx_stxx_min_bst_s cn58xxp1; +}; + +union cvmx_stxx_spi4_calx { + uint64_t u64; + struct cvmx_stxx_spi4_calx_s { + uint64_t reserved_17_63:47; + uint64_t oddpar:1; + uint64_t prt3:4; + uint64_t prt2:4; + uint64_t prt1:4; + uint64_t prt0:4; + } s; + struct cvmx_stxx_spi4_calx_s cn38xx; + struct cvmx_stxx_spi4_calx_s cn38xxp2; + struct cvmx_stxx_spi4_calx_s cn58xx; + struct cvmx_stxx_spi4_calx_s cn58xxp1; +}; + +union cvmx_stxx_spi4_dat { + uint64_t u64; + struct cvmx_stxx_spi4_dat_s { + uint64_t reserved_32_63:32; + uint64_t alpha:16; + uint64_t max_t:16; + } s; + struct cvmx_stxx_spi4_dat_s cn38xx; + struct cvmx_stxx_spi4_dat_s cn38xxp2; + struct cvmx_stxx_spi4_dat_s cn58xx; + struct cvmx_stxx_spi4_dat_s cn58xxp1; +}; + +union cvmx_stxx_spi4_stat { + uint64_t u64; + struct cvmx_stxx_spi4_stat_s { + uint64_t reserved_16_63:48; + uint64_t m:8; + uint64_t reserved_7_7:1; + uint64_t len:7; + } s; + struct cvmx_stxx_spi4_stat_s cn38xx; + struct cvmx_stxx_spi4_stat_s cn38xxp2; + struct cvmx_stxx_spi4_stat_s cn58xx; + struct cvmx_stxx_spi4_stat_s cn58xxp1; +}; + +union cvmx_stxx_stat_bytes_hi { + uint64_t u64; + struct cvmx_stxx_stat_bytes_hi_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_stxx_stat_bytes_hi_s cn38xx; + struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; + struct cvmx_stxx_stat_bytes_hi_s cn58xx; + struct cvmx_stxx_stat_bytes_hi_s cn58xxp1; +}; + +union cvmx_stxx_stat_bytes_lo { + uint64_t u64; + struct cvmx_stxx_stat_bytes_lo_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_stxx_stat_bytes_lo_s cn38xx; + struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; + struct cvmx_stxx_stat_bytes_lo_s cn58xx; + struct cvmx_stxx_stat_bytes_lo_s cn58xxp1; +}; + +union cvmx_stxx_stat_ctl { + uint64_t u64; + struct cvmx_stxx_stat_ctl_s { + uint64_t reserved_5_63:59; + uint64_t clr:1; + uint64_t bckprs:4; + } s; + struct cvmx_stxx_stat_ctl_s cn38xx; + struct cvmx_stxx_stat_ctl_s cn38xxp2; + struct cvmx_stxx_stat_ctl_s cn58xx; + struct cvmx_stxx_stat_ctl_s cn58xxp1; +}; + +union cvmx_stxx_stat_pkt_xmt { + uint64_t u64; + struct cvmx_stxx_stat_pkt_xmt_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_stxx_stat_pkt_xmt_s cn38xx; + struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; + struct cvmx_stxx_stat_pkt_xmt_s cn58xx; + struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1; +}; + +#endif diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h new file mode 100644 index 000000000000..653610953d28 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-wqe.h @@ -0,0 +1,397 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * This header file defines the work queue entry (wqe) data structure. + * Since this is a commonly used structure that depends on structures + * from several hardware blocks, those definitions have been placed + * in this file to create a single point of definition of the wqe + * format. + * Data structures are still named according to the block that they + * relate to. + * + */ + +#ifndef __CVMX_WQE_H__ +#define __CVMX_WQE_H__ + +#include "cvmx-packet.h" + + +#define OCT_TAG_TYPE_STRING(x) \ + (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \ + (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \ + (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \ + "NULL_NULL"))) + +/** + * HW decode / err_code in work queue entry + */ +typedef union { + uint64_t u64; + + /* Use this struct if the hardware determines that the packet is IP */ + struct { + /* HW sets this to the number of buffers used by this packet */ + uint64_t bufs:8; + /* HW sets to the number of L2 bytes prior to the IP */ + uint64_t ip_offset:8; + /* set to 1 if we found DSA/VLAN in the L2 */ + uint64_t vlan_valid:1; + /* Set to 1 if the DSA/VLAN tag is stacked */ + uint64_t vlan_stacked:1; + uint64_t unassigned:1; + /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */ + uint64_t vlan_cfi:1; + /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */ + uint64_t vlan_id:12; + /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */ + uint64_t pr:4; + uint64_t unassigned2:8; + /* the packet needs to be decompressed */ + uint64_t dec_ipcomp:1; + /* the packet is either TCP or UDP */ + uint64_t tcp_or_udp:1; + /* the packet needs to be decrypted (ESP or AH) */ + uint64_t dec_ipsec:1; + /* the packet is IPv6 */ + uint64_t is_v6:1; + + /* + * (rcv_error, not_IP, IP_exc, is_frag, L4_error, + * software, etc.). + */ + + /* + * reserved for software use, hardware will clear on + * packet creation. + */ + uint64_t software:1; + /* exceptional conditions below */ + /* the receive interface hardware detected an L4 error + * (only applies if !is_frag) (only applies if + * !rcv_error && !not_IP && !IP_exc && !is_frag) + * failure indicated in err_code below, decode: + * + * - 1 = Malformed L4 + * - 2 = L4 Checksum Error: the L4 checksum value is + * - 3 = UDP Length Error: The UDP length field would + * make the UDP data longer than what remains in + * the IP packet (as defined by the IP header + * length field). + * - 4 = Bad L4 Port: either the source or destination + * TCP/UDP port is 0. + * - 8 = TCP FIN Only: the packet is TCP and only the + * FIN flag set. + * - 9 = TCP No Flags: the packet is TCP and no flags + * are set. + * - 10 = TCP FIN RST: the packet is TCP and both FIN + * and RST are set. + * - 11 = TCP SYN URG: the packet is TCP and both SYN + * and URG are set. + * - 12 = TCP SYN RST: the packet is TCP and both SYN + * and RST are set. + * - 13 = TCP SYN FIN: the packet is TCP and both SYN + * and FIN are set. + */ + uint64_t L4_error:1; + /* set if the packet is a fragment */ + uint64_t is_frag:1; + /* the receive interface hardware detected an IP error + * / exception (only applies if !rcv_error && !not_IP) + * failure indicated in err_code below, decode: + * + * - 1 = Not IP: the IP version field is neither 4 nor + * 6. + * - 2 = IPv4 Header Checksum Error: the IPv4 header + * has a checksum violation. + * - 3 = IP Malformed Header: the packet is not long + * enough to contain the IP header. + * - 4 = IP Malformed: the packet is not long enough + * to contain the bytes indicated by the IP + * header. Pad is allowed. + * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 + * Hop Count field are zero. + * - 6 = IP Options + */ + uint64_t IP_exc:1; + /* + * Set if the hardware determined that the packet is a + * broadcast. + */ + uint64_t is_bcast:1; + /* + * St if the hardware determined that the packet is a + * multi-cast. + */ + uint64_t is_mcast:1; + /* + * Set if the packet may not be IP (must be zero in + * this case). + */ + uint64_t not_IP:1; + /* + * The receive interface hardware detected a receive + * error (must be zero in this case). + */ + uint64_t rcv_error:1; + /* lower err_code = first-level descriptor of the + * work */ + /* zero for packet submitted by hardware that isn't on + * the slow path */ + /* type is cvmx_pip_err_t */ + uint64_t err_code:8; + } s; + + /* use this to get at the 16 vlan bits */ + struct { + uint64_t unused1:16; + uint64_t vlan:16; + uint64_t unused2:32; + } svlan; + + /* + * use this struct if the hardware could not determine that + * the packet is ip. + */ + struct { + /* + * HW sets this to the number of buffers used by this + * packet. + */ + uint64_t bufs:8; + uint64_t unused:8; + /* set to 1 if we found DSA/VLAN in the L2 */ + uint64_t vlan_valid:1; + /* Set to 1 if the DSA/VLAN tag is stacked */ + uint64_t vlan_stacked:1; + uint64_t unassigned:1; + /* + * HW sets to the DSA/VLAN CFI flag (valid when + * vlan_valid) + */ + uint64_t vlan_cfi:1; + /* + * HW sets to the DSA/VLAN_ID field (valid when + * vlan_valid). + */ + uint64_t vlan_id:12; + /* + * Ring Identifier (if PCIe). Requires + * PIP_GBL_CTL[RING_EN]=1 + */ + uint64_t pr:4; + uint64_t unassigned2:12; + /* + * reserved for software use, hardware will clear on + * packet creation. + */ + uint64_t software:1; + uint64_t unassigned3:1; + /* + * set if the hardware determined that the packet is + * rarp. + */ + uint64_t is_rarp:1; + /* + * set if the hardware determined that the packet is + * arp + */ + uint64_t is_arp:1; + /* + * set if the hardware determined that the packet is a + * broadcast. + */ + uint64_t is_bcast:1; + /* + * set if the hardware determined that the packet is a + * multi-cast + */ + uint64_t is_mcast:1; + /* + * set if the packet may not be IP (must be one in + * this case) + */ + uint64_t not_IP:1; + /* The receive interface hardware detected a receive + * error. Failure indicated in err_code below, + * decode: + * + * - 1 = partial error: a packet was partially + * received, but internal buffering / bandwidth + * was not adequate to receive the entire + * packet. + * - 2 = jabber error: the RGMII packet was too large + * and is truncated. + * - 3 = overrun error: the RGMII packet is longer + * than allowed and had an FCS error. + * - 4 = oversize error: the RGMII packet is longer + * than allowed. + * - 5 = alignment error: the RGMII packet is not an + * integer number of bytes + * and had an FCS error (100M and 10M only). + * - 6 = fragment error: the RGMII packet is shorter + * than allowed and had an FCS error. + * - 7 = GMX FCS error: the RGMII packet had an FCS + * error. + * - 8 = undersize error: the RGMII packet is shorter + * than allowed. + * - 9 = extend error: the RGMII packet had an extend + * error. + * - 10 = length mismatch error: the RGMII packet had + * a length that did not match the length field + * in the L2 HDR. + * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII + * packet had one or more data reception errors + * (RXERR) or the SPI4 packet had one or more + * DIP4 errors. + * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII + * packet was not large enough to cover the + * skipped bytes or the SPI4 packet was + * terminated with an About EOPS. + * - 13 = RGMII nibble error/SPI4 Port NXA Error: the + * RGMII packet had a studder error (data not + * repeated - 10/100M only) or the SPI4 packet + * was sent to an NXA. + * - 16 = FCS error: a SPI4.2 packet had an FCS error. + * - 17 = Skip error: a packet was not large enough to + * cover the skipped bytes. + * - 18 = L2 header malformed: the packet is not long + * enough to contain the L2. + */ + + uint64_t rcv_error:1; + /* + * lower err_code = first-level descriptor of the + * work + */ + /* + * zero for packet submitted by hardware that isn't on + * the slow path + */ + /* type is cvmx_pip_err_t (union, so can't use directly */ + uint64_t err_code:8; + } snoip; + +} cvmx_pip_wqe_word2; + +/** + * Work queue entry format + * + * must be 8-byte aligned + */ +typedef struct { + + /***************************************************************** + * WORD 0 + * HW WRITE: the following 64 bits are filled by HW when a packet arrives + */ + + /** + * raw chksum result generated by the HW + */ + uint16_t hw_chksum; + /** + * Field unused by hardware - available for software + */ + uint8_t unused; + /** + * Next pointer used by hardware for list maintenance. + * May be written/read by HW before the work queue + * entry is scheduled to a PP + * (Only 36 bits used in Octeon 1) + */ + uint64_t next_ptr:40; + + /***************************************************************** + * WORD 1 + * HW WRITE: the following 64 bits are filled by HW when a packet arrives + */ + + /** + * HW sets to the total number of bytes in the packet + */ + uint64_t len:16; + /** + * HW sets this to input physical port + */ + uint64_t ipprt:6; + + /** + * HW sets this to what it thought the priority of the input packet was + */ + uint64_t qos:3; + + /** + * the group that the work queue entry will be scheduled to + */ + uint64_t grp:4; + /** + * the type of the tag (ORDERED, ATOMIC, NULL) + */ + uint64_t tag_type:3; + /** + * the synchronization/ordering tag + */ + uint64_t tag:32; + + /** + * WORD 2 HW WRITE: the following 64-bits are filled in by + * hardware when a packet arrives This indicates a variety of + * status and error conditions. + */ + cvmx_pip_wqe_word2 word2; + + /** + * Pointer to the first segment of the packet. + */ + union cvmx_buf_ptr packet_ptr; + + /** + * HW WRITE: octeon will fill in a programmable amount from the + * packet, up to (at most, but perhaps less) the amount + * needed to fill the work queue entry to 128 bytes + * + * If the packet is recognized to be IP, the hardware starts + * (except that the IPv4 header is padded for appropriate + * alignment) writing here where the IP header starts. If the + * packet is not recognized to be IP, the hardware starts + * writing the beginning of the packet here. + */ + uint8_t packet_data[96]; + + /** + * If desired, SW can make the work Q entry any length. For the + * purposes of discussion here, Assume 128B always, as this is all that + * the hardware deals with. + * + */ + +} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t; + +#endif /* __CVMX_WQE_H__ */ diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile index fc850bac88c1..9012dee0c348 100644 --- a/drivers/staging/octeon/Makefile +++ b/drivers/staging/octeon/Makefile @@ -20,9 +20,4 @@ octeon-ethernet-y += ethernet-sgmii.o octeon-ethernet-y += ethernet-spi.o octeon-ethernet-y += ethernet-tx.o octeon-ethernet-y += ethernet-xaui.o -octeon-ethernet-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ - cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ - cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ - cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ - cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o diff --git a/drivers/staging/octeon/cvmx-address.h b/drivers/staging/octeon/cvmx-address.h deleted file mode 100644 index 3c74d826e2e6..000000000000 --- a/drivers/staging/octeon/cvmx-address.h +++ /dev/null @@ -1,274 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2009 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * Typedefs and defines for working with Octeon physical addresses. - * - */ -#ifndef __CVMX_ADDRESS_H__ -#define __CVMX_ADDRESS_H__ - -#if 0 -typedef enum { - CVMX_MIPS_SPACE_XKSEG = 3LL, - CVMX_MIPS_SPACE_XKPHYS = 2LL, - CVMX_MIPS_SPACE_XSSEG = 1LL, - CVMX_MIPS_SPACE_XUSEG = 0LL -} cvmx_mips_space_t; -#endif - -typedef enum { - CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, - CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, - CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, - CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL -} cvmx_mips_xkseg_space_t; - -/* decodes <14:13> of a kseg3 window address */ -typedef enum { - CVMX_ADD_WIN_SCR = 0L, - /* see cvmx_add_win_dma_dec_t for further decode */ - CVMX_ADD_WIN_DMA = 1L, - CVMX_ADD_WIN_UNUSED = 2L, - CVMX_ADD_WIN_UNUSED2 = 3L -} cvmx_add_win_dec_t; - -/* decode within DMA space */ -typedef enum { - /* - * Add store data to the write buffer entry, allocating it if - * necessary. - */ - CVMX_ADD_WIN_DMA_ADD = 0L, - /* send out the write buffer entry to DRAM */ - CVMX_ADD_WIN_DMA_SENDMEM = 1L, - /* store data must be normal DRAM memory space address in this case */ - /* send out the write buffer entry as an IOBDMA command */ - CVMX_ADD_WIN_DMA_SENDDMA = 2L, - /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ - /* send out the write buffer entry as an IO write */ - CVMX_ADD_WIN_DMA_SENDIO = 3L, - /* store data must be normal IO space address in this case */ - /* send out a single-tick command on the NCB bus */ - CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, - /* no write buffer data needed/used */ -} cvmx_add_win_dma_dec_t; - -/* - * Physical Address Decode - * - * Octeon-I HW never interprets this X (<39:36> reserved - * for future expansion), software should set to 0. - * - * - 0x0 XXX0 0000 0000 to DRAM Cached - * - 0x0 XXX0 0FFF FFFF - * - * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 - * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) - * - * - 0x0 XXX0 2000 0000 to DRAM Cached - * - 0x0 XXXF FFFF FFFF - * - * - 0x1 00X0 0000 0000 to Boot Bus Uncached - * - 0x1 00XF FFFF FFFF - * - * - 0x1 01X0 0000 0000 to Other NCB Uncached - * - 0x1 FFXF FFFF FFFF devices - * - * Decode of all Octeon addresses - */ -typedef union { - - uint64_t u64; - /* mapped or unmapped virtual address */ - struct { - uint64_t R:2; - uint64_t offset:62; - } sva; - - /* mapped USEG virtual addresses (typically) */ - struct { - uint64_t zeroes:33; - uint64_t offset:31; - } suseg; - - /* mapped or unmapped virtual address */ - struct { - uint64_t ones:33; - uint64_t sp:2; - uint64_t offset:29; - } sxkseg; - - /* - * physical address accessed through xkphys unmapped virtual - * address. - */ - struct { - uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ - uint64_t cca:3; /* ignored by octeon */ - uint64_t mbz:10; - uint64_t pa:49; /* physical address */ - } sxkphys; - - /* physical address */ - struct { - uint64_t mbz:15; - /* if set, the address is uncached and resides on MCB bus */ - uint64_t is_io:1; - /* - * the hardware ignores this field when is_io==0, else - * device ID. - */ - uint64_t did:8; - /* the hardware ignores <39:36> in Octeon I */ - uint64_t unaddr:4; - uint64_t offset:36; - } sphys; - - /* physical mem address */ - struct { - /* techically, <47:40> are dont-cares */ - uint64_t zeroes:24; - /* the hardware ignores <39:36> in Octeon I */ - uint64_t unaddr:4; - uint64_t offset:36; - } smem; - - /* physical IO address */ - struct { - uint64_t mem_region:2; - uint64_t mbz:13; - /* 1 in this case */ - uint64_t is_io:1; - /* - * The hardware ignores this field when is_io==0, else - * device ID. - */ - uint64_t did:8; - /* the hardware ignores <39:36> in Octeon I */ - uint64_t unaddr:4; - uint64_t offset:36; - } sio; - - /* - * Scratchpad virtual address - accessed through a window at - * the end of kseg3 - */ - struct { - uint64_t ones:49; - /* CVMX_ADD_WIN_SCR (0) in this case */ - cvmx_add_win_dec_t csrdec:2; - uint64_t addr:13; - } sscr; - - /* there should only be stores to IOBDMA space, no loads */ - /* - * IOBDMA virtual address - accessed through a window at the - * end of kseg3 - */ - struct { - uint64_t ones:49; - uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */ - uint64_t unused2:3; - uint64_t type:3; - uint64_t addr:7; - } sdma; - - struct { - uint64_t didspace:24; - uint64_t unused:40; - } sfilldidspace; - -} cvmx_addr_t; - -/* These macros for used by 32 bit applications */ - -#define CVMX_MIPS32_SPACE_KSEG0 1l -#define CVMX_ADD_SEG32(segment, add) \ - (((int32_t)segment << 31) | (int32_t)(add)) - -/* - * Currently all IOs are performed using XKPHYS addressing. Linux uses - * the CvmMemCtl register to enable XKPHYS addressing to IO space from - * user mode. Future OSes may need to change the upper bits of IO - * addresses. The following define controls the upper two bits for all - * IO addresses generated by the simple executive library. - */ -#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS - -/* These macros simplify the process of creating common IO addresses */ -#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) -#ifndef CVMX_ADD_IO_SEG -#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) -#endif -#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) -#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) -#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid)) - - /* from include/ncb_rsl_id.v */ -#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ -#define CVMX_OCT_DID_GMX0 1ULL -#define CVMX_OCT_DID_GMX1 2ULL -#define CVMX_OCT_DID_PCI 3ULL -#define CVMX_OCT_DID_KEY 4ULL -#define CVMX_OCT_DID_FPA 5ULL -#define CVMX_OCT_DID_DFA 6ULL -#define CVMX_OCT_DID_ZIP 7ULL -#define CVMX_OCT_DID_RNG 8ULL -#define CVMX_OCT_DID_IPD 9ULL -#define CVMX_OCT_DID_PKT 10ULL -#define CVMX_OCT_DID_TIM 11ULL -#define CVMX_OCT_DID_TAG 12ULL - /* the rest are not on the IO bus */ -#define CVMX_OCT_DID_L2C 16ULL -#define CVMX_OCT_DID_LMC 17ULL -#define CVMX_OCT_DID_SPX0 18ULL -#define CVMX_OCT_DID_SPX1 19ULL -#define CVMX_OCT_DID_PIP 20ULL -#define CVMX_OCT_DID_ASX0 22ULL -#define CVMX_OCT_DID_ASX1 23ULL -#define CVMX_OCT_DID_IOB 30ULL - -#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) -#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) -#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) -#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) -#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) -#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) -#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) -#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) -#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) -#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) -#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) -#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) -#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) -#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) -#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) -#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) -#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) - -#endif /* __CVMX_ADDRESS_H__ */ diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/drivers/staging/octeon/cvmx-asxx-defs.h deleted file mode 100644 index 91415a85e8d2..000000000000 --- a/drivers/staging/octeon/cvmx-asxx-defs.h +++ /dev/null @@ -1,475 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_ASXX_DEFS_H__ -#define __CVMX_ASXX_DEFS_H__ - -#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_INT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_ASXX_PRT_LOOP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_BYPASS(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_COMP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_DATA_DRV(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RLD_SETTING(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_PRT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_POWOK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_RX_WOL_SIG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_COMP_BYP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_ASXX_TX_PRT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull)) - -union cvmx_asxx_gmii_rx_clk_set { - uint64_t u64; - struct cvmx_asxx_gmii_rx_clk_set_s { - uint64_t reserved_5_63:59; - uint64_t setting:5; - } s; - struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; - struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; - struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; -}; - -union cvmx_asxx_gmii_rx_dat_set { - uint64_t u64; - struct cvmx_asxx_gmii_rx_dat_set_s { - uint64_t reserved_5_63:59; - uint64_t setting:5; - } s; - struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; - struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; - struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; -}; - -union cvmx_asxx_int_en { - uint64_t u64; - struct cvmx_asxx_int_en_s { - uint64_t reserved_12_63:52; - uint64_t txpsh:4; - uint64_t txpop:4; - uint64_t ovrflw:4; - } s; - struct cvmx_asxx_int_en_cn30xx { - uint64_t reserved_11_63:53; - uint64_t txpsh:3; - uint64_t reserved_7_7:1; - uint64_t txpop:3; - uint64_t reserved_3_3:1; - uint64_t ovrflw:3; - } cn30xx; - struct cvmx_asxx_int_en_cn30xx cn31xx; - struct cvmx_asxx_int_en_s cn38xx; - struct cvmx_asxx_int_en_s cn38xxp2; - struct cvmx_asxx_int_en_cn30xx cn50xx; - struct cvmx_asxx_int_en_s cn58xx; - struct cvmx_asxx_int_en_s cn58xxp1; -}; - -union cvmx_asxx_int_reg { - uint64_t u64; - struct cvmx_asxx_int_reg_s { - uint64_t reserved_12_63:52; - uint64_t txpsh:4; - uint64_t txpop:4; - uint64_t ovrflw:4; - } s; - struct cvmx_asxx_int_reg_cn30xx { - uint64_t reserved_11_63:53; - uint64_t txpsh:3; - uint64_t reserved_7_7:1; - uint64_t txpop:3; - uint64_t reserved_3_3:1; - uint64_t ovrflw:3; - } cn30xx; - struct cvmx_asxx_int_reg_cn30xx cn31xx; - struct cvmx_asxx_int_reg_s cn38xx; - struct cvmx_asxx_int_reg_s cn38xxp2; - struct cvmx_asxx_int_reg_cn30xx cn50xx; - struct cvmx_asxx_int_reg_s cn58xx; - struct cvmx_asxx_int_reg_s cn58xxp1; -}; - -union cvmx_asxx_mii_rx_dat_set { - uint64_t u64; - struct cvmx_asxx_mii_rx_dat_set_s { - uint64_t reserved_5_63:59; - uint64_t setting:5; - } s; - struct cvmx_asxx_mii_rx_dat_set_s cn30xx; - struct cvmx_asxx_mii_rx_dat_set_s cn50xx; -}; - -union cvmx_asxx_prt_loop { - uint64_t u64; - struct cvmx_asxx_prt_loop_s { - uint64_t reserved_8_63:56; - uint64_t ext_loop:4; - uint64_t int_loop:4; - } s; - struct cvmx_asxx_prt_loop_cn30xx { - uint64_t reserved_7_63:57; - uint64_t ext_loop:3; - uint64_t reserved_3_3:1; - uint64_t int_loop:3; - } cn30xx; - struct cvmx_asxx_prt_loop_cn30xx cn31xx; - struct cvmx_asxx_prt_loop_s cn38xx; - struct cvmx_asxx_prt_loop_s cn38xxp2; - struct cvmx_asxx_prt_loop_cn30xx cn50xx; - struct cvmx_asxx_prt_loop_s cn58xx; - struct cvmx_asxx_prt_loop_s cn58xxp1; -}; - -union cvmx_asxx_rld_bypass { - uint64_t u64; - struct cvmx_asxx_rld_bypass_s { - uint64_t reserved_1_63:63; - uint64_t bypass:1; - } s; - struct cvmx_asxx_rld_bypass_s cn38xx; - struct cvmx_asxx_rld_bypass_s cn38xxp2; - struct cvmx_asxx_rld_bypass_s cn58xx; - struct cvmx_asxx_rld_bypass_s cn58xxp1; -}; - -union cvmx_asxx_rld_bypass_setting { - uint64_t u64; - struct cvmx_asxx_rld_bypass_setting_s { - uint64_t reserved_5_63:59; - uint64_t setting:5; - } s; - struct cvmx_asxx_rld_bypass_setting_s cn38xx; - struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; - struct cvmx_asxx_rld_bypass_setting_s cn58xx; - struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; -}; - -union cvmx_asxx_rld_comp { - uint64_t u64; - struct cvmx_asxx_rld_comp_s { - uint64_t reserved_9_63:55; - uint64_t pctl:5; - uint64_t nctl:4; - } s; - struct cvmx_asxx_rld_comp_cn38xx { - uint64_t reserved_8_63:56; - uint64_t pctl:4; - uint64_t nctl:4; - } cn38xx; - struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; - struct cvmx_asxx_rld_comp_s cn58xx; - struct cvmx_asxx_rld_comp_s cn58xxp1; -}; - -union cvmx_asxx_rld_data_drv { - uint64_t u64; - struct cvmx_asxx_rld_data_drv_s { - uint64_t reserved_8_63:56; - uint64_t pctl:4; - uint64_t nctl:4; - } s; - struct cvmx_asxx_rld_data_drv_s cn38xx; - struct cvmx_asxx_rld_data_drv_s cn38xxp2; - struct cvmx_asxx_rld_data_drv_s cn58xx; - struct cvmx_asxx_rld_data_drv_s cn58xxp1; -}; - -union cvmx_asxx_rld_fcram_mode { - uint64_t u64; - struct cvmx_asxx_rld_fcram_mode_s { - uint64_t reserved_1_63:63; - uint64_t mode:1; - } s; - struct cvmx_asxx_rld_fcram_mode_s cn38xx; - struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; -}; - -union cvmx_asxx_rld_nctl_strong { - uint64_t u64; - struct cvmx_asxx_rld_nctl_strong_s { - uint64_t reserved_5_63:59; - uint64_t nctl:5; - } s; - struct cvmx_asxx_rld_nctl_strong_s cn38xx; - struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; - struct cvmx_asxx_rld_nctl_strong_s cn58xx; - struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; -}; - -union cvmx_asxx_rld_nctl_weak { - uint64_t u64; - struct cvmx_asxx_rld_nctl_weak_s { - uint64_t reserved_5_63:59; - uint64_t nctl:5; - } s; - struct cvmx_asxx_rld_nctl_weak_s cn38xx; - struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; - struct cvmx_asxx_rld_nctl_weak_s cn58xx; - struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; -}; - -union cvmx_asxx_rld_pctl_strong { - uint64_t u64; - struct cvmx_asxx_rld_pctl_strong_s { - uint64_t reserved_5_63:59; - uint64_t pctl:5; - } s; - struct cvmx_asxx_rld_pctl_strong_s cn38xx; - struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; - struct cvmx_asxx_rld_pctl_strong_s cn58xx; - struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; -}; - -union cvmx_asxx_rld_pctl_weak { - uint64_t u64; - struct cvmx_asxx_rld_pctl_weak_s { - uint64_t reserved_5_63:59; - uint64_t pctl:5; - } s; - struct cvmx_asxx_rld_pctl_weak_s cn38xx; - struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; - struct cvmx_asxx_rld_pctl_weak_s cn58xx; - struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; -}; - -union cvmx_asxx_rld_setting { - uint64_t u64; - struct cvmx_asxx_rld_setting_s { - uint64_t reserved_13_63:51; - uint64_t dfaset:5; - uint64_t dfalag:1; - uint64_t dfalead:1; - uint64_t dfalock:1; - uint64_t setting:5; - } s; - struct cvmx_asxx_rld_setting_cn38xx { - uint64_t reserved_5_63:59; - uint64_t setting:5; - } cn38xx; - struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; - struct cvmx_asxx_rld_setting_s cn58xx; - struct cvmx_asxx_rld_setting_s cn58xxp1; -}; - -union cvmx_asxx_rx_clk_setx { - uint64_t u64; - struct cvmx_asxx_rx_clk_setx_s { - uint64_t reserved_5_63:59; - uint64_t setting:5; - } s; - struct cvmx_asxx_rx_clk_setx_s cn30xx; - struct cvmx_asxx_rx_clk_setx_s cn31xx; - struct cvmx_asxx_rx_clk_setx_s cn38xx; - struct cvmx_asxx_rx_clk_setx_s cn38xxp2; - struct cvmx_asxx_rx_clk_setx_s cn50xx; - struct cvmx_asxx_rx_clk_setx_s cn58xx; - struct cvmx_asxx_rx_clk_setx_s cn58xxp1; -}; - -union cvmx_asxx_rx_prt_en { - uint64_t u64; - struct cvmx_asxx_rx_prt_en_s { - uint64_t reserved_4_63:60; - uint64_t prt_en:4; - } s; - struct cvmx_asxx_rx_prt_en_cn30xx { - uint64_t reserved_3_63:61; - uint64_t prt_en:3; - } cn30xx; - struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; - struct cvmx_asxx_rx_prt_en_s cn38xx; - struct cvmx_asxx_rx_prt_en_s cn38xxp2; - struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; - struct cvmx_asxx_rx_prt_en_s cn58xx; - struct cvmx_asxx_rx_prt_en_s cn58xxp1; -}; - -union cvmx_asxx_rx_wol { - uint64_t u64; - struct cvmx_asxx_rx_wol_s { - uint64_t reserved_2_63:62; - uint64_t status:1; - uint64_t enable:1; - } s; - struct cvmx_asxx_rx_wol_s cn38xx; - struct cvmx_asxx_rx_wol_s cn38xxp2; -}; - -union cvmx_asxx_rx_wol_msk { - uint64_t u64; - struct cvmx_asxx_rx_wol_msk_s { - uint64_t msk:64; - } s; - struct cvmx_asxx_rx_wol_msk_s cn38xx; - struct cvmx_asxx_rx_wol_msk_s cn38xxp2; -}; - -union cvmx_asxx_rx_wol_powok { - uint64_t u64; - struct cvmx_asxx_rx_wol_powok_s { - uint64_t reserved_1_63:63; - uint64_t powerok:1; - } s; - struct cvmx_asxx_rx_wol_powok_s cn38xx; - struct cvmx_asxx_rx_wol_powok_s cn38xxp2; -}; - -union cvmx_asxx_rx_wol_sig { - uint64_t u64; - struct cvmx_asxx_rx_wol_sig_s { - uint64_t reserved_32_63:32; - uint64_t sig:32; - } s; - struct cvmx_asxx_rx_wol_sig_s cn38xx; - struct cvmx_asxx_rx_wol_sig_s cn38xxp2; -}; - -union cvmx_asxx_tx_clk_setx { - uint64_t u64; - struct cvmx_asxx_tx_clk_setx_s { - uint64_t reserved_5_63:59; - uint64_t setting:5; - } s; - struct cvmx_asxx_tx_clk_setx_s cn30xx; - struct cvmx_asxx_tx_clk_setx_s cn31xx; - struct cvmx_asxx_tx_clk_setx_s cn38xx; - struct cvmx_asxx_tx_clk_setx_s cn38xxp2; - struct cvmx_asxx_tx_clk_setx_s cn50xx; - struct cvmx_asxx_tx_clk_setx_s cn58xx; - struct cvmx_asxx_tx_clk_setx_s cn58xxp1; -}; - -union cvmx_asxx_tx_comp_byp { - uint64_t u64; - struct cvmx_asxx_tx_comp_byp_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_asxx_tx_comp_byp_cn30xx { - uint64_t reserved_9_63:55; - uint64_t bypass:1; - uint64_t pctl:4; - uint64_t nctl:4; - } cn30xx; - struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; - struct cvmx_asxx_tx_comp_byp_cn38xx { - uint64_t reserved_8_63:56; - uint64_t pctl:4; - uint64_t nctl:4; - } cn38xx; - struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; - struct cvmx_asxx_tx_comp_byp_cn50xx { - uint64_t reserved_17_63:47; - uint64_t bypass:1; - uint64_t reserved_13_15:3; - uint64_t pctl:5; - uint64_t reserved_5_7:3; - uint64_t nctl:5; - } cn50xx; - struct cvmx_asxx_tx_comp_byp_cn58xx { - uint64_t reserved_13_63:51; - uint64_t pctl:5; - uint64_t reserved_5_7:3; - uint64_t nctl:5; - } cn58xx; - struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; -}; - -union cvmx_asxx_tx_hi_waterx { - uint64_t u64; - struct cvmx_asxx_tx_hi_waterx_s { - uint64_t reserved_4_63:60; - uint64_t mark:4; - } s; - struct cvmx_asxx_tx_hi_waterx_cn30xx { - uint64_t reserved_3_63:61; - uint64_t mark:3; - } cn30xx; - struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; - struct cvmx_asxx_tx_hi_waterx_s cn38xx; - struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; - struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; - struct cvmx_asxx_tx_hi_waterx_s cn58xx; - struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; -}; - -union cvmx_asxx_tx_prt_en { - uint64_t u64; - struct cvmx_asxx_tx_prt_en_s { - uint64_t reserved_4_63:60; - uint64_t prt_en:4; - } s; - struct cvmx_asxx_tx_prt_en_cn30xx { - uint64_t reserved_3_63:61; - uint64_t prt_en:3; - } cn30xx; - struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; - struct cvmx_asxx_tx_prt_en_s cn38xx; - struct cvmx_asxx_tx_prt_en_s cn38xxp2; - struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; - struct cvmx_asxx_tx_prt_en_s cn58xx; - struct cvmx_asxx_tx_prt_en_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/drivers/staging/octeon/cvmx-cmd-queue.c deleted file mode 100644 index e9809d375162..000000000000 --- a/drivers/staging/octeon/cvmx-cmd-queue.c +++ /dev/null @@ -1,306 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Support functions for managing command queues used for - * various hardware blocks. - */ - -#include - -#include - -#include "cvmx-config.h" -#include "cvmx-fpa.h" -#include "cvmx-cmd-queue.h" - -#include -#include -#include "cvmx-pko-defs.h" - -/** - * This application uses this pointer to access the global queue - * state. It points to a bootmem named block. - */ -__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; - -/** - * Initialize the Global queue state pointer. - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ -static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void) -{ - char *alloc_name = "cvmx_cmd_queues"; -#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32 - extern uint64_t octeon_reserve32_memory; -#endif - - if (likely(__cvmx_cmd_queue_state_ptr)) - return CVMX_CMD_QUEUE_SUCCESS; - -#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32 - if (octeon_reserve32_memory) - __cvmx_cmd_queue_state_ptr = - cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr), - octeon_reserve32_memory, - octeon_reserve32_memory + - (CONFIG_CAVIUM_RESERVE32 << - 20) - 1, 128, alloc_name); - else -#endif - __cvmx_cmd_queue_state_ptr = - cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr), - 128, - alloc_name); - if (__cvmx_cmd_queue_state_ptr) - memset(__cvmx_cmd_queue_state_ptr, 0, - sizeof(*__cvmx_cmd_queue_state_ptr)); - else { - struct cvmx_bootmem_named_block_desc *block_desc = - cvmx_bootmem_find_named_block(alloc_name); - if (block_desc) - __cvmx_cmd_queue_state_ptr = - cvmx_phys_to_ptr(block_desc->base_addr); - else { - cvmx_dprintf - ("ERROR: cvmx_cmd_queue_initialize: Unable to get named block %s.\n", - alloc_name); - return CVMX_CMD_QUEUE_NO_MEMORY; - } - } - return CVMX_CMD_QUEUE_SUCCESS; -} - -/** - * Initialize a command queue for use. The initial FPA buffer is - * allocated and the hardware unit is configured to point to the - * new command queue. - * - * @queue_id: Hardware command queue to initialize. - * @max_depth: Maximum outstanding commands that can be queued. - * @fpa_pool: FPA pool the command queues should come from. - * @pool_size: Size of each buffer in the FPA pool (bytes) - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ -cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, - int max_depth, int fpa_pool, - int pool_size) -{ - __cvmx_cmd_queue_state_t *qstate; - cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr(); - if (result != CVMX_CMD_QUEUE_SUCCESS) - return result; - - qstate = __cvmx_cmd_queue_get_state(queue_id); - if (qstate == NULL) - return CVMX_CMD_QUEUE_INVALID_PARAM; - - /* - * We artificially limit max_depth to 1<<20 words. It is an - * arbitrary limit. - */ - if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH) { - if ((max_depth < 0) || (max_depth > 1 << 20)) - return CVMX_CMD_QUEUE_INVALID_PARAM; - } else if (max_depth != 0) - return CVMX_CMD_QUEUE_INVALID_PARAM; - - if ((fpa_pool < 0) || (fpa_pool > 7)) - return CVMX_CMD_QUEUE_INVALID_PARAM; - if ((pool_size < 128) || (pool_size > 65536)) - return CVMX_CMD_QUEUE_INVALID_PARAM; - - /* See if someone else has already initialized the queue */ - if (qstate->base_ptr_div128) { - if (max_depth != (int)qstate->max_depth) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "Queue already initialized with different " - "max_depth (%d).\n", - (int)qstate->max_depth); - return CVMX_CMD_QUEUE_INVALID_PARAM; - } - if (fpa_pool != qstate->fpa_pool) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "Queue already initialized with different " - "FPA pool (%u).\n", - qstate->fpa_pool); - return CVMX_CMD_QUEUE_INVALID_PARAM; - } - if ((pool_size >> 3) - 1 != qstate->pool_size_m1) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "Queue already initialized with different " - "FPA pool size (%u).\n", - (qstate->pool_size_m1 + 1) << 3); - return CVMX_CMD_QUEUE_INVALID_PARAM; - } - CVMX_SYNCWS; - return CVMX_CMD_QUEUE_ALREADY_SETUP; - } else { - union cvmx_fpa_ctl_status status; - void *buffer; - - status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); - if (!status.s.enb) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "FPA is not enabled.\n"); - return CVMX_CMD_QUEUE_NO_MEMORY; - } - buffer = cvmx_fpa_alloc(fpa_pool); - if (buffer == NULL) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " - "Unable to allocate initial buffer.\n"); - return CVMX_CMD_QUEUE_NO_MEMORY; - } - - memset(qstate, 0, sizeof(*qstate)); - qstate->max_depth = max_depth; - qstate->fpa_pool = fpa_pool; - qstate->pool_size_m1 = (pool_size >> 3) - 1; - qstate->base_ptr_div128 = cvmx_ptr_to_phys(buffer) / 128; - /* - * We zeroed the now serving field so we need to also - * zero the ticket. - */ - __cvmx_cmd_queue_state_ptr-> - ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0; - CVMX_SYNCWS; - return CVMX_CMD_QUEUE_SUCCESS; - } -} - -/** - * Shutdown a queue a free it's command buffers to the FPA. The - * hardware connected to the queue must be stopped before this - * function is called. - * - * @queue_id: Queue to shutdown - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ -cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id) -{ - __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); - if (qptr == NULL) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to " - "get queue information.\n"); - return CVMX_CMD_QUEUE_INVALID_PARAM; - } - - if (cvmx_cmd_queue_length(queue_id) > 0) { - cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still " - "has data in it.\n"); - return CVMX_CMD_QUEUE_FULL; - } - - __cvmx_cmd_queue_lock(queue_id, qptr); - if (qptr->base_ptr_div128) { - cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) qptr->base_ptr_div128 << 7), - qptr->fpa_pool, 0); - qptr->base_ptr_div128 = 0; - } - __cvmx_cmd_queue_unlock(qptr); - - return CVMX_CMD_QUEUE_SUCCESS; -} - -/** - * Return the number of command words pending in the queue. This - * function may be relatively slow for some hardware units. - * - * @queue_id: Hardware command queue to query - * - * Returns Number of outstanding commands - */ -int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) -{ - if (CVMX_ENABLE_PARAMETER_CHECKING) { - if (__cvmx_cmd_queue_get_state(queue_id) == NULL) - return CVMX_CMD_QUEUE_INVALID_PARAM; - } - - /* - * The cast is here so gcc with check that all values in the - * cvmx_cmd_queue_id_t enumeration are here. - */ - switch ((cvmx_cmd_queue_id_t) (queue_id & 0xff0000)) { - case CVMX_CMD_QUEUE_PKO_BASE: - /* - * FIXME: Need atomic lock on - * CVMX_PKO_REG_READ_IDX. Right now we are normally - * called with the queue lock, so that is a SLIGHT - * amount of protection. - */ - cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff); - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { - union cvmx_pko_mem_debug9 debug9; - debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); - return debug9.cn38xx.doorbell; - } else { - union cvmx_pko_mem_debug8 debug8; - debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); - return debug8.cn58xx.doorbell; - } - case CVMX_CMD_QUEUE_ZIP: - case CVMX_CMD_QUEUE_DFA: - case CVMX_CMD_QUEUE_RAID: - /* FIXME: Implement other lengths */ - return 0; - case CVMX_CMD_QUEUE_DMA_BASE: - { - union cvmx_npei_dmax_counts dmax_counts; - dmax_counts.u64 = - cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS - (queue_id & 0x7)); - return dmax_counts.s.dbell; - } - case CVMX_CMD_QUEUE_END: - return CVMX_CMD_QUEUE_INVALID_PARAM; - } - return CVMX_CMD_QUEUE_INVALID_PARAM; -} - -/** - * Return the command buffer to be written to. The purpose of this - * function is to allow CVMX routine access t othe low level buffer - * for initial hardware setup. User applications should not call this - * function directly. - * - * @queue_id: Command queue to query - * - * Returns Command buffer or NULL on failure - */ -void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id) -{ - __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); - if (qptr && qptr->base_ptr_div128) - return cvmx_phys_to_ptr((uint64_t) qptr->base_ptr_div128 << 7); - else - return NULL; -} diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/drivers/staging/octeon/cvmx-cmd-queue.h deleted file mode 100644 index 614653b686a0..000000000000 --- a/drivers/staging/octeon/cvmx-cmd-queue.h +++ /dev/null @@ -1,617 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Support functions for managing command queues used for - * various hardware blocks. - * - * The common command queue infrastructure abstracts out the - * software necessary for adding to Octeon's chained queue - * structures. These structures are used for commands to the - * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each - * hardware unit takes commands and CSRs of different types, - * they all use basic linked command buffers to store the - * pending request. In general, users of the CVMX API don't - * call cvmx-cmd-queue functions directly. Instead the hardware - * unit specific wrapper should be used. The wrappers perform - * unit specific validation and CSR writes to submit the - * commands. - * - * Even though most software will never directly interact with - * cvmx-cmd-queue, knowledge of its internal working can help - * in diagnosing performance problems and help with debugging. - * - * Command queue pointers are stored in a global named block - * called "cvmx_cmd_queues". Except for the PKO queues, each - * hardware queue is stored in its own cache line to reduce SMP - * contention on spin locks. The PKO queues are stored such that - * every 16th queue is next to each other in memory. This scheme - * allows for queues being in separate cache lines when there - * are low number of queues per port. With 16 queues per port, - * the first queue for each port is in the same cache area. The - * second queues for each port are in another area, etc. This - * allows software to implement very efficient lockless PKO with - * 16 queues per port using a minimum of cache lines per core. - * All queues for a given core will be isolated in the same - * cache area. - * - * In addition to the memory pointer layout, cvmx-cmd-queue - * provides an optimized fair ll/sc locking mechanism for the - * queues. The lock uses a "ticket / now serving" model to - * maintain fair order on contended locks. In addition, it uses - * predicted locking time to limit cache contention. When a core - * know it must wait in line for a lock, it spins on the - * internal cycle counter to completely eliminate any causes of - * bus traffic. - * - */ - -#ifndef __CVMX_CMD_QUEUE_H__ -#define __CVMX_CMD_QUEUE_H__ - -#include - -#include "cvmx-fpa.h" -/** - * By default we disable the max depth support. Most programs - * don't use it and it slows down the command queue processing - * significantly. - */ -#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH -#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0 -#endif - -/** - * Enumeration representing all hardware blocks that use command - * queues. Each hardware block has up to 65536 sub identifiers for - * multiple command queues. Not all chips support all hardware - * units. - */ -typedef enum { - CVMX_CMD_QUEUE_PKO_BASE = 0x00000, - -#define CVMX_CMD_QUEUE_PKO(queue) \ - ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue)))) - - CVMX_CMD_QUEUE_ZIP = 0x10000, - CVMX_CMD_QUEUE_DFA = 0x20000, - CVMX_CMD_QUEUE_RAID = 0x30000, - CVMX_CMD_QUEUE_DMA_BASE = 0x40000, - -#define CVMX_CMD_QUEUE_DMA(queue) \ - ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue)))) - - CVMX_CMD_QUEUE_END = 0x50000, -} cvmx_cmd_queue_id_t; - -/** - * Command write operations can fail if the command queue needs - * a new buffer and the associated FPA pool is empty. It can also - * fail if the number of queued command words reaches the maximum - * set at initialization. - */ -typedef enum { - CVMX_CMD_QUEUE_SUCCESS = 0, - CVMX_CMD_QUEUE_NO_MEMORY = -1, - CVMX_CMD_QUEUE_FULL = -2, - CVMX_CMD_QUEUE_INVALID_PARAM = -3, - CVMX_CMD_QUEUE_ALREADY_SETUP = -4, -} cvmx_cmd_queue_result_t; - -typedef struct { - /* You have lock when this is your ticket */ - uint8_t now_serving; - uint64_t unused1:24; - /* Maximum outstanding command words */ - uint32_t max_depth; - /* FPA pool buffers come from */ - uint64_t fpa_pool:3; - /* Top of command buffer pointer shifted 7 */ - uint64_t base_ptr_div128:29; - uint64_t unused2:6; - /* FPA buffer size in 64bit words minus 1 */ - uint64_t pool_size_m1:13; - /* Number of commands already used in buffer */ - uint64_t index:13; -} __cvmx_cmd_queue_state_t; - -/** - * This structure contains the global state of all command queues. - * It is stored in a bootmem named block and shared by all - * applications running on Octeon. Tickets are stored in a differnet - * cahce line that queue information to reduce the contention on the - * ll/sc used to get a ticket. If this is not the case, the update - * of queue state causes the ll/sc to fail quite often. - */ -typedef struct { - uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256]; - __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256]; -} __cvmx_cmd_queue_all_state_t; - -/** - * Initialize a command queue for use. The initial FPA buffer is - * allocated and the hardware unit is configured to point to the - * new command queue. - * - * @queue_id: Hardware command queue to initialize. - * @max_depth: Maximum outstanding commands that can be queued. - * @fpa_pool: FPA pool the command queues should come from. - * @pool_size: Size of each buffer in the FPA pool (bytes) - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ -cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, - int max_depth, int fpa_pool, - int pool_size); - -/** - * Shutdown a queue a free it's command buffers to the FPA. The - * hardware connected to the queue must be stopped before this - * function is called. - * - * @queue_id: Queue to shutdown - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ -cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id); - -/** - * Return the number of command words pending in the queue. This - * function may be relatively slow for some hardware units. - * - * @queue_id: Hardware command queue to query - * - * Returns Number of outstanding commands - */ -int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id); - -/** - * Return the command buffer to be written to. The purpose of this - * function is to allow CVMX routine access t othe low level buffer - * for initial hardware setup. User applications should not call this - * function directly. - * - * @queue_id: Command queue to query - * - * Returns Command buffer or NULL on failure - */ -void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id); - -/** - * Get the index into the state arrays for the supplied queue id. - * - * @queue_id: Queue ID to get an index for - * - * Returns Index into the state arrays - */ -static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id) -{ - /* - * Warning: This code currently only works with devices that - * have 256 queues or less. Devices with more than 16 queues - * are laid out in memory to allow cores quick access to - * every 16th queue. This reduces cache thrashing when you are - * running 16 queues per port to support lockless operation. - */ - int unit = queue_id >> 16; - int q = (queue_id >> 4) & 0xf; - int core = queue_id & 0xf; - return unit * 256 + core * 16 + q; -} - -/** - * Lock the supplied queue so nobody else is updating it at the same - * time as us. - * - * @queue_id: Queue ID to lock - * @qptr: Pointer to the queue's global state - */ -static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, - __cvmx_cmd_queue_state_t *qptr) -{ - extern __cvmx_cmd_queue_all_state_t - *__cvmx_cmd_queue_state_ptr; - int tmp; - int my_ticket; - prefetch(qptr); - asm volatile ( - ".set push\n" - ".set noreorder\n" - "1:\n" - /* Atomic add one to ticket_ptr */ - "ll %[my_ticket], %[ticket_ptr]\n" - /* and store the original value */ - "li %[ticket], 1\n" - /* in my_ticket */ - "baddu %[ticket], %[my_ticket]\n" - "sc %[ticket], %[ticket_ptr]\n" - "beqz %[ticket], 1b\n" - " nop\n" - /* Load the current now_serving ticket */ - "lbu %[ticket], %[now_serving]\n" - "2:\n" - /* Jump out if now_serving == my_ticket */ - "beq %[ticket], %[my_ticket], 4f\n" - /* Find out how many tickets are in front of me */ - " subu %[ticket], %[my_ticket], %[ticket]\n" - /* Use tickets in front of me minus one to delay */ - "subu %[ticket], 1\n" - /* Delay will be ((tickets in front)-1)*32 loops */ - "cins %[ticket], %[ticket], 5, 7\n" - "3:\n" - /* Loop here until our ticket might be up */ - "bnez %[ticket], 3b\n" - " subu %[ticket], 1\n" - /* Jump back up to check out ticket again */ - "b 2b\n" - /* Load the current now_serving ticket */ - " lbu %[ticket], %[now_serving]\n" - "4:\n" - ".set pop\n" : - [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), - [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp), - [my_ticket] "=r"(my_ticket) - ); -} - -/** - * Unlock the queue, flushing all writes. - * - * @qptr: Queue to unlock - */ -static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr) -{ - qptr->now_serving++; - CVMX_SYNCWS; -} - -/** - * Get the queue state structure for the given queue id - * - * @queue_id: Queue id to get - * - * Returns Queue structure or NULL on failure - */ -static inline __cvmx_cmd_queue_state_t - *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id) -{ - extern __cvmx_cmd_queue_all_state_t - *__cvmx_cmd_queue_state_ptr; - return &__cvmx_cmd_queue_state_ptr-> - state[__cvmx_cmd_queue_get_index(queue_id)]; -} - -/** - * Write an arbitrary number of command words to a command queue. - * This is a generic function; the fixed number of command word - * functions yield higher performance. - * - * @queue_id: Hardware command queue to write to - * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. - * @cmd_count: Number of command words to write - * @cmds: Array of commands to write - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ -static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t - queue_id, - int use_locking, - int cmd_count, - uint64_t *cmds) -{ - __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); - - /* Make sure nobody else is updating the same queue */ - if (likely(use_locking)) - __cvmx_cmd_queue_lock(queue_id, qptr); - - /* - * If a max queue length was specified then make sure we don't - * exceed it. If any part of the command would be below the - * limit we allow it. - */ - if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { - if (unlikely - (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_FULL; - } - } - - /* - * Normally there is plenty of room in the current buffer for - * the command. - */ - if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) { - uint64_t *ptr = - (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> - base_ptr_div128 << 7); - ptr += qptr->index; - qptr->index += cmd_count; - while (cmd_count--) - *ptr++ = *cmds++; - } else { - uint64_t *ptr; - int count; - /* - * We need a new command buffer. Fail if there isn't - * one available. - */ - uint64_t *new_buffer = - (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); - if (unlikely(new_buffer == NULL)) { - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_NO_MEMORY; - } - ptr = - (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> - base_ptr_div128 << 7); - /* - * Figure out how many command words will fit in this - * buffer. One location will be needed for the next - * buffer pointer. - */ - count = qptr->pool_size_m1 - qptr->index; - ptr += qptr->index; - cmd_count -= count; - while (count--) - *ptr++ = *cmds++; - *ptr = cvmx_ptr_to_phys(new_buffer); - /* - * The current buffer is full and has a link to the - * next buffer. Time to write the rest of the commands - * into the new buffer. - */ - qptr->base_ptr_div128 = *ptr >> 7; - qptr->index = cmd_count; - ptr = new_buffer; - while (cmd_count--) - *ptr++ = *cmds++; - } - - /* All updates are complete. Release the lock and return */ - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_SUCCESS; -} - -/** - * Simple function to write two command words to a command - * queue. - * - * @queue_id: Hardware command queue to write to - * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. - * @cmd1: Command - * @cmd2: Command - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ -static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t - queue_id, - int use_locking, - uint64_t cmd1, - uint64_t cmd2) -{ - __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); - - /* Make sure nobody else is updating the same queue */ - if (likely(use_locking)) - __cvmx_cmd_queue_lock(queue_id, qptr); - - /* - * If a max queue length was specified then make sure we don't - * exceed it. If any part of the command would be below the - * limit we allow it. - */ - if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { - if (unlikely - (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_FULL; - } - } - - /* - * Normally there is plenty of room in the current buffer for - * the command. - */ - if (likely(qptr->index + 2 < qptr->pool_size_m1)) { - uint64_t *ptr = - (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> - base_ptr_div128 << 7); - ptr += qptr->index; - qptr->index += 2; - ptr[0] = cmd1; - ptr[1] = cmd2; - } else { - uint64_t *ptr; - /* - * Figure out how many command words will fit in this - * buffer. One location will be needed for the next - * buffer pointer. - */ - int count = qptr->pool_size_m1 - qptr->index; - /* - * We need a new command buffer. Fail if there isn't - * one available. - */ - uint64_t *new_buffer = - (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); - if (unlikely(new_buffer == NULL)) { - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_NO_MEMORY; - } - count--; - ptr = - (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> - base_ptr_div128 << 7); - ptr += qptr->index; - *ptr++ = cmd1; - if (likely(count)) - *ptr++ = cmd2; - *ptr = cvmx_ptr_to_phys(new_buffer); - /* - * The current buffer is full and has a link to the - * next buffer. Time to write the rest of the commands - * into the new buffer. - */ - qptr->base_ptr_div128 = *ptr >> 7; - qptr->index = 0; - if (unlikely(count == 0)) { - qptr->index = 1; - new_buffer[0] = cmd2; - } - } - - /* All updates are complete. Release the lock and return */ - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_SUCCESS; -} - -/** - * Simple function to write three command words to a command - * queue. - * - * @queue_id: Hardware command queue to write to - * @use_locking: - * Use internal locking to ensure exclusive access for queue - * updates. If you don't use this locking you must ensure - * exclusivity some other way. Locking is strongly recommended. - * @cmd1: Command - * @cmd2: Command - * @cmd3: Command - * - * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code - */ -static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t - queue_id, - int use_locking, - uint64_t cmd1, - uint64_t cmd2, - uint64_t cmd3) -{ - __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); - - /* Make sure nobody else is updating the same queue */ - if (likely(use_locking)) - __cvmx_cmd_queue_lock(queue_id, qptr); - - /* - * If a max queue length was specified then make sure we don't - * exceed it. If any part of the command would be below the - * limit we allow it. - */ - if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { - if (unlikely - (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_FULL; - } - } - - /* - * Normally there is plenty of room in the current buffer for - * the command. - */ - if (likely(qptr->index + 3 < qptr->pool_size_m1)) { - uint64_t *ptr = - (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> - base_ptr_div128 << 7); - ptr += qptr->index; - qptr->index += 3; - ptr[0] = cmd1; - ptr[1] = cmd2; - ptr[2] = cmd3; - } else { - uint64_t *ptr; - /* - * Figure out how many command words will fit in this - * buffer. One location will be needed for the next - * buffer pointer - */ - int count = qptr->pool_size_m1 - qptr->index; - /* - * We need a new command buffer. Fail if there isn't - * one available - */ - uint64_t *new_buffer = - (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); - if (unlikely(new_buffer == NULL)) { - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_NO_MEMORY; - } - count--; - ptr = - (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> - base_ptr_div128 << 7); - ptr += qptr->index; - *ptr++ = cmd1; - if (count) { - *ptr++ = cmd2; - if (count > 1) - *ptr++ = cmd3; - } - *ptr = cvmx_ptr_to_phys(new_buffer); - /* - * The current buffer is full and has a link to the - * next buffer. Time to write the rest of the commands - * into the new buffer. - */ - qptr->base_ptr_div128 = *ptr >> 7; - qptr->index = 0; - ptr = new_buffer; - if (count == 0) { - *ptr++ = cmd2; - qptr->index++; - } - if (count < 2) { - *ptr++ = cmd3; - qptr->index++; - } - } - - /* All updates are complete. Release the lock and return */ - if (likely(use_locking)) - __cvmx_cmd_queue_unlock(qptr); - return CVMX_CMD_QUEUE_SUCCESS; -} - -#endif /* __CVMX_CMD_QUEUE_H__ */ diff --git a/drivers/staging/octeon/cvmx-config.h b/drivers/staging/octeon/cvmx-config.h deleted file mode 100644 index 078a520481cf..000000000000 --- a/drivers/staging/octeon/cvmx-config.h +++ /dev/null @@ -1,169 +0,0 @@ -#ifndef __CVMX_CONFIG_H__ -#define __CVMX_CONFIG_H__ - -/************************* Config Specific Defines ************************/ -#define CVMX_LLM_NUM_PORTS 1 -#define CVMX_NULL_POINTER_PROTECT 1 -#define CVMX_ENABLE_DEBUG_PRINTS 1 -/* PKO queues per port for interface 0 (ports 0-15) */ -#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 -/* PKO queues per port for interface 1 (ports 16-31) */ -#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 -/* Limit on the number of PKO ports enabled for interface 0 */ -#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 -/* Limit on the number of PKO ports enabled for interface 1 */ -#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 -/* PKO queues per port for PCI (ports 32-35) */ -#define CVMX_PKO_QUEUES_PER_PORT_PCI 1 -/* PKO queues per port for Loop devices (ports 36-39) */ -#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 - -/************************* FPA allocation *********************************/ -/* Pool sizes in bytes, must be multiple of a cache line */ -#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) -#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) -#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) -#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE) -#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) -#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) -#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE) -#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE) - -/* Pools in use */ -/* Packet buffers */ -#define CVMX_FPA_PACKET_POOL (0) -#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE -/* Work queue entrys */ -#define CVMX_FPA_WQE_POOL (1) -#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE -/* PKO queue command buffers */ -#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) -#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE - -/************************* FAU allocation ********************************/ -/* The fetch and add registers are allocated here. They are arranged - * in order of descending size so that all alignment constraints are - * automatically met. The enums are linked so that the following enum - * continues allocating where the previous one left off, so the - * numbering within each enum always starts with zero. The macros - * take care of the address increment size, so the values entered - * always increase by 1. FAU registers are accessed with byte - * addresses. - */ - -#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START) -typedef enum { - CVMX_FAU_REG_64_START = 0, - CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0), -} cvmx_fau_reg_64_t; - -#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START) -typedef enum { - CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END, - CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0), -} cvmx_fau_reg_32_t; - -#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START) -typedef enum { - CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END, - CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0), -} cvmx_fau_reg_16_t; - -#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START) -typedef enum { - CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END, - CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0), -} cvmx_fau_reg_8_t; - -/* - * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first - * available FAU address that is not allocated in cvmx-config.h. This - * is 64 bit aligned. - */ -#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL)) -#define CVMX_FAU_REG_END (2048) - -/********************** scratch memory allocation *************************/ -/* Scratchpad memory allocation. Note that these are byte memory - * addresses. Some uses of scratchpad (IOBDMA for example) require - * the use of 8-byte aligned addresses, so proper alignment needs to - * be taken into account. - */ -/* Generic scratch iobdma area */ -#define CVMX_SCR_SCRATCH (0) -/* First location available after cvmx-config.h allocated region. */ -#define CVMX_SCR_REG_AVAIL_BASE (8) - -/* - * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve - * before the beginning of the packet. If necessary, override the - * default here. See the IPD section of the hardware manual for MBUFF - * SKIP details. - */ -#define CVMX_HELPER_FIRST_MBUFF_SKIP 184 - -/* - * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve - * in each chained packet element. If necessary, override the default - * here. - */ -#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0 - -/* - * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is - * enabled for all input ports. This controls if IPD sends - * backpressure to all ports if Octeon's FPA pools don't have enough - * packet or work queue entries. Even when this is off, it is still - * possible to get backpressure from individual hardware ports. When - * configuring backpressure, also check - * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override - * the default here. - */ -#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1 - -/* - * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper - * function. Once it is enabled the hardware starts accepting - * packets. You might want to skip the IPD enable if configuration - * changes are need from the default helper setup. If necessary, - * override the default here. - */ -#define CVMX_HELPER_ENABLE_IPD 0 - -/* - * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns - * to incoming packets. - */ -#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED - -#define CVMX_ENABLE_PARAMETER_CHECKING 0 - -/* - * The following select which fields are used by the PIP to generate - * the tag on INPUT - * 0: don't include - * 1: include - */ -#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 -#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0 -#define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1 - -/* Select skip mode for input ports */ -#define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2 - -/* - * Force backpressure to be disabled. This overrides all other - * backpressure configuration. - */ -#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0 - -#endif /* __CVMX_CONFIG_H__ */ - diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/drivers/staging/octeon/cvmx-dbg-defs.h deleted file mode 100644 index abbf42d05e5a..000000000000 --- a/drivers/staging/octeon/cvmx-dbg-defs.h +++ /dev/null @@ -1,72 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_DBG_DEFS_H__ -#define __CVMX_DBG_DEFS_H__ - -#define CVMX_DBG_DATA \ - CVMX_ADD_IO_SEG(0x00011F00000001E8ull) - -union cvmx_dbg_data { - uint64_t u64; - struct cvmx_dbg_data_s { - uint64_t reserved_23_63:41; - uint64_t c_mul:5; - uint64_t dsel_ext:1; - uint64_t data:17; - } s; - struct cvmx_dbg_data_cn30xx { - uint64_t reserved_31_63:33; - uint64_t pll_mul:3; - uint64_t reserved_23_27:5; - uint64_t c_mul:5; - uint64_t dsel_ext:1; - uint64_t data:17; - } cn30xx; - struct cvmx_dbg_data_cn30xx cn31xx; - struct cvmx_dbg_data_cn38xx { - uint64_t reserved_29_63:35; - uint64_t d_mul:4; - uint64_t dclk_mul2:1; - uint64_t cclk_div2:1; - uint64_t c_mul:5; - uint64_t dsel_ext:1; - uint64_t data:17; - } cn38xx; - struct cvmx_dbg_data_cn38xx cn38xxp2; - struct cvmx_dbg_data_cn30xx cn50xx; - struct cvmx_dbg_data_cn58xx { - uint64_t reserved_29_63:35; - uint64_t rem:6; - uint64_t c_mul:5; - uint64_t dsel_ext:1; - uint64_t data:17; - } cn58xx; - struct cvmx_dbg_data_cn58xx cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-fau.h b/drivers/staging/octeon/cvmx-fau.h deleted file mode 100644 index a6939fc8ba18..000000000000 --- a/drivers/staging/octeon/cvmx-fau.h +++ /dev/null @@ -1,597 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Interface to the hardware Fetch and Add Unit. - */ - -#ifndef __CVMX_FAU_H__ -#define __CVMX_FAU_H__ - -/* - * Octeon Fetch and Add Unit (FAU) - */ - -#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) -#define CVMX_FAU_BITS_SCRADDR 63, 56 -#define CVMX_FAU_BITS_LEN 55, 48 -#define CVMX_FAU_BITS_INEVAL 35, 14 -#define CVMX_FAU_BITS_TAGWAIT 13, 13 -#define CVMX_FAU_BITS_NOADD 13, 13 -#define CVMX_FAU_BITS_SIZE 12, 11 -#define CVMX_FAU_BITS_REGISTER 10, 0 - -typedef enum { - CVMX_FAU_OP_SIZE_8 = 0, - CVMX_FAU_OP_SIZE_16 = 1, - CVMX_FAU_OP_SIZE_32 = 2, - CVMX_FAU_OP_SIZE_64 = 3 -} cvmx_fau_op_size_t; - -/** - * Tagwait return definition. If a timeout occurs, the error - * bit will be set. Otherwise the value of the register before - * the update will be returned. - */ -typedef struct { - uint64_t error:1; - int64_t value:63; -} cvmx_fau_tagwait64_t; - -/** - * Tagwait return definition. If a timeout occurs, the error - * bit will be set. Otherwise the value of the register before - * the update will be returned. - */ -typedef struct { - uint64_t error:1; - int32_t value:31; -} cvmx_fau_tagwait32_t; - -/** - * Tagwait return definition. If a timeout occurs, the error - * bit will be set. Otherwise the value of the register before - * the update will be returned. - */ -typedef struct { - uint64_t error:1; - int16_t value:15; -} cvmx_fau_tagwait16_t; - -/** - * Tagwait return definition. If a timeout occurs, the error - * bit will be set. Otherwise the value of the register before - * the update will be returned. - */ -typedef struct { - uint64_t error:1; - int8_t value:7; -} cvmx_fau_tagwait8_t; - -/** - * Asynchronous tagwait return definition. If a timeout occurs, - * the error bit will be set. Otherwise the value of the - * register before the update will be returned. - */ -typedef union { - uint64_t u64; - struct { - uint64_t invalid:1; - uint64_t data:63; /* unpredictable if invalid is set */ - } s; -} cvmx_fau_async_tagwait_result_t; - -/** - * Builds a store I/O address for writing to the FAU - * - * @noadd: 0 = Store value is atomically added to the current value - * 1 = Store value is atomically written over the current value - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. - * Returns Address to store for atomic update - */ -static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) -{ - return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | - cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) | - cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); -} - -/** - * Builds a I/O address for accessing the FAU - * - * @tagwait: Should the atomic add wait for the current tag switch - * operation to complete. - * - 0 = Don't wait - * - 1 = Wait for tag switch to complete - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. - * @value: Signed value to add. - * Note: When performing 32 and 64 bit access, only the low - * 22 bits are available. - * Returns Address to read from for atomic update - */ -static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, - int64_t value) -{ - return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | - cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | - cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | - cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); -} - -/** - * Perform an atomic 64 bit add - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. - * @value: Signed value to add. - * Note: Only the low 22 bits are available. - * Returns Value of the register before the update - */ -static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, - int64_t value) -{ - return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); -} - -/** - * Perform an atomic 32 bit add - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. - * @value: Signed value to add. - * Note: Only the low 22 bits are available. - * Returns Value of the register before the update - */ -static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, - int32_t value) -{ - return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); -} - -/** - * Perform an atomic 16 bit add - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * @value: Signed value to add. - * Returns Value of the register before the update - */ -static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, - int16_t value) -{ - return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); -} - -/** - * Perform an atomic 8 bit add - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * @value: Signed value to add. - * Returns Value of the register before the update - */ -static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) -{ - return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); -} - -/** - * Perform an atomic 64 bit add after the current tag switch - * completes - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. - * @value: Signed value to add. - * Note: Only the low 22 bits are available. - * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned - */ -static inline cvmx_fau_tagwait64_t -cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) -{ - union { - uint64_t i64; - cvmx_fau_tagwait64_t t; - } result; - result.i64 = - cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); - return result.t; -} - -/** - * Perform an atomic 32 bit add after the current tag switch - * completes - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. - * @value: Signed value to add. - * Note: Only the low 22 bits are available. - * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned - */ -static inline cvmx_fau_tagwait32_t -cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) -{ - union { - uint64_t i32; - cvmx_fau_tagwait32_t t; - } result; - result.i32 = - cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); - return result.t; -} - -/** - * Perform an atomic 16 bit add after the current tag switch - * completes - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * @value: Signed value to add. - * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned - */ -static inline cvmx_fau_tagwait16_t -cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) -{ - union { - uint64_t i16; - cvmx_fau_tagwait16_t t; - } result; - result.i16 = - cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); - return result.t; -} - -/** - * Perform an atomic 8 bit add after the current tag switch - * completes - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * @value: Signed value to add. - * Returns If a timeout occurs, the error bit will be set. Otherwise - * the value of the register before the update will be - * returned - */ -static inline cvmx_fau_tagwait8_t -cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) -{ - union { - uint64_t i8; - cvmx_fau_tagwait8_t t; - } result; - result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); - return result.t; -} - -/** - * Builds I/O data for async operations - * - * @scraddr: Scratch pad byte address to write to. Must be 8 byte aligned - * @value: Signed value to add. - * Note: When performing 32 and 64 bit access, only the low - * 22 bits are available. - * @tagwait: Should the atomic add wait for the current tag switch - * operation to complete. - * - 0 = Don't wait - * - 1 = Wait for tag switch to complete - * @size: The size of the operation: - * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits - * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits - * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits - * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * - Step by 4 for 32 bit access. - * - Step by 8 for 64 bit access. - * Returns Data to write using cvmx_send_single - */ -static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, - uint64_t tagwait, - cvmx_fau_op_size_t size, - uint64_t reg) -{ - return CVMX_FAU_LOAD_IO_ADDRESS | - cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) | - cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) | - cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | - cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | - cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) | - cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); -} - -/** - * Perform an async atomic 64 bit add. The old value is - * placed in the scratch memory at byte address scraddr. - * - * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. - * @value: Signed value to add. - * Note: Only the low 22 bits are available. - * Returns Placed in the scratch pad register - */ -static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, - cvmx_fau_reg_64_t reg, - int64_t value) -{ - cvmx_send_single(__cvmx_fau_iobdma_data - (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); -} - -/** - * Perform an async atomic 32 bit add. The old value is - * placed in the scratch memory at byte address scraddr. - * - * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. - * @value: Signed value to add. - * Note: Only the low 22 bits are available. - * Returns Placed in the scratch pad register - */ -static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, - cvmx_fau_reg_32_t reg, - int32_t value) -{ - cvmx_send_single(__cvmx_fau_iobdma_data - (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); -} - -/** - * Perform an async atomic 16 bit add. The old value is - * placed in the scratch memory at byte address scraddr. - * - * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * @value: Signed value to add. - * Returns Placed in the scratch pad register - */ -static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, - cvmx_fau_reg_16_t reg, - int16_t value) -{ - cvmx_send_single(__cvmx_fau_iobdma_data - (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); -} - -/** - * Perform an async atomic 8 bit add. The old value is - * placed in the scratch memory at byte address scraddr. - * - * @scraddr: Scratch memory byte address to put response in. - * Must be 8 byte aligned. - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * @value: Signed value to add. - * Returns Placed in the scratch pad register - */ -static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, - cvmx_fau_reg_8_t reg, - int8_t value) -{ - cvmx_send_single(__cvmx_fau_iobdma_data - (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); -} - -/** - * Perform an async atomic 64 bit add after the current tag - * switch completes. - * - * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. - * @value: Signed value to add. - * Note: Only the low 22 bits are available. - * Returns Placed in the scratch pad register - */ -static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, - cvmx_fau_reg_64_t reg, - int64_t value) -{ - cvmx_send_single(__cvmx_fau_iobdma_data - (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); -} - -/** - * Perform an async atomic 32 bit add after the current tag - * switch completes. - * - * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. - * @value: Signed value to add. - * Note: Only the low 22 bits are available. - * Returns Placed in the scratch pad register - */ -static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, - cvmx_fau_reg_32_t reg, - int32_t value) -{ - cvmx_send_single(__cvmx_fau_iobdma_data - (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); -} - -/** - * Perform an async atomic 16 bit add after the current tag - * switch completes. - * - * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * @value: Signed value to add. - * - * Returns Placed in the scratch pad register - */ -static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, - cvmx_fau_reg_16_t reg, - int16_t value) -{ - cvmx_send_single(__cvmx_fau_iobdma_data - (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); -} - -/** - * Perform an async atomic 8 bit add after the current tag - * switch completes. - * - * @scraddr: Scratch memory byte address to put response in. Must be - * 8 byte aligned. If a timeout occurs, the error bit (63) - * will be set. Otherwise the value of the register before - * the update will be returned - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * @value: Signed value to add. - * - * Returns Placed in the scratch pad register - */ -static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, - cvmx_fau_reg_8_t reg, - int8_t value) -{ - cvmx_send_single(__cvmx_fau_iobdma_data - (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); -} - -/** - * Perform an atomic 64 bit add - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. - * @value: Signed value to add. - */ -static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) -{ - cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); -} - -/** - * Perform an atomic 32 bit add - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. - * @value: Signed value to add. - */ -static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) -{ - cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); -} - -/** - * Perform an atomic 16 bit add - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * @value: Signed value to add. - */ -static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) -{ - cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); -} - -/** - * Perform an atomic 8 bit add - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * @value: Signed value to add. - */ -static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) -{ - cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); -} - -/** - * Perform an atomic 64 bit write - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 8 for 64 bit access. - * @value: Signed value to write. - */ -static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) -{ - cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); -} - -/** - * Perform an atomic 32 bit write - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 4 for 32 bit access. - * @value: Signed value to write. - */ -static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) -{ - cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); -} - -/** - * Perform an atomic 16 bit write - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * - Step by 2 for 16 bit access. - * @value: Signed value to write. - */ -static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) -{ - cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); -} - -/** - * Perform an atomic 8 bit write - * - * @reg: FAU atomic register to access. 0 <= reg < 2048. - * @value: Signed value to write. - */ -static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) -{ - cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); -} - -#endif /* __CVMX_FAU_H__ */ diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/drivers/staging/octeon/cvmx-fpa-defs.h deleted file mode 100644 index bf5546b90110..000000000000 --- a/drivers/staging/octeon/cvmx-fpa-defs.h +++ /dev/null @@ -1,403 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_FPA_DEFS_H__ -#define __CVMX_FPA_DEFS_H__ - -#define CVMX_FPA_BIST_STATUS \ - CVMX_ADD_IO_SEG(0x00011800280000E8ull) -#define CVMX_FPA_CTL_STATUS \ - CVMX_ADD_IO_SEG(0x0001180028000050ull) -#define CVMX_FPA_FPF0_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000000ull) -#define CVMX_FPA_FPF0_SIZE \ - CVMX_ADD_IO_SEG(0x0001180028000058ull) -#define CVMX_FPA_FPF1_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000008ull) -#define CVMX_FPA_FPF2_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000010ull) -#define CVMX_FPA_FPF3_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000018ull) -#define CVMX_FPA_FPF4_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000020ull) -#define CVMX_FPA_FPF5_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000028ull) -#define CVMX_FPA_FPF6_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000030ull) -#define CVMX_FPA_FPF7_MARKS \ - CVMX_ADD_IO_SEG(0x0001180028000038ull) -#define CVMX_FPA_FPFX_MARKS(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1) -#define CVMX_FPA_FPFX_SIZE(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1) -#define CVMX_FPA_INT_ENB \ - CVMX_ADD_IO_SEG(0x0001180028000048ull) -#define CVMX_FPA_INT_SUM \ - CVMX_ADD_IO_SEG(0x0001180028000040ull) -#define CVMX_FPA_QUE0_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x00011800280000F0ull) -#define CVMX_FPA_QUE1_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x00011800280000F8ull) -#define CVMX_FPA_QUE2_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000100ull) -#define CVMX_FPA_QUE3_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000108ull) -#define CVMX_FPA_QUE4_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000110ull) -#define CVMX_FPA_QUE5_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000118ull) -#define CVMX_FPA_QUE6_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000120ull) -#define CVMX_FPA_QUE7_PAGE_INDEX \ - CVMX_ADD_IO_SEG(0x0001180028000128ull) -#define CVMX_FPA_QUEX_AVAILABLE(offset) \ - CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8)) -#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \ - CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8)) -#define CVMX_FPA_QUE_ACT \ - CVMX_ADD_IO_SEG(0x0001180028000138ull) -#define CVMX_FPA_QUE_EXP \ - CVMX_ADD_IO_SEG(0x0001180028000130ull) -#define CVMX_FPA_WART_CTL \ - CVMX_ADD_IO_SEG(0x00011800280000D8ull) -#define CVMX_FPA_WART_STATUS \ - CVMX_ADD_IO_SEG(0x00011800280000E0ull) - -union cvmx_fpa_bist_status { - uint64_t u64; - struct cvmx_fpa_bist_status_s { - uint64_t reserved_5_63:59; - uint64_t frd:1; - uint64_t fpf0:1; - uint64_t fpf1:1; - uint64_t ffr:1; - uint64_t fdr:1; - } s; - struct cvmx_fpa_bist_status_s cn30xx; - struct cvmx_fpa_bist_status_s cn31xx; - struct cvmx_fpa_bist_status_s cn38xx; - struct cvmx_fpa_bist_status_s cn38xxp2; - struct cvmx_fpa_bist_status_s cn50xx; - struct cvmx_fpa_bist_status_s cn52xx; - struct cvmx_fpa_bist_status_s cn52xxp1; - struct cvmx_fpa_bist_status_s cn56xx; - struct cvmx_fpa_bist_status_s cn56xxp1; - struct cvmx_fpa_bist_status_s cn58xx; - struct cvmx_fpa_bist_status_s cn58xxp1; -}; - -union cvmx_fpa_ctl_status { - uint64_t u64; - struct cvmx_fpa_ctl_status_s { - uint64_t reserved_18_63:46; - uint64_t reset:1; - uint64_t use_ldt:1; - uint64_t use_stt:1; - uint64_t enb:1; - uint64_t mem1_err:7; - uint64_t mem0_err:7; - } s; - struct cvmx_fpa_ctl_status_s cn30xx; - struct cvmx_fpa_ctl_status_s cn31xx; - struct cvmx_fpa_ctl_status_s cn38xx; - struct cvmx_fpa_ctl_status_s cn38xxp2; - struct cvmx_fpa_ctl_status_s cn50xx; - struct cvmx_fpa_ctl_status_s cn52xx; - struct cvmx_fpa_ctl_status_s cn52xxp1; - struct cvmx_fpa_ctl_status_s cn56xx; - struct cvmx_fpa_ctl_status_s cn56xxp1; - struct cvmx_fpa_ctl_status_s cn58xx; - struct cvmx_fpa_ctl_status_s cn58xxp1; -}; - -union cvmx_fpa_fpfx_marks { - uint64_t u64; - struct cvmx_fpa_fpfx_marks_s { - uint64_t reserved_22_63:42; - uint64_t fpf_wr:11; - uint64_t fpf_rd:11; - } s; - struct cvmx_fpa_fpfx_marks_s cn38xx; - struct cvmx_fpa_fpfx_marks_s cn38xxp2; - struct cvmx_fpa_fpfx_marks_s cn56xx; - struct cvmx_fpa_fpfx_marks_s cn56xxp1; - struct cvmx_fpa_fpfx_marks_s cn58xx; - struct cvmx_fpa_fpfx_marks_s cn58xxp1; -}; - -union cvmx_fpa_fpfx_size { - uint64_t u64; - struct cvmx_fpa_fpfx_size_s { - uint64_t reserved_11_63:53; - uint64_t fpf_siz:11; - } s; - struct cvmx_fpa_fpfx_size_s cn38xx; - struct cvmx_fpa_fpfx_size_s cn38xxp2; - struct cvmx_fpa_fpfx_size_s cn56xx; - struct cvmx_fpa_fpfx_size_s cn56xxp1; - struct cvmx_fpa_fpfx_size_s cn58xx; - struct cvmx_fpa_fpfx_size_s cn58xxp1; -}; - -union cvmx_fpa_fpf0_marks { - uint64_t u64; - struct cvmx_fpa_fpf0_marks_s { - uint64_t reserved_24_63:40; - uint64_t fpf_wr:12; - uint64_t fpf_rd:12; - } s; - struct cvmx_fpa_fpf0_marks_s cn38xx; - struct cvmx_fpa_fpf0_marks_s cn38xxp2; - struct cvmx_fpa_fpf0_marks_s cn56xx; - struct cvmx_fpa_fpf0_marks_s cn56xxp1; - struct cvmx_fpa_fpf0_marks_s cn58xx; - struct cvmx_fpa_fpf0_marks_s cn58xxp1; -}; - -union cvmx_fpa_fpf0_size { - uint64_t u64; - struct cvmx_fpa_fpf0_size_s { - uint64_t reserved_12_63:52; - uint64_t fpf_siz:12; - } s; - struct cvmx_fpa_fpf0_size_s cn38xx; - struct cvmx_fpa_fpf0_size_s cn38xxp2; - struct cvmx_fpa_fpf0_size_s cn56xx; - struct cvmx_fpa_fpf0_size_s cn56xxp1; - struct cvmx_fpa_fpf0_size_s cn58xx; - struct cvmx_fpa_fpf0_size_s cn58xxp1; -}; - -union cvmx_fpa_int_enb { - uint64_t u64; - struct cvmx_fpa_int_enb_s { - uint64_t reserved_28_63:36; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; - } s; - struct cvmx_fpa_int_enb_s cn30xx; - struct cvmx_fpa_int_enb_s cn31xx; - struct cvmx_fpa_int_enb_s cn38xx; - struct cvmx_fpa_int_enb_s cn38xxp2; - struct cvmx_fpa_int_enb_s cn50xx; - struct cvmx_fpa_int_enb_s cn52xx; - struct cvmx_fpa_int_enb_s cn52xxp1; - struct cvmx_fpa_int_enb_s cn56xx; - struct cvmx_fpa_int_enb_s cn56xxp1; - struct cvmx_fpa_int_enb_s cn58xx; - struct cvmx_fpa_int_enb_s cn58xxp1; -}; - -union cvmx_fpa_int_sum { - uint64_t u64; - struct cvmx_fpa_int_sum_s { - uint64_t reserved_28_63:36; - uint64_t q7_perr:1; - uint64_t q7_coff:1; - uint64_t q7_und:1; - uint64_t q6_perr:1; - uint64_t q6_coff:1; - uint64_t q6_und:1; - uint64_t q5_perr:1; - uint64_t q5_coff:1; - uint64_t q5_und:1; - uint64_t q4_perr:1; - uint64_t q4_coff:1; - uint64_t q4_und:1; - uint64_t q3_perr:1; - uint64_t q3_coff:1; - uint64_t q3_und:1; - uint64_t q2_perr:1; - uint64_t q2_coff:1; - uint64_t q2_und:1; - uint64_t q1_perr:1; - uint64_t q1_coff:1; - uint64_t q1_und:1; - uint64_t q0_perr:1; - uint64_t q0_coff:1; - uint64_t q0_und:1; - uint64_t fed1_dbe:1; - uint64_t fed1_sbe:1; - uint64_t fed0_dbe:1; - uint64_t fed0_sbe:1; - } s; - struct cvmx_fpa_int_sum_s cn30xx; - struct cvmx_fpa_int_sum_s cn31xx; - struct cvmx_fpa_int_sum_s cn38xx; - struct cvmx_fpa_int_sum_s cn38xxp2; - struct cvmx_fpa_int_sum_s cn50xx; - struct cvmx_fpa_int_sum_s cn52xx; - struct cvmx_fpa_int_sum_s cn52xxp1; - struct cvmx_fpa_int_sum_s cn56xx; - struct cvmx_fpa_int_sum_s cn56xxp1; - struct cvmx_fpa_int_sum_s cn58xx; - struct cvmx_fpa_int_sum_s cn58xxp1; -}; - -union cvmx_fpa_quex_available { - uint64_t u64; - struct cvmx_fpa_quex_available_s { - uint64_t reserved_29_63:35; - uint64_t que_siz:29; - } s; - struct cvmx_fpa_quex_available_s cn30xx; - struct cvmx_fpa_quex_available_s cn31xx; - struct cvmx_fpa_quex_available_s cn38xx; - struct cvmx_fpa_quex_available_s cn38xxp2; - struct cvmx_fpa_quex_available_s cn50xx; - struct cvmx_fpa_quex_available_s cn52xx; - struct cvmx_fpa_quex_available_s cn52xxp1; - struct cvmx_fpa_quex_available_s cn56xx; - struct cvmx_fpa_quex_available_s cn56xxp1; - struct cvmx_fpa_quex_available_s cn58xx; - struct cvmx_fpa_quex_available_s cn58xxp1; -}; - -union cvmx_fpa_quex_page_index { - uint64_t u64; - struct cvmx_fpa_quex_page_index_s { - uint64_t reserved_25_63:39; - uint64_t pg_num:25; - } s; - struct cvmx_fpa_quex_page_index_s cn30xx; - struct cvmx_fpa_quex_page_index_s cn31xx; - struct cvmx_fpa_quex_page_index_s cn38xx; - struct cvmx_fpa_quex_page_index_s cn38xxp2; - struct cvmx_fpa_quex_page_index_s cn50xx; - struct cvmx_fpa_quex_page_index_s cn52xx; - struct cvmx_fpa_quex_page_index_s cn52xxp1; - struct cvmx_fpa_quex_page_index_s cn56xx; - struct cvmx_fpa_quex_page_index_s cn56xxp1; - struct cvmx_fpa_quex_page_index_s cn58xx; - struct cvmx_fpa_quex_page_index_s cn58xxp1; -}; - -union cvmx_fpa_que_act { - uint64_t u64; - struct cvmx_fpa_que_act_s { - uint64_t reserved_29_63:35; - uint64_t act_que:3; - uint64_t act_indx:26; - } s; - struct cvmx_fpa_que_act_s cn30xx; - struct cvmx_fpa_que_act_s cn31xx; - struct cvmx_fpa_que_act_s cn38xx; - struct cvmx_fpa_que_act_s cn38xxp2; - struct cvmx_fpa_que_act_s cn50xx; - struct cvmx_fpa_que_act_s cn52xx; - struct cvmx_fpa_que_act_s cn52xxp1; - struct cvmx_fpa_que_act_s cn56xx; - struct cvmx_fpa_que_act_s cn56xxp1; - struct cvmx_fpa_que_act_s cn58xx; - struct cvmx_fpa_que_act_s cn58xxp1; -}; - -union cvmx_fpa_que_exp { - uint64_t u64; - struct cvmx_fpa_que_exp_s { - uint64_t reserved_29_63:35; - uint64_t exp_que:3; - uint64_t exp_indx:26; - } s; - struct cvmx_fpa_que_exp_s cn30xx; - struct cvmx_fpa_que_exp_s cn31xx; - struct cvmx_fpa_que_exp_s cn38xx; - struct cvmx_fpa_que_exp_s cn38xxp2; - struct cvmx_fpa_que_exp_s cn50xx; - struct cvmx_fpa_que_exp_s cn52xx; - struct cvmx_fpa_que_exp_s cn52xxp1; - struct cvmx_fpa_que_exp_s cn56xx; - struct cvmx_fpa_que_exp_s cn56xxp1; - struct cvmx_fpa_que_exp_s cn58xx; - struct cvmx_fpa_que_exp_s cn58xxp1; -}; - -union cvmx_fpa_wart_ctl { - uint64_t u64; - struct cvmx_fpa_wart_ctl_s { - uint64_t reserved_16_63:48; - uint64_t ctl:16; - } s; - struct cvmx_fpa_wart_ctl_s cn30xx; - struct cvmx_fpa_wart_ctl_s cn31xx; - struct cvmx_fpa_wart_ctl_s cn38xx; - struct cvmx_fpa_wart_ctl_s cn38xxp2; - struct cvmx_fpa_wart_ctl_s cn50xx; - struct cvmx_fpa_wart_ctl_s cn52xx; - struct cvmx_fpa_wart_ctl_s cn52xxp1; - struct cvmx_fpa_wart_ctl_s cn56xx; - struct cvmx_fpa_wart_ctl_s cn56xxp1; - struct cvmx_fpa_wart_ctl_s cn58xx; - struct cvmx_fpa_wart_ctl_s cn58xxp1; -}; - -union cvmx_fpa_wart_status { - uint64_t u64; - struct cvmx_fpa_wart_status_s { - uint64_t reserved_32_63:32; - uint64_t status:32; - } s; - struct cvmx_fpa_wart_status_s cn30xx; - struct cvmx_fpa_wart_status_s cn31xx; - struct cvmx_fpa_wart_status_s cn38xx; - struct cvmx_fpa_wart_status_s cn38xxp2; - struct cvmx_fpa_wart_status_s cn50xx; - struct cvmx_fpa_wart_status_s cn52xx; - struct cvmx_fpa_wart_status_s cn52xxp1; - struct cvmx_fpa_wart_status_s cn56xx; - struct cvmx_fpa_wart_status_s cn56xxp1; - struct cvmx_fpa_wart_status_s cn58xx; - struct cvmx_fpa_wart_status_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-fpa.c b/drivers/staging/octeon/cvmx-fpa.c deleted file mode 100644 index ad44b8bd8057..000000000000 --- a/drivers/staging/octeon/cvmx-fpa.c +++ /dev/null @@ -1,183 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Support library for the hardware Free Pool Allocator. - * - * - */ - -#include "cvmx-config.h" -#include "cvmx.h" -#include "cvmx-fpa.h" -#include "cvmx-ipd.h" - -/** - * Current state of all the pools. Use access functions - * instead of using it directly. - */ -CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; - -/** - * Setup a FPA pool to control a new block of memory. The - * buffer pointer must be a physical address. - * - * @pool: Pool to initialize - * 0 <= pool < 8 - * @name: Constant character string to name this pool. - * String is not copied. - * @buffer: Pointer to the block of memory to use. This must be - * accessible by all processors and external hardware. - * @block_size: Size for each block controlled by the FPA - * @num_blocks: Number of blocks - * - * Returns 0 on Success, - * -1 on failure - */ -int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, - uint64_t block_size, uint64_t num_blocks) -{ - char *ptr; - if (!buffer) { - cvmx_dprintf - ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n"); - return -1; - } - if (pool >= CVMX_FPA_NUM_POOLS) { - cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n"); - return -1; - } - - if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) { - cvmx_dprintf - ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n"); - return -1; - } - - if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) { - cvmx_dprintf - ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n"); - return -1; - } - - cvmx_fpa_pool_info[pool].name = name; - cvmx_fpa_pool_info[pool].size = block_size; - cvmx_fpa_pool_info[pool].starting_element_count = num_blocks; - cvmx_fpa_pool_info[pool].base = buffer; - - ptr = (char *)buffer; - while (num_blocks--) { - cvmx_fpa_free(ptr, pool, 0); - ptr += block_size; - } - return 0; -} - -/** - * Shutdown a Memory pool and validate that it had all of - * the buffers originally placed in it. - * - * @pool: Pool to shutdown - * Returns Zero on success - * - Positive is count of missing buffers - * - Negative is too many buffers or corrupted pointers - */ -uint64_t cvmx_fpa_shutdown_pool(uint64_t pool) -{ - uint64_t errors = 0; - uint64_t count = 0; - uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base); - uint64_t finish = - base + - cvmx_fpa_pool_info[pool].size * - cvmx_fpa_pool_info[pool].starting_element_count; - void *ptr; - uint64_t address; - - count = 0; - do { - ptr = cvmx_fpa_alloc(pool); - if (ptr) - address = cvmx_ptr_to_phys(ptr); - else - address = 0; - if (address) { - if ((address >= base) && (address < finish) && - (((address - - base) % cvmx_fpa_pool_info[pool].size) == 0)) { - count++; - } else { - cvmx_dprintf - ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n", - (unsigned long long)address, - cvmx_fpa_pool_info[pool].name, (int)pool); - errors++; - } - } - } while (address); - -#ifdef CVMX_ENABLE_PKO_FUNCTIONS - if (pool == 0) - cvmx_ipd_free_ptr(); -#endif - - if (errors) { - cvmx_dprintf - ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n", - cvmx_fpa_pool_info[pool].name, (int)pool, - (unsigned long long)base, (unsigned long long)finish, - (unsigned long long)cvmx_fpa_pool_info[pool].size); - return -errors; - } else - return 0; -} - -uint64_t cvmx_fpa_get_block_size(uint64_t pool) -{ - switch (pool) { - case 0: - return CVMX_FPA_POOL_0_SIZE; - case 1: - return CVMX_FPA_POOL_1_SIZE; - case 2: - return CVMX_FPA_POOL_2_SIZE; - case 3: - return CVMX_FPA_POOL_3_SIZE; - case 4: - return CVMX_FPA_POOL_4_SIZE; - case 5: - return CVMX_FPA_POOL_5_SIZE; - case 6: - return CVMX_FPA_POOL_6_SIZE; - case 7: - return CVMX_FPA_POOL_7_SIZE; - default: - return 0; - } -} diff --git a/drivers/staging/octeon/cvmx-fpa.h b/drivers/staging/octeon/cvmx-fpa.h deleted file mode 100644 index 1f04f9658736..000000000000 --- a/drivers/staging/octeon/cvmx-fpa.h +++ /dev/null @@ -1,299 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Interface to the hardware Free Pool Allocator. - * - * - */ - -#ifndef __CVMX_FPA_H__ -#define __CVMX_FPA_H__ - -#include "cvmx-address.h" -#include "cvmx-fpa-defs.h" - -#define CVMX_FPA_NUM_POOLS 8 -#define CVMX_FPA_MIN_BLOCK_SIZE 128 -#define CVMX_FPA_ALIGNMENT 128 - -/** - * Structure describing the data format used for stores to the FPA. - */ -typedef union { - uint64_t u64; - struct { - /* - * the (64-bit word) location in scratchpad to write - * to (if len != 0) - */ - uint64_t scraddr:8; - /* the number of words in the response (0 => no response) */ - uint64_t len:8; - /* the ID of the device on the non-coherent bus */ - uint64_t did:8; - /* - * the address that will appear in the first tick on - * the NCB bus. - */ - uint64_t addr:40; - } s; -} cvmx_fpa_iobdma_data_t; - -/** - * Structure describing the current state of a FPA pool. - */ -typedef struct { - /* Name it was created under */ - const char *name; - /* Size of each block */ - uint64_t size; - /* The base memory address of whole block */ - void *base; - /* The number of elements in the pool at creation */ - uint64_t starting_element_count; -} cvmx_fpa_pool_info_t; - -/** - * Current state of all the pools. Use access functions - * instead of using it directly. - */ -extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; - -/* CSR typedefs have been moved to cvmx-csr-*.h */ - -/** - * Return the name of the pool - * - * @pool: Pool to get the name of - * Returns The name - */ -static inline const char *cvmx_fpa_get_name(uint64_t pool) -{ - return cvmx_fpa_pool_info[pool].name; -} - -/** - * Return the base of the pool - * - * @pool: Pool to get the base of - * Returns The base - */ -static inline void *cvmx_fpa_get_base(uint64_t pool) -{ - return cvmx_fpa_pool_info[pool].base; -} - -/** - * Check if a pointer belongs to an FPA pool. Return non-zero - * if the supplied pointer is inside the memory controlled by - * an FPA pool. - * - * @pool: Pool to check - * @ptr: Pointer to check - * Returns Non-zero if pointer is in the pool. Zero if not - */ -static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr) -{ - return ((ptr >= cvmx_fpa_pool_info[pool].base) && - ((char *)ptr < - ((char *)(cvmx_fpa_pool_info[pool].base)) + - cvmx_fpa_pool_info[pool].size * - cvmx_fpa_pool_info[pool].starting_element_count)); -} - -/** - * Enable the FPA for use. Must be performed after any CSR - * configuration but before any other FPA functions. - */ -static inline void cvmx_fpa_enable(void) -{ - union cvmx_fpa_ctl_status status; - - status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); - if (status.s.enb) { - cvmx_dprintf - ("Warning: Enabling FPA when FPA already enabled.\n"); - } - - /* - * Do runtime check as we allow pass1 compiled code to run on - * pass2 chips. - */ - if (cvmx_octeon_is_pass1()) { - union cvmx_fpa_fpfx_marks marks; - int i; - for (i = 1; i < 8; i++) { - marks.u64 = - cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull); - marks.s.fpf_wr = 0xe0; - cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull, - marks.u64); - } - - /* Enforce a 10 cycle delay between config and enable */ - cvmx_wait(10); - } - - /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */ - status.u64 = 0; - status.s.enb = 1; - cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64); -} - -/** - * Get a new block from the FPA - * - * @pool: Pool to get the block from - * Returns Pointer to the block or NULL on failure - */ -static inline void *cvmx_fpa_alloc(uint64_t pool) -{ - uint64_t address = - cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool))); - if (address) - return cvmx_phys_to_ptr(address); - else - return NULL; -} - -/** - * Asynchronously get a new block from the FPA - * - * @scr_addr: Local scratch address to put response in. This is a byte address, - * but must be 8 byte aligned. - * @pool: Pool to get the block from - */ -static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool) -{ - cvmx_fpa_iobdma_data_t data; - - /* - * Hardware only uses 64 bit aligned locations, so convert - * from byte address to 64-bit index - */ - data.s.scraddr = scr_addr >> 3; - data.s.len = 1; - data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool); - data.s.addr = 0; - cvmx_send_single(data.u64); -} - -/** - * Free a block allocated with a FPA pool. Does NOT provide memory - * ordering in cases where the memory block was modified by the core. - * - * @ptr: Block to free - * @pool: Pool to put it in - * @num_cache_lines: - * Cache lines to invalidate - */ -static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, - uint64_t num_cache_lines) -{ - cvmx_addr_t newptr; - newptr.u64 = cvmx_ptr_to_phys(ptr); - newptr.sfilldidspace.didspace = - CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); - /* Prevent GCC from reordering around free */ - barrier(); - /* value written is number of cache lines not written back */ - cvmx_write_io(newptr.u64, num_cache_lines); -} - -/** - * Free a block allocated with a FPA pool. Provides required memory - * ordering in cases where memory block was modified by core. - * - * @ptr: Block to free - * @pool: Pool to put it in - * @num_cache_lines: - * Cache lines to invalidate - */ -static inline void cvmx_fpa_free(void *ptr, uint64_t pool, - uint64_t num_cache_lines) -{ - cvmx_addr_t newptr; - newptr.u64 = cvmx_ptr_to_phys(ptr); - newptr.sfilldidspace.didspace = - CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); - /* - * Make sure that any previous writes to memory go out before - * we free this buffer. This also serves as a barrier to - * prevent GCC from reordering operations to after the - * free. - */ - CVMX_SYNCWS; - /* value written is number of cache lines not written back */ - cvmx_write_io(newptr.u64, num_cache_lines); -} - -/** - * Setup a FPA pool to control a new block of memory. - * This can only be called once per pool. Make sure proper - * locking enforces this. - * - * @pool: Pool to initialize - * 0 <= pool < 8 - * @name: Constant character string to name this pool. - * String is not copied. - * @buffer: Pointer to the block of memory to use. This must be - * accessible by all processors and external hardware. - * @block_size: Size for each block controlled by the FPA - * @num_blocks: Number of blocks - * - * Returns 0 on Success, - * -1 on failure - */ -extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, - uint64_t block_size, uint64_t num_blocks); - -/** - * Shutdown a Memory pool and validate that it had all of - * the buffers originally placed in it. This should only be - * called by one processor after all hardware has finished - * using the pool. - * - * @pool: Pool to shutdown - * Returns Zero on success - * - Positive is count of missing buffers - * - Negative is too many buffers or corrupted pointers - */ -extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool); - -/** - * Get the size of blocks controlled by the pool - * This is resolved to a constant at compile time. - * - * @pool: Pool to access - * Returns Size of the block in bytes - */ -uint64_t cvmx_fpa_get_block_size(uint64_t pool); - -#endif /* __CVM_FPA_H__ */ diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/drivers/staging/octeon/cvmx-gmxx-defs.h deleted file mode 100644 index 946a43a73fd7..000000000000 --- a/drivers/staging/octeon/cvmx-gmxx-defs.h +++ /dev/null @@ -1,2529 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_GMXX_DEFS_H__ -#define __CVMX_GMXX_DEFS_H__ - -#define CVMX_GMXX_BAD_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_BIST(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_CLK_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_HG2_CONTROL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_INF_MODE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_NXA_ADR(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_PRTX_CFG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_DECISION(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_IFG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_JABBER(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_HG2_STATUS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PASS_EN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PRTS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_PRT_INFO(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_TX_STATUS(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull)) -#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_RX_XAUI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_SMACX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_STAT_BP(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_APPEND(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_BURST(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CLK(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SLOT(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT0(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT1(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT2(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT3(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT4(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT5(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT6(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT7(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT8(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STAT9(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TXX_THRESH(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_BP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull)) -#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_CORRUPT(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_HG2_REG1(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_HG2_REG2(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_IFG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_INT_EN(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_JAM(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_LFSR(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_OVR_BP(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_PRTS(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_MAX(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_SPI_THRESH(block_id) \ - CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_TX_XAUI_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \ - CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull)) - -union cvmx_gmxx_bad_reg { - uint64_t u64; - struct cvmx_gmxx_bad_reg_s { - uint64_t reserved_31_63:33; - uint64_t inb_nxa:4; - uint64_t statovr:1; - uint64_t loststat:4; - uint64_t reserved_18_21:4; - uint64_t out_ovr:16; - uint64_t ncb_ovr:1; - uint64_t out_col:1; - } s; - struct cvmx_gmxx_bad_reg_cn30xx { - uint64_t reserved_31_63:33; - uint64_t inb_nxa:4; - uint64_t statovr:1; - uint64_t reserved_25_25:1; - uint64_t loststat:3; - uint64_t reserved_5_21:17; - uint64_t out_ovr:3; - uint64_t reserved_0_1:2; - } cn30xx; - struct cvmx_gmxx_bad_reg_cn30xx cn31xx; - struct cvmx_gmxx_bad_reg_s cn38xx; - struct cvmx_gmxx_bad_reg_s cn38xxp2; - struct cvmx_gmxx_bad_reg_cn30xx cn50xx; - struct cvmx_gmxx_bad_reg_cn52xx { - uint64_t reserved_31_63:33; - uint64_t inb_nxa:4; - uint64_t statovr:1; - uint64_t loststat:4; - uint64_t reserved_6_21:16; - uint64_t out_ovr:4; - uint64_t reserved_0_1:2; - } cn52xx; - struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; - struct cvmx_gmxx_bad_reg_cn52xx cn56xx; - struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; - struct cvmx_gmxx_bad_reg_s cn58xx; - struct cvmx_gmxx_bad_reg_s cn58xxp1; -}; - -union cvmx_gmxx_bist { - uint64_t u64; - struct cvmx_gmxx_bist_s { - uint64_t reserved_17_63:47; - uint64_t status:17; - } s; - struct cvmx_gmxx_bist_cn30xx { - uint64_t reserved_10_63:54; - uint64_t status:10; - } cn30xx; - struct cvmx_gmxx_bist_cn30xx cn31xx; - struct cvmx_gmxx_bist_cn30xx cn38xx; - struct cvmx_gmxx_bist_cn30xx cn38xxp2; - struct cvmx_gmxx_bist_cn50xx { - uint64_t reserved_12_63:52; - uint64_t status:12; - } cn50xx; - struct cvmx_gmxx_bist_cn52xx { - uint64_t reserved_16_63:48; - uint64_t status:16; - } cn52xx; - struct cvmx_gmxx_bist_cn52xx cn52xxp1; - struct cvmx_gmxx_bist_cn52xx cn56xx; - struct cvmx_gmxx_bist_cn52xx cn56xxp1; - struct cvmx_gmxx_bist_s cn58xx; - struct cvmx_gmxx_bist_s cn58xxp1; -}; - -union cvmx_gmxx_clk_en { - uint64_t u64; - struct cvmx_gmxx_clk_en_s { - uint64_t reserved_1_63:63; - uint64_t clk_en:1; - } s; - struct cvmx_gmxx_clk_en_s cn52xx; - struct cvmx_gmxx_clk_en_s cn52xxp1; - struct cvmx_gmxx_clk_en_s cn56xx; - struct cvmx_gmxx_clk_en_s cn56xxp1; -}; - -union cvmx_gmxx_hg2_control { - uint64_t u64; - struct cvmx_gmxx_hg2_control_s { - uint64_t reserved_19_63:45; - uint64_t hg2tx_en:1; - uint64_t hg2rx_en:1; - uint64_t phys_en:1; - uint64_t logl_en:16; - } s; - struct cvmx_gmxx_hg2_control_s cn52xx; - struct cvmx_gmxx_hg2_control_s cn52xxp1; - struct cvmx_gmxx_hg2_control_s cn56xx; -}; - -union cvmx_gmxx_inf_mode { - uint64_t u64; - struct cvmx_gmxx_inf_mode_s { - uint64_t reserved_10_63:54; - uint64_t speed:2; - uint64_t reserved_6_7:2; - uint64_t mode:2; - uint64_t reserved_3_3:1; - uint64_t p0mii:1; - uint64_t en:1; - uint64_t type:1; - } s; - struct cvmx_gmxx_inf_mode_cn30xx { - uint64_t reserved_3_63:61; - uint64_t p0mii:1; - uint64_t en:1; - uint64_t type:1; - } cn30xx; - struct cvmx_gmxx_inf_mode_cn31xx { - uint64_t reserved_2_63:62; - uint64_t en:1; - uint64_t type:1; - } cn31xx; - struct cvmx_gmxx_inf_mode_cn31xx cn38xx; - struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; - struct cvmx_gmxx_inf_mode_cn30xx cn50xx; - struct cvmx_gmxx_inf_mode_cn52xx { - uint64_t reserved_10_63:54; - uint64_t speed:2; - uint64_t reserved_6_7:2; - uint64_t mode:2; - uint64_t reserved_2_3:2; - uint64_t en:1; - uint64_t type:1; - } cn52xx; - struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; - struct cvmx_gmxx_inf_mode_cn52xx cn56xx; - struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; - struct cvmx_gmxx_inf_mode_cn31xx cn58xx; - struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; -}; - -union cvmx_gmxx_nxa_adr { - uint64_t u64; - struct cvmx_gmxx_nxa_adr_s { - uint64_t reserved_6_63:58; - uint64_t prt:6; - } s; - struct cvmx_gmxx_nxa_adr_s cn30xx; - struct cvmx_gmxx_nxa_adr_s cn31xx; - struct cvmx_gmxx_nxa_adr_s cn38xx; - struct cvmx_gmxx_nxa_adr_s cn38xxp2; - struct cvmx_gmxx_nxa_adr_s cn50xx; - struct cvmx_gmxx_nxa_adr_s cn52xx; - struct cvmx_gmxx_nxa_adr_s cn52xxp1; - struct cvmx_gmxx_nxa_adr_s cn56xx; - struct cvmx_gmxx_nxa_adr_s cn56xxp1; - struct cvmx_gmxx_nxa_adr_s cn58xx; - struct cvmx_gmxx_nxa_adr_s cn58xxp1; -}; - -union cvmx_gmxx_prtx_cbfc_ctl { - uint64_t u64; - struct cvmx_gmxx_prtx_cbfc_ctl_s { - uint64_t phys_en:16; - uint64_t logl_en:16; - uint64_t phys_bp:16; - uint64_t reserved_4_15:12; - uint64_t bck_en:1; - uint64_t drp_en:1; - uint64_t tx_en:1; - uint64_t rx_en:1; - } s; - struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; - struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; -}; - -union cvmx_gmxx_prtx_cfg { - uint64_t u64; - struct cvmx_gmxx_prtx_cfg_s { - uint64_t reserved_14_63:50; - uint64_t tx_idle:1; - uint64_t rx_idle:1; - uint64_t reserved_9_11:3; - uint64_t speed_msb:1; - uint64_t reserved_4_7:4; - uint64_t slottime:1; - uint64_t duplex:1; - uint64_t speed:1; - uint64_t en:1; - } s; - struct cvmx_gmxx_prtx_cfg_cn30xx { - uint64_t reserved_4_63:60; - uint64_t slottime:1; - uint64_t duplex:1; - uint64_t speed:1; - uint64_t en:1; - } cn30xx; - struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; - struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; - struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; - struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; - struct cvmx_gmxx_prtx_cfg_s cn52xx; - struct cvmx_gmxx_prtx_cfg_s cn52xxp1; - struct cvmx_gmxx_prtx_cfg_s cn56xx; - struct cvmx_gmxx_prtx_cfg_s cn56xxp1; - struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; - struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; -}; - -union cvmx_gmxx_rxx_adr_cam0 { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_cam0_s { - uint64_t adr:64; - } s; - struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn38xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2; - struct cvmx_gmxx_rxx_adr_cam0_s cn50xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn52xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1; - struct cvmx_gmxx_rxx_adr_cam0_s cn56xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; - struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; - struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_adr_cam1 { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_cam1_s { - uint64_t adr:64; - } s; - struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn38xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2; - struct cvmx_gmxx_rxx_adr_cam1_s cn50xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn52xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1; - struct cvmx_gmxx_rxx_adr_cam1_s cn56xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; - struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; - struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_adr_cam2 { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_cam2_s { - uint64_t adr:64; - } s; - struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn38xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2; - struct cvmx_gmxx_rxx_adr_cam2_s cn50xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn52xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1; - struct cvmx_gmxx_rxx_adr_cam2_s cn56xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; - struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; - struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_adr_cam3 { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_cam3_s { - uint64_t adr:64; - } s; - struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn38xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2; - struct cvmx_gmxx_rxx_adr_cam3_s cn50xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn52xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1; - struct cvmx_gmxx_rxx_adr_cam3_s cn56xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; - struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; - struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_adr_cam4 { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_cam4_s { - uint64_t adr:64; - } s; - struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn38xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2; - struct cvmx_gmxx_rxx_adr_cam4_s cn50xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn52xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1; - struct cvmx_gmxx_rxx_adr_cam4_s cn56xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; - struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; - struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_adr_cam5 { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_cam5_s { - uint64_t adr:64; - } s; - struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn38xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2; - struct cvmx_gmxx_rxx_adr_cam5_s cn50xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn52xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1; - struct cvmx_gmxx_rxx_adr_cam5_s cn56xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; - struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; - struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_adr_cam_en { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_cam_en_s { - uint64_t reserved_8_63:56; - uint64_t en:8; - } s; - struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2; - struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1; - struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; - struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; - struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_adr_ctl { - uint64_t u64; - struct cvmx_gmxx_rxx_adr_ctl_s { - uint64_t reserved_4_63:60; - uint64_t cam_mode:1; - uint64_t mcst:2; - uint64_t bcst:1; - } s; - struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn38xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2; - struct cvmx_gmxx_rxx_adr_ctl_s cn50xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn52xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1; - struct cvmx_gmxx_rxx_adr_ctl_s cn56xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; - struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; - struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_decision { - uint64_t u64; - struct cvmx_gmxx_rxx_decision_s { - uint64_t reserved_5_63:59; - uint64_t cnt:5; - } s; - struct cvmx_gmxx_rxx_decision_s cn30xx; - struct cvmx_gmxx_rxx_decision_s cn31xx; - struct cvmx_gmxx_rxx_decision_s cn38xx; - struct cvmx_gmxx_rxx_decision_s cn38xxp2; - struct cvmx_gmxx_rxx_decision_s cn50xx; - struct cvmx_gmxx_rxx_decision_s cn52xx; - struct cvmx_gmxx_rxx_decision_s cn52xxp1; - struct cvmx_gmxx_rxx_decision_s cn56xx; - struct cvmx_gmxx_rxx_decision_s cn56xxp1; - struct cvmx_gmxx_rxx_decision_s cn58xx; - struct cvmx_gmxx_rxx_decision_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_frm_chk { - uint64_t u64; - struct cvmx_gmxx_rxx_frm_chk_s { - uint64_t reserved_10_63:54; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t carext:1; - uint64_t minerr:1; - } s; - struct cvmx_gmxx_rxx_frm_chk_s cn30xx; - struct cvmx_gmxx_rxx_frm_chk_s cn31xx; - struct cvmx_gmxx_rxx_frm_chk_s cn38xx; - struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; - struct cvmx_gmxx_rxx_frm_chk_cn50xx { - uint64_t reserved_10_63:54; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_6_6:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t reserved_0_0:1; - } cn50xx; - struct cvmx_gmxx_rxx_frm_chk_cn52xx { - uint64_t reserved_9_63:55; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_5_6:2; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t reserved_0_0:1; - } cn52xx; - struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; - struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; - struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; - struct cvmx_gmxx_rxx_frm_chk_s cn58xx; - struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_frm_ctl { - uint64_t u64; - struct cvmx_gmxx_rxx_frm_ctl_s { - uint64_t reserved_11_63:53; - uint64_t null_dis:1; - uint64_t pre_align:1; - uint64_t pad_len:1; - uint64_t vlan_len:1; - uint64_t pre_free:1; - uint64_t ctl_smac:1; - uint64_t ctl_mcst:1; - uint64_t ctl_bck:1; - uint64_t ctl_drp:1; - uint64_t pre_strp:1; - uint64_t pre_chk:1; - } s; - struct cvmx_gmxx_rxx_frm_ctl_cn30xx { - uint64_t reserved_9_63:55; - uint64_t pad_len:1; - uint64_t vlan_len:1; - uint64_t pre_free:1; - uint64_t ctl_smac:1; - uint64_t ctl_mcst:1; - uint64_t ctl_bck:1; - uint64_t ctl_drp:1; - uint64_t pre_strp:1; - uint64_t pre_chk:1; - } cn30xx; - struct cvmx_gmxx_rxx_frm_ctl_cn31xx { - uint64_t reserved_8_63:56; - uint64_t vlan_len:1; - uint64_t pre_free:1; - uint64_t ctl_smac:1; - uint64_t ctl_mcst:1; - uint64_t ctl_bck:1; - uint64_t ctl_drp:1; - uint64_t pre_strp:1; - uint64_t pre_chk:1; - } cn31xx; - struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; - struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; - struct cvmx_gmxx_rxx_frm_ctl_cn50xx { - uint64_t reserved_11_63:53; - uint64_t null_dis:1; - uint64_t pre_align:1; - uint64_t reserved_7_8:2; - uint64_t pre_free:1; - uint64_t ctl_smac:1; - uint64_t ctl_mcst:1; - uint64_t ctl_bck:1; - uint64_t ctl_drp:1; - uint64_t pre_strp:1; - uint64_t pre_chk:1; - } cn50xx; - struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; - struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; - struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; - struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { - uint64_t reserved_10_63:54; - uint64_t pre_align:1; - uint64_t reserved_7_8:2; - uint64_t pre_free:1; - uint64_t ctl_smac:1; - uint64_t ctl_mcst:1; - uint64_t ctl_bck:1; - uint64_t ctl_drp:1; - uint64_t pre_strp:1; - uint64_t pre_chk:1; - } cn56xxp1; - struct cvmx_gmxx_rxx_frm_ctl_s cn58xx; - struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; -}; - -union cvmx_gmxx_rxx_frm_max { - uint64_t u64; - struct cvmx_gmxx_rxx_frm_max_s { - uint64_t reserved_16_63:48; - uint64_t len:16; - } s; - struct cvmx_gmxx_rxx_frm_max_s cn30xx; - struct cvmx_gmxx_rxx_frm_max_s cn31xx; - struct cvmx_gmxx_rxx_frm_max_s cn38xx; - struct cvmx_gmxx_rxx_frm_max_s cn38xxp2; - struct cvmx_gmxx_rxx_frm_max_s cn58xx; - struct cvmx_gmxx_rxx_frm_max_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_frm_min { - uint64_t u64; - struct cvmx_gmxx_rxx_frm_min_s { - uint64_t reserved_16_63:48; - uint64_t len:16; - } s; - struct cvmx_gmxx_rxx_frm_min_s cn30xx; - struct cvmx_gmxx_rxx_frm_min_s cn31xx; - struct cvmx_gmxx_rxx_frm_min_s cn38xx; - struct cvmx_gmxx_rxx_frm_min_s cn38xxp2; - struct cvmx_gmxx_rxx_frm_min_s cn58xx; - struct cvmx_gmxx_rxx_frm_min_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_ifg { - uint64_t u64; - struct cvmx_gmxx_rxx_ifg_s { - uint64_t reserved_4_63:60; - uint64_t ifg:4; - } s; - struct cvmx_gmxx_rxx_ifg_s cn30xx; - struct cvmx_gmxx_rxx_ifg_s cn31xx; - struct cvmx_gmxx_rxx_ifg_s cn38xx; - struct cvmx_gmxx_rxx_ifg_s cn38xxp2; - struct cvmx_gmxx_rxx_ifg_s cn50xx; - struct cvmx_gmxx_rxx_ifg_s cn52xx; - struct cvmx_gmxx_rxx_ifg_s cn52xxp1; - struct cvmx_gmxx_rxx_ifg_s cn56xx; - struct cvmx_gmxx_rxx_ifg_s cn56xxp1; - struct cvmx_gmxx_rxx_ifg_s cn58xx; - struct cvmx_gmxx_rxx_ifg_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_int_en { - uint64_t u64; - struct cvmx_gmxx_rxx_int_en_s { - uint64_t reserved_29_63:35; - uint64_t hg2cc:1; - uint64_t hg2fld:1; - uint64_t undat:1; - uint64_t uneop:1; - uint64_t unsop:1; - uint64_t bad_term:1; - uint64_t bad_seq:1; - uint64_t rem_fault:1; - uint64_t loc_fault:1; - uint64_t pause_drp:1; - uint64_t phy_dupx:1; - uint64_t phy_spd:1; - uint64_t phy_link:1; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t carext:1; - uint64_t minerr:1; - } s; - struct cvmx_gmxx_rxx_int_en_cn30xx { - uint64_t reserved_19_63:45; - uint64_t phy_dupx:1; - uint64_t phy_spd:1; - uint64_t phy_link:1; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t carext:1; - uint64_t minerr:1; - } cn30xx; - struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; - struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; - struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; - struct cvmx_gmxx_rxx_int_en_cn50xx { - uint64_t reserved_20_63:44; - uint64_t pause_drp:1; - uint64_t phy_dupx:1; - uint64_t phy_spd:1; - uint64_t phy_link:1; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_6_6:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t reserved_0_0:1; - } cn50xx; - struct cvmx_gmxx_rxx_int_en_cn52xx { - uint64_t reserved_29_63:35; - uint64_t hg2cc:1; - uint64_t hg2fld:1; - uint64_t undat:1; - uint64_t uneop:1; - uint64_t unsop:1; - uint64_t bad_term:1; - uint64_t bad_seq:1; - uint64_t rem_fault:1; - uint64_t loc_fault:1; - uint64_t pause_drp:1; - uint64_t reserved_16_18:3; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t reserved_9_9:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_5_6:2; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t reserved_0_0:1; - } cn52xx; - struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; - struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; - struct cvmx_gmxx_rxx_int_en_cn56xxp1 { - uint64_t reserved_27_63:37; - uint64_t undat:1; - uint64_t uneop:1; - uint64_t unsop:1; - uint64_t bad_term:1; - uint64_t bad_seq:1; - uint64_t rem_fault:1; - uint64_t loc_fault:1; - uint64_t pause_drp:1; - uint64_t reserved_16_18:3; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t reserved_9_9:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_5_6:2; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t reserved_0_0:1; - } cn56xxp1; - struct cvmx_gmxx_rxx_int_en_cn58xx { - uint64_t reserved_20_63:44; - uint64_t pause_drp:1; - uint64_t phy_dupx:1; - uint64_t phy_spd:1; - uint64_t phy_link:1; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t carext:1; - uint64_t minerr:1; - } cn58xx; - struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; -}; - -union cvmx_gmxx_rxx_int_reg { - uint64_t u64; - struct cvmx_gmxx_rxx_int_reg_s { - uint64_t reserved_29_63:35; - uint64_t hg2cc:1; - uint64_t hg2fld:1; - uint64_t undat:1; - uint64_t uneop:1; - uint64_t unsop:1; - uint64_t bad_term:1; - uint64_t bad_seq:1; - uint64_t rem_fault:1; - uint64_t loc_fault:1; - uint64_t pause_drp:1; - uint64_t phy_dupx:1; - uint64_t phy_spd:1; - uint64_t phy_link:1; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t carext:1; - uint64_t minerr:1; - } s; - struct cvmx_gmxx_rxx_int_reg_cn30xx { - uint64_t reserved_19_63:45; - uint64_t phy_dupx:1; - uint64_t phy_spd:1; - uint64_t phy_link:1; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t carext:1; - uint64_t minerr:1; - } cn30xx; - struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; - struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; - struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; - struct cvmx_gmxx_rxx_int_reg_cn50xx { - uint64_t reserved_20_63:44; - uint64_t pause_drp:1; - uint64_t phy_dupx:1; - uint64_t phy_spd:1; - uint64_t phy_link:1; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_6_6:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t reserved_0_0:1; - } cn50xx; - struct cvmx_gmxx_rxx_int_reg_cn52xx { - uint64_t reserved_29_63:35; - uint64_t hg2cc:1; - uint64_t hg2fld:1; - uint64_t undat:1; - uint64_t uneop:1; - uint64_t unsop:1; - uint64_t bad_term:1; - uint64_t bad_seq:1; - uint64_t rem_fault:1; - uint64_t loc_fault:1; - uint64_t pause_drp:1; - uint64_t reserved_16_18:3; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t reserved_9_9:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_5_6:2; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t reserved_0_0:1; - } cn52xx; - struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; - struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; - struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { - uint64_t reserved_27_63:37; - uint64_t undat:1; - uint64_t uneop:1; - uint64_t unsop:1; - uint64_t bad_term:1; - uint64_t bad_seq:1; - uint64_t rem_fault:1; - uint64_t loc_fault:1; - uint64_t pause_drp:1; - uint64_t reserved_16_18:3; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t reserved_9_9:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t reserved_5_6:2; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t reserved_2_2:1; - uint64_t carext:1; - uint64_t reserved_0_0:1; - } cn56xxp1; - struct cvmx_gmxx_rxx_int_reg_cn58xx { - uint64_t reserved_20_63:44; - uint64_t pause_drp:1; - uint64_t phy_dupx:1; - uint64_t phy_spd:1; - uint64_t phy_link:1; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t niberr:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t carext:1; - uint64_t minerr:1; - } cn58xx; - struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; -}; - -union cvmx_gmxx_rxx_jabber { - uint64_t u64; - struct cvmx_gmxx_rxx_jabber_s { - uint64_t reserved_16_63:48; - uint64_t cnt:16; - } s; - struct cvmx_gmxx_rxx_jabber_s cn30xx; - struct cvmx_gmxx_rxx_jabber_s cn31xx; - struct cvmx_gmxx_rxx_jabber_s cn38xx; - struct cvmx_gmxx_rxx_jabber_s cn38xxp2; - struct cvmx_gmxx_rxx_jabber_s cn50xx; - struct cvmx_gmxx_rxx_jabber_s cn52xx; - struct cvmx_gmxx_rxx_jabber_s cn52xxp1; - struct cvmx_gmxx_rxx_jabber_s cn56xx; - struct cvmx_gmxx_rxx_jabber_s cn56xxp1; - struct cvmx_gmxx_rxx_jabber_s cn58xx; - struct cvmx_gmxx_rxx_jabber_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_pause_drop_time { - uint64_t u64; - struct cvmx_gmxx_rxx_pause_drop_time_s { - uint64_t reserved_16_63:48; - uint64_t status:16; - } s; - struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; - struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; - struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1; - struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx; - struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; - struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; - struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_rx_inbnd { - uint64_t u64; - struct cvmx_gmxx_rxx_rx_inbnd_s { - uint64_t reserved_4_63:60; - uint64_t duplex:1; - uint64_t speed:2; - uint64_t status:1; - } s; - struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; - struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; - struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx; - struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2; - struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx; - struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx; - struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_ctl { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_ctl_s { - uint64_t reserved_1_63:63; - uint64_t rd_clr:1; - } s; - struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn38xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_ctl_s cn50xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn52xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_ctl_s cn56xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; - struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_octs { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_octs_s { - uint64_t reserved_48_63:16; - uint64_t cnt:48; - } s; - struct cvmx_gmxx_rxx_stats_octs_s cn30xx; - struct cvmx_gmxx_rxx_stats_octs_s cn31xx; - struct cvmx_gmxx_rxx_stats_octs_s cn38xx; - struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_octs_s cn50xx; - struct cvmx_gmxx_rxx_stats_octs_s cn52xx; - struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_octs_s cn56xx; - struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_octs_s cn58xx; - struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_octs_ctl { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_octs_ctl_s { - uint64_t reserved_48_63:16; - uint64_t cnt:48; - } s; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; - struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_octs_dmac { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_octs_dmac_s { - uint64_t reserved_48_63:16; - uint64_t cnt:48; - } s; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; - struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_octs_drp { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_octs_drp_s { - uint64_t reserved_48_63:16; - uint64_t cnt:48; - } s; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; - struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_pkts { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_pkts_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn38xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_pkts_s cn50xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn52xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_pkts_s cn56xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; - struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_pkts_bad { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_pkts_bad_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; - struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_pkts_ctl { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; - struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_pkts_dmac { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; - struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_stats_pkts_drp { - uint64_t u64; - struct cvmx_gmxx_rxx_stats_pkts_drp_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; - struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; -}; - -union cvmx_gmxx_rxx_udd_skp { - uint64_t u64; - struct cvmx_gmxx_rxx_udd_skp_s { - uint64_t reserved_9_63:55; - uint64_t fcssel:1; - uint64_t reserved_7_7:1; - uint64_t len:7; - } s; - struct cvmx_gmxx_rxx_udd_skp_s cn30xx; - struct cvmx_gmxx_rxx_udd_skp_s cn31xx; - struct cvmx_gmxx_rxx_udd_skp_s cn38xx; - struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2; - struct cvmx_gmxx_rxx_udd_skp_s cn50xx; - struct cvmx_gmxx_rxx_udd_skp_s cn52xx; - struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1; - struct cvmx_gmxx_rxx_udd_skp_s cn56xx; - struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; - struct cvmx_gmxx_rxx_udd_skp_s cn58xx; - struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; -}; - -union cvmx_gmxx_rx_bp_dropx { - uint64_t u64; - struct cvmx_gmxx_rx_bp_dropx_s { - uint64_t reserved_6_63:58; - uint64_t mark:6; - } s; - struct cvmx_gmxx_rx_bp_dropx_s cn30xx; - struct cvmx_gmxx_rx_bp_dropx_s cn31xx; - struct cvmx_gmxx_rx_bp_dropx_s cn38xx; - struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2; - struct cvmx_gmxx_rx_bp_dropx_s cn50xx; - struct cvmx_gmxx_rx_bp_dropx_s cn52xx; - struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1; - struct cvmx_gmxx_rx_bp_dropx_s cn56xx; - struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; - struct cvmx_gmxx_rx_bp_dropx_s cn58xx; - struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; -}; - -union cvmx_gmxx_rx_bp_offx { - uint64_t u64; - struct cvmx_gmxx_rx_bp_offx_s { - uint64_t reserved_6_63:58; - uint64_t mark:6; - } s; - struct cvmx_gmxx_rx_bp_offx_s cn30xx; - struct cvmx_gmxx_rx_bp_offx_s cn31xx; - struct cvmx_gmxx_rx_bp_offx_s cn38xx; - struct cvmx_gmxx_rx_bp_offx_s cn38xxp2; - struct cvmx_gmxx_rx_bp_offx_s cn50xx; - struct cvmx_gmxx_rx_bp_offx_s cn52xx; - struct cvmx_gmxx_rx_bp_offx_s cn52xxp1; - struct cvmx_gmxx_rx_bp_offx_s cn56xx; - struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; - struct cvmx_gmxx_rx_bp_offx_s cn58xx; - struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; -}; - -union cvmx_gmxx_rx_bp_onx { - uint64_t u64; - struct cvmx_gmxx_rx_bp_onx_s { - uint64_t reserved_9_63:55; - uint64_t mark:9; - } s; - struct cvmx_gmxx_rx_bp_onx_s cn30xx; - struct cvmx_gmxx_rx_bp_onx_s cn31xx; - struct cvmx_gmxx_rx_bp_onx_s cn38xx; - struct cvmx_gmxx_rx_bp_onx_s cn38xxp2; - struct cvmx_gmxx_rx_bp_onx_s cn50xx; - struct cvmx_gmxx_rx_bp_onx_s cn52xx; - struct cvmx_gmxx_rx_bp_onx_s cn52xxp1; - struct cvmx_gmxx_rx_bp_onx_s cn56xx; - struct cvmx_gmxx_rx_bp_onx_s cn56xxp1; - struct cvmx_gmxx_rx_bp_onx_s cn58xx; - struct cvmx_gmxx_rx_bp_onx_s cn58xxp1; -}; - -union cvmx_gmxx_rx_hg2_status { - uint64_t u64; - struct cvmx_gmxx_rx_hg2_status_s { - uint64_t reserved_48_63:16; - uint64_t phtim2go:16; - uint64_t xof:16; - uint64_t lgtim2go:16; - } s; - struct cvmx_gmxx_rx_hg2_status_s cn52xx; - struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; - struct cvmx_gmxx_rx_hg2_status_s cn56xx; -}; - -union cvmx_gmxx_rx_pass_en { - uint64_t u64; - struct cvmx_gmxx_rx_pass_en_s { - uint64_t reserved_16_63:48; - uint64_t en:16; - } s; - struct cvmx_gmxx_rx_pass_en_s cn38xx; - struct cvmx_gmxx_rx_pass_en_s cn38xxp2; - struct cvmx_gmxx_rx_pass_en_s cn58xx; - struct cvmx_gmxx_rx_pass_en_s cn58xxp1; -}; - -union cvmx_gmxx_rx_pass_mapx { - uint64_t u64; - struct cvmx_gmxx_rx_pass_mapx_s { - uint64_t reserved_4_63:60; - uint64_t dprt:4; - } s; - struct cvmx_gmxx_rx_pass_mapx_s cn38xx; - struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; - struct cvmx_gmxx_rx_pass_mapx_s cn58xx; - struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1; -}; - -union cvmx_gmxx_rx_prt_info { - uint64_t u64; - struct cvmx_gmxx_rx_prt_info_s { - uint64_t reserved_32_63:32; - uint64_t drop:16; - uint64_t commit:16; - } s; - struct cvmx_gmxx_rx_prt_info_cn30xx { - uint64_t reserved_19_63:45; - uint64_t drop:3; - uint64_t reserved_3_15:13; - uint64_t commit:3; - } cn30xx; - struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; - struct cvmx_gmxx_rx_prt_info_s cn38xx; - struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; - struct cvmx_gmxx_rx_prt_info_cn52xx { - uint64_t reserved_20_63:44; - uint64_t drop:4; - uint64_t reserved_4_15:12; - uint64_t commit:4; - } cn52xx; - struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; - struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; - struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; - struct cvmx_gmxx_rx_prt_info_s cn58xx; - struct cvmx_gmxx_rx_prt_info_s cn58xxp1; -}; - -union cvmx_gmxx_rx_prts { - uint64_t u64; - struct cvmx_gmxx_rx_prts_s { - uint64_t reserved_3_63:61; - uint64_t prts:3; - } s; - struct cvmx_gmxx_rx_prts_s cn30xx; - struct cvmx_gmxx_rx_prts_s cn31xx; - struct cvmx_gmxx_rx_prts_s cn38xx; - struct cvmx_gmxx_rx_prts_s cn38xxp2; - struct cvmx_gmxx_rx_prts_s cn50xx; - struct cvmx_gmxx_rx_prts_s cn52xx; - struct cvmx_gmxx_rx_prts_s cn52xxp1; - struct cvmx_gmxx_rx_prts_s cn56xx; - struct cvmx_gmxx_rx_prts_s cn56xxp1; - struct cvmx_gmxx_rx_prts_s cn58xx; - struct cvmx_gmxx_rx_prts_s cn58xxp1; -}; - -union cvmx_gmxx_rx_tx_status { - uint64_t u64; - struct cvmx_gmxx_rx_tx_status_s { - uint64_t reserved_7_63:57; - uint64_t tx:3; - uint64_t reserved_3_3:1; - uint64_t rx:3; - } s; - struct cvmx_gmxx_rx_tx_status_s cn30xx; - struct cvmx_gmxx_rx_tx_status_s cn31xx; - struct cvmx_gmxx_rx_tx_status_s cn50xx; -}; - -union cvmx_gmxx_rx_xaui_bad_col { - uint64_t u64; - struct cvmx_gmxx_rx_xaui_bad_col_s { - uint64_t reserved_40_63:24; - uint64_t val:1; - uint64_t state:3; - uint64_t lane_rxc:4; - uint64_t lane_rxd:32; - } s; - struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; - struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; - struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; - struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; -}; - -union cvmx_gmxx_rx_xaui_ctl { - uint64_t u64; - struct cvmx_gmxx_rx_xaui_ctl_s { - uint64_t reserved_2_63:62; - uint64_t status:2; - } s; - struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; - struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; - struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; - struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; -}; - -union cvmx_gmxx_smacx { - uint64_t u64; - struct cvmx_gmxx_smacx_s { - uint64_t reserved_48_63:16; - uint64_t smac:48; - } s; - struct cvmx_gmxx_smacx_s cn30xx; - struct cvmx_gmxx_smacx_s cn31xx; - struct cvmx_gmxx_smacx_s cn38xx; - struct cvmx_gmxx_smacx_s cn38xxp2; - struct cvmx_gmxx_smacx_s cn50xx; - struct cvmx_gmxx_smacx_s cn52xx; - struct cvmx_gmxx_smacx_s cn52xxp1; - struct cvmx_gmxx_smacx_s cn56xx; - struct cvmx_gmxx_smacx_s cn56xxp1; - struct cvmx_gmxx_smacx_s cn58xx; - struct cvmx_gmxx_smacx_s cn58xxp1; -}; - -union cvmx_gmxx_stat_bp { - uint64_t u64; - struct cvmx_gmxx_stat_bp_s { - uint64_t reserved_17_63:47; - uint64_t bp:1; - uint64_t cnt:16; - } s; - struct cvmx_gmxx_stat_bp_s cn30xx; - struct cvmx_gmxx_stat_bp_s cn31xx; - struct cvmx_gmxx_stat_bp_s cn38xx; - struct cvmx_gmxx_stat_bp_s cn38xxp2; - struct cvmx_gmxx_stat_bp_s cn50xx; - struct cvmx_gmxx_stat_bp_s cn52xx; - struct cvmx_gmxx_stat_bp_s cn52xxp1; - struct cvmx_gmxx_stat_bp_s cn56xx; - struct cvmx_gmxx_stat_bp_s cn56xxp1; - struct cvmx_gmxx_stat_bp_s cn58xx; - struct cvmx_gmxx_stat_bp_s cn58xxp1; -}; - -union cvmx_gmxx_txx_append { - uint64_t u64; - struct cvmx_gmxx_txx_append_s { - uint64_t reserved_4_63:60; - uint64_t force_fcs:1; - uint64_t fcs:1; - uint64_t pad:1; - uint64_t preamble:1; - } s; - struct cvmx_gmxx_txx_append_s cn30xx; - struct cvmx_gmxx_txx_append_s cn31xx; - struct cvmx_gmxx_txx_append_s cn38xx; - struct cvmx_gmxx_txx_append_s cn38xxp2; - struct cvmx_gmxx_txx_append_s cn50xx; - struct cvmx_gmxx_txx_append_s cn52xx; - struct cvmx_gmxx_txx_append_s cn52xxp1; - struct cvmx_gmxx_txx_append_s cn56xx; - struct cvmx_gmxx_txx_append_s cn56xxp1; - struct cvmx_gmxx_txx_append_s cn58xx; - struct cvmx_gmxx_txx_append_s cn58xxp1; -}; - -union cvmx_gmxx_txx_burst { - uint64_t u64; - struct cvmx_gmxx_txx_burst_s { - uint64_t reserved_16_63:48; - uint64_t burst:16; - } s; - struct cvmx_gmxx_txx_burst_s cn30xx; - struct cvmx_gmxx_txx_burst_s cn31xx; - struct cvmx_gmxx_txx_burst_s cn38xx; - struct cvmx_gmxx_txx_burst_s cn38xxp2; - struct cvmx_gmxx_txx_burst_s cn50xx; - struct cvmx_gmxx_txx_burst_s cn52xx; - struct cvmx_gmxx_txx_burst_s cn52xxp1; - struct cvmx_gmxx_txx_burst_s cn56xx; - struct cvmx_gmxx_txx_burst_s cn56xxp1; - struct cvmx_gmxx_txx_burst_s cn58xx; - struct cvmx_gmxx_txx_burst_s cn58xxp1; -}; - -union cvmx_gmxx_txx_cbfc_xoff { - uint64_t u64; - struct cvmx_gmxx_txx_cbfc_xoff_s { - uint64_t reserved_16_63:48; - uint64_t xoff:16; - } s; - struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; - struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; -}; - -union cvmx_gmxx_txx_cbfc_xon { - uint64_t u64; - struct cvmx_gmxx_txx_cbfc_xon_s { - uint64_t reserved_16_63:48; - uint64_t xon:16; - } s; - struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; - struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; -}; - -union cvmx_gmxx_txx_clk { - uint64_t u64; - struct cvmx_gmxx_txx_clk_s { - uint64_t reserved_6_63:58; - uint64_t clk_cnt:6; - } s; - struct cvmx_gmxx_txx_clk_s cn30xx; - struct cvmx_gmxx_txx_clk_s cn31xx; - struct cvmx_gmxx_txx_clk_s cn38xx; - struct cvmx_gmxx_txx_clk_s cn38xxp2; - struct cvmx_gmxx_txx_clk_s cn50xx; - struct cvmx_gmxx_txx_clk_s cn58xx; - struct cvmx_gmxx_txx_clk_s cn58xxp1; -}; - -union cvmx_gmxx_txx_ctl { - uint64_t u64; - struct cvmx_gmxx_txx_ctl_s { - uint64_t reserved_2_63:62; - uint64_t xsdef_en:1; - uint64_t xscol_en:1; - } s; - struct cvmx_gmxx_txx_ctl_s cn30xx; - struct cvmx_gmxx_txx_ctl_s cn31xx; - struct cvmx_gmxx_txx_ctl_s cn38xx; - struct cvmx_gmxx_txx_ctl_s cn38xxp2; - struct cvmx_gmxx_txx_ctl_s cn50xx; - struct cvmx_gmxx_txx_ctl_s cn52xx; - struct cvmx_gmxx_txx_ctl_s cn52xxp1; - struct cvmx_gmxx_txx_ctl_s cn56xx; - struct cvmx_gmxx_txx_ctl_s cn56xxp1; - struct cvmx_gmxx_txx_ctl_s cn58xx; - struct cvmx_gmxx_txx_ctl_s cn58xxp1; -}; - -union cvmx_gmxx_txx_min_pkt { - uint64_t u64; - struct cvmx_gmxx_txx_min_pkt_s { - uint64_t reserved_8_63:56; - uint64_t min_size:8; - } s; - struct cvmx_gmxx_txx_min_pkt_s cn30xx; - struct cvmx_gmxx_txx_min_pkt_s cn31xx; - struct cvmx_gmxx_txx_min_pkt_s cn38xx; - struct cvmx_gmxx_txx_min_pkt_s cn38xxp2; - struct cvmx_gmxx_txx_min_pkt_s cn50xx; - struct cvmx_gmxx_txx_min_pkt_s cn52xx; - struct cvmx_gmxx_txx_min_pkt_s cn52xxp1; - struct cvmx_gmxx_txx_min_pkt_s cn56xx; - struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; - struct cvmx_gmxx_txx_min_pkt_s cn58xx; - struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; -}; - -union cvmx_gmxx_txx_pause_pkt_interval { - uint64_t u64; - struct cvmx_gmxx_txx_pause_pkt_interval_s { - uint64_t reserved_16_63:48; - uint64_t interval:16; - } s; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; - struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; -}; - -union cvmx_gmxx_txx_pause_pkt_time { - uint64_t u64; - struct cvmx_gmxx_txx_pause_pkt_time_s { - uint64_t reserved_16_63:48; - uint64_t time:16; - } s; - struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2; - struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1; - struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; - struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; - struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; -}; - -union cvmx_gmxx_txx_pause_togo { - uint64_t u64; - struct cvmx_gmxx_txx_pause_togo_s { - uint64_t reserved_32_63:32; - uint64_t msg_time:16; - uint64_t time:16; - } s; - struct cvmx_gmxx_txx_pause_togo_cn30xx { - uint64_t reserved_16_63:48; - uint64_t time:16; - } cn30xx; - struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; - struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; - struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2; - struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx; - struct cvmx_gmxx_txx_pause_togo_s cn52xx; - struct cvmx_gmxx_txx_pause_togo_s cn52xxp1; - struct cvmx_gmxx_txx_pause_togo_s cn56xx; - struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; - struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; - struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; -}; - -union cvmx_gmxx_txx_pause_zero { - uint64_t u64; - struct cvmx_gmxx_txx_pause_zero_s { - uint64_t reserved_1_63:63; - uint64_t send:1; - } s; - struct cvmx_gmxx_txx_pause_zero_s cn30xx; - struct cvmx_gmxx_txx_pause_zero_s cn31xx; - struct cvmx_gmxx_txx_pause_zero_s cn38xx; - struct cvmx_gmxx_txx_pause_zero_s cn38xxp2; - struct cvmx_gmxx_txx_pause_zero_s cn50xx; - struct cvmx_gmxx_txx_pause_zero_s cn52xx; - struct cvmx_gmxx_txx_pause_zero_s cn52xxp1; - struct cvmx_gmxx_txx_pause_zero_s cn56xx; - struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; - struct cvmx_gmxx_txx_pause_zero_s cn58xx; - struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; -}; - -union cvmx_gmxx_txx_sgmii_ctl { - uint64_t u64; - struct cvmx_gmxx_txx_sgmii_ctl_s { - uint64_t reserved_1_63:63; - uint64_t align:1; - } s; - struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; - struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; - struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; - struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; -}; - -union cvmx_gmxx_txx_slot { - uint64_t u64; - struct cvmx_gmxx_txx_slot_s { - uint64_t reserved_10_63:54; - uint64_t slot:10; - } s; - struct cvmx_gmxx_txx_slot_s cn30xx; - struct cvmx_gmxx_txx_slot_s cn31xx; - struct cvmx_gmxx_txx_slot_s cn38xx; - struct cvmx_gmxx_txx_slot_s cn38xxp2; - struct cvmx_gmxx_txx_slot_s cn50xx; - struct cvmx_gmxx_txx_slot_s cn52xx; - struct cvmx_gmxx_txx_slot_s cn52xxp1; - struct cvmx_gmxx_txx_slot_s cn56xx; - struct cvmx_gmxx_txx_slot_s cn56xxp1; - struct cvmx_gmxx_txx_slot_s cn58xx; - struct cvmx_gmxx_txx_slot_s cn58xxp1; -}; - -union cvmx_gmxx_txx_soft_pause { - uint64_t u64; - struct cvmx_gmxx_txx_soft_pause_s { - uint64_t reserved_16_63:48; - uint64_t time:16; - } s; - struct cvmx_gmxx_txx_soft_pause_s cn30xx; - struct cvmx_gmxx_txx_soft_pause_s cn31xx; - struct cvmx_gmxx_txx_soft_pause_s cn38xx; - struct cvmx_gmxx_txx_soft_pause_s cn38xxp2; - struct cvmx_gmxx_txx_soft_pause_s cn50xx; - struct cvmx_gmxx_txx_soft_pause_s cn52xx; - struct cvmx_gmxx_txx_soft_pause_s cn52xxp1; - struct cvmx_gmxx_txx_soft_pause_s cn56xx; - struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; - struct cvmx_gmxx_txx_soft_pause_s cn58xx; - struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat0 { - uint64_t u64; - struct cvmx_gmxx_txx_stat0_s { - uint64_t xsdef:32; - uint64_t xscol:32; - } s; - struct cvmx_gmxx_txx_stat0_s cn30xx; - struct cvmx_gmxx_txx_stat0_s cn31xx; - struct cvmx_gmxx_txx_stat0_s cn38xx; - struct cvmx_gmxx_txx_stat0_s cn38xxp2; - struct cvmx_gmxx_txx_stat0_s cn50xx; - struct cvmx_gmxx_txx_stat0_s cn52xx; - struct cvmx_gmxx_txx_stat0_s cn52xxp1; - struct cvmx_gmxx_txx_stat0_s cn56xx; - struct cvmx_gmxx_txx_stat0_s cn56xxp1; - struct cvmx_gmxx_txx_stat0_s cn58xx; - struct cvmx_gmxx_txx_stat0_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat1 { - uint64_t u64; - struct cvmx_gmxx_txx_stat1_s { - uint64_t scol:32; - uint64_t mcol:32; - } s; - struct cvmx_gmxx_txx_stat1_s cn30xx; - struct cvmx_gmxx_txx_stat1_s cn31xx; - struct cvmx_gmxx_txx_stat1_s cn38xx; - struct cvmx_gmxx_txx_stat1_s cn38xxp2; - struct cvmx_gmxx_txx_stat1_s cn50xx; - struct cvmx_gmxx_txx_stat1_s cn52xx; - struct cvmx_gmxx_txx_stat1_s cn52xxp1; - struct cvmx_gmxx_txx_stat1_s cn56xx; - struct cvmx_gmxx_txx_stat1_s cn56xxp1; - struct cvmx_gmxx_txx_stat1_s cn58xx; - struct cvmx_gmxx_txx_stat1_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat2 { - uint64_t u64; - struct cvmx_gmxx_txx_stat2_s { - uint64_t reserved_48_63:16; - uint64_t octs:48; - } s; - struct cvmx_gmxx_txx_stat2_s cn30xx; - struct cvmx_gmxx_txx_stat2_s cn31xx; - struct cvmx_gmxx_txx_stat2_s cn38xx; - struct cvmx_gmxx_txx_stat2_s cn38xxp2; - struct cvmx_gmxx_txx_stat2_s cn50xx; - struct cvmx_gmxx_txx_stat2_s cn52xx; - struct cvmx_gmxx_txx_stat2_s cn52xxp1; - struct cvmx_gmxx_txx_stat2_s cn56xx; - struct cvmx_gmxx_txx_stat2_s cn56xxp1; - struct cvmx_gmxx_txx_stat2_s cn58xx; - struct cvmx_gmxx_txx_stat2_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat3 { - uint64_t u64; - struct cvmx_gmxx_txx_stat3_s { - uint64_t reserved_32_63:32; - uint64_t pkts:32; - } s; - struct cvmx_gmxx_txx_stat3_s cn30xx; - struct cvmx_gmxx_txx_stat3_s cn31xx; - struct cvmx_gmxx_txx_stat3_s cn38xx; - struct cvmx_gmxx_txx_stat3_s cn38xxp2; - struct cvmx_gmxx_txx_stat3_s cn50xx; - struct cvmx_gmxx_txx_stat3_s cn52xx; - struct cvmx_gmxx_txx_stat3_s cn52xxp1; - struct cvmx_gmxx_txx_stat3_s cn56xx; - struct cvmx_gmxx_txx_stat3_s cn56xxp1; - struct cvmx_gmxx_txx_stat3_s cn58xx; - struct cvmx_gmxx_txx_stat3_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat4 { - uint64_t u64; - struct cvmx_gmxx_txx_stat4_s { - uint64_t hist1:32; - uint64_t hist0:32; - } s; - struct cvmx_gmxx_txx_stat4_s cn30xx; - struct cvmx_gmxx_txx_stat4_s cn31xx; - struct cvmx_gmxx_txx_stat4_s cn38xx; - struct cvmx_gmxx_txx_stat4_s cn38xxp2; - struct cvmx_gmxx_txx_stat4_s cn50xx; - struct cvmx_gmxx_txx_stat4_s cn52xx; - struct cvmx_gmxx_txx_stat4_s cn52xxp1; - struct cvmx_gmxx_txx_stat4_s cn56xx; - struct cvmx_gmxx_txx_stat4_s cn56xxp1; - struct cvmx_gmxx_txx_stat4_s cn58xx; - struct cvmx_gmxx_txx_stat4_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat5 { - uint64_t u64; - struct cvmx_gmxx_txx_stat5_s { - uint64_t hist3:32; - uint64_t hist2:32; - } s; - struct cvmx_gmxx_txx_stat5_s cn30xx; - struct cvmx_gmxx_txx_stat5_s cn31xx; - struct cvmx_gmxx_txx_stat5_s cn38xx; - struct cvmx_gmxx_txx_stat5_s cn38xxp2; - struct cvmx_gmxx_txx_stat5_s cn50xx; - struct cvmx_gmxx_txx_stat5_s cn52xx; - struct cvmx_gmxx_txx_stat5_s cn52xxp1; - struct cvmx_gmxx_txx_stat5_s cn56xx; - struct cvmx_gmxx_txx_stat5_s cn56xxp1; - struct cvmx_gmxx_txx_stat5_s cn58xx; - struct cvmx_gmxx_txx_stat5_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat6 { - uint64_t u64; - struct cvmx_gmxx_txx_stat6_s { - uint64_t hist5:32; - uint64_t hist4:32; - } s; - struct cvmx_gmxx_txx_stat6_s cn30xx; - struct cvmx_gmxx_txx_stat6_s cn31xx; - struct cvmx_gmxx_txx_stat6_s cn38xx; - struct cvmx_gmxx_txx_stat6_s cn38xxp2; - struct cvmx_gmxx_txx_stat6_s cn50xx; - struct cvmx_gmxx_txx_stat6_s cn52xx; - struct cvmx_gmxx_txx_stat6_s cn52xxp1; - struct cvmx_gmxx_txx_stat6_s cn56xx; - struct cvmx_gmxx_txx_stat6_s cn56xxp1; - struct cvmx_gmxx_txx_stat6_s cn58xx; - struct cvmx_gmxx_txx_stat6_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat7 { - uint64_t u64; - struct cvmx_gmxx_txx_stat7_s { - uint64_t hist7:32; - uint64_t hist6:32; - } s; - struct cvmx_gmxx_txx_stat7_s cn30xx; - struct cvmx_gmxx_txx_stat7_s cn31xx; - struct cvmx_gmxx_txx_stat7_s cn38xx; - struct cvmx_gmxx_txx_stat7_s cn38xxp2; - struct cvmx_gmxx_txx_stat7_s cn50xx; - struct cvmx_gmxx_txx_stat7_s cn52xx; - struct cvmx_gmxx_txx_stat7_s cn52xxp1; - struct cvmx_gmxx_txx_stat7_s cn56xx; - struct cvmx_gmxx_txx_stat7_s cn56xxp1; - struct cvmx_gmxx_txx_stat7_s cn58xx; - struct cvmx_gmxx_txx_stat7_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat8 { - uint64_t u64; - struct cvmx_gmxx_txx_stat8_s { - uint64_t mcst:32; - uint64_t bcst:32; - } s; - struct cvmx_gmxx_txx_stat8_s cn30xx; - struct cvmx_gmxx_txx_stat8_s cn31xx; - struct cvmx_gmxx_txx_stat8_s cn38xx; - struct cvmx_gmxx_txx_stat8_s cn38xxp2; - struct cvmx_gmxx_txx_stat8_s cn50xx; - struct cvmx_gmxx_txx_stat8_s cn52xx; - struct cvmx_gmxx_txx_stat8_s cn52xxp1; - struct cvmx_gmxx_txx_stat8_s cn56xx; - struct cvmx_gmxx_txx_stat8_s cn56xxp1; - struct cvmx_gmxx_txx_stat8_s cn58xx; - struct cvmx_gmxx_txx_stat8_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stat9 { - uint64_t u64; - struct cvmx_gmxx_txx_stat9_s { - uint64_t undflw:32; - uint64_t ctl:32; - } s; - struct cvmx_gmxx_txx_stat9_s cn30xx; - struct cvmx_gmxx_txx_stat9_s cn31xx; - struct cvmx_gmxx_txx_stat9_s cn38xx; - struct cvmx_gmxx_txx_stat9_s cn38xxp2; - struct cvmx_gmxx_txx_stat9_s cn50xx; - struct cvmx_gmxx_txx_stat9_s cn52xx; - struct cvmx_gmxx_txx_stat9_s cn52xxp1; - struct cvmx_gmxx_txx_stat9_s cn56xx; - struct cvmx_gmxx_txx_stat9_s cn56xxp1; - struct cvmx_gmxx_txx_stat9_s cn58xx; - struct cvmx_gmxx_txx_stat9_s cn58xxp1; -}; - -union cvmx_gmxx_txx_stats_ctl { - uint64_t u64; - struct cvmx_gmxx_txx_stats_ctl_s { - uint64_t reserved_1_63:63; - uint64_t rd_clr:1; - } s; - struct cvmx_gmxx_txx_stats_ctl_s cn30xx; - struct cvmx_gmxx_txx_stats_ctl_s cn31xx; - struct cvmx_gmxx_txx_stats_ctl_s cn38xx; - struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2; - struct cvmx_gmxx_txx_stats_ctl_s cn50xx; - struct cvmx_gmxx_txx_stats_ctl_s cn52xx; - struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1; - struct cvmx_gmxx_txx_stats_ctl_s cn56xx; - struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; - struct cvmx_gmxx_txx_stats_ctl_s cn58xx; - struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; -}; - -union cvmx_gmxx_txx_thresh { - uint64_t u64; - struct cvmx_gmxx_txx_thresh_s { - uint64_t reserved_9_63:55; - uint64_t cnt:9; - } s; - struct cvmx_gmxx_txx_thresh_cn30xx { - uint64_t reserved_7_63:57; - uint64_t cnt:7; - } cn30xx; - struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; - struct cvmx_gmxx_txx_thresh_s cn38xx; - struct cvmx_gmxx_txx_thresh_s cn38xxp2; - struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; - struct cvmx_gmxx_txx_thresh_s cn52xx; - struct cvmx_gmxx_txx_thresh_s cn52xxp1; - struct cvmx_gmxx_txx_thresh_s cn56xx; - struct cvmx_gmxx_txx_thresh_s cn56xxp1; - struct cvmx_gmxx_txx_thresh_s cn58xx; - struct cvmx_gmxx_txx_thresh_s cn58xxp1; -}; - -union cvmx_gmxx_tx_bp { - uint64_t u64; - struct cvmx_gmxx_tx_bp_s { - uint64_t reserved_4_63:60; - uint64_t bp:4; - } s; - struct cvmx_gmxx_tx_bp_cn30xx { - uint64_t reserved_3_63:61; - uint64_t bp:3; - } cn30xx; - struct cvmx_gmxx_tx_bp_cn30xx cn31xx; - struct cvmx_gmxx_tx_bp_s cn38xx; - struct cvmx_gmxx_tx_bp_s cn38xxp2; - struct cvmx_gmxx_tx_bp_cn30xx cn50xx; - struct cvmx_gmxx_tx_bp_s cn52xx; - struct cvmx_gmxx_tx_bp_s cn52xxp1; - struct cvmx_gmxx_tx_bp_s cn56xx; - struct cvmx_gmxx_tx_bp_s cn56xxp1; - struct cvmx_gmxx_tx_bp_s cn58xx; - struct cvmx_gmxx_tx_bp_s cn58xxp1; -}; - -union cvmx_gmxx_tx_clk_mskx { - uint64_t u64; - struct cvmx_gmxx_tx_clk_mskx_s { - uint64_t reserved_1_63:63; - uint64_t msk:1; - } s; - struct cvmx_gmxx_tx_clk_mskx_s cn30xx; - struct cvmx_gmxx_tx_clk_mskx_s cn50xx; -}; - -union cvmx_gmxx_tx_col_attempt { - uint64_t u64; - struct cvmx_gmxx_tx_col_attempt_s { - uint64_t reserved_5_63:59; - uint64_t limit:5; - } s; - struct cvmx_gmxx_tx_col_attempt_s cn30xx; - struct cvmx_gmxx_tx_col_attempt_s cn31xx; - struct cvmx_gmxx_tx_col_attempt_s cn38xx; - struct cvmx_gmxx_tx_col_attempt_s cn38xxp2; - struct cvmx_gmxx_tx_col_attempt_s cn50xx; - struct cvmx_gmxx_tx_col_attempt_s cn52xx; - struct cvmx_gmxx_tx_col_attempt_s cn52xxp1; - struct cvmx_gmxx_tx_col_attempt_s cn56xx; - struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; - struct cvmx_gmxx_tx_col_attempt_s cn58xx; - struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; -}; - -union cvmx_gmxx_tx_corrupt { - uint64_t u64; - struct cvmx_gmxx_tx_corrupt_s { - uint64_t reserved_4_63:60; - uint64_t corrupt:4; - } s; - struct cvmx_gmxx_tx_corrupt_cn30xx { - uint64_t reserved_3_63:61; - uint64_t corrupt:3; - } cn30xx; - struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; - struct cvmx_gmxx_tx_corrupt_s cn38xx; - struct cvmx_gmxx_tx_corrupt_s cn38xxp2; - struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx; - struct cvmx_gmxx_tx_corrupt_s cn52xx; - struct cvmx_gmxx_tx_corrupt_s cn52xxp1; - struct cvmx_gmxx_tx_corrupt_s cn56xx; - struct cvmx_gmxx_tx_corrupt_s cn56xxp1; - struct cvmx_gmxx_tx_corrupt_s cn58xx; - struct cvmx_gmxx_tx_corrupt_s cn58xxp1; -}; - -union cvmx_gmxx_tx_hg2_reg1 { - uint64_t u64; - struct cvmx_gmxx_tx_hg2_reg1_s { - uint64_t reserved_16_63:48; - uint64_t tx_xof:16; - } s; - struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; - struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; - struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; -}; - -union cvmx_gmxx_tx_hg2_reg2 { - uint64_t u64; - struct cvmx_gmxx_tx_hg2_reg2_s { - uint64_t reserved_16_63:48; - uint64_t tx_xon:16; - } s; - struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; - struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; - struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; -}; - -union cvmx_gmxx_tx_ifg { - uint64_t u64; - struct cvmx_gmxx_tx_ifg_s { - uint64_t reserved_8_63:56; - uint64_t ifg2:4; - uint64_t ifg1:4; - } s; - struct cvmx_gmxx_tx_ifg_s cn30xx; - struct cvmx_gmxx_tx_ifg_s cn31xx; - struct cvmx_gmxx_tx_ifg_s cn38xx; - struct cvmx_gmxx_tx_ifg_s cn38xxp2; - struct cvmx_gmxx_tx_ifg_s cn50xx; - struct cvmx_gmxx_tx_ifg_s cn52xx; - struct cvmx_gmxx_tx_ifg_s cn52xxp1; - struct cvmx_gmxx_tx_ifg_s cn56xx; - struct cvmx_gmxx_tx_ifg_s cn56xxp1; - struct cvmx_gmxx_tx_ifg_s cn58xx; - struct cvmx_gmxx_tx_ifg_s cn58xxp1; -}; - -union cvmx_gmxx_tx_int_en { - uint64_t u64; - struct cvmx_gmxx_tx_int_en_s { - uint64_t reserved_20_63:44; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t ncb_nxa:1; - uint64_t pko_nxa:1; - } s; - struct cvmx_gmxx_tx_int_en_cn30xx { - uint64_t reserved_19_63:45; - uint64_t late_col:3; - uint64_t reserved_15_15:1; - uint64_t xsdef:3; - uint64_t reserved_11_11:1; - uint64_t xscol:3; - uint64_t reserved_5_7:3; - uint64_t undflw:3; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } cn30xx; - struct cvmx_gmxx_tx_int_en_cn31xx { - uint64_t reserved_15_63:49; - uint64_t xsdef:3; - uint64_t reserved_11_11:1; - uint64_t xscol:3; - uint64_t reserved_5_7:3; - uint64_t undflw:3; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } cn31xx; - struct cvmx_gmxx_tx_int_en_s cn38xx; - struct cvmx_gmxx_tx_int_en_cn38xxp2 { - uint64_t reserved_16_63:48; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t ncb_nxa:1; - uint64_t pko_nxa:1; - } cn38xxp2; - struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; - struct cvmx_gmxx_tx_int_en_cn52xx { - uint64_t reserved_20_63:44; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } cn52xx; - struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; - struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; - struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; - struct cvmx_gmxx_tx_int_en_s cn58xx; - struct cvmx_gmxx_tx_int_en_s cn58xxp1; -}; - -union cvmx_gmxx_tx_int_reg { - uint64_t u64; - struct cvmx_gmxx_tx_int_reg_s { - uint64_t reserved_20_63:44; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t ncb_nxa:1; - uint64_t pko_nxa:1; - } s; - struct cvmx_gmxx_tx_int_reg_cn30xx { - uint64_t reserved_19_63:45; - uint64_t late_col:3; - uint64_t reserved_15_15:1; - uint64_t xsdef:3; - uint64_t reserved_11_11:1; - uint64_t xscol:3; - uint64_t reserved_5_7:3; - uint64_t undflw:3; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } cn30xx; - struct cvmx_gmxx_tx_int_reg_cn31xx { - uint64_t reserved_15_63:49; - uint64_t xsdef:3; - uint64_t reserved_11_11:1; - uint64_t xscol:3; - uint64_t reserved_5_7:3; - uint64_t undflw:3; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } cn31xx; - struct cvmx_gmxx_tx_int_reg_s cn38xx; - struct cvmx_gmxx_tx_int_reg_cn38xxp2 { - uint64_t reserved_16_63:48; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t ncb_nxa:1; - uint64_t pko_nxa:1; - } cn38xxp2; - struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; - struct cvmx_gmxx_tx_int_reg_cn52xx { - uint64_t reserved_20_63:44; - uint64_t late_col:4; - uint64_t xsdef:4; - uint64_t xscol:4; - uint64_t reserved_6_7:2; - uint64_t undflw:4; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } cn52xx; - struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; - struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; - struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; - struct cvmx_gmxx_tx_int_reg_s cn58xx; - struct cvmx_gmxx_tx_int_reg_s cn58xxp1; -}; - -union cvmx_gmxx_tx_jam { - uint64_t u64; - struct cvmx_gmxx_tx_jam_s { - uint64_t reserved_8_63:56; - uint64_t jam:8; - } s; - struct cvmx_gmxx_tx_jam_s cn30xx; - struct cvmx_gmxx_tx_jam_s cn31xx; - struct cvmx_gmxx_tx_jam_s cn38xx; - struct cvmx_gmxx_tx_jam_s cn38xxp2; - struct cvmx_gmxx_tx_jam_s cn50xx; - struct cvmx_gmxx_tx_jam_s cn52xx; - struct cvmx_gmxx_tx_jam_s cn52xxp1; - struct cvmx_gmxx_tx_jam_s cn56xx; - struct cvmx_gmxx_tx_jam_s cn56xxp1; - struct cvmx_gmxx_tx_jam_s cn58xx; - struct cvmx_gmxx_tx_jam_s cn58xxp1; -}; - -union cvmx_gmxx_tx_lfsr { - uint64_t u64; - struct cvmx_gmxx_tx_lfsr_s { - uint64_t reserved_16_63:48; - uint64_t lfsr:16; - } s; - struct cvmx_gmxx_tx_lfsr_s cn30xx; - struct cvmx_gmxx_tx_lfsr_s cn31xx; - struct cvmx_gmxx_tx_lfsr_s cn38xx; - struct cvmx_gmxx_tx_lfsr_s cn38xxp2; - struct cvmx_gmxx_tx_lfsr_s cn50xx; - struct cvmx_gmxx_tx_lfsr_s cn52xx; - struct cvmx_gmxx_tx_lfsr_s cn52xxp1; - struct cvmx_gmxx_tx_lfsr_s cn56xx; - struct cvmx_gmxx_tx_lfsr_s cn56xxp1; - struct cvmx_gmxx_tx_lfsr_s cn58xx; - struct cvmx_gmxx_tx_lfsr_s cn58xxp1; -}; - -union cvmx_gmxx_tx_ovr_bp { - uint64_t u64; - struct cvmx_gmxx_tx_ovr_bp_s { - uint64_t reserved_48_63:16; - uint64_t tx_prt_bp:16; - uint64_t reserved_12_31:20; - uint64_t en:4; - uint64_t bp:4; - uint64_t ign_full:4; - } s; - struct cvmx_gmxx_tx_ovr_bp_cn30xx { - uint64_t reserved_11_63:53; - uint64_t en:3; - uint64_t reserved_7_7:1; - uint64_t bp:3; - uint64_t reserved_3_3:1; - uint64_t ign_full:3; - } cn30xx; - struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; - struct cvmx_gmxx_tx_ovr_bp_cn38xx { - uint64_t reserved_12_63:52; - uint64_t en:4; - uint64_t bp:4; - uint64_t ign_full:4; - } cn38xx; - struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; - struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; - struct cvmx_gmxx_tx_ovr_bp_s cn52xx; - struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1; - struct cvmx_gmxx_tx_ovr_bp_s cn56xx; - struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; - struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; - struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; -}; - -union cvmx_gmxx_tx_pause_pkt_dmac { - uint64_t u64; - struct cvmx_gmxx_tx_pause_pkt_dmac_s { - uint64_t reserved_48_63:16; - uint64_t dmac:48; - } s; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; - struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; -}; - -union cvmx_gmxx_tx_pause_pkt_type { - uint64_t u64; - struct cvmx_gmxx_tx_pause_pkt_type_s { - uint64_t reserved_16_63:48; - uint64_t type:16; - } s; - struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2; - struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1; - struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; - struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; - struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; -}; - -union cvmx_gmxx_tx_prts { - uint64_t u64; - struct cvmx_gmxx_tx_prts_s { - uint64_t reserved_5_63:59; - uint64_t prts:5; - } s; - struct cvmx_gmxx_tx_prts_s cn30xx; - struct cvmx_gmxx_tx_prts_s cn31xx; - struct cvmx_gmxx_tx_prts_s cn38xx; - struct cvmx_gmxx_tx_prts_s cn38xxp2; - struct cvmx_gmxx_tx_prts_s cn50xx; - struct cvmx_gmxx_tx_prts_s cn52xx; - struct cvmx_gmxx_tx_prts_s cn52xxp1; - struct cvmx_gmxx_tx_prts_s cn56xx; - struct cvmx_gmxx_tx_prts_s cn56xxp1; - struct cvmx_gmxx_tx_prts_s cn58xx; - struct cvmx_gmxx_tx_prts_s cn58xxp1; -}; - -union cvmx_gmxx_tx_spi_ctl { - uint64_t u64; - struct cvmx_gmxx_tx_spi_ctl_s { - uint64_t reserved_2_63:62; - uint64_t tpa_clr:1; - uint64_t cont_pkt:1; - } s; - struct cvmx_gmxx_tx_spi_ctl_s cn38xx; - struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; - struct cvmx_gmxx_tx_spi_ctl_s cn58xx; - struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1; -}; - -union cvmx_gmxx_tx_spi_drain { - uint64_t u64; - struct cvmx_gmxx_tx_spi_drain_s { - uint64_t reserved_16_63:48; - uint64_t drain:16; - } s; - struct cvmx_gmxx_tx_spi_drain_s cn38xx; - struct cvmx_gmxx_tx_spi_drain_s cn58xx; - struct cvmx_gmxx_tx_spi_drain_s cn58xxp1; -}; - -union cvmx_gmxx_tx_spi_max { - uint64_t u64; - struct cvmx_gmxx_tx_spi_max_s { - uint64_t reserved_23_63:41; - uint64_t slice:7; - uint64_t max2:8; - uint64_t max1:8; - } s; - struct cvmx_gmxx_tx_spi_max_cn38xx { - uint64_t reserved_16_63:48; - uint64_t max2:8; - uint64_t max1:8; - } cn38xx; - struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; - struct cvmx_gmxx_tx_spi_max_s cn58xx; - struct cvmx_gmxx_tx_spi_max_s cn58xxp1; -}; - -union cvmx_gmxx_tx_spi_roundx { - uint64_t u64; - struct cvmx_gmxx_tx_spi_roundx_s { - uint64_t reserved_16_63:48; - uint64_t round:16; - } s; - struct cvmx_gmxx_tx_spi_roundx_s cn58xx; - struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; -}; - -union cvmx_gmxx_tx_spi_thresh { - uint64_t u64; - struct cvmx_gmxx_tx_spi_thresh_s { - uint64_t reserved_6_63:58; - uint64_t thresh:6; - } s; - struct cvmx_gmxx_tx_spi_thresh_s cn38xx; - struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; - struct cvmx_gmxx_tx_spi_thresh_s cn58xx; - struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1; -}; - -union cvmx_gmxx_tx_xaui_ctl { - uint64_t u64; - struct cvmx_gmxx_tx_xaui_ctl_s { - uint64_t reserved_11_63:53; - uint64_t hg_pause_hgi:2; - uint64_t hg_en:1; - uint64_t reserved_7_7:1; - uint64_t ls_byp:1; - uint64_t ls:2; - uint64_t reserved_2_3:2; - uint64_t uni_en:1; - uint64_t dic_en:1; - } s; - struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; - struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; - struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; - struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; -}; - -union cvmx_gmxx_xaui_ext_loopback { - uint64_t u64; - struct cvmx_gmxx_xaui_ext_loopback_s { - uint64_t reserved_5_63:59; - uint64_t en:1; - uint64_t thresh:4; - } s; - struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; - struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; - struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; - struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/drivers/staging/octeon/cvmx-helper-board.c deleted file mode 100644 index 57d35dc63ddb..000000000000 --- a/drivers/staging/octeon/cvmx-helper-board.c +++ /dev/null @@ -1,695 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Helper functions to abstract board specific data about - * network ports from the rest of the cvmx-helper files. - */ - -#include -#include - -#include "cvmx-config.h" - -#include "cvmx-mdio.h" - -#include "cvmx-helper.h" -#include "cvmx-helper-util.h" -#include "cvmx-helper-board.h" - -#include "cvmx-gmxx-defs.h" -#include "cvmx-asxx-defs.h" - -/** - * cvmx_override_board_link_get(int ipd_port) is a function - * pointer. It is meant to allow customization of the process of - * talking to a PHY to determine link speed. It is called every - * time a PHY must be polled for link status. Users should set - * this pointer to a function before calling any cvmx-helper - * operations. - */ -cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) = - NULL; - -/** - * Return the MII PHY address associated with the given IPD - * port. A result of -1 means there isn't a MII capable PHY - * connected to this port. On chips supporting multiple MII - * busses the bus number is encoded in bits <15:8>. - * - * This function must be modified for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It replies on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @ipd_port: Octeon IPD port to get the MII address for. - * - * Returns MII PHY address and bus number or -1. - */ -int cvmx_helper_board_get_mii_address(int ipd_port) -{ - switch (cvmx_sysinfo_get()->board_type) { - case CVMX_BOARD_TYPE_SIM: - /* Simulator doesn't have MII */ - return -1; - case CVMX_BOARD_TYPE_EBT3000: - case CVMX_BOARD_TYPE_EBT5800: - case CVMX_BOARD_TYPE_THUNDER: - case CVMX_BOARD_TYPE_NICPRO2: - /* Interface 0 is SPI4, interface 1 is RGMII */ - if ((ipd_port >= 16) && (ipd_port < 20)) - return ipd_port - 16; - else - return -1; - case CVMX_BOARD_TYPE_KODAMA: - case CVMX_BOARD_TYPE_EBH3100: - case CVMX_BOARD_TYPE_HIKARI: - case CVMX_BOARD_TYPE_CN3010_EVB_HS5: - case CVMX_BOARD_TYPE_CN3005_EVB_HS5: - case CVMX_BOARD_TYPE_CN3020_EVB_HS5: - /* - * Port 0 is WAN connected to a PHY, Port 1 is GMII - * connected to a switch - */ - if (ipd_port == 0) - return 4; - else if (ipd_port == 1) - return 9; - else - return -1; - case CVMX_BOARD_TYPE_NAC38: - /* Board has 8 RGMII ports PHYs are 0-7 */ - if ((ipd_port >= 0) && (ipd_port < 4)) - return ipd_port; - else if ((ipd_port >= 16) && (ipd_port < 20)) - return ipd_port - 16 + 4; - else - return -1; - case CVMX_BOARD_TYPE_EBH3000: - /* Board has dual SPI4 and no PHYs */ - return -1; - case CVMX_BOARD_TYPE_EBH5200: - case CVMX_BOARD_TYPE_EBH5201: - case CVMX_BOARD_TYPE_EBT5200: - /* - * Board has 4 SGMII ports. The PHYs start right after the MII - * ports MII0 = 0, MII1 = 1, SGMII = 2-5. - */ - if ((ipd_port >= 0) && (ipd_port < 4)) - return ipd_port + 2; - else - return -1; - case CVMX_BOARD_TYPE_EBH5600: - case CVMX_BOARD_TYPE_EBH5601: - case CVMX_BOARD_TYPE_EBH5610: - /* - * Board has 8 SGMII ports. 4 connect out, two connect - * to a switch, and 2 loop to each other - */ - if ((ipd_port >= 0) && (ipd_port < 4)) - return ipd_port + 1; - else - return -1; - case CVMX_BOARD_TYPE_CUST_NB5: - if (ipd_port == 2) - return 4; - else - return -1; - case CVMX_BOARD_TYPE_NIC_XLE_4G: - /* Board has 4 SGMII ports. connected QLM3(interface 1) */ - if ((ipd_port >= 16) && (ipd_port < 20)) - return ipd_port - 16 + 1; - else - return -1; - case CVMX_BOARD_TYPE_BBGW_REF: - /* - * No PHYs are connected to Octeon, everything is - * through switch. - */ - return -1; - - case CVMX_BOARD_TYPE_CUST_WSX16: - if (ipd_port >= 0 && ipd_port <= 3) - return ipd_port; - else if (ipd_port >= 16 && ipd_port <= 19) - return ipd_port - 16 + 4; - else - return -1; - } - - /* Some unknown board. Somebody forgot to update this function... */ - cvmx_dprintf - ("cvmx_helper_board_get_mii_address: Unknown board type %d\n", - cvmx_sysinfo_get()->board_type); - return -1; -} - -/** - * This function is the board specific method of determining an - * ethernet ports link speed. Most Octeon boards have Marvell PHYs - * and are handled by the fall through case. This function must be - * updated for boards that don't have the normal Marvell PHYs. - * - * This function must be modified for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It relies on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @ipd_port: IPD input port associated with the port we want to get link - * status for. - * - * Returns The ports link status. If the link isn't fully resolved, this must - * return zero. - */ -cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) -{ - cvmx_helper_link_info_t result; - int phy_addr; - int is_broadcom_phy = 0; - - /* Give the user a chance to override the processing of this function */ - if (cvmx_override_board_link_get) - return cvmx_override_board_link_get(ipd_port); - - /* Unless we fix it later, all links are defaulted to down */ - result.u64 = 0; - - /* - * This switch statement should handle all ports that either don't use - * Marvell PHYS, or don't support in-band status. - */ - switch (cvmx_sysinfo_get()->board_type) { - case CVMX_BOARD_TYPE_SIM: - /* The simulator gives you a simulated 1Gbps full duplex link */ - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - case CVMX_BOARD_TYPE_EBH3100: - case CVMX_BOARD_TYPE_CN3010_EVB_HS5: - case CVMX_BOARD_TYPE_CN3005_EVB_HS5: - case CVMX_BOARD_TYPE_CN3020_EVB_HS5: - /* Port 1 on these boards is always Gigabit */ - if (ipd_port == 1) { - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - } - /* Fall through to the generic code below */ - break; - case CVMX_BOARD_TYPE_CUST_NB5: - /* Port 1 on these boards is always Gigabit */ - if (ipd_port == 1) { - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - } else /* The other port uses a broadcom PHY */ - is_broadcom_phy = 1; - break; - case CVMX_BOARD_TYPE_BBGW_REF: - /* Port 1 on these boards is always Gigabit */ - if (ipd_port == 2) { - /* Port 2 is not hooked up */ - result.u64 = 0; - return result; - } else { - /* Ports 0 and 1 connect to the switch */ - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - } - break; - } - - phy_addr = cvmx_helper_board_get_mii_address(ipd_port); - if (phy_addr != -1) { - if (is_broadcom_phy) { - /* - * Below we are going to read SMI/MDIO - * register 0x19 which works on Broadcom - * parts - */ - int phy_status = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - 0x19); - switch ((phy_status >> 8) & 0x7) { - case 0: - result.u64 = 0; - break; - case 1: - result.s.link_up = 1; - result.s.full_duplex = 0; - result.s.speed = 10; - break; - case 2: - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 10; - break; - case 3: - result.s.link_up = 1; - result.s.full_duplex = 0; - result.s.speed = 100; - break; - case 4: - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 100; - break; - case 5: - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 100; - break; - case 6: - result.s.link_up = 1; - result.s.full_duplex = 0; - result.s.speed = 1000; - break; - case 7: - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - break; - } - } else { - /* - * This code assumes we are using a Marvell - * Gigabit PHY. All the speed information can - * be read from register 17 in one - * go. Somebody using a different PHY will - * need to handle it above in the board - * specific area. - */ - int phy_status = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17); - - /* - * If the resolve bit 11 isn't set, see if - * autoneg is turned off (bit 12, reg 0). The - * resolve bit doesn't get set properly when - * autoneg is off, so force it. - */ - if ((phy_status & (1 << 11)) == 0) { - int auto_status = - cvmx_mdio_read(phy_addr >> 8, - phy_addr & 0xff, 0); - if ((auto_status & (1 << 12)) == 0) - phy_status |= 1 << 11; - } - - /* - * Only return a link if the PHY has finished - * auto negotiation and set the resolved bit - * (bit 11) - */ - if (phy_status & (1 << 11)) { - result.s.link_up = 1; - result.s.full_duplex = ((phy_status >> 13) & 1); - switch ((phy_status >> 14) & 3) { - case 0: /* 10 Mbps */ - result.s.speed = 10; - break; - case 1: /* 100 Mbps */ - result.s.speed = 100; - break; - case 2: /* 1 Gbps */ - result.s.speed = 1000; - break; - case 3: /* Illegal */ - result.u64 = 0; - break; - } - } - } - } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) - || OCTEON_IS_MODEL(OCTEON_CN58XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) { - /* - * We don't have a PHY address, so attempt to use - * in-band status. It is really important that boards - * not supporting in-band status never get - * here. Reading broken in-band status tends to do bad - * things - */ - union cvmx_gmxx_rxx_rx_inbnd inband_status; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - inband_status.u64 = - cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); - - result.s.link_up = inband_status.s.status; - result.s.full_duplex = inband_status.s.duplex; - switch (inband_status.s.speed) { - case 0: /* 10 Mbps */ - result.s.speed = 10; - break; - case 1: /* 100 Mbps */ - result.s.speed = 100; - break; - case 2: /* 1 Gbps */ - result.s.speed = 1000; - break; - case 3: /* Illegal */ - result.u64 = 0; - break; - } - } else { - /* - * We don't have a PHY address and we don't have - * in-band status. There is no way to determine the - * link speed. Return down assuming this port isn't - * wired - */ - result.u64 = 0; - } - - /* If link is down, return all fields as zero. */ - if (!result.s.link_up) - result.u64 = 0; - - return result; -} - -/** - * This function as a board specific method of changing the PHY - * speed, duplex, and auto-negotiation. This programs the PHY and - * not Octeon. This can be used to force Octeon's links to - * specific settings. - * - * @phy_addr: The address of the PHY to program - * @enable_autoneg: - * Non zero if you want to enable auto-negotiation. - * @link_info: Link speed to program. If the speed is zero and auto-negotiation - * is enabled, all possible negotiation speeds are advertised. - * - * Returns Zero on success, negative on failure - */ -int cvmx_helper_board_link_set_phy(int phy_addr, - cvmx_helper_board_set_phy_link_flags_types_t - link_flags, - cvmx_helper_link_info_t link_info) -{ - - /* Set the flow control settings based on link_flags */ - if ((link_flags & set_phy_link_flags_flow_control_mask) != - set_phy_link_flags_flow_control_dont_touch) { - cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; - reg_autoneg_adver.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_AUTONEG_ADVER); - reg_autoneg_adver.s.asymmetric_pause = - (link_flags & set_phy_link_flags_flow_control_mask) == - set_phy_link_flags_flow_control_enable; - reg_autoneg_adver.s.pause = - (link_flags & set_phy_link_flags_flow_control_mask) == - set_phy_link_flags_flow_control_enable; - cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_AUTONEG_ADVER, - reg_autoneg_adver.u16); - } - - /* If speed isn't set and autoneg is on advertise all supported modes */ - if ((link_flags & set_phy_link_flags_autoneg) - && (link_info.s.speed == 0)) { - cvmx_mdio_phy_reg_control_t reg_control; - cvmx_mdio_phy_reg_status_t reg_status; - cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; - cvmx_mdio_phy_reg_extended_status_t reg_extended_status; - cvmx_mdio_phy_reg_control_1000_t reg_control_1000; - - reg_status.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_STATUS); - reg_autoneg_adver.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_AUTONEG_ADVER); - reg_autoneg_adver.s.advert_100base_t4 = - reg_status.s.capable_100base_t4; - reg_autoneg_adver.s.advert_10base_tx_full = - reg_status.s.capable_10_full; - reg_autoneg_adver.s.advert_10base_tx_half = - reg_status.s.capable_10_half; - reg_autoneg_adver.s.advert_100base_tx_full = - reg_status.s.capable_100base_x_full; - reg_autoneg_adver.s.advert_100base_tx_half = - reg_status.s.capable_100base_x_half; - cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_AUTONEG_ADVER, - reg_autoneg_adver.u16); - if (reg_status.s.capable_extended_status) { - reg_extended_status.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_EXTENDED_STATUS); - reg_control_1000.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL_1000); - reg_control_1000.s.advert_1000base_t_full = - reg_extended_status.s.capable_1000base_t_full; - reg_control_1000.s.advert_1000base_t_half = - reg_extended_status.s.capable_1000base_t_half; - cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL_1000, - reg_control_1000.u16); - } - reg_control.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL); - reg_control.s.autoneg_enable = 1; - reg_control.s.restart_autoneg = 1; - cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); - } else if ((link_flags & set_phy_link_flags_autoneg)) { - cvmx_mdio_phy_reg_control_t reg_control; - cvmx_mdio_phy_reg_status_t reg_status; - cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; - cvmx_mdio_phy_reg_extended_status_t reg_extended_status; - cvmx_mdio_phy_reg_control_1000_t reg_control_1000; - - reg_status.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_STATUS); - reg_autoneg_adver.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_AUTONEG_ADVER); - reg_autoneg_adver.s.advert_100base_t4 = 0; - reg_autoneg_adver.s.advert_10base_tx_full = 0; - reg_autoneg_adver.s.advert_10base_tx_half = 0; - reg_autoneg_adver.s.advert_100base_tx_full = 0; - reg_autoneg_adver.s.advert_100base_tx_half = 0; - if (reg_status.s.capable_extended_status) { - reg_extended_status.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_EXTENDED_STATUS); - reg_control_1000.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL_1000); - reg_control_1000.s.advert_1000base_t_full = 0; - reg_control_1000.s.advert_1000base_t_half = 0; - } - switch (link_info.s.speed) { - case 10: - reg_autoneg_adver.s.advert_10base_tx_full = - link_info.s.full_duplex; - reg_autoneg_adver.s.advert_10base_tx_half = - !link_info.s.full_duplex; - break; - case 100: - reg_autoneg_adver.s.advert_100base_tx_full = - link_info.s.full_duplex; - reg_autoneg_adver.s.advert_100base_tx_half = - !link_info.s.full_duplex; - break; - case 1000: - reg_control_1000.s.advert_1000base_t_full = - link_info.s.full_duplex; - reg_control_1000.s.advert_1000base_t_half = - !link_info.s.full_duplex; - break; - } - cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_AUTONEG_ADVER, - reg_autoneg_adver.u16); - if (reg_status.s.capable_extended_status) - cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL_1000, - reg_control_1000.u16); - reg_control.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL); - reg_control.s.autoneg_enable = 1; - reg_control.s.restart_autoneg = 1; - cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); - } else { - cvmx_mdio_phy_reg_control_t reg_control; - reg_control.u16 = - cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL); - reg_control.s.autoneg_enable = 0; - reg_control.s.restart_autoneg = 1; - reg_control.s.duplex = link_info.s.full_duplex; - if (link_info.s.speed == 1000) { - reg_control.s.speed_msb = 1; - reg_control.s.speed_lsb = 0; - } else if (link_info.s.speed == 100) { - reg_control.s.speed_msb = 0; - reg_control.s.speed_lsb = 1; - } else if (link_info.s.speed == 10) { - reg_control.s.speed_msb = 0; - reg_control.s.speed_lsb = 0; - } - cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, - CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); - } - return 0; -} - -/** - * This function is called by cvmx_helper_interface_probe() after it - * determines the number of ports Octeon can support on a specific - * interface. This function is the per board location to override - * this value. It is called with the number of ports Octeon might - * support and should return the number of actual ports on the - * board. - * - * This function must be modifed for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It relys on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @interface: Interface to probe - * @supported_ports: - * Number of ports Octeon supports. - * - * Returns Number of ports the actual board supports. Many times this will - * simple be "support_ports". - */ -int __cvmx_helper_board_interface_probe(int interface, int supported_ports) -{ - switch (cvmx_sysinfo_get()->board_type) { - case CVMX_BOARD_TYPE_CN3005_EVB_HS5: - if (interface == 0) - return 2; - break; - case CVMX_BOARD_TYPE_BBGW_REF: - if (interface == 0) - return 2; - break; - case CVMX_BOARD_TYPE_NIC_XLE_4G: - if (interface == 0) - return 0; - break; - /* The 2nd interface on the EBH5600 is connected to the Marvel switch, - which we don't support. Disable ports connected to it */ - case CVMX_BOARD_TYPE_EBH5600: - if (interface == 1) - return 0; - break; - } - return supported_ports; -} - -/** - * Enable packet input/output from the hardware. This function is - * called after by cvmx_helper_packet_hardware_enable() to - * perform board specific initialization. For most boards - * nothing is needed. - * - * @interface: Interface to enable - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_board_hardware_enable(int interface) -{ - if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) { - if (interface == 0) { - /* Different config for switch port */ - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); - /* - * Boards with gigabit WAN ports need a - * different setting that is compatible with - * 100 Mbit settings - */ - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), - 0xc); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), - 0xc); - } - } else if (cvmx_sysinfo_get()->board_type == - CVMX_BOARD_TYPE_CN3010_EVB_HS5) { - /* - * Broadcom PHYs require differnet ASX - * clocks. Unfortunately many boards don't define a - * new board Id and simply mangle the - * CN3010_EVB_HS5 - */ - if (interface == 0) { - /* - * Some boards use a hacked up bootloader that - * identifies them as CN3010_EVB_HS5 - * evaluation boards. This leads to all kinds - * of configuration problems. Detect one - * case, and print warning, while trying to do - * the right thing. - */ - int phy_addr = cvmx_helper_board_get_mii_address(0); - if (phy_addr != -1) { - int phy_identifier = - cvmx_mdio_read(phy_addr >> 8, - phy_addr & 0xff, 0x2); - /* Is it a Broadcom PHY? */ - if (phy_identifier == 0x0143) { - cvmx_dprintf("\n"); - cvmx_dprintf("ERROR:\n"); - cvmx_dprintf - ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n"); - cvmx_dprintf - ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n"); - cvmx_dprintf - ("ERROR: All boards require a unique board type to identify them.\n"); - cvmx_dprintf("ERROR:\n"); - cvmx_dprintf("\n"); - cvmx_wait(1000000000); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX - (0, interface), 5); - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX - (0, interface), 5); - } - } - } - } - return 0; -} diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/drivers/staging/octeon/cvmx-helper-board.h deleted file mode 100644 index b465bec43553..000000000000 --- a/drivers/staging/octeon/cvmx-helper-board.h +++ /dev/null @@ -1,151 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Helper functions to abstract board specific data about - * network ports from the rest of the cvmx-helper files. - * - */ -#ifndef __CVMX_HELPER_BOARD_H__ -#define __CVMX_HELPER_BOARD_H__ - -#include "cvmx-helper.h" - -typedef enum { - set_phy_link_flags_autoneg = 0x1, - set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, - set_phy_link_flags_flow_control_enable = 0x1 << 1, - set_phy_link_flags_flow_control_disable = 0x2 << 1, - set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */ -} cvmx_helper_board_set_phy_link_flags_types_t; - -/** - * cvmx_override_board_link_get(int ipd_port) is a function - * pointer. It is meant to allow customization of the process of - * talking to a PHY to determine link speed. It is called every - * time a PHY must be polled for link status. Users should set - * this pointer to a function before calling any cvmx-helper - * operations. - */ -extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port); - -/** - * Return the MII PHY address associated with the given IPD - * port. A result of -1 means there isn't a MII capable PHY - * connected to this port. On chips supporting multiple MII - * busses the bus number is encoded in bits <15:8>. - * - * This function must be modifed for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It relys on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @ipd_port: Octeon IPD port to get the MII address for. - * - * Returns MII PHY address and bus number or -1. - */ -extern int cvmx_helper_board_get_mii_address(int ipd_port); - -/** - * This function as a board specific method of changing the PHY - * speed, duplex, and autonegotiation. This programs the PHY and - * not Octeon. This can be used to force Octeon's links to - * specific settings. - * - * @phy_addr: The address of the PHY to program - * @link_flags: - * Flags to control autonegotiation. Bit 0 is autonegotiation - * enable/disable to maintain backware compatibility. - * @link_info: Link speed to program. If the speed is zero and autonegotiation - * is enabled, all possible negotiation speeds are advertised. - * - * Returns Zero on success, negative on failure - */ -int cvmx_helper_board_link_set_phy(int phy_addr, - cvmx_helper_board_set_phy_link_flags_types_t - link_flags, - cvmx_helper_link_info_t link_info); - -/** - * This function is the board specific method of determining an - * ethernet ports link speed. Most Octeon boards have Marvell PHYs - * and are handled by the fall through case. This function must be - * updated for boards that don't have the normal Marvell PHYs. - * - * This function must be modifed for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It relys on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @ipd_port: IPD input port associated with the port we want to get link - * status for. - * - * Returns The ports link status. If the link isn't fully resolved, this must - * return zero. - */ -extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); - -/** - * This function is called by cvmx_helper_interface_probe() after it - * determines the number of ports Octeon can support on a specific - * interface. This function is the per board location to override - * this value. It is called with the number of ports Octeon might - * support and should return the number of actual ports on the - * board. - * - * This function must be modifed for every new Octeon board. - * Internally it uses switch statements based on the cvmx_sysinfo - * data to determine board types and revisions. It relys on the - * fact that every Octeon board receives a unique board type - * enumeration from the bootloader. - * - * @interface: Interface to probe - * @supported_ports: - * Number of ports Octeon supports. - * - * Returns Number of ports the actual board supports. Many times this will - * simple be "support_ports". - */ -extern int __cvmx_helper_board_interface_probe(int interface, - int supported_ports); - -/** - * Enable packet input/output from the hardware. This function is - * called after by cvmx_helper_packet_hardware_enable() to - * perform board specific initialization. For most boards - * nothing is needed. - * - * @interface: Interface to enable - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_board_hardware_enable(int interface); - -#endif /* __CVMX_HELPER_BOARD_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/drivers/staging/octeon/cvmx-helper-fpa.c deleted file mode 100644 index c239e5f4ab9a..000000000000 --- a/drivers/staging/octeon/cvmx-helper-fpa.c +++ /dev/null @@ -1,243 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Helper functions for FPA setup. - * - */ -#include "executive-config.h" -#include "cvmx-config.h" -#include "cvmx.h" -#include "cvmx-bootmem.h" -#include "cvmx-fpa.h" -#include "cvmx-helper-fpa.h" - -/** - * Allocate memory for and initialize a single FPA pool. - * - * @pool: Pool to initialize - * @buffer_size: Size of buffers to allocate in bytes - * @buffers: Number of buffers to put in the pool. Zero is allowed - * @name: String name of the pool for debugging purposes - * Returns Zero on success, non-zero on failure - */ -static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size, - uint64_t buffers, const char *name) -{ - uint64_t current_num; - void *memory; - uint64_t align = CVMX_CACHE_LINE_SIZE; - - /* - * Align the allocation so that power of 2 size buffers are - * naturally aligned. - */ - while (align < buffer_size) - align = align << 1; - - if (buffers == 0) - return 0; - - current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool)); - if (current_num) { - cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. " - "Skipping setup.\n", - pool, name, (unsigned long long)current_num); - return 0; - } - - memory = cvmx_bootmem_alloc(buffer_size * buffers, align); - if (memory == NULL) { - cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n", - pool, name); - return -1; - } - cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers); - return 0; -} - -/** - * Allocate memory and initialize the FPA pools using memory - * from cvmx-bootmem. Specifying zero for the number of - * buffers will cause that FPA pool to not be setup. This is - * useful if you aren't using some of the hardware and want - * to save memory. Use cvmx_helper_initialize_fpa instead of - * this function directly. - * - * @pip_pool: Should always be CVMX_FPA_PACKET_POOL - * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE - * @pip_buffers: - * Number of packet buffers. - * @wqe_pool: Should always be CVMX_FPA_WQE_POOL - * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE - * @wqe_entries: - * Number of work queue entries - * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL - * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - * @pko_buffers: - * PKO Command buffers. You should at minimum have two per - * each PKO queue. - * @tim_pool: Should always be CVMX_FPA_TIMER_POOL - * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE - * @tim_buffers: - * TIM ring buffer command queues. At least two per timer bucket - * is recommened. - * @dfa_pool: Should always be CVMX_FPA_DFA_POOL - * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE - * @dfa_buffers: - * DFA command buffer. A relatively small (32 for example) - * number should work. - * Returns Zero on success, non-zero if out of memory - */ -static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size, - int pip_buffers, int wqe_pool, - int wqe_size, int wqe_entries, - int pko_pool, int pko_size, - int pko_buffers, int tim_pool, - int tim_size, int tim_buffers, - int dfa_pool, int dfa_size, - int dfa_buffers) -{ - int status; - - cvmx_fpa_enable(); - - if ((pip_buffers > 0) && (pip_buffers <= 64)) - cvmx_dprintf - ("Warning: %d packet buffers may not be enough for hardware" - " prefetch. 65 or more is recommended.\n", pip_buffers); - - if (pip_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size, - pip_buffers, - "Packet Buffers"); - if (status) - return status; - } - - if (wqe_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size, - wqe_entries, - "Work Queue Entries"); - if (status) - return status; - } - - if (pko_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size, - pko_buffers, - "PKO Command Buffers"); - if (status) - return status; - } - - if (tim_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size, - tim_buffers, - "TIM Command Buffers"); - if (status) - return status; - } - - if (dfa_pool >= 0) { - status = - __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size, - dfa_buffers, - "DFA Command Buffers"); - if (status) - return status; - } - - return 0; -} - -/** - * Allocate memory and initialize the FPA pools using memory - * from cvmx-bootmem. Sizes of each element in the pools is - * controlled by the cvmx-config.h header file. Specifying - * zero for any parameter will cause that FPA pool to not be - * setup. This is useful if you aren't using some of the - * hardware and want to save memory. - * - * @packet_buffers: - * Number of packet buffers to allocate - * @work_queue_entries: - * Number of work queue entries - * @pko_buffers: - * PKO Command buffers. You should at minimum have two per - * each PKO queue. - * @tim_buffers: - * TIM ring buffer command queues. At least two per timer bucket - * is recommened. - * @dfa_buffers: - * DFA command buffer. A relatively small (32 for example) - * number should work. - * Returns Zero on success, non-zero if out of memory - */ -int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries, - int pko_buffers, int tim_buffers, - int dfa_buffers) -{ -#ifndef CVMX_FPA_PACKET_POOL -#define CVMX_FPA_PACKET_POOL -1 -#define CVMX_FPA_PACKET_POOL_SIZE 0 -#endif -#ifndef CVMX_FPA_WQE_POOL -#define CVMX_FPA_WQE_POOL -1 -#define CVMX_FPA_WQE_POOL_SIZE 0 -#endif -#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL -#define CVMX_FPA_OUTPUT_BUFFER_POOL -1 -#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0 -#endif -#ifndef CVMX_FPA_TIMER_POOL -#define CVMX_FPA_TIMER_POOL -1 -#define CVMX_FPA_TIMER_POOL_SIZE 0 -#endif -#ifndef CVMX_FPA_DFA_POOL -#define CVMX_FPA_DFA_POOL -1 -#define CVMX_FPA_DFA_POOL_SIZE 0 -#endif - return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL, - CVMX_FPA_PACKET_POOL_SIZE, - packet_buffers, CVMX_FPA_WQE_POOL, - CVMX_FPA_WQE_POOL_SIZE, - work_queue_entries, - CVMX_FPA_OUTPUT_BUFFER_POOL, - CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, - pko_buffers, CVMX_FPA_TIMER_POOL, - CVMX_FPA_TIMER_POOL_SIZE, - tim_buffers, CVMX_FPA_DFA_POOL, - CVMX_FPA_DFA_POOL_SIZE, - dfa_buffers); -} diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/drivers/staging/octeon/cvmx-helper-fpa.h deleted file mode 100644 index 5ff8c93198de..000000000000 --- a/drivers/staging/octeon/cvmx-helper-fpa.h +++ /dev/null @@ -1,64 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Helper functions for FPA setup. - * - */ -#ifndef __CVMX_HELPER_H_FPA__ -#define __CVMX_HELPER_H_FPA__ - -/** - * Allocate memory and initialize the FPA pools using memory - * from cvmx-bootmem. Sizes of each element in the pools is - * controlled by the cvmx-config.h header file. Specifying - * zero for any parameter will cause that FPA pool to not be - * setup. This is useful if you aren't using some of the - * hardware and want to save memory. - * - * @packet_buffers: - * Number of packet buffers to allocate - * @work_queue_entries: - * Number of work queue entries - * @pko_buffers: - * PKO Command buffers. You should at minimum have two per - * each PKO queue. - * @tim_buffers: - * TIM ring buffer command queues. At least two per timer bucket - * is recommened. - * @dfa_buffers: - * DFA command buffer. A relatively small (32 for example) - * number should work. - * Returns Zero on success, non-zero if out of memory - */ -extern int cvmx_helper_initialize_fpa(int packet_buffers, - int work_queue_entries, int pko_buffers, - int tim_buffers, int dfa_buffers); - -#endif /* __CVMX_HELPER_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/drivers/staging/octeon/cvmx-helper-loop.c deleted file mode 100644 index 55a571a69529..000000000000 --- a/drivers/staging/octeon/cvmx-helper-loop.c +++ /dev/null @@ -1,85 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Functions for LOOP initialization, configuration, - * and monitoring. - */ -#include - -#include "cvmx-config.h" - -#include "cvmx-helper.h" -#include "cvmx-pip-defs.h" - -/** - * Probe a LOOP interface and determine the number of ports - * connected to it. The LOOP interface should still be down - * after this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -int __cvmx_helper_loop_probe(int interface) -{ - union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs; - int num_ports = 4; - int port; - - /* We need to disable length checking so packet < 64 bytes and jumbo - frames don't get errors */ - for (port = 0; port < num_ports; port++) { - union cvmx_pip_prt_cfgx port_cfg; - int ipd_port = cvmx_helper_get_ipd_port(interface, port); - port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); - port_cfg.s.maxerr_en = 0; - port_cfg.s.minerr_en = 0; - cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); - } - - /* Disable FCS stripping for loopback ports */ - ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); - ipd_sub_port_fcs.s.port_bit2 = 0; - cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); - return num_ports; -} - -/** - * Bringup and enable a LOOP interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_loop_enable(int interface) -{ - /* Do nothing. */ - return 0; -} diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/drivers/staging/octeon/cvmx-helper-loop.h deleted file mode 100644 index e646a6ccce75..000000000000 --- a/drivers/staging/octeon/cvmx-helper-loop.h +++ /dev/null @@ -1,59 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as published by - * the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. - * See the GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Functions for LOOP initialization, configuration, - * and monitoring. - * - */ -#ifndef __CVMX_HELPER_LOOP_H__ -#define __CVMX_HELPER_LOOP_H__ - -/** - * Probe a LOOP interface and determine the number of ports - * connected to it. The LOOP interface should still be down after - * this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -extern int __cvmx_helper_loop_probe(int interface); - -/** - * Bringup and enable a LOOP interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_loop_enable(int interface); - -#endif diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/drivers/staging/octeon/cvmx-helper-npi.c deleted file mode 100644 index 7388a1e72b38..000000000000 --- a/drivers/staging/octeon/cvmx-helper-npi.c +++ /dev/null @@ -1,113 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Functions for NPI initialization, configuration, - * and monitoring. - */ -#include - -#include "cvmx-config.h" - -#include "cvmx-helper.h" - -#include "cvmx-pip-defs.h" - -/** - * Probe a NPI interface and determine the number of ports - * connected to it. The NPI interface should still be down - * after this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -int __cvmx_helper_npi_probe(int interface) -{ -#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0 - if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) - return 4; - else if (OCTEON_IS_MODEL(OCTEON_CN56XX) - && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) - /* The packet engines didn't exist before pass 2 */ - return 4; - else if (OCTEON_IS_MODEL(OCTEON_CN52XX) - && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) - /* The packet engines didn't exist before pass 2 */ - return 4; -#if 0 - /* - * Technically CN30XX, CN31XX, and CN50XX contain packet - * engines, but nobody ever uses them. Since this is the case, - * we disable them here. - */ - else if (OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) - return 2; - else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) - return 1; -#endif -#endif - return 0; -} - -/** - * Bringup and enable a NPI interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_npi_enable(int interface) -{ - /* - * On CN50XX, CN52XX, and CN56XX we need to disable length - * checking so packet < 64 bytes and jumbo frames don't get - * errors. - */ - if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && - !OCTEON_IS_MODEL(OCTEON_CN58XX)) { - int num_ports = cvmx_helper_ports_on_interface(interface); - int port; - for (port = 0; port < num_ports; port++) { - union cvmx_pip_prt_cfgx port_cfg; - int ipd_port = - cvmx_helper_get_ipd_port(interface, port); - port_cfg.u64 = - cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); - port_cfg.s.maxerr_en = 0; - port_cfg.s.minerr_en = 0; - cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), - port_cfg.u64); - } - } - - /* Enables are controlled by the remote host, so nothing to do here */ - return 0; -} diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/drivers/staging/octeon/cvmx-helper-npi.h deleted file mode 100644 index 908e7b08c214..000000000000 --- a/drivers/staging/octeon/cvmx-helper-npi.h +++ /dev/null @@ -1,60 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Functions for NPI initialization, configuration, - * and monitoring. - * - */ -#ifndef __CVMX_HELPER_NPI_H__ -#define __CVMX_HELPER_NPI_H__ - -/** - * Probe a NPI interface and determine the number of ports - * connected to it. The NPI interface should still be down after - * this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -extern int __cvmx_helper_npi_probe(int interface); - -/** - * Bringup and enable a NPI interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_npi_enable(int interface); - -#endif diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/drivers/staging/octeon/cvmx-helper-rgmii.c deleted file mode 100644 index aa2d5d7fee2b..000000000000 --- a/drivers/staging/octeon/cvmx-helper-rgmii.c +++ /dev/null @@ -1,525 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Functions for RGMII/GMII/MII initialization, configuration, - * and monitoring. - */ -#include - -#include "cvmx-config.h" - - -#include "cvmx-mdio.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" - -#include -#include "cvmx-gmxx-defs.h" -#include "cvmx-asxx-defs.h" -#include "cvmx-dbg-defs.h" - -void __cvmx_interrupt_gmxx_enable(int interface); -void __cvmx_interrupt_asxx_enable(int block); - -/** - * Probe RGMII ports and determine the number present - * - * @interface: Interface to probe - * - * Returns Number of RGMII/GMII/MII ports (0-4). - */ -int __cvmx_helper_rgmii_probe(int interface) -{ - int num_ports = 0; - union cvmx_gmxx_inf_mode mode; - mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); - - if (mode.s.type) { - if (OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)) { - cvmx_dprintf("ERROR: RGMII initialize called in " - "SPI interface\n"); - } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN30XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) { - /* - * On these chips "type" says we're in - * GMII/MII mode. This limits us to 2 ports - */ - num_ports = 2; - } else { - cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", - __func__); - } - } else { - if (OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)) { - num_ports = 4; - } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN30XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) { - num_ports = 3; - } else { - cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", - __func__); - } - } - return num_ports; -} - -/** - * Put an RGMII interface in loopback mode. Internal packets sent - * out will be received back again on the same port. Externally - * received packets will echo back out. - * - * @port: IPD port number to loop. - */ -void cvmx_helper_rgmii_internal_loopback(int port) -{ - int interface = (port >> 4) & 1; - int index = port & 0xf; - uint64_t tmp; - - union cvmx_gmxx_prtx_cfg gmx_cfg; - gmx_cfg.u64 = 0; - gmx_cfg.s.duplex = 1; - gmx_cfg.s.slottime = 1; - gmx_cfg.s.speed = 1; - cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); - tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); - cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); - tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); - cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); - tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); - cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); - gmx_cfg.s.en = 1; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); -} - -/** - * Workaround ASX setup errata with CN38XX pass1 - * - * @interface: Interface to setup - * @port: Port to setup (0..3) - * @cpu_clock_hz: - * Chip frequency in Hertz - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_errata_asx_pass1(int interface, int port, - int cpu_clock_hz) -{ - /* Set hi water mark as per errata GMX-4 */ - if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000) - cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12); - else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000) - cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11); - else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000) - cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10); - else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000) - cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9); - else - cvmx_dprintf("Illegal clock frequency (%d). " - "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz); - return 0; -} - -/** - * Configure all of the ASX, GMX, and PKO regsiters required - * to get RGMII to function on the supplied interface. - * - * @interface: PKO Interface to configure (0 or 1) - * - * Returns Zero on success - */ -int __cvmx_helper_rgmii_enable(int interface) -{ - int num_ports = cvmx_helper_ports_on_interface(interface); - int port; - struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get(); - union cvmx_gmxx_inf_mode mode; - union cvmx_asxx_tx_prt_en asx_tx; - union cvmx_asxx_rx_prt_en asx_rx; - - mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); - - if (mode.s.en == 0) - return -1; - if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || - OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1) - /* Ignore SPI interfaces */ - return -1; - - /* Configure the ASX registers needed to use the RGMII ports */ - asx_tx.u64 = 0; - asx_tx.s.prt_en = cvmx_build_mask(num_ports); - cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); - - asx_rx.u64 = 0; - asx_rx.s.prt_en = cvmx_build_mask(num_ports); - cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64); - - /* Configure the GMX registers needed to use the RGMII ports */ - for (port = 0; port < num_ports; port++) { - /* Setting of CVMX_GMXX_TXX_THRESH has been moved to - __cvmx_helper_setup_gmx() */ - - if (cvmx_octeon_is_pass1()) - __cvmx_helper_errata_asx_pass1(interface, port, - sys_info_ptr-> - cpu_clock_hz); - else { - /* - * Configure more flexible RGMII preamble - * checking. Pass 1 doesn't support this - * feature. - */ - union cvmx_gmxx_rxx_frm_ctl frm_ctl; - frm_ctl.u64 = - cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL - (port, interface)); - /* New field, so must be compile time */ - frm_ctl.s.pre_free = 1; - cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), - frm_ctl.u64); - } - - /* - * Each pause frame transmitted will ask for about 10M - * bit times before resume. If buffer space comes - * available before that time has expired, an XON - * pause frame (0 time) will be transmitted to restart - * the flow. - */ - cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), - 20000); - cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL - (port, interface), 19000); - - if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), - 16); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), - 16); - } else { - cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), - 24); - cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), - 24); - } - } - - __cvmx_helper_setup_gmx(interface, num_ports); - - /* enable the ports now */ - for (port = 0; port < num_ports; port++) { - union cvmx_gmxx_prtx_cfg gmx_cfg; - cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port - (interface, port)); - gmx_cfg.u64 = - cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface)); - gmx_cfg.s.en = 1; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), - gmx_cfg.u64); - } - __cvmx_interrupt_asxx_enable(interface); - __cvmx_interrupt_gmxx_enable(interface); - - return 0; -} - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port) -{ - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - union cvmx_asxx_prt_loop asxx_prt_loop; - - asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); - if (asxx_prt_loop.s.int_loop & (1 << index)) { - /* Force 1Gbps full duplex on internal loopback */ - cvmx_helper_link_info_t result; - result.u64 = 0; - result.s.full_duplex = 1; - result.s.link_up = 1; - result.s.speed = 1000; - return result; - } else - return __cvmx_helper_board_link_get(ipd_port); -} - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_rgmii_link_set(int ipd_port, - cvmx_helper_link_info_t link_info) -{ - int result = 0; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - union cvmx_gmxx_prtx_cfg original_gmx_cfg; - union cvmx_gmxx_prtx_cfg new_gmx_cfg; - union cvmx_pko_mem_queue_qos pko_mem_queue_qos; - union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16]; - union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp; - union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save; - int i; - - /* Ignore speed sets in the simulator */ - if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) - return 0; - - /* Read the current settings so we know the current enable state */ - original_gmx_cfg.u64 = - cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - new_gmx_cfg = original_gmx_cfg; - - /* Disable the lowest level RX */ - cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), - cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & - ~(1 << index)); - - /* Disable all queues so that TX should become idle */ - for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { - int queue = cvmx_pko_get_base_queue(ipd_port) + i; - cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); - pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS); - pko_mem_queue_qos.s.pid = ipd_port; - pko_mem_queue_qos.s.qid = queue; - pko_mem_queue_qos_save[i] = pko_mem_queue_qos; - pko_mem_queue_qos.s.qos_mask = 0; - cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64); - } - - /* Disable backpressure */ - gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); - gmx_tx_ovr_bp_save = gmx_tx_ovr_bp; - gmx_tx_ovr_bp.s.bp &= ~(1 << index); - gmx_tx_ovr_bp.s.en |= 1 << index; - cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); - cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); - - /* - * Poll the GMX state machine waiting for it to become - * idle. Preferably we should only change speed when it is - * idle. If it doesn't become idle we will still do the speed - * change, but there is a slight chance that GMX will - * lockup. - */ - cvmx_write_csr(CVMX_NPI_DBG_SELECT, - interface * 0x800 + index * 0x100 + 0x880); - CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7, - ==, 0, 10000); - CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf, - ==, 0, 10000); - - /* Disable the port before we make any changes */ - new_gmx_cfg.s.en = 0; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); - cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - - /* Set full/half duplex */ - if (cvmx_octeon_is_pass1()) - /* Half duplex is broken for 38XX Pass 1 */ - new_gmx_cfg.s.duplex = 1; - else if (!link_info.s.link_up) - /* Force full duplex on down links */ - new_gmx_cfg.s.duplex = 1; - else - new_gmx_cfg.s.duplex = link_info.s.full_duplex; - - /* Set the link speed. Anything unknown is set to 1Gbps */ - if (link_info.s.speed == 10) { - new_gmx_cfg.s.slottime = 0; - new_gmx_cfg.s.speed = 0; - } else if (link_info.s.speed == 100) { - new_gmx_cfg.s.slottime = 0; - new_gmx_cfg.s.speed = 0; - } else { - new_gmx_cfg.s.slottime = 1; - new_gmx_cfg.s.speed = 1; - } - - /* Adjust the clocks */ - if (link_info.s.speed == 10) { - cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50); - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); - } else if (link_info.s.speed == 100) { - cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5); - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); - } else { - cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); - } - - if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { - if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) { - union cvmx_gmxx_inf_mode mode; - mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); - - /* - * Port .en .type .p0mii Configuration - * ---- --- ----- ------ ----------------------------------------- - * X 0 X X All links are disabled. - * 0 1 X 0 Port 0 is RGMII - * 0 1 X 1 Port 0 is MII - * 1 1 0 X Ports 1 and 2 are configured as RGMII ports. - * 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or - * MII port is selected by GMX_PRT1_CFG[SPEED]. - */ - - /* In MII mode, CLK_CNT = 1. */ - if (((index == 0) && (mode.s.p0mii == 1)) - || ((index != 0) && (mode.s.type == 1))) { - cvmx_write_csr(CVMX_GMXX_TXX_CLK - (index, interface), 1); - } - } - } - - /* Do a read to make sure all setup stuff is complete */ - cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - - /* Save the new GMX setting without enabling the port */ - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); - - /* Enable the lowest level RX */ - cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), - cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 << - index)); - - /* Re-enable the TX path */ - for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { - int queue = cvmx_pko_get_base_queue(ipd_port) + i; - cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); - cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, - pko_mem_queue_qos_save[i].u64); - } - - /* Restore backpressure */ - cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64); - - /* Restore the GMX enable state. Port config is complete */ - new_gmx_cfg.s.en = original_gmx_cfg.s.en; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); - - return result; -} - -/** - * Configure a port for internal and/or external loopback. Internal loopback - * causes packets sent by the port to be received by Octeon. External loopback - * causes packets received from the wire to sent out again. - * - * @ipd_port: IPD/PKO port to loopback. - * @enable_internal: - * Non zero if you want internal loopback - * @enable_external: - * Non zero if you want external loopback - * - * Returns Zero on success, negative on failure. - */ -int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal, - int enable_external) -{ - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - int original_enable; - union cvmx_gmxx_prtx_cfg gmx_cfg; - union cvmx_asxx_prt_loop asxx_prt_loop; - - /* Read the current enable state and save it */ - gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - original_enable = gmx_cfg.s.en; - /* Force port to be disabled */ - gmx_cfg.s.en = 0; - if (enable_internal) { - /* Force speed if we're doing internal loopback */ - gmx_cfg.s.duplex = 1; - gmx_cfg.s.slottime = 1; - gmx_cfg.s.speed = 1; - cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); - } - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); - - /* Set the loopback bits */ - asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); - if (enable_internal) - asxx_prt_loop.s.int_loop |= 1 << index; - else - asxx_prt_loop.s.int_loop &= ~(1 << index); - if (enable_external) - asxx_prt_loop.s.ext_loop |= 1 << index; - else - asxx_prt_loop.s.ext_loop &= ~(1 << index); - cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64); - - /* Force enables in internal loopback */ - if (enable_internal) { - uint64_t tmp; - tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); - cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), - (1 << index) | tmp); - tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); - cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), - (1 << index) | tmp); - original_enable = 1; - } - - /* Restore the enable state */ - gmx_cfg.s.en = original_enable; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); - return 0; -} diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/drivers/staging/octeon/cvmx-helper-rgmii.h deleted file mode 100644 index ea2652604a57..000000000000 --- a/drivers/staging/octeon/cvmx-helper-rgmii.h +++ /dev/null @@ -1,110 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Functions for RGMII/GMII/MII initialization, configuration, - * and monitoring. - * - */ -#ifndef __CVMX_HELPER_RGMII_H__ -#define __CVMX_HELPER_RGMII_H__ - -/** - * Probe RGMII ports and determine the number present - * - * @interface: Interface to probe - * - * Returns Number of RGMII/GMII/MII ports (0-4). - */ -extern int __cvmx_helper_rgmii_probe(int interface); - -/** - * Put an RGMII interface in loopback mode. Internal packets sent - * out will be received back again on the same port. Externally - * received packets will echo back out. - * - * @port: IPD port number to loop. - */ -extern void cvmx_helper_rgmii_internal_loopback(int port); - -/** - * Configure all of the ASX, GMX, and PKO regsiters required - * to get RGMII to function on the supplied interface. - * - * @interface: PKO Interface to configure (0 or 1) - * - * Returns Zero on success - */ -extern int __cvmx_helper_rgmii_enable(int interface); - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port); - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_rgmii_link_set(int ipd_port, - cvmx_helper_link_info_t link_info); - -/** - * Configure a port for internal and/or external loopback. Internal loopback - * causes packets sent by the port to be received by Octeon. External loopback - * causes packets received from the wire to sent out again. - * - * @ipd_port: IPD/PKO port to loopback. - * @enable_internal: - * Non zero if you want internal loopback - * @enable_external: - * Non zero if you want external loopback - * - * Returns Zero on success, negative on failure. - */ -extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port, - int enable_internal, - int enable_external); - -#endif diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/drivers/staging/octeon/cvmx-helper-sgmii.c deleted file mode 100644 index 6214e3b6d975..000000000000 --- a/drivers/staging/octeon/cvmx-helper-sgmii.c +++ /dev/null @@ -1,550 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Functions for SGMII initialization, configuration, - * and monitoring. - */ - -#include - -#include "cvmx-config.h" - -#include "cvmx-mdio.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" - -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsx-defs.h" - -void __cvmx_interrupt_gmxx_enable(int interface); -void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); -void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); - -/** - * Perform initialization required only once for an SGMII port. - * - * @interface: Interface to init - * @index: Index of prot on the interface - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) -{ - const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; - union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; - union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg; - union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; - - /* Disable GMX */ - gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - gmxx_prtx_cfg.s.en = 0; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); - - /* - * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the - * appropriate value. 1000BASE-X specifies a 10ms - * interval. SGMII specifies a 1.6ms interval. - */ - pcs_misc_ctl_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); - pcsx_linkx_timer_count_reg.u64 = - cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); - if (pcs_misc_ctl_reg.s.mode) { - /* 1000BASE-X */ - pcsx_linkx_timer_count_reg.s.count = - (10000ull * clock_mhz) >> 10; - } else { - /* SGMII */ - pcsx_linkx_timer_count_reg.s.count = - (1600ull * clock_mhz) >> 10; - } - cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), - pcsx_linkx_timer_count_reg.u64); - - /* - * Write the advertisement register to be used as the - * tx_Config_Reg of the autonegotiation. In - * 1000BASE-X mode, tx_Config_Reg is PCS*_AN*_ADV_REG. - * In SGMII PHY mode, tx_Config_Reg is - * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, - * tx_Config_Reg is the fixed value 0x4001, so this - * step can be skipped. - */ - if (pcs_misc_ctl_reg.s.mode) { - /* 1000BASE-X */ - union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg; - pcsx_anx_adv_reg.u64 = - cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); - pcsx_anx_adv_reg.s.rem_flt = 0; - pcsx_anx_adv_reg.s.pause = 3; - pcsx_anx_adv_reg.s.hfd = 1; - pcsx_anx_adv_reg.s.fd = 1; - cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), - pcsx_anx_adv_reg.u64); - } else { - union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; - pcsx_miscx_ctl_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); - if (pcsx_miscx_ctl_reg.s.mac_phy) { - /* PHY Mode */ - union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg; - pcsx_sgmx_an_adv_reg.u64 = - cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG - (index, interface)); - pcsx_sgmx_an_adv_reg.s.link = 1; - pcsx_sgmx_an_adv_reg.s.dup = 1; - pcsx_sgmx_an_adv_reg.s.speed = 2; - cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG - (index, interface), - pcsx_sgmx_an_adv_reg.u64); - } else { - /* MAC Mode - Nothing to do */ - } - } - return 0; -} - -/** - * Initialize the SERTES link for the first time or after a loss - * of link. - * - * @interface: Interface to init - * @index: Index of prot on the interface - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index) -{ - union cvmx_pcsx_mrx_control_reg control_reg; - - /* - * Take PCS through a reset sequence. - * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. - * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the - * value of the other PCS*_MR*_CONTROL_REG bits). Read - * PCS*_MR*_CONTROL_REG[RESET] until it changes value to - * zero. - */ - control_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); - if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { - control_reg.s.reset = 1; - cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), - control_reg.u64); - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_PCSX_MRX_CONTROL_REG(index, interface), - union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) { - cvmx_dprintf("SGMII%d: Timeout waiting for port %d " - "to finish reset\n", - interface, index); - return -1; - } - } - - /* - * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh - * sgmii negotiation starts. - */ - control_reg.s.rst_an = 1; - control_reg.s.an_en = 1; - control_reg.s.pwr_dn = 0; - cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), - control_reg.u64); - - /* - * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating - * that sgmii autonegotiation is complete. In MAC mode this - * isn't an ethernet link, but a link between Octeon and the - * PHY. - */ - if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && - CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface), - union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1, - 10000)) { - /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */ - return -1; - } - return 0; -} - -/** - * Configure an SGMII link to the specified speed after the SERTES - * link is up. - * - * @interface: Interface to init - * @index: Index of prot on the interface - * @link_info: Link state to configure - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, - int index, - cvmx_helper_link_info_t - link_info) -{ - int is_enabled; - union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; - union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; - - /* Disable GMX before we make any changes. Remember the enable state */ - gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - is_enabled = gmxx_prtx_cfg.s.en; - gmxx_prtx_cfg.s.en = 0; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); - - /* Wait for GMX to be idle */ - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg, - rx_idle, ==, 1, 10000) - || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), - union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1, - 10000)) { - cvmx_dprintf - ("SGMII%d: Timeout waiting for port %d to be idle\n", - interface, index); - return -1; - } - - /* Read GMX CFG again to make sure the disable completed */ - gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - - /* - * Get the misc control for PCS. We will need to set the - * duplication amount. - */ - pcsx_miscx_ctl_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); - - /* - * Use GMXENO to force the link down if the status we get says - * it should be down. - */ - pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up; - - /* Only change the duplex setting if the link is up */ - if (link_info.s.link_up) - gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex; - - /* Do speed based setting for GMX */ - switch (link_info.s.speed) { - case 10: - gmxx_prtx_cfg.s.speed = 0; - gmxx_prtx_cfg.s.speed_msb = 1; - gmxx_prtx_cfg.s.slottime = 0; - /* Setting from GMX-603 */ - pcsx_miscx_ctl_reg.s.samp_pt = 25; - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); - break; - case 100: - gmxx_prtx_cfg.s.speed = 0; - gmxx_prtx_cfg.s.speed_msb = 0; - gmxx_prtx_cfg.s.slottime = 0; - pcsx_miscx_ctl_reg.s.samp_pt = 0x5; - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); - break; - case 1000: - gmxx_prtx_cfg.s.speed = 1; - gmxx_prtx_cfg.s.speed_msb = 0; - gmxx_prtx_cfg.s.slottime = 1; - pcsx_miscx_ctl_reg.s.samp_pt = 1; - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192); - break; - default: - break; - } - - /* Write the new misc control for PCS */ - cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), - pcsx_miscx_ctl_reg.u64); - - /* Write the new GMX settings with the port still disabled */ - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); - - /* Read GMX CFG again to make sure the config completed */ - gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - - /* Restore the enabled / disabled state */ - gmxx_prtx_cfg.s.en = is_enabled; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); - - return 0; -} - -/** - * Bring up the SGMII interface to be ready for packet I/O but - * leave I/O disabled using the GMX override. This function - * follows the bringup documented in 10.6.3 of the manual. - * - * @interface: Interface to bringup - * @num_ports: Number of ports on the interface - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) -{ - int index; - - __cvmx_helper_setup_gmx(interface, num_ports); - - for (index = 0; index < num_ports; index++) { - int ipd_port = cvmx_helper_get_ipd_port(interface, index); - __cvmx_helper_sgmii_hardware_init_one_time(interface, index); - __cvmx_helper_sgmii_link_set(ipd_port, - __cvmx_helper_sgmii_link_get - (ipd_port)); - - } - - return 0; -} - -/** - * Probe a SGMII interface and determine the number of ports - * connected to it. The SGMII interface should still be down after - * this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -int __cvmx_helper_sgmii_probe(int interface) -{ - union cvmx_gmxx_inf_mode mode; - - /* - * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the - * interface needs to be enabled before IPD otherwise per port - * backpressure may not work properly - */ - mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); - mode.s.en = 1; - cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); - return 4; -} - -/** - * Bringup and enable a SGMII interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_sgmii_enable(int interface) -{ - int num_ports = cvmx_helper_ports_on_interface(interface); - int index; - - __cvmx_helper_sgmii_hardware_init(interface, num_ports); - - for (index = 0; index < num_ports; index++) { - union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; - gmxx_prtx_cfg.u64 = - cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); - gmxx_prtx_cfg.s.en = 1; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), - gmxx_prtx_cfg.u64); - __cvmx_interrupt_pcsx_intx_en_reg_enable(index, interface); - } - __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); - __cvmx_interrupt_gmxx_enable(interface); - return 0; -} - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port) -{ - cvmx_helper_link_info_t result; - union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg; - - result.u64 = 0; - - if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { - /* The simulator gives you a simulated 1Gbps full duplex link */ - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - } - - pcsx_mrx_control_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); - if (pcsx_mrx_control_reg.s.loopbck1) { - /* Force 1Gbps full duplex link for internal loopback */ - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 1000; - return result; - } - - pcs_misc_ctl_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); - if (pcs_misc_ctl_reg.s.mode) { - /* 1000BASE-X */ - /* FIXME */ - } else { - union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; - pcsx_miscx_ctl_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); - if (pcsx_miscx_ctl_reg.s.mac_phy) { - /* PHY Mode */ - union cvmx_pcsx_mrx_status_reg pcsx_mrx_status_reg; - union cvmx_pcsx_anx_results_reg pcsx_anx_results_reg; - - /* - * Don't bother continuing if the SERTES low - * level link is down - */ - pcsx_mrx_status_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG - (index, interface)); - if (pcsx_mrx_status_reg.s.lnk_st == 0) { - if (__cvmx_helper_sgmii_hardware_init_link - (interface, index) != 0) - return result; - } - - /* Read the autoneg results */ - pcsx_anx_results_reg.u64 = - cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG - (index, interface)); - if (pcsx_anx_results_reg.s.an_cpt) { - /* - * Auto negotiation is complete. Set - * status accordingly. - */ - result.s.full_duplex = - pcsx_anx_results_reg.s.dup; - result.s.link_up = - pcsx_anx_results_reg.s.link_ok; - switch (pcsx_anx_results_reg.s.spd) { - case 0: - result.s.speed = 10; - break; - case 1: - result.s.speed = 100; - break; - case 2: - result.s.speed = 1000; - break; - default: - result.s.speed = 0; - result.s.link_up = 0; - break; - } - } else { - /* - * Auto negotiation isn't - * complete. Return link down. - */ - result.s.speed = 0; - result.s.link_up = 0; - } - } else { /* MAC Mode */ - - result = __cvmx_helper_board_link_get(ipd_port); - } - } - return result; -} - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_sgmii_link_set(int ipd_port, - cvmx_helper_link_info_t link_info) -{ - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - __cvmx_helper_sgmii_hardware_init_link(interface, index); - return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, - link_info); -} - -/** - * Configure a port for internal and/or external loopback. Internal - * loopback causes packets sent by the port to be received by - * Octeon. External loopback causes packets received from the wire to - * sent out again. - * - * @ipd_port: IPD/PKO port to loopback. - * @enable_internal: - * Non zero if you want internal loopback - * @enable_external: - * Non zero if you want external loopback - * - * Returns Zero on success, negative on failure. - */ -int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal, - int enable_external) -{ - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg; - union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; - - pcsx_mrx_control_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); - pcsx_mrx_control_reg.s.loopbck1 = enable_internal; - cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), - pcsx_mrx_control_reg.u64); - - pcsx_miscx_ctl_reg.u64 = - cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); - pcsx_miscx_ctl_reg.s.loopbck2 = enable_external; - cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), - pcsx_miscx_ctl_reg.u64); - - __cvmx_helper_sgmii_hardware_init_link(interface, index); - return 0; -} diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/drivers/staging/octeon/cvmx-helper-sgmii.h deleted file mode 100644 index 19b48d60857f..000000000000 --- a/drivers/staging/octeon/cvmx-helper-sgmii.h +++ /dev/null @@ -1,104 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Functions for SGMII initialization, configuration, - * and monitoring. - * - */ -#ifndef __CVMX_HELPER_SGMII_H__ -#define __CVMX_HELPER_SGMII_H__ - -/** - * Probe a SGMII interface and determine the number of ports - * connected to it. The SGMII interface should still be down after - * this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -extern int __cvmx_helper_sgmii_probe(int interface); - -/** - * Bringup and enable a SGMII interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_sgmii_enable(int interface); - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port); - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_sgmii_link_set(int ipd_port, - cvmx_helper_link_info_t link_info); - -/** - * Configure a port for internal and/or external loopback. Internal loopback - * causes packets sent by the port to be received by Octeon. External loopback - * causes packets received from the wire to sent out again. - * - * @ipd_port: IPD/PKO port to loopback. - * @enable_internal: - * Non zero if you want internal loopback - * @enable_external: - * Non zero if you want external loopback - * - * Returns Zero on success, negative on failure. - */ -extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port, - int enable_internal, - int enable_external); - -#endif diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/drivers/staging/octeon/cvmx-helper-spi.c deleted file mode 100644 index 8ba6c832471e..000000000000 --- a/drivers/staging/octeon/cvmx-helper-spi.c +++ /dev/null @@ -1,195 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -void __cvmx_interrupt_gmxx_enable(int interface); -void __cvmx_interrupt_spxx_int_msk_enable(int index); -void __cvmx_interrupt_stxx_int_msk_enable(int index); - -/* - * Functions for SPI initialization, configuration, - * and monitoring. - */ -#include - -#include "cvmx-config.h" -#include "cvmx-spi.h" -#include "cvmx-helper.h" - -#include "cvmx-pip-defs.h" -#include "cvmx-pko-defs.h" - -/* - * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI - * initialization routines wait for SPI training. You can override the - * value using executive-config.h if necessary. - */ -#ifndef CVMX_HELPER_SPI_TIMEOUT -#define CVMX_HELPER_SPI_TIMEOUT 10 -#endif - -/** - * Probe a SPI interface and determine the number of ports - * connected to it. The SPI interface should still be down after - * this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -int __cvmx_helper_spi_probe(int interface) -{ - int num_ports = 0; - - if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && - cvmx_spi4000_is_present(interface)) { - num_ports = 10; - } else { - union cvmx_pko_reg_crc_enable enable; - num_ports = 16; - /* - * Unlike the SPI4000, most SPI devices don't - * automatically put on the L2 CRC. For everything - * except for the SPI4000 have PKO append the L2 CRC - * to the packet. - */ - enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE); - enable.s.enable |= 0xffff << (interface * 16); - cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64); - } - __cvmx_helper_setup_gmx(interface, num_ports); - return num_ports; -} - -/** - * Bringup and enable a SPI interface. After this call packet I/O - * should be fully functional. This is called with IPD enabled but - * PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_spi_enable(int interface) -{ - /* - * Normally the ethernet L2 CRC is checked and stripped in the - * GMX block. When you are using SPI, this isn' the case and - * IPD needs to check the L2 CRC. - */ - int num_ports = cvmx_helper_ports_on_interface(interface); - int ipd_port; - for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports; - ipd_port++) { - union cvmx_pip_prt_cfgx port_config; - port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); - port_config.s.crc_en = 1; - cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); - } - - if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { - cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX, - CVMX_HELPER_SPI_TIMEOUT, num_ports); - if (cvmx_spi4000_is_present(interface)) - cvmx_spi4000_initialize(interface); - } - __cvmx_interrupt_spxx_int_msk_enable(interface); - __cvmx_interrupt_stxx_int_msk_enable(interface); - __cvmx_interrupt_gmxx_enable(interface); - return 0; -} - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port) -{ - cvmx_helper_link_info_t result; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - result.u64 = 0; - - if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { - /* The simulator gives you a simulated full duplex link */ - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 10000; - } else if (cvmx_spi4000_is_present(interface)) { - union cvmx_gmxx_rxx_rx_inbnd inband = - cvmx_spi4000_check_speed(interface, index); - result.s.link_up = inband.s.status; - result.s.full_duplex = inband.s.duplex; - switch (inband.s.speed) { - case 0: /* 10 Mbps */ - result.s.speed = 10; - break; - case 1: /* 100 Mbps */ - result.s.speed = 100; - break; - case 2: /* 1 Gbps */ - result.s.speed = 1000; - break; - case 3: /* Illegal */ - result.s.speed = 0; - result.s.link_up = 0; - break; - } - } else { - /* For generic SPI we can't determine the link, just return some - sane results */ - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 10000; - } - return result; -} - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info) -{ - /* Nothing to do. If we have a SPI4000 then the setup was already performed - by cvmx_spi4000_check_speed(). If not then there isn't any link - info */ - return 0; -} diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/drivers/staging/octeon/cvmx-helper-spi.h deleted file mode 100644 index 69bac036d10e..000000000000 --- a/drivers/staging/octeon/cvmx-helper-spi.h +++ /dev/null @@ -1,84 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Functions for SPI initialization, configuration, - * and monitoring. - */ -#ifndef __CVMX_HELPER_SPI_H__ -#define __CVMX_HELPER_SPI_H__ - -/** - * Probe a SPI interface and determine the number of ports - * connected to it. The SPI interface should still be down after - * this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -extern int __cvmx_helper_spi_probe(int interface); - -/** - * Bringup and enable a SPI interface. After this call packet I/O - * should be fully functional. This is called with IPD enabled but - * PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_spi_enable(int interface); - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port); - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_spi_link_set(int ipd_port, - cvmx_helper_link_info_t link_info); - -#endif diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/drivers/staging/octeon/cvmx-helper-util.c deleted file mode 100644 index 131182bf5abb..000000000000 --- a/drivers/staging/octeon/cvmx-helper-util.c +++ /dev/null @@ -1,433 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Small helper utilities. - */ -#include - -#include - -#include "cvmx-config.h" - -#include "cvmx-fpa.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-ipd.h" -#include "cvmx-spi.h" - -#include "cvmx-helper.h" -#include "cvmx-helper-util.h" - -#include - -/** - * Convert a interface mode into a human readable string - * - * @mode: Mode to convert - * - * Returns String - */ -const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t - mode) -{ - switch (mode) { - case CVMX_HELPER_INTERFACE_MODE_DISABLED: - return "DISABLED"; - case CVMX_HELPER_INTERFACE_MODE_RGMII: - return "RGMII"; - case CVMX_HELPER_INTERFACE_MODE_GMII: - return "GMII"; - case CVMX_HELPER_INTERFACE_MODE_SPI: - return "SPI"; - case CVMX_HELPER_INTERFACE_MODE_PCIE: - return "PCIE"; - case CVMX_HELPER_INTERFACE_MODE_XAUI: - return "XAUI"; - case CVMX_HELPER_INTERFACE_MODE_SGMII: - return "SGMII"; - case CVMX_HELPER_INTERFACE_MODE_PICMG: - return "PICMG"; - case CVMX_HELPER_INTERFACE_MODE_NPI: - return "NPI"; - case CVMX_HELPER_INTERFACE_MODE_LOOP: - return "LOOP"; - } - return "UNKNOWN"; -} - -/** - * Debug routine to dump the packet structure to the console - * - * @work: Work queue entry containing the packet to dump - * Returns - */ -int cvmx_helper_dump_packet(cvmx_wqe_t *work) -{ - uint64_t count; - uint64_t remaining_bytes; - union cvmx_buf_ptr buffer_ptr; - uint64_t start_of_buffer; - uint8_t *data_address; - uint8_t *end_of_data; - - cvmx_dprintf("Packet Length: %u\n", work->len); - cvmx_dprintf(" Input Port: %u\n", work->ipprt); - cvmx_dprintf(" QoS: %u\n", work->qos); - cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs); - - if (work->word2.s.bufs == 0) { - union cvmx_ipd_wqe_fpa_queue wqe_pool; - wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE); - buffer_ptr.u64 = 0; - buffer_ptr.s.pool = wqe_pool.s.wqe_pool; - buffer_ptr.s.size = 128; - buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data); - if (likely(!work->word2.s.not_IP)) { - union cvmx_pip_ip_offset pip_ip_offset; - pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET); - buffer_ptr.s.addr += - (pip_ip_offset.s.offset << 3) - - work->word2.s.ip_offset; - buffer_ptr.s.addr += (work->word2.s.is_v6 ^ 1) << 2; - } else { - /* - * WARNING: This code assumes that the packet - * is not RAW. If it was, we would use - * PIP_GBL_CFG[RAW_SHF] instead of - * PIP_GBL_CFG[NIP_SHF]. - */ - union cvmx_pip_gbl_cfg pip_gbl_cfg; - pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG); - buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf; - } - } else - buffer_ptr = work->packet_ptr; - remaining_bytes = work->len; - - while (remaining_bytes) { - start_of_buffer = - ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; - cvmx_dprintf(" Buffer Start:%llx\n", - (unsigned long long)start_of_buffer); - cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i); - cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back); - cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool); - cvmx_dprintf(" Buffer Data: %llx\n", - (unsigned long long)buffer_ptr.s.addr); - cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size); - - cvmx_dprintf("\t\t"); - data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr); - end_of_data = data_address + buffer_ptr.s.size; - count = 0; - while (data_address < end_of_data) { - if (remaining_bytes == 0) - break; - else - remaining_bytes--; - cvmx_dprintf("%02x", (unsigned int)*data_address); - data_address++; - if (remaining_bytes && (count == 7)) { - cvmx_dprintf("\n\t\t"); - count = 0; - } else - count++; - } - cvmx_dprintf("\n"); - - if (remaining_bytes) - buffer_ptr = *(union cvmx_buf_ptr *) - cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); - } - return 0; -} - -/** - * Setup Random Early Drop on a specific input queue - * - * @queue: Input queue to setup RED on (0-7) - * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. - * @drop_thresh: - * All incomming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. - * Returns Zero on success. Negative on failure - */ -int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh) -{ - union cvmx_ipd_qosx_red_marks red_marks; - union cvmx_ipd_red_quex_param red_param; - - /* Set RED to begin dropping packets when there are pass_thresh buffers - left. It will linearly drop more packets until reaching drop_thresh - buffers */ - red_marks.u64 = 0; - red_marks.s.drop = drop_thresh; - red_marks.s.pass = pass_thresh; - cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); - - /* Use the actual queue 0 counter, not the average */ - red_param.u64 = 0; - red_param.s.prb_con = - (255ul << 24) / (red_marks.s.pass - red_marks.s.drop); - red_param.s.avg_con = 1; - red_param.s.new_con = 255; - red_param.s.use_pcnt = 1; - cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); - return 0; -} - -/** - * Setup Random Early Drop to automatically begin dropping packets. - * - * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. - * @drop_thresh: - * All incomming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. - * Returns Zero on success. Negative on failure - */ -int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) -{ - union cvmx_ipd_portx_bp_page_cnt page_cnt; - union cvmx_ipd_bp_prt_red_end ipd_bp_prt_red_end; - union cvmx_ipd_red_port_enable red_port_enable; - int queue; - int interface; - int port; - - /* Disable backpressure based on queued buffers. It needs SW support */ - page_cnt.u64 = 0; - page_cnt.s.bp_enb = 0; - page_cnt.s.page_cnt = 100; - for (interface = 0; interface < 2; interface++) { - for (port = cvmx_helper_get_first_ipd_port(interface); - port < cvmx_helper_get_last_ipd_port(interface); port++) - cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), - page_cnt.u64); - } - - for (queue = 0; queue < 8; queue++) - cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh); - - /* Shutoff the dropping based on the per port page count. SW isn't - decrementing it right now */ - ipd_bp_prt_red_end.u64 = 0; - ipd_bp_prt_red_end.s.prt_enb = 0; - cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); - - red_port_enable.u64 = 0; - red_port_enable.s.prt_enb = 0xfffffffffull; - red_port_enable.s.avg_dly = 10000; - red_port_enable.s.prb_dly = 10000; - cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); - - return 0; -} - -/** - * Setup the common GMX settings that determine the number of - * ports. These setting apply to almost all configurations of all - * chips. - * - * @interface: Interface to configure - * @num_ports: Number of ports on the interface - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_setup_gmx(int interface, int num_ports) -{ - union cvmx_gmxx_tx_prts gmx_tx_prts; - union cvmx_gmxx_rx_prts gmx_rx_prts; - union cvmx_pko_reg_gmx_port_mode pko_mode; - union cvmx_gmxx_txx_thresh gmx_tx_thresh; - int index; - - /* Tell GMX the number of TX ports on this interface */ - gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); - gmx_tx_prts.s.prts = num_ports; - cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); - - /* Tell GMX the number of RX ports on this interface. This only - ** applies to *GMII and XAUI ports */ - if (cvmx_helper_interface_get_mode(interface) == - CVMX_HELPER_INTERFACE_MODE_RGMII - || cvmx_helper_interface_get_mode(interface) == - CVMX_HELPER_INTERFACE_MODE_SGMII - || cvmx_helper_interface_get_mode(interface) == - CVMX_HELPER_INTERFACE_MODE_GMII - || cvmx_helper_interface_get_mode(interface) == - CVMX_HELPER_INTERFACE_MODE_XAUI) { - if (num_ports > 4) { - cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal " - "num_ports\n"); - return -1; - } - - gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); - gmx_rx_prts.s.prts = num_ports; - cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); - } - - /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */ - if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) - && !OCTEON_IS_MODEL(OCTEON_CN50XX)) { - /* Tell PKO the number of ports on this interface */ - pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); - if (interface == 0) { - if (num_ports == 1) - pko_mode.s.mode0 = 4; - else if (num_ports == 2) - pko_mode.s.mode0 = 3; - else if (num_ports <= 4) - pko_mode.s.mode0 = 2; - else if (num_ports <= 8) - pko_mode.s.mode0 = 1; - else - pko_mode.s.mode0 = 0; - } else { - if (num_ports == 1) - pko_mode.s.mode1 = 4; - else if (num_ports == 2) - pko_mode.s.mode1 = 3; - else if (num_ports <= 4) - pko_mode.s.mode1 = 2; - else if (num_ports <= 8) - pko_mode.s.mode1 = 1; - else - pko_mode.s.mode1 = 0; - } - cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); - } - - /* - * Set GMX to buffer as much data as possible before starting - * transmit. This reduces the chances that we have a TX under - * run due to memory contention. Any packet that fits entirely - * in the GMX FIFO can never have an under run regardless of - * memory load. - */ - gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); - if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX)) { - /* These chips have a fixed max threshold of 0x40 */ - gmx_tx_thresh.s.cnt = 0x40; - } else { - /* Choose the max value for the number of ports */ - if (num_ports <= 1) - gmx_tx_thresh.s.cnt = 0x100 / 1; - else if (num_ports == 2) - gmx_tx_thresh.s.cnt = 0x100 / 2; - else - gmx_tx_thresh.s.cnt = 0x100 / 4; - } - /* - * SPI and XAUI can have lots of ports but the GMX hardware - * only ever has a max of 4. - */ - if (num_ports > 4) - num_ports = 4; - for (index = 0; index < num_ports; index++) - cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), - gmx_tx_thresh.u64); - - return 0; -} - -/** - * Returns the IPD/PKO port number for a port on the given - * interface. - * - * @interface: Interface to use - * @port: Port on the interface - * - * Returns IPD/PKO port number - */ -int cvmx_helper_get_ipd_port(int interface, int port) -{ - switch (interface) { - case 0: - return port; - case 1: - return port + 16; - case 2: - return port + 32; - case 3: - return port + 36; - } - return -1; -} - -/** - * Returns the interface number for an IPD/PKO port number. - * - * @ipd_port: IPD/PKO port number - * - * Returns Interface number - */ -int cvmx_helper_get_interface_num(int ipd_port) -{ - if (ipd_port < 16) - return 0; - else if (ipd_port < 32) - return 1; - else if (ipd_port < 36) - return 2; - else if (ipd_port < 40) - return 3; - else - cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD " - "port number\n"); - - return -1; -} - -/** - * Returns the interface index number for an IPD/PKO port - * number. - * - * @ipd_port: IPD/PKO port number - * - * Returns Interface index number - */ -int cvmx_helper_get_interface_index_num(int ipd_port) -{ - if (ipd_port < 32) - return ipd_port & 15; - else if (ipd_port < 36) - return ipd_port & 3; - else if (ipd_port < 40) - return ipd_port & 3; - else - cvmx_dprintf("cvmx_helper_get_interface_index_num: " - "Illegal IPD port number\n"); - - return -1; -} diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/drivers/staging/octeon/cvmx-helper-util.h deleted file mode 100644 index 6a6e52fc22c1..000000000000 --- a/drivers/staging/octeon/cvmx-helper-util.h +++ /dev/null @@ -1,215 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Small helper utilities. - * - */ - -#ifndef __CVMX_HELPER_UTIL_H__ -#define __CVMX_HELPER_UTIL_H__ - -/** - * Convert a interface mode into a human readable string - * - * @mode: Mode to convert - * - * Returns String - */ -extern const char - *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode); - -/** - * Debug routine to dump the packet structure to the console - * - * @work: Work queue entry containing the packet to dump - * Returns - */ -extern int cvmx_helper_dump_packet(cvmx_wqe_t *work); - -/** - * Setup Random Early Drop on a specific input queue - * - * @queue: Input queue to setup RED on (0-7) - * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. - * @drop_thresh: - * All incomming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. - * Returns Zero on success. Negative on failure - */ -extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, - int drop_thresh); - -/** - * Setup Random Early Drop to automatically begin dropping packets. - * - * @pass_thresh: - * Packets will begin slowly dropping when there are less than - * this many packet buffers free in FPA 0. - * @drop_thresh: - * All incomming packets will be dropped when there are less - * than this many free packet buffers in FPA 0. - * Returns Zero on success. Negative on failure - */ -extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); - -/** - * Get the version of the CVMX libraries. - * - * Returns Version string. Note this buffer is allocated statically - * and will be shared by all callers. - */ -extern const char *cvmx_helper_get_version(void); - -/** - * Setup the common GMX settings that determine the number of - * ports. These setting apply to almost all configurations of all - * chips. - * - * @interface: Interface to configure - * @num_ports: Number of ports on the interface - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_setup_gmx(int interface, int num_ports); - -/** - * Returns the IPD/PKO port number for a port on the given - * interface. - * - * @interface: Interface to use - * @port: Port on the interface - * - * Returns IPD/PKO port number - */ -extern int cvmx_helper_get_ipd_port(int interface, int port); - -/** - * Returns the IPD/PKO port number for the first port on the given - * interface. - * - * @interface: Interface to use - * - * Returns IPD/PKO port number - */ -static inline int cvmx_helper_get_first_ipd_port(int interface) -{ - return cvmx_helper_get_ipd_port(interface, 0); -} - -/** - * Returns the IPD/PKO port number for the last port on the given - * interface. - * - * @interface: Interface to use - * - * Returns IPD/PKO port number - */ -static inline int cvmx_helper_get_last_ipd_port(int interface) -{ - extern int cvmx_helper_ports_on_interface(int interface); - - return cvmx_helper_get_first_ipd_port(interface) + - cvmx_helper_ports_on_interface(interface) - 1; -} - -/** - * Free the packet buffers contained in a work queue entry. - * The work queue entry is not freed. - * - * @work: Work queue entry with packet to free - */ -static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work) -{ - uint64_t number_buffers; - union cvmx_buf_ptr buffer_ptr; - union cvmx_buf_ptr next_buffer_ptr; - uint64_t start_of_buffer; - - number_buffers = work->word2.s.bufs; - if (number_buffers == 0) - return; - buffer_ptr = work->packet_ptr; - - /* - * Since the number of buffers is not zero, we know this is - * not a dynamic short packet. We need to check if it is a - * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is - * true, we need to free all buffers except for the first - * one. The caller doesn't expect their WQE pointer to be - * freed - */ - start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; - if (cvmx_ptr_to_phys(work) == start_of_buffer) { - next_buffer_ptr = - *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); - buffer_ptr = next_buffer_ptr; - number_buffers--; - } - - while (number_buffers--) { - /* - * Remember the back pointer is in cache lines, not - * 64bit words - */ - start_of_buffer = - ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; - /* - * Read pointer to next buffer before we free the - * current buffer. - */ - next_buffer_ptr = - *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); - cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer), - buffer_ptr.s.pool, 0); - buffer_ptr = next_buffer_ptr; - } -} - -/** - * Returns the interface number for an IPD/PKO port number. - * - * @ipd_port: IPD/PKO port number - * - * Returns Interface number - */ -extern int cvmx_helper_get_interface_num(int ipd_port); - -/** - * Returns the interface index number for an IPD/PKO port - * number. - * - * @ipd_port: IPD/PKO port number - * - * Returns Interface index number - */ -extern int cvmx_helper_get_interface_index_num(int ipd_port); - -#endif /* __CVMX_HELPER_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/drivers/staging/octeon/cvmx-helper-xaui.c deleted file mode 100644 index a11e6769e234..000000000000 --- a/drivers/staging/octeon/cvmx-helper-xaui.c +++ /dev/null @@ -1,348 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Functions for XAUI initialization, configuration, - * and monitoring. - * - */ - -#include - -#include "cvmx-config.h" - -#include "cvmx-helper.h" - -#include "cvmx-pko-defs.h" -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsxx-defs.h" - -void __cvmx_interrupt_gmxx_enable(int interface); -void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); -void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); -/** - * Probe a XAUI interface and determine the number of ports - * connected to it. The XAUI interface should still be down - * after this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -int __cvmx_helper_xaui_probe(int interface) -{ - int i; - union cvmx_gmxx_hg2_control gmx_hg2_control; - union cvmx_gmxx_inf_mode mode; - - /* - * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the - * interface needs to be enabled before IPD otherwise per port - * backpressure may not work properly. - */ - mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); - mode.s.en = 1; - cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); - - __cvmx_helper_setup_gmx(interface, 1); - - /* - * Setup PKO to support 16 ports for HiGig2 virtual - * ports. We're pointing all of the PKO packet ports for this - * interface to the XAUI. This allows us to use HiGig2 - * backpressure per port. - */ - for (i = 0; i < 16; i++) { - union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs; - pko_mem_port_ptrs.u64 = 0; - /* - * We set each PKO port to have equal priority in a - * round robin fashion. - */ - pko_mem_port_ptrs.s.static_p = 0; - pko_mem_port_ptrs.s.qos_mask = 0xff; - /* All PKO ports map to the same XAUI hardware port */ - pko_mem_port_ptrs.s.eid = interface * 4; - pko_mem_port_ptrs.s.pid = interface * 16 + i; - cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); - } - - /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ - gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); - if (gmx_hg2_control.s.hg2tx_en) - return 16; - else - return 1; -} - -/** - * Bringup and enable a XAUI interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_xaui_enable(int interface) -{ - union cvmx_gmxx_prtx_cfg gmx_cfg; - union cvmx_pcsxx_control1_reg xauiCtl; - union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl; - union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl; - union cvmx_gmxx_rxx_int_en gmx_rx_int_en; - union cvmx_gmxx_tx_int_en gmx_tx_int_en; - union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; - - /* (1) Interface has already been enabled. */ - - /* (2) Disable GMX. */ - xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface)); - xauiMiscCtl.s.gmxeno = 1; - cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); - - /* (3) Disable GMX and PCSX interrupts. */ - gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface)); - cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); - gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface)); - cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); - pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface)); - cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); - - /* (4) Bring up the PCSX and GMX reconciliation layer. */ - /* (4)a Set polarity and lane swapping. */ - /* (4)b */ - gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); - /* Enable better IFG packing and improves performance */ - gmxXauiTxCtl.s.dic_en = 1; - gmxXauiTxCtl.s.uni_en = 0; - cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); - - /* (4)c Aply reset sequence */ - xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); - xauiCtl.s.lo_pwr = 0; - xauiCtl.s.reset = 1; - cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64); - - /* Wait for PCS to come out of reset */ - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg, - reset, ==, 0, 10000)) - return -1; - /* Wait for PCS to be aligned */ - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_PCSXX_10GBX_STATUS_REG(interface), - union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000)) - return -1; - /* Wait for RX to be ready */ - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl, - status, ==, 0, 10000)) - return -1; - - /* (6) Configure GMX */ - gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); - gmx_cfg.s.en = 0; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); - - /* Wait for GMX RX to be idle */ - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, - rx_idle, ==, 1, 10000)) - return -1; - /* Wait for GMX TX to be idle */ - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, - tx_idle, ==, 1, 10000)) - return -1; - - /* GMX configure */ - gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); - gmx_cfg.s.speed = 1; - gmx_cfg.s.speed_msb = 0; - gmx_cfg.s.slottime = 1; - cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1); - cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512); - cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192); - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); - - /* (7) Clear out any error state */ - cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface), - cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface))); - cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), - cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface))); - cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), - cvmx_read_csr(CVMX_PCSXX_INT_REG(interface))); - - /* Wait for receive link */ - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg, - rcv_lnk, ==, 1, 10000)) - return -1; - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, - xmtflt, ==, 0, 10000)) - return -1; - if (CVMX_WAIT_FOR_FIELD64 - (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, - rcvflt, ==, 0, 10000)) - return -1; - - cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64); - cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); - cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64); - - cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0)); - - /* (8) Enable packet reception */ - xauiMiscCtl.s.gmxeno = 0; - cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); - - gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); - gmx_cfg.s.en = 1; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); - - __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface); - __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface); - __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface); - __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface); - __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); - __cvmx_interrupt_gmxx_enable(interface); - - return 0; -} - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port) -{ - int interface = cvmx_helper_get_interface_num(ipd_port); - union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; - union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; - union cvmx_pcsxx_status1_reg pcsxx_status1_reg; - cvmx_helper_link_info_t result; - - gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); - gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); - pcsxx_status1_reg.u64 = - cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface)); - result.u64 = 0; - - /* Only return a link if both RX and TX are happy */ - if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) && - (pcsxx_status1_reg.s.rcv_lnk == 1)) { - result.s.link_up = 1; - result.s.full_duplex = 1; - result.s.speed = 10000; - } else { - /* Disable GMX and PCSX interrupts. */ - cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); - cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); - cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); - } - return result; -} - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info) -{ - int interface = cvmx_helper_get_interface_num(ipd_port); - union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; - union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; - - gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); - gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); - - /* If the link shouldn't be up, then just return */ - if (!link_info.s.link_up) - return 0; - - /* Do nothing if both RX and TX are happy */ - if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0)) - return 0; - - /* Bring the link up */ - return __cvmx_helper_xaui_enable(interface); -} - -/** - * Configure a port for internal and/or external loopback. Internal loopback - * causes packets sent by the port to be received by Octeon. External loopback - * causes packets received from the wire to sent out again. - * - * @ipd_port: IPD/PKO port to loopback. - * @enable_internal: - * Non zero if you want internal loopback - * @enable_external: - * Non zero if you want external loopback - * - * Returns Zero on success, negative on failure. - */ -extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, - int enable_internal, - int enable_external) -{ - int interface = cvmx_helper_get_interface_num(ipd_port); - union cvmx_pcsxx_control1_reg pcsxx_control1_reg; - union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback; - - /* Set the internal loop */ - pcsxx_control1_reg.u64 = - cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); - pcsxx_control1_reg.s.loopbck1 = enable_internal; - cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), - pcsxx_control1_reg.u64); - - /* Set the external loop */ - gmxx_xaui_ext_loopback.u64 = - cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface)); - gmxx_xaui_ext_loopback.s.en = enable_external; - cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), - gmxx_xaui_ext_loopback.u64); - - /* Take the link through a reset */ - return __cvmx_helper_xaui_enable(interface); -} diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/drivers/staging/octeon/cvmx-helper-xaui.h deleted file mode 100644 index 4b4db2f93cd4..000000000000 --- a/drivers/staging/octeon/cvmx-helper-xaui.h +++ /dev/null @@ -1,103 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * @file - * - * Functions for XAUI initialization, configuration, - * and monitoring. - * - */ -#ifndef __CVMX_HELPER_XAUI_H__ -#define __CVMX_HELPER_XAUI_H__ - -/** - * Probe a XAUI interface and determine the number of ports - * connected to it. The XAUI interface should still be down - * after this call. - * - * @interface: Interface to probe - * - * Returns Number of ports on the interface. Zero to disable. - */ -extern int __cvmx_helper_xaui_probe(int interface); - -/** - * Bringup and enable a XAUI interface. After this call packet - * I/O should be fully functional. This is called with IPD - * enabled but PKO disabled. - * - * @interface: Interface to bring up - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_xaui_enable(int interface); - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port); - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -extern int __cvmx_helper_xaui_link_set(int ipd_port, - cvmx_helper_link_info_t link_info); - -/** - * Configure a port for internal and/or external loopback. Internal loopback - * causes packets sent by the port to be received by Octeon. External loopback - * causes packets received from the wire to sent out again. - * - * @ipd_port: IPD/PKO port to loopback. - * @enable_internal: - * Non zero if you want internal loopback - * @enable_external: - * Non zero if you want external loopback - * - * Returns Zero on success, negative on failure. - */ -extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, - int enable_internal, - int enable_external); -#endif diff --git a/drivers/staging/octeon/cvmx-helper.c b/drivers/staging/octeon/cvmx-helper.c deleted file mode 100644 index e9c5c836ceff..000000000000 --- a/drivers/staging/octeon/cvmx-helper.c +++ /dev/null @@ -1,1058 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Helper functions for common, but complicated tasks. - * - */ -#include - -#include "cvmx-config.h" - -#include "cvmx-fpa.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-ipd.h" -#include "cvmx-spi.h" -#include "cvmx-helper.h" -#include "cvmx-helper-board.h" - -#include "cvmx-pip-defs.h" -#include "cvmx-smix-defs.h" -#include "cvmx-asxx-defs.h" - -/** - * cvmx_override_pko_queue_priority(int ipd_port, uint64_t - * priorities[16]) is a function pointer. It is meant to allow - * customization of the PKO queue priorities based on the port - * number. Users should set this pointer to a function before - * calling any cvmx-helper operations. - */ -void (*cvmx_override_pko_queue_priority) (int pko_port, - uint64_t priorities[16]); - -/** - * cvmx_override_ipd_port_setup(int ipd_port) is a function - * pointer. It is meant to allow customization of the IPD port - * setup before packet input/output comes online. It is called - * after cvmx-helper does the default IPD configuration, but - * before IPD is enabled. Users should set this pointer to a - * function before calling any cvmx-helper operations. - */ -void (*cvmx_override_ipd_port_setup) (int ipd_port); - -/* Port count per interface */ -static int interface_port_count[4] = { 0, 0, 0, 0 }; - -/* Port last configured link info index by IPD/PKO port */ -static cvmx_helper_link_info_t - port_link_info[CVMX_PIP_NUM_INPUT_PORTS]; - -/** - * Return the number of interfaces the chip has. Each interface - * may have multiple ports. Most chips support two interfaces, - * but the CNX0XX and CNX1XX are exceptions. These only support - * one interface. - * - * Returns Number of interfaces on chip - */ -int cvmx_helper_get_number_of_interfaces(void) -{ - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) - return 4; - else - return 3; -} - -/** - * Return the number of ports on an interface. Depending on the - * chip and configuration, this can be 1-16. A value of 0 - * specifies that the interface doesn't exist or isn't usable. - * - * @interface: Interface to get the port count for - * - * Returns Number of ports on interface. Can be Zero. - */ -int cvmx_helper_ports_on_interface(int interface) -{ - return interface_port_count[interface]; -} - -/** - * Get the operating mode of an interface. Depending on the Octeon - * chip and configuration, this function returns an enumeration - * of the type of packet I/O supported by an interface. - * - * @interface: Interface to probe - * - * Returns Mode of the interface. Unknown or unsupported interfaces return - * DISABLED. - */ -cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) -{ - union cvmx_gmxx_inf_mode mode; - if (interface == 2) - return CVMX_HELPER_INTERFACE_MODE_NPI; - - if (interface == 3) { - if (OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) - return CVMX_HELPER_INTERFACE_MODE_LOOP; - else - return CVMX_HELPER_INTERFACE_MODE_DISABLED; - } - - if (interface == 0 - && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 - && cvmx_sysinfo_get()->board_rev_major == 1) { - /* - * Lie about interface type of CN3005 board. This - * board has a switch on port 1 like the other - * evaluation boards, but it is connected over RGMII - * instead of GMII. Report GMII mode so that the - * speed is forced to 1 Gbit full duplex. Other than - * some initial configuration (which does not use the - * output of this function) there is no difference in - * setup between GMII and RGMII modes. - */ - return CVMX_HELPER_INTERFACE_MODE_GMII; - } - - /* Interface 1 is always disabled on CN31XX and CN30XX */ - if ((interface == 1) - && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) - || OCTEON_IS_MODEL(OCTEON_CN50XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX))) - return CVMX_HELPER_INTERFACE_MODE_DISABLED; - - mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); - - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { - switch (mode.cn56xx.mode) { - case 0: - return CVMX_HELPER_INTERFACE_MODE_DISABLED; - case 1: - return CVMX_HELPER_INTERFACE_MODE_XAUI; - case 2: - return CVMX_HELPER_INTERFACE_MODE_SGMII; - case 3: - return CVMX_HELPER_INTERFACE_MODE_PICMG; - default: - return CVMX_HELPER_INTERFACE_MODE_DISABLED; - } - } else { - if (!mode.s.en) - return CVMX_HELPER_INTERFACE_MODE_DISABLED; - - if (mode.s.type) { - if (OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)) - return CVMX_HELPER_INTERFACE_MODE_SPI; - else - return CVMX_HELPER_INTERFACE_MODE_GMII; - } else - return CVMX_HELPER_INTERFACE_MODE_RGMII; - } -} - -/** - * Configure the IPD/PIP tagging and QoS options for a specific - * port. This function determines the POW work queue entry - * contents for a port. The setup performed here is controlled by - * the defines in executive-config.h. - * - * @ipd_port: Port to configure. This follows the IPD numbering, not the - * per interface numbering - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_port_setup_ipd(int ipd_port) -{ - union cvmx_pip_prt_cfgx port_config; - union cvmx_pip_prt_tagx tag_config; - - port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); - tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port)); - - /* Have each port go to a different POW queue */ - port_config.s.qos = ipd_port & 0x7; - - /* Process the headers and place the IP header in the work queue */ - port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE; - - tag_config.s.ip6_src_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP; - tag_config.s.ip6_dst_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_IP; - tag_config.s.ip6_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT; - tag_config.s.ip6_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT; - tag_config.s.ip6_nxth_flag = CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER; - tag_config.s.ip4_src_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP; - tag_config.s.ip4_dst_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_IP; - tag_config.s.ip4_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT; - tag_config.s.ip4_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT; - tag_config.s.ip4_pctl_flag = CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL; - tag_config.s.inc_prt_flag = CVMX_HELPER_INPUT_TAG_INPUT_PORT; - tag_config.s.tcp6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; - tag_config.s.tcp4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; - tag_config.s.ip6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; - tag_config.s.ip4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; - tag_config.s.non_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; - /* Put all packets in group 0. Other groups can be used by the app */ - tag_config.s.grp = 0; - - cvmx_pip_config_port(ipd_port, port_config, tag_config); - - /* Give the user a chance to override our setting for each port */ - if (cvmx_override_ipd_port_setup) - cvmx_override_ipd_port_setup(ipd_port); - - return 0; -} - -/** - * This function probes an interface to determine the actual - * number of hardware ports connected to it. It doesn't setup the - * ports or enable them. The main goal here is to set the global - * interface_port_count[interface] correctly. Hardware setup of the - * ports will be performed later. - * - * @interface: Interface to probe - * - * Returns Zero on success, negative on failure - */ -int cvmx_helper_interface_probe(int interface) -{ - /* At this stage in the game we don't want packets to be moving yet. - The following probe calls should perform hardware setup - needed to determine port counts. Receive must still be disabled */ - switch (cvmx_helper_interface_get_mode(interface)) { - /* These types don't support ports to IPD/PKO */ - case CVMX_HELPER_INTERFACE_MODE_DISABLED: - case CVMX_HELPER_INTERFACE_MODE_PCIE: - interface_port_count[interface] = 0; - break; - /* XAUI is a single high speed port */ - case CVMX_HELPER_INTERFACE_MODE_XAUI: - interface_port_count[interface] = - __cvmx_helper_xaui_probe(interface); - break; - /* - * RGMII/GMII/MII are all treated about the same. Most - * functions refer to these ports as RGMII. - */ - case CVMX_HELPER_INTERFACE_MODE_RGMII: - case CVMX_HELPER_INTERFACE_MODE_GMII: - interface_port_count[interface] = - __cvmx_helper_rgmii_probe(interface); - break; - /* - * SPI4 can have 1-16 ports depending on the device at - * the other end. - */ - case CVMX_HELPER_INTERFACE_MODE_SPI: - interface_port_count[interface] = - __cvmx_helper_spi_probe(interface); - break; - /* - * SGMII can have 1-4 ports depending on how many are - * hooked up. - */ - case CVMX_HELPER_INTERFACE_MODE_SGMII: - case CVMX_HELPER_INTERFACE_MODE_PICMG: - interface_port_count[interface] = - __cvmx_helper_sgmii_probe(interface); - break; - /* PCI target Network Packet Interface */ - case CVMX_HELPER_INTERFACE_MODE_NPI: - interface_port_count[interface] = - __cvmx_helper_npi_probe(interface); - break; - /* - * Special loopback only ports. These are not the same - * as other ports in loopback mode. - */ - case CVMX_HELPER_INTERFACE_MODE_LOOP: - interface_port_count[interface] = - __cvmx_helper_loop_probe(interface); - break; - } - - interface_port_count[interface] = - __cvmx_helper_board_interface_probe(interface, - interface_port_count - [interface]); - - /* Make sure all global variables propagate to other cores */ - CVMX_SYNCWS; - - return 0; -} - -/** - * Setup the IPD/PIP for the ports on an interface. Packet - * classification and tagging are set for every port on the - * interface. The number of ports on the interface must already - * have been probed. - * - * @interface: Interface to setup IPD/PIP for - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_interface_setup_ipd(int interface) -{ - int ipd_port = cvmx_helper_get_ipd_port(interface, 0); - int num_ports = interface_port_count[interface]; - - while (num_ports--) { - __cvmx_helper_port_setup_ipd(ipd_port); - ipd_port++; - } - return 0; -} - -/** - * Setup global setting for IPD/PIP not related to a specific - * interface or port. This must be called before IPD is enabled. - * - * Returns Zero on success, negative on failure. - */ -static int __cvmx_helper_global_setup_ipd(void) -{ - /* Setup the global packet input options */ - cvmx_ipd_config(CVMX_FPA_PACKET_POOL_SIZE / 8, - CVMX_HELPER_FIRST_MBUFF_SKIP / 8, - CVMX_HELPER_NOT_FIRST_MBUFF_SKIP / 8, - /* The +8 is to account for the next ptr */ - (CVMX_HELPER_FIRST_MBUFF_SKIP + 8) / 128, - /* The +8 is to account for the next ptr */ - (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP + 8) / 128, - CVMX_FPA_WQE_POOL, - CVMX_IPD_OPC_MODE_STT, - CVMX_HELPER_ENABLE_BACK_PRESSURE); - return 0; -} - -/** - * Setup the PKO for the ports on an interface. The number of - * queues per port and the priority of each PKO output queue - * is set here. PKO must be disabled when this function is called. - * - * @interface: Interface to setup PKO for - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_interface_setup_pko(int interface) -{ - /* - * Each packet output queue has an associated priority. The - * higher the priority, the more often it can send a packet. A - * priority of 8 means it can send in all 8 rounds of - * contention. We're going to make each queue one less than - * the last. The vector of priorities has been extended to - * support CN5xxx CPUs, where up to 16 queues can be - * associated to a port. To keep backward compatibility we - * don't change the initial 8 priorities and replicate them in - * the second half. With per-core PKO queues (PKO lockless - * operation) all queues have the same priority. - */ - uint64_t priorities[16] = - { 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 }; - - /* - * Setup the IPD/PIP and PKO for the ports discovered - * above. Here packet classification, tagging and output - * priorities are set. - */ - int ipd_port = cvmx_helper_get_ipd_port(interface, 0); - int num_ports = interface_port_count[interface]; - while (num_ports--) { - /* - * Give the user a chance to override the per queue - * priorities. - */ - if (cvmx_override_pko_queue_priority) - cvmx_override_pko_queue_priority(ipd_port, priorities); - - cvmx_pko_config_port(ipd_port, - cvmx_pko_get_base_queue_per_core(ipd_port, - 0), - cvmx_pko_get_num_queues(ipd_port), - priorities); - ipd_port++; - } - return 0; -} - -/** - * Setup global setting for PKO not related to a specific - * interface or port. This must be called before PKO is enabled. - * - * Returns Zero on success, negative on failure. - */ -static int __cvmx_helper_global_setup_pko(void) -{ - /* - * Disable tagwait FAU timeout. This needs to be done before - * anyone might start packet output using tags. - */ - union cvmx_iob_fau_timeout fau_to; - fau_to.u64 = 0; - fau_to.s.tout_val = 0xfff; - fau_to.s.tout_enb = 0; - cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); - return 0; -} - -/** - * Setup global backpressure setting. - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_global_setup_backpressure(void) -{ -#if CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE - /* Disable backpressure if configured to do so */ - /* Disable backpressure (pause frame) generation */ - int num_interfaces = cvmx_helper_get_number_of_interfaces(); - int interface; - for (interface = 0; interface < num_interfaces; interface++) { - switch (cvmx_helper_interface_get_mode(interface)) { - case CVMX_HELPER_INTERFACE_MODE_DISABLED: - case CVMX_HELPER_INTERFACE_MODE_PCIE: - case CVMX_HELPER_INTERFACE_MODE_NPI: - case CVMX_HELPER_INTERFACE_MODE_LOOP: - case CVMX_HELPER_INTERFACE_MODE_XAUI: - break; - case CVMX_HELPER_INTERFACE_MODE_RGMII: - case CVMX_HELPER_INTERFACE_MODE_GMII: - case CVMX_HELPER_INTERFACE_MODE_SPI: - case CVMX_HELPER_INTERFACE_MODE_SGMII: - case CVMX_HELPER_INTERFACE_MODE_PICMG: - cvmx_gmx_set_backpressure_override(interface, 0xf); - break; - } - } -#endif - - return 0; -} - -/** - * Enable packet input/output from the hardware. This function is - * called after all internal setup is complete and IPD is enabled. - * After this function completes, packets will be accepted from the - * hardware ports. PKO should still be disabled to make sure packets - * aren't sent out partially setup hardware. - * - * @interface: Interface to enable - * - * Returns Zero on success, negative on failure - */ -static int __cvmx_helper_packet_hardware_enable(int interface) -{ - int result = 0; - switch (cvmx_helper_interface_get_mode(interface)) { - /* These types don't support ports to IPD/PKO */ - case CVMX_HELPER_INTERFACE_MODE_DISABLED: - case CVMX_HELPER_INTERFACE_MODE_PCIE: - /* Nothing to do */ - break; - /* XAUI is a single high speed port */ - case CVMX_HELPER_INTERFACE_MODE_XAUI: - result = __cvmx_helper_xaui_enable(interface); - break; - /* - * RGMII/GMII/MII are all treated about the same. Most - * functions refer to these ports as RGMII - */ - case CVMX_HELPER_INTERFACE_MODE_RGMII: - case CVMX_HELPER_INTERFACE_MODE_GMII: - result = __cvmx_helper_rgmii_enable(interface); - break; - /* - * SPI4 can have 1-16 ports depending on the device at - * the other end - */ - case CVMX_HELPER_INTERFACE_MODE_SPI: - result = __cvmx_helper_spi_enable(interface); - break; - /* - * SGMII can have 1-4 ports depending on how many are - * hooked up - */ - case CVMX_HELPER_INTERFACE_MODE_SGMII: - case CVMX_HELPER_INTERFACE_MODE_PICMG: - result = __cvmx_helper_sgmii_enable(interface); - break; - /* PCI target Network Packet Interface */ - case CVMX_HELPER_INTERFACE_MODE_NPI: - result = __cvmx_helper_npi_enable(interface); - break; - /* - * Special loopback only ports. These are not the same - * as other ports in loopback mode - */ - case CVMX_HELPER_INTERFACE_MODE_LOOP: - result = __cvmx_helper_loop_enable(interface); - break; - } - result |= __cvmx_helper_board_hardware_enable(interface); - return result; -} - -/** - * Function to adjust internal IPD pointer alignments - * - * Returns 0 on success - * !0 on failure - */ -int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) -{ -#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \ - (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP) -#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \ - (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP) -#define FIX_IPD_OUTPORT 0 - /* Ports 0-15 are interface 0, 16-31 are interface 1 */ -#define INTERFACE(port) (port >> 4) -#define INDEX(port) (port & 0xf) - uint64_t *p64; - cvmx_pko_command_word0_t pko_command; - union cvmx_buf_ptr g_buffer, pkt_buffer; - cvmx_wqe_t *work; - int size, num_segs = 0, wqe_pcnt, pkt_pcnt; - union cvmx_gmxx_prtx_cfg gmx_cfg; - int retry_cnt; - int retry_loop_cnt; - int mtu; - int i; - cvmx_helper_link_info_t link_info; - - /* Save values for restore at end */ - uint64_t prtx_cfg = - cvmx_read_csr(CVMX_GMXX_PRTX_CFG - (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); - uint64_t tx_ptr_en = - cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); - uint64_t rx_ptr_en = - cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); - uint64_t rxx_jabber = - cvmx_read_csr(CVMX_GMXX_RXX_JABBER - (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); - uint64_t frame_max = - cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX - (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); - - /* Configure port to gig FDX as required for loopback mode */ - cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT); - - /* - * Disable reception on all ports so if traffic is present it - * will not interfere. - */ - cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); - - cvmx_wait(100000000ull); - - for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) { - retry_cnt = 100000; - wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT); - pkt_pcnt = (wqe_pcnt >> 7) & 0x7f; - wqe_pcnt &= 0x7f; - - num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3; - - if (num_segs == 0) - goto fix_ipd_exit; - - num_segs += 1; - - size = - FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES + - ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) - - (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2); - - cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), - 1 << INDEX(FIX_IPD_OUTPORT)); - CVMX_SYNC; - - g_buffer.u64 = 0; - g_buffer.s.addr = - cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL)); - if (g_buffer.s.addr == 0) { - cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " - "buffer allocation failure.\n"); - goto fix_ipd_exit; - } - - g_buffer.s.pool = CVMX_FPA_WQE_POOL; - g_buffer.s.size = num_segs; - - pkt_buffer.u64 = 0; - pkt_buffer.s.addr = - cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL)); - if (pkt_buffer.s.addr == 0) { - cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " - "buffer allocation failure.\n"); - goto fix_ipd_exit; - } - pkt_buffer.s.i = 1; - pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL; - pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES; - - p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr); - p64[0] = 0xffffffffffff0000ull; - p64[1] = 0x08004510ull; - p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull; - p64[3] = 0x3a5fc0a81073c0a8ull; - - for (i = 0; i < num_segs; i++) { - if (i > 0) - pkt_buffer.s.size = - FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES; - - if (i == (num_segs - 1)) - pkt_buffer.s.i = 0; - - *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr + - 8 * i) = pkt_buffer.u64; - } - - /* Build the PKO command */ - pko_command.u64 = 0; - pko_command.s.segs = num_segs; - pko_command.s.total_bytes = size; - pko_command.s.dontfree = 0; - pko_command.s.gather = 1; - - gmx_cfg.u64 = - cvmx_read_csr(CVMX_GMXX_PRTX_CFG - (INDEX(FIX_IPD_OUTPORT), - INTERFACE(FIX_IPD_OUTPORT))); - gmx_cfg.s.en = 1; - cvmx_write_csr(CVMX_GMXX_PRTX_CFG - (INDEX(FIX_IPD_OUTPORT), - INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64); - cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), - 1 << INDEX(FIX_IPD_OUTPORT)); - cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), - 1 << INDEX(FIX_IPD_OUTPORT)); - - mtu = - cvmx_read_csr(CVMX_GMXX_RXX_JABBER - (INDEX(FIX_IPD_OUTPORT), - INTERFACE(FIX_IPD_OUTPORT))); - cvmx_write_csr(CVMX_GMXX_RXX_JABBER - (INDEX(FIX_IPD_OUTPORT), - INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); - cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX - (INDEX(FIX_IPD_OUTPORT), - INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); - - cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT, - cvmx_pko_get_base_queue - (FIX_IPD_OUTPORT), - CVMX_PKO_LOCK_CMD_QUEUE); - cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT, - cvmx_pko_get_base_queue - (FIX_IPD_OUTPORT), pko_command, - g_buffer, CVMX_PKO_LOCK_CMD_QUEUE); - - CVMX_SYNC; - - do { - work = cvmx_pow_work_request_sync(CVMX_POW_WAIT); - retry_cnt--; - } while ((work == NULL) && (retry_cnt > 0)); - - if (!retry_cnt) - cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " - "get_work() timeout occurred.\n"); - - /* Free packet */ - if (work) - cvmx_helper_free_packet_data(work); - } - -fix_ipd_exit: - - /* Return CSR configs to saved values */ - cvmx_write_csr(CVMX_GMXX_PRTX_CFG - (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), - prtx_cfg); - cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), - tx_ptr_en); - cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), - rx_ptr_en); - cvmx_write_csr(CVMX_GMXX_RXX_JABBER - (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), - rxx_jabber); - cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX - (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), - frame_max); - cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0); - /* Set link to down so autonegotiation will set it up again */ - link_info.u64 = 0; - cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info); - - /* - * Bring the link back up as autonegotiation is not done in - * user applications. - */ - cvmx_helper_link_autoconf(FIX_IPD_OUTPORT); - - CVMX_SYNC; - if (num_segs) - cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n"); - - return !!num_segs; - -} - -/** - * Called after all internal packet IO paths are setup. This - * function enables IPD/PIP and begins packet input and output. - * - * Returns Zero on success, negative on failure - */ -int cvmx_helper_ipd_and_packet_input_enable(void) -{ - int num_interfaces; - int interface; - - /* Enable IPD */ - cvmx_ipd_enable(); - - /* - * Time to enable hardware ports packet input and output. Note - * that at this point IPD/PIP must be fully functional and PKO - * must be disabled - */ - num_interfaces = cvmx_helper_get_number_of_interfaces(); - for (interface = 0; interface < num_interfaces; interface++) { - if (cvmx_helper_ports_on_interface(interface) > 0) - __cvmx_helper_packet_hardware_enable(interface); - } - - /* Finally enable PKO now that the entire path is up and running */ - cvmx_pko_enable(); - - if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1) - || OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1)) - && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)) - __cvmx_helper_errata_fix_ipd_ptr_alignment(); - return 0; -} - -/** - * Initialize the PIP, IPD, and PKO hardware to support - * simple priority based queues for the ethernet ports. Each - * port is configured with a number of priority queues based - * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower - * priority than the previous. - * - * Returns Zero on success, non-zero on failure - */ -int cvmx_helper_initialize_packet_io_global(void) -{ - int result = 0; - int interface; - union cvmx_l2c_cfg l2c_cfg; - union cvmx_smix_en smix_en; - const int num_interfaces = cvmx_helper_get_number_of_interfaces(); - - /* - * CN52XX pass 1: Due to a bug in 2nd order CDR, it needs to - * be disabled. - */ - if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0)) - __cvmx_helper_errata_qlm_disable_2nd_order_cdr(1); - - /* - * Tell L2 to give the IOB statically higher priority compared - * to the cores. This avoids conditions where IO blocks might - * be starved under very high L2 loads. - */ - l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); - l2c_cfg.s.lrf_arb_mode = 0; - l2c_cfg.s.rfb_arb_mode = 0; - cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64); - - /* Make sure SMI/MDIO is enabled so we can query PHYs */ - smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0)); - if (!smix_en.s.en) { - smix_en.s.en = 1; - cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64); - } - - /* Newer chips actually have two SMI/MDIO interfaces */ - if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && - !OCTEON_IS_MODEL(OCTEON_CN58XX) && - !OCTEON_IS_MODEL(OCTEON_CN50XX)) { - smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1)); - if (!smix_en.s.en) { - smix_en.s.en = 1; - cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64); - } - } - - cvmx_pko_initialize_global(); - for (interface = 0; interface < num_interfaces; interface++) { - result |= cvmx_helper_interface_probe(interface); - if (cvmx_helper_ports_on_interface(interface) > 0) - cvmx_dprintf("Interface %d has %d ports (%s)\n", - interface, - cvmx_helper_ports_on_interface(interface), - cvmx_helper_interface_mode_to_string - (cvmx_helper_interface_get_mode - (interface))); - result |= __cvmx_helper_interface_setup_ipd(interface); - result |= __cvmx_helper_interface_setup_pko(interface); - } - - result |= __cvmx_helper_global_setup_ipd(); - result |= __cvmx_helper_global_setup_pko(); - - /* Enable any flow control and backpressure */ - result |= __cvmx_helper_global_setup_backpressure(); - -#if CVMX_HELPER_ENABLE_IPD - result |= cvmx_helper_ipd_and_packet_input_enable(); -#endif - return result; -} - -/** - * Does core local initialization for packet io - * - * Returns Zero on success, non-zero on failure - */ -int cvmx_helper_initialize_packet_io_local(void) -{ - return cvmx_pko_initialize_local(); -} - -/** - * Auto configure an IPD/PKO port link state and speed. This - * function basically does the equivalent of: - * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); - * - * @ipd_port: IPD/PKO port to auto configure - * - * Returns Link state after configure - */ -cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port) -{ - cvmx_helper_link_info_t link_info; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - - if (index >= cvmx_helper_ports_on_interface(interface)) { - link_info.u64 = 0; - return link_info; - } - - link_info = cvmx_helper_link_get(ipd_port); - if (link_info.u64 == port_link_info[ipd_port].u64) - return link_info; - - /* If we fail to set the link speed, port_link_info will not change */ - cvmx_helper_link_set(ipd_port, link_info); - - /* - * port_link_info should be the current value, which will be - * different than expect if cvmx_helper_link_set() failed. - */ - return port_link_info[ipd_port]; -} - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port) -{ - cvmx_helper_link_info_t result; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - - /* The default result will be a down link unless the code below - changes it */ - result.u64 = 0; - - if (index >= cvmx_helper_ports_on_interface(interface)) - return result; - - switch (cvmx_helper_interface_get_mode(interface)) { - case CVMX_HELPER_INTERFACE_MODE_DISABLED: - case CVMX_HELPER_INTERFACE_MODE_PCIE: - /* Network links are not supported */ - break; - case CVMX_HELPER_INTERFACE_MODE_XAUI: - result = __cvmx_helper_xaui_link_get(ipd_port); - break; - case CVMX_HELPER_INTERFACE_MODE_GMII: - if (index == 0) - result = __cvmx_helper_rgmii_link_get(ipd_port); - else { - result.s.full_duplex = 1; - result.s.link_up = 1; - result.s.speed = 1000; - } - break; - case CVMX_HELPER_INTERFACE_MODE_RGMII: - result = __cvmx_helper_rgmii_link_get(ipd_port); - break; - case CVMX_HELPER_INTERFACE_MODE_SPI: - result = __cvmx_helper_spi_link_get(ipd_port); - break; - case CVMX_HELPER_INTERFACE_MODE_SGMII: - case CVMX_HELPER_INTERFACE_MODE_PICMG: - result = __cvmx_helper_sgmii_link_get(ipd_port); - break; - case CVMX_HELPER_INTERFACE_MODE_NPI: - case CVMX_HELPER_INTERFACE_MODE_LOOP: - /* Network links are not supported */ - break; - } - return result; -} - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info) -{ - int result = -1; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - - if (index >= cvmx_helper_ports_on_interface(interface)) - return -1; - - switch (cvmx_helper_interface_get_mode(interface)) { - case CVMX_HELPER_INTERFACE_MODE_DISABLED: - case CVMX_HELPER_INTERFACE_MODE_PCIE: - break; - case CVMX_HELPER_INTERFACE_MODE_XAUI: - result = __cvmx_helper_xaui_link_set(ipd_port, link_info); - break; - /* - * RGMII/GMII/MII are all treated about the same. Most - * functions refer to these ports as RGMII. - */ - case CVMX_HELPER_INTERFACE_MODE_RGMII: - case CVMX_HELPER_INTERFACE_MODE_GMII: - result = __cvmx_helper_rgmii_link_set(ipd_port, link_info); - break; - case CVMX_HELPER_INTERFACE_MODE_SPI: - result = __cvmx_helper_spi_link_set(ipd_port, link_info); - break; - case CVMX_HELPER_INTERFACE_MODE_SGMII: - case CVMX_HELPER_INTERFACE_MODE_PICMG: - result = __cvmx_helper_sgmii_link_set(ipd_port, link_info); - break; - case CVMX_HELPER_INTERFACE_MODE_NPI: - case CVMX_HELPER_INTERFACE_MODE_LOOP: - break; - } - /* Set the port_link_info here so that the link status is updated - no matter how cvmx_helper_link_set is called. We don't change - the value if link_set failed */ - if (result == 0) - port_link_info[ipd_port].u64 = link_info.u64; - return result; -} - -/** - * Configure a port for internal and/or external loopback. Internal loopback - * causes packets sent by the port to be received by Octeon. External loopback - * causes packets received from the wire to sent out again. - * - * @ipd_port: IPD/PKO port to loopback. - * @enable_internal: - * Non zero if you want internal loopback - * @enable_external: - * Non zero if you want external loopback - * - * Returns Zero on success, negative on failure. - */ -int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, - int enable_external) -{ - int result = -1; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - - if (index >= cvmx_helper_ports_on_interface(interface)) - return -1; - - switch (cvmx_helper_interface_get_mode(interface)) { - case CVMX_HELPER_INTERFACE_MODE_DISABLED: - case CVMX_HELPER_INTERFACE_MODE_PCIE: - case CVMX_HELPER_INTERFACE_MODE_SPI: - case CVMX_HELPER_INTERFACE_MODE_NPI: - case CVMX_HELPER_INTERFACE_MODE_LOOP: - break; - case CVMX_HELPER_INTERFACE_MODE_XAUI: - result = - __cvmx_helper_xaui_configure_loopback(ipd_port, - enable_internal, - enable_external); - break; - case CVMX_HELPER_INTERFACE_MODE_RGMII: - case CVMX_HELPER_INTERFACE_MODE_GMII: - result = - __cvmx_helper_rgmii_configure_loopback(ipd_port, - enable_internal, - enable_external); - break; - case CVMX_HELPER_INTERFACE_MODE_SGMII: - case CVMX_HELPER_INTERFACE_MODE_PICMG: - result = - __cvmx_helper_sgmii_configure_loopback(ipd_port, - enable_internal, - enable_external); - break; - } - return result; -} diff --git a/drivers/staging/octeon/cvmx-helper.h b/drivers/staging/octeon/cvmx-helper.h deleted file mode 100644 index 51916f3cc40c..000000000000 --- a/drivers/staging/octeon/cvmx-helper.h +++ /dev/null @@ -1,227 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Helper functions for common, but complicated tasks. - * - */ - -#ifndef __CVMX_HELPER_H__ -#define __CVMX_HELPER_H__ - -#include "cvmx-config.h" -#include "cvmx-fpa.h" -#include "cvmx-wqe.h" - -typedef enum { - CVMX_HELPER_INTERFACE_MODE_DISABLED, - CVMX_HELPER_INTERFACE_MODE_RGMII, - CVMX_HELPER_INTERFACE_MODE_GMII, - CVMX_HELPER_INTERFACE_MODE_SPI, - CVMX_HELPER_INTERFACE_MODE_PCIE, - CVMX_HELPER_INTERFACE_MODE_XAUI, - CVMX_HELPER_INTERFACE_MODE_SGMII, - CVMX_HELPER_INTERFACE_MODE_PICMG, - CVMX_HELPER_INTERFACE_MODE_NPI, - CVMX_HELPER_INTERFACE_MODE_LOOP, -} cvmx_helper_interface_mode_t; - -typedef union { - uint64_t u64; - struct { - uint64_t reserved_20_63:44; - uint64_t link_up:1; /**< Is the physical link up? */ - uint64_t full_duplex:1; /**< 1 if the link is full duplex */ - uint64_t speed:18; /**< Speed of the link in Mbps */ - } s; -} cvmx_helper_link_info_t; - -#include "cvmx-helper-fpa.h" - -#include -#include "cvmx-helper-loop.h" -#include "cvmx-helper-npi.h" -#include "cvmx-helper-rgmii.h" -#include "cvmx-helper-sgmii.h" -#include "cvmx-helper-spi.h" -#include "cvmx-helper-util.h" -#include "cvmx-helper-xaui.h" - -/** - * cvmx_override_pko_queue_priority(int ipd_port, uint64_t - * priorities[16]) is a function pointer. It is meant to allow - * customization of the PKO queue priorities based on the port - * number. Users should set this pointer to a function before - * calling any cvmx-helper operations. - */ -extern void (*cvmx_override_pko_queue_priority) (int pko_port, - uint64_t priorities[16]); - -/** - * cvmx_override_ipd_port_setup(int ipd_port) is a function - * pointer. It is meant to allow customization of the IPD port - * setup before packet input/output comes online. It is called - * after cvmx-helper does the default IPD configuration, but - * before IPD is enabled. Users should set this pointer to a - * function before calling any cvmx-helper operations. - */ -extern void (*cvmx_override_ipd_port_setup) (int ipd_port); - -/** - * This function enables the IPD and also enables the packet interfaces. - * The packet interfaces (RGMII and SPI) must be enabled after the - * IPD. This should be called by the user program after any additional - * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD - * is not set in the executive-config.h file. - * - * Returns 0 on success - * -1 on failure - */ -extern int cvmx_helper_ipd_and_packet_input_enable(void); - -/** - * Initialize the PIP, IPD, and PKO hardware to support - * simple priority based queues for the ethernet ports. Each - * port is configured with a number of priority queues based - * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower - * priority than the previous. - * - * Returns Zero on success, non-zero on failure - */ -extern int cvmx_helper_initialize_packet_io_global(void); - -/** - * Does core local initialization for packet io - * - * Returns Zero on success, non-zero on failure - */ -extern int cvmx_helper_initialize_packet_io_local(void); - -/** - * Returns the number of ports on the given interface. - * The interface must be initialized before the port count - * can be returned. - * - * @interface: Which interface to return port count for. - * - * Returns Port count for interface - * -1 for uninitialized interface - */ -extern int cvmx_helper_ports_on_interface(int interface); - -/** - * Return the number of interfaces the chip has. Each interface - * may have multiple ports. Most chips support two interfaces, - * but the CNX0XX and CNX1XX are exceptions. These only support - * one interface. - * - * Returns Number of interfaces on chip - */ -extern int cvmx_helper_get_number_of_interfaces(void); - -/** - * Get the operating mode of an interface. Depending on the Octeon - * chip and configuration, this function returns an enumeration - * of the type of packet I/O supported by an interface. - * - * @interface: Interface to probe - * - * Returns Mode of the interface. Unknown or unsupported interfaces return - * DISABLED. - */ -extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int - interface); - -/** - * Auto configure an IPD/PKO port link state and speed. This - * function basically does the equivalent of: - * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); - * - * @ipd_port: IPD/PKO port to auto configure - * - * Returns Link state after configure - */ -extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port); - -/** - * Return the link state of an IPD/PKO port as returned by - * auto negotiation. The result of this function may not match - * Octeon's link config if auto negotiation has changed since - * the last call to cvmx_helper_link_set(). - * - * @ipd_port: IPD/PKO port to query - * - * Returns Link state - */ -extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port); - -/** - * Configure an IPD/PKO port for the specified link state. This - * function does not influence auto negotiation at the PHY level. - * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. - * - * @ipd_port: IPD/PKO port to configure - * @link_info: The new link state - * - * Returns Zero on success, negative on failure - */ -extern int cvmx_helper_link_set(int ipd_port, - cvmx_helper_link_info_t link_info); - -/** - * This function probes an interface to determine the actual - * number of hardware ports connected to it. It doesn't setup the - * ports or enable them. The main goal here is to set the global - * interface_port_count[interface] correctly. Hardware setup of the - * ports will be performed later. - * - * @interface: Interface to probe - * - * Returns Zero on success, negative on failure - */ -extern int cvmx_helper_interface_probe(int interface); - -/** - * Configure a port for internal and/or external loopback. Internal loopback - * causes packets sent by the port to be received by Octeon. External loopback - * causes packets received from the wire to sent out again. - * - * @ipd_port: IPD/PKO port to loopback. - * @enable_internal: - * Non zero if you want internal loopback - * @enable_external: - * Non zero if you want external loopback - * - * Returns Zero on success, negative on failure. - */ -extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, - int enable_external); - -#endif /* __CVMX_HELPER_H__ */ diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/drivers/staging/octeon/cvmx-interrupt-decodes.c deleted file mode 100644 index a3337e382ee9..000000000000 --- a/drivers/staging/octeon/cvmx-interrupt-decodes.c +++ /dev/null @@ -1,371 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2009 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Automatically generated functions useful for enabling - * and decoding RSL_INT_BLOCKS interrupts. - * - */ - -#include - -#include "cvmx-gmxx-defs.h" -#include "cvmx-pcsx-defs.h" -#include "cvmx-pcsxx-defs.h" -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" - -#ifndef PRINT_ERROR -#define PRINT_ERROR(format, ...) -#endif - - -/** - * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t - */ -void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) -{ - union cvmx_gmxx_rxx_int_en gmx_rx_int_en; - cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), - cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); - gmx_rx_int_en.u64 = 0; - if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { - /* Skipping gmx_rx_int_en.s.reserved_29_63 */ - gmx_rx_int_en.s.hg2cc = 1; - gmx_rx_int_en.s.hg2fld = 1; - gmx_rx_int_en.s.undat = 1; - gmx_rx_int_en.s.uneop = 1; - gmx_rx_int_en.s.unsop = 1; - gmx_rx_int_en.s.bad_term = 1; - gmx_rx_int_en.s.bad_seq = 1; - gmx_rx_int_en.s.rem_fault = 1; - gmx_rx_int_en.s.loc_fault = 1; - gmx_rx_int_en.s.pause_drp = 1; - /* Skipping gmx_rx_int_en.s.reserved_16_18 */ - /*gmx_rx_int_en.s.ifgerr = 1; */ - /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ - /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ - /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ - /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ - gmx_rx_int_en.s.ovrerr = 1; - /* Skipping gmx_rx_int_en.s.reserved_9_9 */ - gmx_rx_int_en.s.skperr = 1; - gmx_rx_int_en.s.rcverr = 1; - /* Skipping gmx_rx_int_en.s.reserved_5_6 */ - /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ - gmx_rx_int_en.s.jabber = 1; - /* Skipping gmx_rx_int_en.s.reserved_2_2 */ - gmx_rx_int_en.s.carext = 1; - /* Skipping gmx_rx_int_en.s.reserved_0_0 */ - } - if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { - /* Skipping gmx_rx_int_en.s.reserved_19_63 */ - /*gmx_rx_int_en.s.phy_dupx = 1; */ - /*gmx_rx_int_en.s.phy_spd = 1; */ - /*gmx_rx_int_en.s.phy_link = 1; */ - /*gmx_rx_int_en.s.ifgerr = 1; */ - /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ - /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ - /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ - /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ - gmx_rx_int_en.s.ovrerr = 1; - gmx_rx_int_en.s.niberr = 1; - gmx_rx_int_en.s.skperr = 1; - gmx_rx_int_en.s.rcverr = 1; - /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ - gmx_rx_int_en.s.alnerr = 1; - /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ - gmx_rx_int_en.s.jabber = 1; - gmx_rx_int_en.s.maxerr = 1; - gmx_rx_int_en.s.carext = 1; - gmx_rx_int_en.s.minerr = 1; - } - if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { - /* Skipping gmx_rx_int_en.s.reserved_20_63 */ - gmx_rx_int_en.s.pause_drp = 1; - /*gmx_rx_int_en.s.phy_dupx = 1; */ - /*gmx_rx_int_en.s.phy_spd = 1; */ - /*gmx_rx_int_en.s.phy_link = 1; */ - /*gmx_rx_int_en.s.ifgerr = 1; */ - /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ - /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ - /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ - /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ - gmx_rx_int_en.s.ovrerr = 1; - gmx_rx_int_en.s.niberr = 1; - gmx_rx_int_en.s.skperr = 1; - gmx_rx_int_en.s.rcverr = 1; - /* Skipping gmx_rx_int_en.s.reserved_6_6 */ - gmx_rx_int_en.s.alnerr = 1; - /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ - gmx_rx_int_en.s.jabber = 1; - /* Skipping gmx_rx_int_en.s.reserved_2_2 */ - gmx_rx_int_en.s.carext = 1; - /* Skipping gmx_rx_int_en.s.reserved_0_0 */ - } - if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { - /* Skipping gmx_rx_int_en.s.reserved_19_63 */ - /*gmx_rx_int_en.s.phy_dupx = 1; */ - /*gmx_rx_int_en.s.phy_spd = 1; */ - /*gmx_rx_int_en.s.phy_link = 1; */ - /*gmx_rx_int_en.s.ifgerr = 1; */ - /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ - /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ - /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ - /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ - gmx_rx_int_en.s.ovrerr = 1; - gmx_rx_int_en.s.niberr = 1; - gmx_rx_int_en.s.skperr = 1; - gmx_rx_int_en.s.rcverr = 1; - /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ - gmx_rx_int_en.s.alnerr = 1; - /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ - gmx_rx_int_en.s.jabber = 1; - gmx_rx_int_en.s.maxerr = 1; - gmx_rx_int_en.s.carext = 1; - gmx_rx_int_en.s.minerr = 1; - } - if (OCTEON_IS_MODEL(OCTEON_CN31XX)) { - /* Skipping gmx_rx_int_en.s.reserved_19_63 */ - /*gmx_rx_int_en.s.phy_dupx = 1; */ - /*gmx_rx_int_en.s.phy_spd = 1; */ - /*gmx_rx_int_en.s.phy_link = 1; */ - /*gmx_rx_int_en.s.ifgerr = 1; */ - /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ - /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ - /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ - /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ - gmx_rx_int_en.s.ovrerr = 1; - gmx_rx_int_en.s.niberr = 1; - gmx_rx_int_en.s.skperr = 1; - gmx_rx_int_en.s.rcverr = 1; - /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ - gmx_rx_int_en.s.alnerr = 1; - /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ - gmx_rx_int_en.s.jabber = 1; - gmx_rx_int_en.s.maxerr = 1; - gmx_rx_int_en.s.carext = 1; - gmx_rx_int_en.s.minerr = 1; - } - if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { - /* Skipping gmx_rx_int_en.s.reserved_20_63 */ - gmx_rx_int_en.s.pause_drp = 1; - /*gmx_rx_int_en.s.phy_dupx = 1; */ - /*gmx_rx_int_en.s.phy_spd = 1; */ - /*gmx_rx_int_en.s.phy_link = 1; */ - /*gmx_rx_int_en.s.ifgerr = 1; */ - /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ - /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ - /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ - /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ - gmx_rx_int_en.s.ovrerr = 1; - gmx_rx_int_en.s.niberr = 1; - gmx_rx_int_en.s.skperr = 1; - gmx_rx_int_en.s.rcverr = 1; - /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ - gmx_rx_int_en.s.alnerr = 1; - /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ - gmx_rx_int_en.s.jabber = 1; - gmx_rx_int_en.s.maxerr = 1; - gmx_rx_int_en.s.carext = 1; - gmx_rx_int_en.s.minerr = 1; - } - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { - /* Skipping gmx_rx_int_en.s.reserved_29_63 */ - gmx_rx_int_en.s.hg2cc = 1; - gmx_rx_int_en.s.hg2fld = 1; - gmx_rx_int_en.s.undat = 1; - gmx_rx_int_en.s.uneop = 1; - gmx_rx_int_en.s.unsop = 1; - gmx_rx_int_en.s.bad_term = 1; - gmx_rx_int_en.s.bad_seq = 0; - gmx_rx_int_en.s.rem_fault = 1; - gmx_rx_int_en.s.loc_fault = 0; - gmx_rx_int_en.s.pause_drp = 1; - /* Skipping gmx_rx_int_en.s.reserved_16_18 */ - /*gmx_rx_int_en.s.ifgerr = 1; */ - /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ - /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ - /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ - /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ - gmx_rx_int_en.s.ovrerr = 1; - /* Skipping gmx_rx_int_en.s.reserved_9_9 */ - gmx_rx_int_en.s.skperr = 1; - gmx_rx_int_en.s.rcverr = 1; - /* Skipping gmx_rx_int_en.s.reserved_5_6 */ - /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ - gmx_rx_int_en.s.jabber = 1; - /* Skipping gmx_rx_int_en.s.reserved_2_2 */ - gmx_rx_int_en.s.carext = 1; - /* Skipping gmx_rx_int_en.s.reserved_0_0 */ - } - cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); -} -/** - * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t - */ -void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block) -{ - union cvmx_pcsx_intx_en_reg pcs_int_en_reg; - cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), - cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); - pcs_int_en_reg.u64 = 0; - if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { - /* Skipping pcs_int_en_reg.s.reserved_12_63 */ - /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ - pcs_int_en_reg.s.sync_bad_en = 1; - pcs_int_en_reg.s.an_bad_en = 1; - pcs_int_en_reg.s.rxlock_en = 1; - pcs_int_en_reg.s.rxbad_en = 1; - /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ - pcs_int_en_reg.s.txbad_en = 1; - pcs_int_en_reg.s.txfifo_en = 1; - pcs_int_en_reg.s.txfifu_en = 1; - pcs_int_en_reg.s.an_err_en = 1; - /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ - /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ - } - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { - /* Skipping pcs_int_en_reg.s.reserved_12_63 */ - /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ - pcs_int_en_reg.s.sync_bad_en = 1; - pcs_int_en_reg.s.an_bad_en = 1; - pcs_int_en_reg.s.rxlock_en = 1; - pcs_int_en_reg.s.rxbad_en = 1; - /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ - pcs_int_en_reg.s.txbad_en = 1; - pcs_int_en_reg.s.txfifo_en = 1; - pcs_int_en_reg.s.txfifu_en = 1; - pcs_int_en_reg.s.an_err_en = 1; - /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ - /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ - } - cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); -} -/** - * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t - */ -void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index) -{ - union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; - cvmx_write_csr(CVMX_PCSXX_INT_REG(index), - cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); - pcsx_int_en_reg.u64 = 0; - if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { - /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ - pcsx_int_en_reg.s.algnlos_en = 1; - pcsx_int_en_reg.s.synlos_en = 1; - pcsx_int_en_reg.s.bitlckls_en = 1; - pcsx_int_en_reg.s.rxsynbad_en = 1; - pcsx_int_en_reg.s.rxbad_en = 1; - pcsx_int_en_reg.s.txflt_en = 1; - } - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { - /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ - pcsx_int_en_reg.s.algnlos_en = 1; - pcsx_int_en_reg.s.synlos_en = 1; - pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */ - pcsx_int_en_reg.s.rxsynbad_en = 1; - pcsx_int_en_reg.s.rxbad_en = 1; - pcsx_int_en_reg.s.txflt_en = 1; - } - cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); -} - -/** - * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t - */ -void __cvmx_interrupt_spxx_int_msk_enable(int index) -{ - union cvmx_spxx_int_msk spx_int_msk; - cvmx_write_csr(CVMX_SPXX_INT_REG(index), - cvmx_read_csr(CVMX_SPXX_INT_REG(index))); - spx_int_msk.u64 = 0; - if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { - /* Skipping spx_int_msk.s.reserved_12_63 */ - spx_int_msk.s.calerr = 1; - spx_int_msk.s.syncerr = 1; - spx_int_msk.s.diperr = 1; - spx_int_msk.s.tpaovr = 1; - spx_int_msk.s.rsverr = 1; - spx_int_msk.s.drwnng = 1; - spx_int_msk.s.clserr = 1; - spx_int_msk.s.spiovr = 1; - /* Skipping spx_int_msk.s.reserved_2_3 */ - spx_int_msk.s.abnorm = 1; - spx_int_msk.s.prtnxa = 1; - } - if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { - /* Skipping spx_int_msk.s.reserved_12_63 */ - spx_int_msk.s.calerr = 1; - spx_int_msk.s.syncerr = 1; - spx_int_msk.s.diperr = 1; - spx_int_msk.s.tpaovr = 1; - spx_int_msk.s.rsverr = 1; - spx_int_msk.s.drwnng = 1; - spx_int_msk.s.clserr = 1; - spx_int_msk.s.spiovr = 1; - /* Skipping spx_int_msk.s.reserved_2_3 */ - spx_int_msk.s.abnorm = 1; - spx_int_msk.s.prtnxa = 1; - } - cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); -} -/** - * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t - */ -void __cvmx_interrupt_stxx_int_msk_enable(int index) -{ - union cvmx_stxx_int_msk stx_int_msk; - cvmx_write_csr(CVMX_STXX_INT_REG(index), - cvmx_read_csr(CVMX_STXX_INT_REG(index))); - stx_int_msk.u64 = 0; - if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { - /* Skipping stx_int_msk.s.reserved_8_63 */ - stx_int_msk.s.frmerr = 1; - stx_int_msk.s.unxfrm = 1; - stx_int_msk.s.nosync = 1; - stx_int_msk.s.diperr = 1; - stx_int_msk.s.datovr = 1; - stx_int_msk.s.ovrbst = 1; - stx_int_msk.s.calpar1 = 1; - stx_int_msk.s.calpar0 = 1; - } - if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { - /* Skipping stx_int_msk.s.reserved_8_63 */ - stx_int_msk.s.frmerr = 1; - stx_int_msk.s.unxfrm = 1; - stx_int_msk.s.nosync = 1; - stx_int_msk.s.diperr = 1; - stx_int_msk.s.datovr = 1; - stx_int_msk.s.ovrbst = 1; - stx_int_msk.s.calpar1 = 1; - stx_int_msk.s.calpar0 = 1; - } - cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); -} diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/drivers/staging/octeon/cvmx-interrupt-rsl.c deleted file mode 100644 index df50048cfbc0..000000000000 --- a/drivers/staging/octeon/cvmx-interrupt-rsl.c +++ /dev/null @@ -1,140 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Utility functions to decode Octeon's RSL_INT_BLOCKS - * interrupts into error messages. - */ - -#include - -#include "cvmx-asxx-defs.h" -#include "cvmx-gmxx-defs.h" - -#ifndef PRINT_ERROR -#define PRINT_ERROR(format, ...) -#endif - -void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block); - -/** - * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and - * CN58XX. - * - * @block: Interface to enable 0-1 - */ -void __cvmx_interrupt_asxx_enable(int block) -{ - int mask; - union cvmx_asxx_int_en csr; - /* - * CN38XX and CN58XX have two interfaces with 4 ports per - * interface. All other chips have a max of 3 ports on - * interface 0 - */ - if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) - mask = 0xf; /* Set enables for 4 ports */ - else - mask = 0x7; /* Set enables for 3 ports */ - - /* Enable interface interrupts */ - csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); - csr.s.txpsh = mask; - csr.s.txpop = mask; - csr.s.ovrflw = mask; - cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); -} -/** - * Enable GMX error reporting for the supplied interface - * - * @interface: Interface to enable - */ -void __cvmx_interrupt_gmxx_enable(int interface) -{ - union cvmx_gmxx_inf_mode mode; - union cvmx_gmxx_tx_int_en gmx_tx_int_en; - int num_ports; - int index; - - mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); - - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { - if (mode.s.en) { - switch (mode.cn56xx.mode) { - case 1: /* XAUI */ - num_ports = 1; - break; - case 2: /* SGMII */ - case 3: /* PICMG */ - num_ports = 4; - break; - default: /* Disabled */ - num_ports = 0; - break; - } - } else - num_ports = 0; - } else { - if (mode.s.en) { - if (OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)) { - /* - * SPI on CN38XX and CN58XX report all - * errors through port 0. RGMII needs - * to check all 4 ports - */ - if (mode.s.type) - num_ports = 1; - else - num_ports = 4; - } else { - /* - * CN30XX, CN31XX, and CN50XX have two - * or three ports. GMII and MII has 2, - * RGMII has three - */ - if (mode.s.type) - num_ports = 2; - else - num_ports = 3; - } - } else - num_ports = 0; - } - - gmx_tx_int_en.u64 = 0; - if (num_ports) { - if (OCTEON_IS_MODEL(OCTEON_CN38XX) - || OCTEON_IS_MODEL(OCTEON_CN58XX)) - gmx_tx_int_en.s.ncb_nxa = 1; - gmx_tx_int_en.s.pko_nxa = 1; - } - gmx_tx_int_en.s.undflw = (1 << num_ports) - 1; - cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); - for (index = 0; index < num_ports; index++) - __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface); -} diff --git a/drivers/staging/octeon/cvmx-ipd.h b/drivers/staging/octeon/cvmx-ipd.h deleted file mode 100644 index 115a552c5c7f..000000000000 --- a/drivers/staging/octeon/cvmx-ipd.h +++ /dev/null @@ -1,338 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Interface to the hardware Input Packet Data unit. - */ - -#ifndef __CVMX_IPD_H__ -#define __CVMX_IPD_H__ - -#include - -#include - -enum cvmx_ipd_mode { - CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ - CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ - CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ - CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ -}; - -#ifndef CVMX_ENABLE_LEN_M8_FIX -#define CVMX_ENABLE_LEN_M8_FIX 0 -#endif - -/* CSR typedefs have been moved to cvmx-csr-*.h */ -typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t; -typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t; - -typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t; -typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t; - -/** - * Configure IPD - * - * @mbuff_size: Packets buffer size in 8 byte words - * @first_mbuff_skip: - * Number of 8 byte words to skip in the first buffer - * @not_first_mbuff_skip: - * Number of 8 byte words to skip in each following buffer - * @first_back: Must be same as first_mbuff_skip / 128 - * @second_back: - * Must be same as not_first_mbuff_skip / 128 - * @wqe_fpa_pool: - * FPA pool to get work entries from - * @cache_mode: - * @back_pres_enable_flag: - * Enable or disable port back pressure - */ -static inline void cvmx_ipd_config(uint64_t mbuff_size, - uint64_t first_mbuff_skip, - uint64_t not_first_mbuff_skip, - uint64_t first_back, - uint64_t second_back, - uint64_t wqe_fpa_pool, - enum cvmx_ipd_mode cache_mode, - uint64_t back_pres_enable_flag) -{ - cvmx_ipd_mbuff_first_skip_t first_skip; - cvmx_ipd_mbuff_not_first_skip_t not_first_skip; - union cvmx_ipd_packet_mbuff_size size; - cvmx_ipd_first_next_ptr_back_t first_back_struct; - cvmx_ipd_second_next_ptr_back_t second_back_struct; - union cvmx_ipd_wqe_fpa_queue wqe_pool; - union cvmx_ipd_ctl_status ipd_ctl_reg; - - first_skip.u64 = 0; - first_skip.s.skip_sz = first_mbuff_skip; - cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); - - not_first_skip.u64 = 0; - not_first_skip.s.skip_sz = not_first_mbuff_skip; - cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); - - size.u64 = 0; - size.s.mb_size = mbuff_size; - cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); - - first_back_struct.u64 = 0; - first_back_struct.s.back = first_back; - cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); - - second_back_struct.u64 = 0; - second_back_struct.s.back = second_back; - cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); - - wqe_pool.u64 = 0; - wqe_pool.s.wqe_pool = wqe_fpa_pool; - cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); - - ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); - ipd_ctl_reg.s.opc_mode = cache_mode; - ipd_ctl_reg.s.pbp_en = back_pres_enable_flag; - cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); - - /* Note: the example RED code that used to be here has been moved to - cvmx_helper_setup_red */ -} - -/** - * Enable IPD - */ -static inline void cvmx_ipd_enable(void) -{ - union cvmx_ipd_ctl_status ipd_reg; - ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); - if (ipd_reg.s.ipd_en) { - cvmx_dprintf - ("Warning: Enabling IPD when IPD already enabled.\n"); - } - ipd_reg.s.ipd_en = 1; -#if CVMX_ENABLE_LEN_M8_FIX - if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) - ipd_reg.s.len_m8 = TRUE; -#endif - cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); -} - -/** - * Disable IPD - */ -static inline void cvmx_ipd_disable(void) -{ - union cvmx_ipd_ctl_status ipd_reg; - ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); - ipd_reg.s.ipd_en = 0; - cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); -} - -/** - * Supportive function for cvmx_fpa_shutdown_pool. - */ -static inline void cvmx_ipd_free_ptr(void) -{ - /* Only CN38XXp{1,2} cannot read pointer out of the IPD */ - if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) - && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) { - int no_wptr = 0; - union cvmx_ipd_ptr_count ipd_ptr_count; - ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); - - /* Handle Work Queue Entry in cn56xx and cn52xx */ - if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) { - union cvmx_ipd_ctl_status ipd_ctl_status; - ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); - if (ipd_ctl_status.s.no_wptr) - no_wptr = 1; - } - - /* Free the prefetched WQE */ - if (ipd_ptr_count.s.wqev_cnt) { - union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid; - ipd_wqe_ptr_valid.u64 = - cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); - if (no_wptr) - cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) ipd_wqe_ptr_valid.s. - ptr << 7), CVMX_FPA_PACKET_POOL, - 0); - else - cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) ipd_wqe_ptr_valid.s. - ptr << 7), CVMX_FPA_WQE_POOL, 0); - } - - /* Free all WQE in the fifo */ - if (ipd_ptr_count.s.wqe_pcnt) { - int i; - union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; - ipd_pwp_ptr_fifo_ctl.u64 = - cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); - for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) { - ipd_pwp_ptr_fifo_ctl.s.cena = 0; - ipd_pwp_ptr_fifo_ctl.s.raddr = - ipd_pwp_ptr_fifo_ctl.s.max_cnts + - (ipd_pwp_ptr_fifo_ctl.s.wraddr + - i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; - cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, - ipd_pwp_ptr_fifo_ctl.u64); - ipd_pwp_ptr_fifo_ctl.u64 = - cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); - if (no_wptr) - cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) - ipd_pwp_ptr_fifo_ctl.s. - ptr << 7), - CVMX_FPA_PACKET_POOL, 0); - else - cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) - ipd_pwp_ptr_fifo_ctl.s. - ptr << 7), - CVMX_FPA_WQE_POOL, 0); - } - ipd_pwp_ptr_fifo_ctl.s.cena = 1; - cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, - ipd_pwp_ptr_fifo_ctl.u64); - } - - /* Free the prefetched packet */ - if (ipd_ptr_count.s.pktv_cnt) { - union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid; - ipd_pkt_ptr_valid.u64 = - cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); - cvmx_fpa_free(cvmx_phys_to_ptr - (ipd_pkt_ptr_valid.s.ptr << 7), - CVMX_FPA_PACKET_POOL, 0); - } - - /* Free the per port prefetched packets */ - if (1) { - int i; - union cvmx_ipd_prc_port_ptr_fifo_ctl - ipd_prc_port_ptr_fifo_ctl; - ipd_prc_port_ptr_fifo_ctl.u64 = - cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); - - for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; - i++) { - ipd_prc_port_ptr_fifo_ctl.s.cena = 0; - ipd_prc_port_ptr_fifo_ctl.s.raddr = - i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt; - cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, - ipd_prc_port_ptr_fifo_ctl.u64); - ipd_prc_port_ptr_fifo_ctl.u64 = - cvmx_read_csr - (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); - cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) - ipd_prc_port_ptr_fifo_ctl.s. - ptr << 7), CVMX_FPA_PACKET_POOL, - 0); - } - ipd_prc_port_ptr_fifo_ctl.s.cena = 1; - cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, - ipd_prc_port_ptr_fifo_ctl.u64); - } - - /* Free all packets in the holding fifo */ - if (ipd_ptr_count.s.pfif_cnt) { - int i; - union cvmx_ipd_prc_hold_ptr_fifo_ctl - ipd_prc_hold_ptr_fifo_ctl; - - ipd_prc_hold_ptr_fifo_ctl.u64 = - cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); - - for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) { - ipd_prc_hold_ptr_fifo_ctl.s.cena = 0; - ipd_prc_hold_ptr_fifo_ctl.s.raddr = - (ipd_prc_hold_ptr_fifo_ctl.s.praddr + - i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt; - cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, - ipd_prc_hold_ptr_fifo_ctl.u64); - ipd_prc_hold_ptr_fifo_ctl.u64 = - cvmx_read_csr - (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); - cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) - ipd_prc_hold_ptr_fifo_ctl.s. - ptr << 7), CVMX_FPA_PACKET_POOL, - 0); - } - ipd_prc_hold_ptr_fifo_ctl.s.cena = 1; - cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, - ipd_prc_hold_ptr_fifo_ctl.u64); - } - - /* Free all packets in the fifo */ - if (ipd_ptr_count.s.pkt_pcnt) { - int i; - union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; - ipd_pwp_ptr_fifo_ctl.u64 = - cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); - - for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) { - ipd_pwp_ptr_fifo_ctl.s.cena = 0; - ipd_pwp_ptr_fifo_ctl.s.raddr = - (ipd_pwp_ptr_fifo_ctl.s.praddr + - i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; - cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, - ipd_pwp_ptr_fifo_ctl.u64); - ipd_pwp_ptr_fifo_ctl.u64 = - cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); - cvmx_fpa_free(cvmx_phys_to_ptr - ((uint64_t) ipd_pwp_ptr_fifo_ctl. - s.ptr << 7), - CVMX_FPA_PACKET_POOL, 0); - } - ipd_pwp_ptr_fifo_ctl.s.cena = 1; - cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, - ipd_pwp_ptr_fifo_ctl.u64); - } - - /* Reset the IPD to get all buffers out of it */ - { - union cvmx_ipd_ctl_status ipd_ctl_status; - ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); - ipd_ctl_status.s.reset = 1; - cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); - } - - /* Reset the PIP */ - { - union cvmx_pip_sft_rst pip_sft_rst; - pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST); - pip_sft_rst.s.rst = 1; - cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64); - } - } -} - -#endif /* __CVMX_IPD_H__ */ diff --git a/drivers/staging/octeon/cvmx-mdio.h b/drivers/staging/octeon/cvmx-mdio.h deleted file mode 100644 index d88ab8d8e37d..000000000000 --- a/drivers/staging/octeon/cvmx-mdio.h +++ /dev/null @@ -1,506 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3 - * clause 22 and clause 45 operations. - * - */ - -#ifndef __CVMX_MIO_H__ -#define __CVMX_MIO_H__ - -#include "cvmx-smix-defs.h" - -/** - * PHY register 0 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_CONTROL 0 -typedef union { - uint16_t u16; - struct { - uint16_t reset:1; - uint16_t loopback:1; - uint16_t speed_lsb:1; - uint16_t autoneg_enable:1; - uint16_t power_down:1; - uint16_t isolate:1; - uint16_t restart_autoneg:1; - uint16_t duplex:1; - uint16_t collision_test:1; - uint16_t speed_msb:1; - uint16_t unidirectional_enable:1; - uint16_t reserved_0_4:5; - } s; -} cvmx_mdio_phy_reg_control_t; - -/** - * PHY register 1 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_STATUS 1 -typedef union { - uint16_t u16; - struct { - uint16_t capable_100base_t4:1; - uint16_t capable_100base_x_full:1; - uint16_t capable_100base_x_half:1; - uint16_t capable_10_full:1; - uint16_t capable_10_half:1; - uint16_t capable_100base_t2_full:1; - uint16_t capable_100base_t2_half:1; - uint16_t capable_extended_status:1; - uint16_t capable_unidirectional:1; - uint16_t capable_mf_preamble_suppression:1; - uint16_t autoneg_complete:1; - uint16_t remote_fault:1; - uint16_t capable_autoneg:1; - uint16_t link_status:1; - uint16_t jabber_detect:1; - uint16_t capable_extended_registers:1; - - } s; -} cvmx_mdio_phy_reg_status_t; - -/** - * PHY register 2 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_ID1 2 -typedef union { - uint16_t u16; - struct { - uint16_t oui_bits_3_18; - } s; -} cvmx_mdio_phy_reg_id1_t; - -/** - * PHY register 3 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_ID2 3 -typedef union { - uint16_t u16; - struct { - uint16_t oui_bits_19_24:6; - uint16_t model:6; - uint16_t revision:4; - } s; -} cvmx_mdio_phy_reg_id2_t; - -/** - * PHY register 4 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4 -typedef union { - uint16_t u16; - struct { - uint16_t next_page:1; - uint16_t reserved_14:1; - uint16_t remote_fault:1; - uint16_t reserved_12:1; - uint16_t asymmetric_pause:1; - uint16_t pause:1; - uint16_t advert_100base_t4:1; - uint16_t advert_100base_tx_full:1; - uint16_t advert_100base_tx_half:1; - uint16_t advert_10base_tx_full:1; - uint16_t advert_10base_tx_half:1; - uint16_t selector:5; - } s; -} cvmx_mdio_phy_reg_autoneg_adver_t; - -/** - * PHY register 5 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5 -typedef union { - uint16_t u16; - struct { - uint16_t next_page:1; - uint16_t ack:1; - uint16_t remote_fault:1; - uint16_t reserved_12:1; - uint16_t asymmetric_pause:1; - uint16_t pause:1; - uint16_t advert_100base_t4:1; - uint16_t advert_100base_tx_full:1; - uint16_t advert_100base_tx_half:1; - uint16_t advert_10base_tx_full:1; - uint16_t advert_10base_tx_half:1; - uint16_t selector:5; - } s; -} cvmx_mdio_phy_reg_link_partner_ability_t; - -/** - * PHY register 6 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6 -typedef union { - uint16_t u16; - struct { - uint16_t reserved_5_15:11; - uint16_t parallel_detection_fault:1; - uint16_t link_partner_next_page_capable:1; - uint16_t local_next_page_capable:1; - uint16_t page_received:1; - uint16_t link_partner_autoneg_capable:1; - - } s; -} cvmx_mdio_phy_reg_autoneg_expansion_t; - -/** - * PHY register 9 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_CONTROL_1000 9 -typedef union { - uint16_t u16; - struct { - uint16_t test_mode:3; - uint16_t manual_master_slave:1; - uint16_t master:1; - uint16_t port_type:1; - uint16_t advert_1000base_t_full:1; - uint16_t advert_1000base_t_half:1; - uint16_t reserved_0_7:8; - } s; -} cvmx_mdio_phy_reg_control_1000_t; - -/** - * PHY register 10 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_STATUS_1000 10 -typedef union { - uint16_t u16; - struct { - uint16_t master_slave_fault:1; - uint16_t is_master:1; - uint16_t local_receiver_ok:1; - uint16_t remote_receiver_ok:1; - uint16_t remote_capable_1000base_t_full:1; - uint16_t remote_capable_1000base_t_half:1; - uint16_t reserved_8_9:2; - uint16_t idle_error_count:8; - } s; -} cvmx_mdio_phy_reg_status_1000_t; - -/** - * PHY register 15 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15 -typedef union { - uint16_t u16; - struct { - uint16_t capable_1000base_x_full:1; - uint16_t capable_1000base_x_half:1; - uint16_t capable_1000base_t_full:1; - uint16_t capable_1000base_t_half:1; - uint16_t reserved_0_11:12; - } s; -} cvmx_mdio_phy_reg_extended_status_t; - -/** - * PHY register 13 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13 -typedef union { - uint16_t u16; - struct { - uint16_t function:2; - uint16_t reserved_5_13:9; - uint16_t devad:5; - } s; -} cvmx_mdio_phy_reg_mmd_control_t; - -/** - * PHY register 14 from the 802.3 spec - */ -#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14 -typedef union { - uint16_t u16; - struct { - uint16_t address_data:16; - } s; -} cvmx_mdio_phy_reg_mmd_address_data_t; - -/* Operating request encodings. */ -#define MDIO_CLAUSE_22_WRITE 0 -#define MDIO_CLAUSE_22_READ 1 - -#define MDIO_CLAUSE_45_ADDRESS 0 -#define MDIO_CLAUSE_45_WRITE 1 -#define MDIO_CLAUSE_45_READ_INC 2 -#define MDIO_CLAUSE_45_READ 3 - -/* MMD identifiers, mostly for accessing devices within XENPAK modules. */ -#define CVMX_MMD_DEVICE_PMA_PMD 1 -#define CVMX_MMD_DEVICE_WIS 2 -#define CVMX_MMD_DEVICE_PCS 3 -#define CVMX_MMD_DEVICE_PHY_XS 4 -#define CVMX_MMD_DEVICE_DTS_XS 5 -#define CVMX_MMD_DEVICE_TC 6 -#define CVMX_MMD_DEVICE_CL22_EXT 29 -#define CVMX_MMD_DEVICE_VENDOR_1 30 -#define CVMX_MMD_DEVICE_VENDOR_2 31 - -/* Helper function to put MDIO interface into clause 45 mode */ -static inline void __cvmx_mdio_set_clause45_mode(int bus_id) -{ - union cvmx_smix_clk smi_clk; - /* Put bus into clause 45 mode */ - smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); - smi_clk.s.mode = 1; - smi_clk.s.preamble = 1; - cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); -} - -/* Helper function to put MDIO interface into clause 22 mode */ -static inline void __cvmx_mdio_set_clause22_mode(int bus_id) -{ - union cvmx_smix_clk smi_clk; - /* Put bus into clause 22 mode */ - smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); - smi_clk.s.mode = 0; - cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); -} - -/** - * Perform an MII read. This function is used to read PHY - * registers controlling auto negotiation. - * - * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. - * @phy_id: The MII phy id - * @location: Register location to read - * - * Returns Result from the read or -1 on failure - */ -static inline int cvmx_mdio_read(int bus_id, int phy_id, int location) -{ - union cvmx_smix_cmd smi_cmd; - union cvmx_smix_rd_dat smi_rd; - int timeout = 1000; - - if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) - __cvmx_mdio_set_clause22_mode(bus_id); - - smi_cmd.u64 = 0; - smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ; - smi_cmd.s.phy_adr = phy_id; - smi_cmd.s.reg_adr = location; - cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); - - do { - cvmx_wait(1000); - smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); - } while (smi_rd.s.pending && timeout--); - - if (smi_rd.s.val) - return smi_rd.s.dat; - else - return -1; -} - -/** - * Perform an MII write. This function is used to write PHY - * registers controlling auto negotiation. - * - * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. - * @phy_id: The MII phy id - * @location: Register location to write - * @val: Value to write - * - * Returns -1 on error - * 0 on success - */ -static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val) -{ - union cvmx_smix_cmd smi_cmd; - union cvmx_smix_wr_dat smi_wr; - int timeout = 1000; - - if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) - __cvmx_mdio_set_clause22_mode(bus_id); - - smi_wr.u64 = 0; - smi_wr.s.dat = val; - cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); - - smi_cmd.u64 = 0; - smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE; - smi_cmd.s.phy_adr = phy_id; - smi_cmd.s.reg_adr = location; - cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); - - do { - cvmx_wait(1000); - smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); - } while (smi_wr.s.pending && --timeout); - if (timeout <= 0) - return -1; - - return 0; -} - -/** - * Perform an IEEE 802.3 clause 45 MII read. This function is used to - * read PHY registers controlling auto negotiation. - * - * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. - * @phy_id: The MII phy id - * @device: MDIO Managable Device (MMD) id - * @location: Register location to read - * - * Returns Result from the read or -1 on failure - */ - -static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, - int location) -{ - union cvmx_smix_cmd smi_cmd; - union cvmx_smix_rd_dat smi_rd; - union cvmx_smix_wr_dat smi_wr; - int timeout = 1000; - - if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) - return -1; - - __cvmx_mdio_set_clause45_mode(bus_id); - - smi_wr.u64 = 0; - smi_wr.s.dat = location; - cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); - - smi_cmd.u64 = 0; - smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS; - smi_cmd.s.phy_adr = phy_id; - smi_cmd.s.reg_adr = device; - cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); - - do { - cvmx_wait(1000); - smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); - } while (smi_wr.s.pending && --timeout); - if (timeout <= 0) { - cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d TIME OUT(address)\n", - bus_id, phy_id, device, location); - return -1; - } - - smi_cmd.u64 = 0; - smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ; - smi_cmd.s.phy_adr = phy_id; - smi_cmd.s.reg_adr = device; - cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); - - do { - cvmx_wait(1000); - smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); - } while (smi_rd.s.pending && --timeout); - - if (timeout <= 0) { - cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d TIME OUT(data)\n", - bus_id, phy_id, device, location); - return -1; - } - - if (smi_rd.s.val) - return smi_rd.s.dat; - else { - cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " - "device %2d register %2d INVALID READ\n", - bus_id, phy_id, device, location); - return -1; - } -} - -/** - * Perform an IEEE 802.3 clause 45 MII write. This function is used to - * write PHY registers controlling auto negotiation. - * - * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) - * support multiple busses. - * @phy_id: The MII phy id - * @device: MDIO Managable Device (MMD) id - * @location: Register location to write - * @val: Value to write - * - * Returns -1 on error - * 0 on success - */ -static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, - int location, int val) -{ - union cvmx_smix_cmd smi_cmd; - union cvmx_smix_wr_dat smi_wr; - int timeout = 1000; - - if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) - return -1; - - __cvmx_mdio_set_clause45_mode(bus_id); - - smi_wr.u64 = 0; - smi_wr.s.dat = location; - cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); - - smi_cmd.u64 = 0; - smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS; - smi_cmd.s.phy_adr = phy_id; - smi_cmd.s.reg_adr = device; - cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); - - do { - cvmx_wait(1000); - smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); - } while (smi_wr.s.pending && --timeout); - if (timeout <= 0) - return -1; - - smi_wr.u64 = 0; - smi_wr.s.dat = val; - cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); - - smi_cmd.u64 = 0; - smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE; - smi_cmd.s.phy_adr = phy_id; - smi_cmd.s.reg_adr = device; - cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); - - do { - cvmx_wait(1000); - smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); - } while (smi_wr.s.pending && --timeout); - if (timeout <= 0) - return -1; - - return 0; -} - -#endif diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h deleted file mode 100644 index 62ffe78a8c81..000000000000 --- a/drivers/staging/octeon/cvmx-packet.h +++ /dev/null @@ -1,65 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Packet buffer defines. - */ - -#ifndef __CVMX_PACKET_H__ -#define __CVMX_PACKET_H__ - -/** - * This structure defines a buffer pointer on Octeon - */ -union cvmx_buf_ptr { - void *ptr; - uint64_t u64; - struct { - /* - * if set, invert the "free" pick of the overall - * packet. HW always sets this bit to 0 on inbound - * packet - */ - uint64_t i:1; - /* - * Indicates the amount to back up to get to the - * buffer start in cache lines. In most cases this is - * less than one complete cache line, so the value is - * zero. - */ - uint64_t back:4; - /* The pool that the buffer came from / goes to */ - uint64_t pool:3; - /* The size of the segment pointed to by addr (in bytes) */ - uint64_t size:16; - /* Pointer to the first byte of the data, NOT buffer */ - uint64_t addr:40; - } s; -}; - -#endif /* __CVMX_PACKET_H__ */ diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/drivers/staging/octeon/cvmx-pcsx-defs.h deleted file mode 100644 index d45952df5f5b..000000000000 --- a/drivers/staging/octeon/cvmx-pcsx-defs.h +++ /dev/null @@ -1,370 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_PCSX_DEFS_H__ -#define __CVMX_PCSX_DEFS_H__ - -#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_INTX_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) - -union cvmx_pcsx_anx_adv_reg { - uint64_t u64; - struct cvmx_pcsx_anx_adv_reg_s { - uint64_t reserved_16_63:48; - uint64_t np:1; - uint64_t reserved_14_14:1; - uint64_t rem_flt:2; - uint64_t reserved_9_11:3; - uint64_t pause:2; - uint64_t hfd:1; - uint64_t fd:1; - uint64_t reserved_0_4:5; - } s; - struct cvmx_pcsx_anx_adv_reg_s cn52xx; - struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; - struct cvmx_pcsx_anx_adv_reg_s cn56xx; - struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; -}; - -union cvmx_pcsx_anx_ext_st_reg { - uint64_t u64; - struct cvmx_pcsx_anx_ext_st_reg_s { - uint64_t reserved_16_63:48; - uint64_t thou_xfd:1; - uint64_t thou_xhd:1; - uint64_t thou_tfd:1; - uint64_t thou_thd:1; - uint64_t reserved_0_11:12; - } s; - struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; - struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; - struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; - struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; -}; - -union cvmx_pcsx_anx_lp_abil_reg { - uint64_t u64; - struct cvmx_pcsx_anx_lp_abil_reg_s { - uint64_t reserved_16_63:48; - uint64_t np:1; - uint64_t ack:1; - uint64_t rem_flt:2; - uint64_t reserved_9_11:3; - uint64_t pause:2; - uint64_t hfd:1; - uint64_t fd:1; - uint64_t reserved_0_4:5; - } s; - struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; - struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; - struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; - struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; -}; - -union cvmx_pcsx_anx_results_reg { - uint64_t u64; - struct cvmx_pcsx_anx_results_reg_s { - uint64_t reserved_7_63:57; - uint64_t pause:2; - uint64_t spd:2; - uint64_t an_cpt:1; - uint64_t dup:1; - uint64_t link_ok:1; - } s; - struct cvmx_pcsx_anx_results_reg_s cn52xx; - struct cvmx_pcsx_anx_results_reg_s cn52xxp1; - struct cvmx_pcsx_anx_results_reg_s cn56xx; - struct cvmx_pcsx_anx_results_reg_s cn56xxp1; -}; - -union cvmx_pcsx_intx_en_reg { - uint64_t u64; - struct cvmx_pcsx_intx_en_reg_s { - uint64_t reserved_12_63:52; - uint64_t dup:1; - uint64_t sync_bad_en:1; - uint64_t an_bad_en:1; - uint64_t rxlock_en:1; - uint64_t rxbad_en:1; - uint64_t rxerr_en:1; - uint64_t txbad_en:1; - uint64_t txfifo_en:1; - uint64_t txfifu_en:1; - uint64_t an_err_en:1; - uint64_t xmit_en:1; - uint64_t lnkspd_en:1; - } s; - struct cvmx_pcsx_intx_en_reg_s cn52xx; - struct cvmx_pcsx_intx_en_reg_s cn52xxp1; - struct cvmx_pcsx_intx_en_reg_s cn56xx; - struct cvmx_pcsx_intx_en_reg_s cn56xxp1; -}; - -union cvmx_pcsx_intx_reg { - uint64_t u64; - struct cvmx_pcsx_intx_reg_s { - uint64_t reserved_12_63:52; - uint64_t dup:1; - uint64_t sync_bad:1; - uint64_t an_bad:1; - uint64_t rxlock:1; - uint64_t rxbad:1; - uint64_t rxerr:1; - uint64_t txbad:1; - uint64_t txfifo:1; - uint64_t txfifu:1; - uint64_t an_err:1; - uint64_t xmit:1; - uint64_t lnkspd:1; - } s; - struct cvmx_pcsx_intx_reg_s cn52xx; - struct cvmx_pcsx_intx_reg_s cn52xxp1; - struct cvmx_pcsx_intx_reg_s cn56xx; - struct cvmx_pcsx_intx_reg_s cn56xxp1; -}; - -union cvmx_pcsx_linkx_timer_count_reg { - uint64_t u64; - struct cvmx_pcsx_linkx_timer_count_reg_s { - uint64_t reserved_16_63:48; - uint64_t count:16; - } s; - struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; - struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; - struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; - struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; -}; - -union cvmx_pcsx_log_anlx_reg { - uint64_t u64; - struct cvmx_pcsx_log_anlx_reg_s { - uint64_t reserved_4_63:60; - uint64_t lafifovfl:1; - uint64_t la_en:1; - uint64_t pkt_sz:2; - } s; - struct cvmx_pcsx_log_anlx_reg_s cn52xx; - struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; - struct cvmx_pcsx_log_anlx_reg_s cn56xx; - struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; -}; - -union cvmx_pcsx_miscx_ctl_reg { - uint64_t u64; - struct cvmx_pcsx_miscx_ctl_reg_s { - uint64_t reserved_13_63:51; - uint64_t sgmii:1; - uint64_t gmxeno:1; - uint64_t loopbck2:1; - uint64_t mac_phy:1; - uint64_t mode:1; - uint64_t an_ovrd:1; - uint64_t samp_pt:7; - } s; - struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; - struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; - struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; - struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; -}; - -union cvmx_pcsx_mrx_control_reg { - uint64_t u64; - struct cvmx_pcsx_mrx_control_reg_s { - uint64_t reserved_16_63:48; - uint64_t reset:1; - uint64_t loopbck1:1; - uint64_t spdlsb:1; - uint64_t an_en:1; - uint64_t pwr_dn:1; - uint64_t reserved_10_10:1; - uint64_t rst_an:1; - uint64_t dup:1; - uint64_t coltst:1; - uint64_t spdmsb:1; - uint64_t uni:1; - uint64_t reserved_0_4:5; - } s; - struct cvmx_pcsx_mrx_control_reg_s cn52xx; - struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; - struct cvmx_pcsx_mrx_control_reg_s cn56xx; - struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; -}; - -union cvmx_pcsx_mrx_status_reg { - uint64_t u64; - struct cvmx_pcsx_mrx_status_reg_s { - uint64_t reserved_16_63:48; - uint64_t hun_t4:1; - uint64_t hun_xfd:1; - uint64_t hun_xhd:1; - uint64_t ten_fd:1; - uint64_t ten_hd:1; - uint64_t hun_t2fd:1; - uint64_t hun_t2hd:1; - uint64_t ext_st:1; - uint64_t reserved_7_7:1; - uint64_t prb_sup:1; - uint64_t an_cpt:1; - uint64_t rm_flt:1; - uint64_t an_abil:1; - uint64_t lnk_st:1; - uint64_t reserved_1_1:1; - uint64_t extnd:1; - } s; - struct cvmx_pcsx_mrx_status_reg_s cn52xx; - struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; - struct cvmx_pcsx_mrx_status_reg_s cn56xx; - struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; -}; - -union cvmx_pcsx_rxx_states_reg { - uint64_t u64; - struct cvmx_pcsx_rxx_states_reg_s { - uint64_t reserved_16_63:48; - uint64_t rx_bad:1; - uint64_t rx_st:5; - uint64_t sync_bad:1; - uint64_t sync:4; - uint64_t an_bad:1; - uint64_t an_st:4; - } s; - struct cvmx_pcsx_rxx_states_reg_s cn52xx; - struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; - struct cvmx_pcsx_rxx_states_reg_s cn56xx; - struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; -}; - -union cvmx_pcsx_rxx_sync_reg { - uint64_t u64; - struct cvmx_pcsx_rxx_sync_reg_s { - uint64_t reserved_2_63:62; - uint64_t sync:1; - uint64_t bit_lock:1; - } s; - struct cvmx_pcsx_rxx_sync_reg_s cn52xx; - struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; - struct cvmx_pcsx_rxx_sync_reg_s cn56xx; - struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; -}; - -union cvmx_pcsx_sgmx_an_adv_reg { - uint64_t u64; - struct cvmx_pcsx_sgmx_an_adv_reg_s { - uint64_t reserved_16_63:48; - uint64_t link:1; - uint64_t ack:1; - uint64_t reserved_13_13:1; - uint64_t dup:1; - uint64_t speed:2; - uint64_t reserved_1_9:9; - uint64_t one:1; - } s; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; - struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; -}; - -union cvmx_pcsx_sgmx_lp_adv_reg { - uint64_t u64; - struct cvmx_pcsx_sgmx_lp_adv_reg_s { - uint64_t reserved_16_63:48; - uint64_t link:1; - uint64_t reserved_13_14:2; - uint64_t dup:1; - uint64_t speed:2; - uint64_t reserved_1_9:9; - uint64_t one:1; - } s; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; - struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; -}; - -union cvmx_pcsx_txx_states_reg { - uint64_t u64; - struct cvmx_pcsx_txx_states_reg_s { - uint64_t reserved_7_63:57; - uint64_t xmit:2; - uint64_t tx_bad:1; - uint64_t ord_st:4; - } s; - struct cvmx_pcsx_txx_states_reg_s cn52xx; - struct cvmx_pcsx_txx_states_reg_s cn52xxp1; - struct cvmx_pcsx_txx_states_reg_s cn56xx; - struct cvmx_pcsx_txx_states_reg_s cn56xxp1; -}; - -union cvmx_pcsx_tx_rxx_polarity_reg { - uint64_t u64; - struct cvmx_pcsx_tx_rxx_polarity_reg_s { - uint64_t reserved_4_63:60; - uint64_t rxovrd:1; - uint64_t autorxpl:1; - uint64_t rxplrt:1; - uint64_t txplrt:1; - } s; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; - struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/drivers/staging/octeon/cvmx-pcsxx-defs.h deleted file mode 100644 index 55d120fe8aed..000000000000 --- a/drivers/staging/octeon/cvmx-pcsxx-defs.h +++ /dev/null @@ -1,316 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_PCSXX_DEFS_H__ -#define __CVMX_PCSXX_DEFS_H__ - -#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_CONTROL1_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_CONTROL2_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_INT_EN_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_LOG_ANL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_MISC_CTL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_STATUS1_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_STATUS2_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ - CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) - -union cvmx_pcsxx_10gbx_status_reg { - uint64_t u64; - struct cvmx_pcsxx_10gbx_status_reg_s { - uint64_t reserved_13_63:51; - uint64_t alignd:1; - uint64_t pattst:1; - uint64_t reserved_4_10:7; - uint64_t l3sync:1; - uint64_t l2sync:1; - uint64_t l1sync:1; - uint64_t l0sync:1; - } s; - struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; - struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; - struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; - struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_bist_status_reg { - uint64_t u64; - struct cvmx_pcsxx_bist_status_reg_s { - uint64_t reserved_1_63:63; - uint64_t bist_status:1; - } s; - struct cvmx_pcsxx_bist_status_reg_s cn52xx; - struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; - struct cvmx_pcsxx_bist_status_reg_s cn56xx; - struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_bit_lock_status_reg { - uint64_t u64; - struct cvmx_pcsxx_bit_lock_status_reg_s { - uint64_t reserved_4_63:60; - uint64_t bitlck3:1; - uint64_t bitlck2:1; - uint64_t bitlck1:1; - uint64_t bitlck0:1; - } s; - struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; - struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; - struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; - struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_control1_reg { - uint64_t u64; - struct cvmx_pcsxx_control1_reg_s { - uint64_t reserved_16_63:48; - uint64_t reset:1; - uint64_t loopbck1:1; - uint64_t spdsel1:1; - uint64_t reserved_12_12:1; - uint64_t lo_pwr:1; - uint64_t reserved_7_10:4; - uint64_t spdsel0:1; - uint64_t spd:4; - uint64_t reserved_0_1:2; - } s; - struct cvmx_pcsxx_control1_reg_s cn52xx; - struct cvmx_pcsxx_control1_reg_s cn52xxp1; - struct cvmx_pcsxx_control1_reg_s cn56xx; - struct cvmx_pcsxx_control1_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_control2_reg { - uint64_t u64; - struct cvmx_pcsxx_control2_reg_s { - uint64_t reserved_2_63:62; - uint64_t type:2; - } s; - struct cvmx_pcsxx_control2_reg_s cn52xx; - struct cvmx_pcsxx_control2_reg_s cn52xxp1; - struct cvmx_pcsxx_control2_reg_s cn56xx; - struct cvmx_pcsxx_control2_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_int_en_reg { - uint64_t u64; - struct cvmx_pcsxx_int_en_reg_s { - uint64_t reserved_6_63:58; - uint64_t algnlos_en:1; - uint64_t synlos_en:1; - uint64_t bitlckls_en:1; - uint64_t rxsynbad_en:1; - uint64_t rxbad_en:1; - uint64_t txflt_en:1; - } s; - struct cvmx_pcsxx_int_en_reg_s cn52xx; - struct cvmx_pcsxx_int_en_reg_s cn52xxp1; - struct cvmx_pcsxx_int_en_reg_s cn56xx; - struct cvmx_pcsxx_int_en_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_int_reg { - uint64_t u64; - struct cvmx_pcsxx_int_reg_s { - uint64_t reserved_6_63:58; - uint64_t algnlos:1; - uint64_t synlos:1; - uint64_t bitlckls:1; - uint64_t rxsynbad:1; - uint64_t rxbad:1; - uint64_t txflt:1; - } s; - struct cvmx_pcsxx_int_reg_s cn52xx; - struct cvmx_pcsxx_int_reg_s cn52xxp1; - struct cvmx_pcsxx_int_reg_s cn56xx; - struct cvmx_pcsxx_int_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_log_anl_reg { - uint64_t u64; - struct cvmx_pcsxx_log_anl_reg_s { - uint64_t reserved_7_63:57; - uint64_t enc_mode:1; - uint64_t drop_ln:2; - uint64_t lafifovfl:1; - uint64_t la_en:1; - uint64_t pkt_sz:2; - } s; - struct cvmx_pcsxx_log_anl_reg_s cn52xx; - struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; - struct cvmx_pcsxx_log_anl_reg_s cn56xx; - struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_misc_ctl_reg { - uint64_t u64; - struct cvmx_pcsxx_misc_ctl_reg_s { - uint64_t reserved_4_63:60; - uint64_t tx_swap:1; - uint64_t rx_swap:1; - uint64_t xaui:1; - uint64_t gmxeno:1; - } s; - struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; - struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; - struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; - struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_rx_sync_states_reg { - uint64_t u64; - struct cvmx_pcsxx_rx_sync_states_reg_s { - uint64_t reserved_16_63:48; - uint64_t sync3st:4; - uint64_t sync2st:4; - uint64_t sync1st:4; - uint64_t sync0st:4; - } s; - struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; - struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; - struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; - struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_spd_abil_reg { - uint64_t u64; - struct cvmx_pcsxx_spd_abil_reg_s { - uint64_t reserved_2_63:62; - uint64_t tenpasst:1; - uint64_t tengb:1; - } s; - struct cvmx_pcsxx_spd_abil_reg_s cn52xx; - struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; - struct cvmx_pcsxx_spd_abil_reg_s cn56xx; - struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_status1_reg { - uint64_t u64; - struct cvmx_pcsxx_status1_reg_s { - uint64_t reserved_8_63:56; - uint64_t flt:1; - uint64_t reserved_3_6:4; - uint64_t rcv_lnk:1; - uint64_t lpable:1; - uint64_t reserved_0_0:1; - } s; - struct cvmx_pcsxx_status1_reg_s cn52xx; - struct cvmx_pcsxx_status1_reg_s cn52xxp1; - struct cvmx_pcsxx_status1_reg_s cn56xx; - struct cvmx_pcsxx_status1_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_status2_reg { - uint64_t u64; - struct cvmx_pcsxx_status2_reg_s { - uint64_t reserved_16_63:48; - uint64_t dev:2; - uint64_t reserved_12_13:2; - uint64_t xmtflt:1; - uint64_t rcvflt:1; - uint64_t reserved_3_9:7; - uint64_t tengb_w:1; - uint64_t tengb_x:1; - uint64_t tengb_r:1; - } s; - struct cvmx_pcsxx_status2_reg_s cn52xx; - struct cvmx_pcsxx_status2_reg_s cn52xxp1; - struct cvmx_pcsxx_status2_reg_s cn56xx; - struct cvmx_pcsxx_status2_reg_s cn56xxp1; -}; - -union cvmx_pcsxx_tx_rx_polarity_reg { - uint64_t u64; - struct cvmx_pcsxx_tx_rx_polarity_reg_s { - uint64_t reserved_10_63:54; - uint64_t xor_rxplrt:4; - uint64_t xor_txplrt:4; - uint64_t rxplrt:1; - uint64_t txplrt:1; - } s; - struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; - struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { - uint64_t reserved_2_63:62; - uint64_t rxplrt:1; - uint64_t txplrt:1; - } cn52xxp1; - struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; - struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; -}; - -union cvmx_pcsxx_tx_rx_states_reg { - uint64_t u64; - struct cvmx_pcsxx_tx_rx_states_reg_s { - uint64_t reserved_14_63:50; - uint64_t term_err:1; - uint64_t syn3bad:1; - uint64_t syn2bad:1; - uint64_t syn1bad:1; - uint64_t syn0bad:1; - uint64_t rxbad:1; - uint64_t algn_st:3; - uint64_t rx_st:2; - uint64_t tx_st:3; - } s; - struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; - struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { - uint64_t reserved_13_63:51; - uint64_t syn3bad:1; - uint64_t syn2bad:1; - uint64_t syn1bad:1; - uint64_t syn0bad:1; - uint64_t rxbad:1; - uint64_t algn_st:3; - uint64_t rx_st:2; - uint64_t tx_st:3; - } cn52xxp1; - struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; - struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/drivers/staging/octeon/cvmx-pip-defs.h deleted file mode 100644 index 5a369100ca68..000000000000 --- a/drivers/staging/octeon/cvmx-pip-defs.h +++ /dev/null @@ -1,1267 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_PIP_DEFS_H__ -#define __CVMX_PIP_DEFS_H__ - -/* - * Enumeration representing the amount of packet processing - * and validation performed by the input hardware. - */ -enum cvmx_pip_port_parse_mode { - /* - * Packet input doesn't perform any processing of the input - * packet. - */ - CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, - /* - * Full packet processing is performed with pointer starting - * at the L2 (ethernet MAC) header. - */ - CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, - /* - * Input packets are assumed to be IP. Results from non IP - * packets is undefined. Pointers reference the beginning of - * the IP header. - */ - CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull -}; - -#define CVMX_PIP_BCK_PRS \ - CVMX_ADD_IO_SEG(0x00011800A0000038ull) -#define CVMX_PIP_BIST_STATUS \ - CVMX_ADD_IO_SEG(0x00011800A0000000ull) -#define CVMX_PIP_CRC_CTLX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8)) -#define CVMX_PIP_CRC_IVX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8)) -#define CVMX_PIP_DEC_IPSECX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8)) -#define CVMX_PIP_DSA_SRC_GRP \ - CVMX_ADD_IO_SEG(0x00011800A0000190ull) -#define CVMX_PIP_DSA_VID_GRP \ - CVMX_ADD_IO_SEG(0x00011800A0000198ull) -#define CVMX_PIP_FRM_LEN_CHKX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8)) -#define CVMX_PIP_GBL_CFG \ - CVMX_ADD_IO_SEG(0x00011800A0000028ull) -#define CVMX_PIP_GBL_CTL \ - CVMX_ADD_IO_SEG(0x00011800A0000020ull) -#define CVMX_PIP_HG_PRI_QOS \ - CVMX_ADD_IO_SEG(0x00011800A00001A0ull) -#define CVMX_PIP_INT_EN \ - CVMX_ADD_IO_SEG(0x00011800A0000010ull) -#define CVMX_PIP_INT_REG \ - CVMX_ADD_IO_SEG(0x00011800A0000008ull) -#define CVMX_PIP_IP_OFFSET \ - CVMX_ADD_IO_SEG(0x00011800A0000060ull) -#define CVMX_PIP_PRT_CFGX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8)) -#define CVMX_PIP_PRT_TAGX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8)) -#define CVMX_PIP_QOS_DIFFX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8)) -#define CVMX_PIP_QOS_VLANX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8)) -#define CVMX_PIP_QOS_WATCHX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8)) -#define CVMX_PIP_RAW_WORD \ - CVMX_ADD_IO_SEG(0x00011800A00000B0ull) -#define CVMX_PIP_SFT_RST \ - CVMX_ADD_IO_SEG(0x00011800A0000030ull) -#define CVMX_PIP_STAT0_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT1_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT2_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT3_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT4_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT5_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT6_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT7_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT8_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT9_PRTX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80)) -#define CVMX_PIP_STAT_CTL \ - CVMX_ADD_IO_SEG(0x00011800A0000018ull) -#define CVMX_PIP_STAT_INB_ERRSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32)) -#define CVMX_PIP_STAT_INB_OCTSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32)) -#define CVMX_PIP_STAT_INB_PKTSX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32)) -#define CVMX_PIP_TAG_INCX(offset) \ - CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8)) -#define CVMX_PIP_TAG_MASK \ - CVMX_ADD_IO_SEG(0x00011800A0000070ull) -#define CVMX_PIP_TAG_SECRET \ - CVMX_ADD_IO_SEG(0x00011800A0000068ull) -#define CVMX_PIP_TODO_ENTRY \ - CVMX_ADD_IO_SEG(0x00011800A0000078ull) - -union cvmx_pip_bck_prs { - uint64_t u64; - struct cvmx_pip_bck_prs_s { - uint64_t bckprs:1; - uint64_t reserved_13_62:50; - uint64_t hiwater:5; - uint64_t reserved_5_7:3; - uint64_t lowater:5; - } s; - struct cvmx_pip_bck_prs_s cn38xx; - struct cvmx_pip_bck_prs_s cn38xxp2; - struct cvmx_pip_bck_prs_s cn56xx; - struct cvmx_pip_bck_prs_s cn56xxp1; - struct cvmx_pip_bck_prs_s cn58xx; - struct cvmx_pip_bck_prs_s cn58xxp1; -}; - -union cvmx_pip_bist_status { - uint64_t u64; - struct cvmx_pip_bist_status_s { - uint64_t reserved_18_63:46; - uint64_t bist:18; - } s; - struct cvmx_pip_bist_status_s cn30xx; - struct cvmx_pip_bist_status_s cn31xx; - struct cvmx_pip_bist_status_s cn38xx; - struct cvmx_pip_bist_status_s cn38xxp2; - struct cvmx_pip_bist_status_cn50xx { - uint64_t reserved_17_63:47; - uint64_t bist:17; - } cn50xx; - struct cvmx_pip_bist_status_s cn52xx; - struct cvmx_pip_bist_status_s cn52xxp1; - struct cvmx_pip_bist_status_s cn56xx; - struct cvmx_pip_bist_status_s cn56xxp1; - struct cvmx_pip_bist_status_s cn58xx; - struct cvmx_pip_bist_status_s cn58xxp1; -}; - -union cvmx_pip_crc_ctlx { - uint64_t u64; - struct cvmx_pip_crc_ctlx_s { - uint64_t reserved_2_63:62; - uint64_t invres:1; - uint64_t reflect:1; - } s; - struct cvmx_pip_crc_ctlx_s cn38xx; - struct cvmx_pip_crc_ctlx_s cn38xxp2; - struct cvmx_pip_crc_ctlx_s cn58xx; - struct cvmx_pip_crc_ctlx_s cn58xxp1; -}; - -union cvmx_pip_crc_ivx { - uint64_t u64; - struct cvmx_pip_crc_ivx_s { - uint64_t reserved_32_63:32; - uint64_t iv:32; - } s; - struct cvmx_pip_crc_ivx_s cn38xx; - struct cvmx_pip_crc_ivx_s cn38xxp2; - struct cvmx_pip_crc_ivx_s cn58xx; - struct cvmx_pip_crc_ivx_s cn58xxp1; -}; - -union cvmx_pip_dec_ipsecx { - uint64_t u64; - struct cvmx_pip_dec_ipsecx_s { - uint64_t reserved_18_63:46; - uint64_t tcp:1; - uint64_t udp:1; - uint64_t dprt:16; - } s; - struct cvmx_pip_dec_ipsecx_s cn30xx; - struct cvmx_pip_dec_ipsecx_s cn31xx; - struct cvmx_pip_dec_ipsecx_s cn38xx; - struct cvmx_pip_dec_ipsecx_s cn38xxp2; - struct cvmx_pip_dec_ipsecx_s cn50xx; - struct cvmx_pip_dec_ipsecx_s cn52xx; - struct cvmx_pip_dec_ipsecx_s cn52xxp1; - struct cvmx_pip_dec_ipsecx_s cn56xx; - struct cvmx_pip_dec_ipsecx_s cn56xxp1; - struct cvmx_pip_dec_ipsecx_s cn58xx; - struct cvmx_pip_dec_ipsecx_s cn58xxp1; -}; - -union cvmx_pip_dsa_src_grp { - uint64_t u64; - struct cvmx_pip_dsa_src_grp_s { - uint64_t map15:4; - uint64_t map14:4; - uint64_t map13:4; - uint64_t map12:4; - uint64_t map11:4; - uint64_t map10:4; - uint64_t map9:4; - uint64_t map8:4; - uint64_t map7:4; - uint64_t map6:4; - uint64_t map5:4; - uint64_t map4:4; - uint64_t map3:4; - uint64_t map2:4; - uint64_t map1:4; - uint64_t map0:4; - } s; - struct cvmx_pip_dsa_src_grp_s cn52xx; - struct cvmx_pip_dsa_src_grp_s cn52xxp1; - struct cvmx_pip_dsa_src_grp_s cn56xx; -}; - -union cvmx_pip_dsa_vid_grp { - uint64_t u64; - struct cvmx_pip_dsa_vid_grp_s { - uint64_t map15:4; - uint64_t map14:4; - uint64_t map13:4; - uint64_t map12:4; - uint64_t map11:4; - uint64_t map10:4; - uint64_t map9:4; - uint64_t map8:4; - uint64_t map7:4; - uint64_t map6:4; - uint64_t map5:4; - uint64_t map4:4; - uint64_t map3:4; - uint64_t map2:4; - uint64_t map1:4; - uint64_t map0:4; - } s; - struct cvmx_pip_dsa_vid_grp_s cn52xx; - struct cvmx_pip_dsa_vid_grp_s cn52xxp1; - struct cvmx_pip_dsa_vid_grp_s cn56xx; -}; - -union cvmx_pip_frm_len_chkx { - uint64_t u64; - struct cvmx_pip_frm_len_chkx_s { - uint64_t reserved_32_63:32; - uint64_t maxlen:16; - uint64_t minlen:16; - } s; - struct cvmx_pip_frm_len_chkx_s cn50xx; - struct cvmx_pip_frm_len_chkx_s cn52xx; - struct cvmx_pip_frm_len_chkx_s cn52xxp1; - struct cvmx_pip_frm_len_chkx_s cn56xx; - struct cvmx_pip_frm_len_chkx_s cn56xxp1; -}; - -union cvmx_pip_gbl_cfg { - uint64_t u64; - struct cvmx_pip_gbl_cfg_s { - uint64_t reserved_19_63:45; - uint64_t tag_syn:1; - uint64_t ip6_udp:1; - uint64_t max_l2:1; - uint64_t reserved_11_15:5; - uint64_t raw_shf:3; - uint64_t reserved_3_7:5; - uint64_t nip_shf:3; - } s; - struct cvmx_pip_gbl_cfg_s cn30xx; - struct cvmx_pip_gbl_cfg_s cn31xx; - struct cvmx_pip_gbl_cfg_s cn38xx; - struct cvmx_pip_gbl_cfg_s cn38xxp2; - struct cvmx_pip_gbl_cfg_s cn50xx; - struct cvmx_pip_gbl_cfg_s cn52xx; - struct cvmx_pip_gbl_cfg_s cn52xxp1; - struct cvmx_pip_gbl_cfg_s cn56xx; - struct cvmx_pip_gbl_cfg_s cn56xxp1; - struct cvmx_pip_gbl_cfg_s cn58xx; - struct cvmx_pip_gbl_cfg_s cn58xxp1; -}; - -union cvmx_pip_gbl_ctl { - uint64_t u64; - struct cvmx_pip_gbl_ctl_s { - uint64_t reserved_27_63:37; - uint64_t dsa_grp_tvid:1; - uint64_t dsa_grp_scmd:1; - uint64_t dsa_grp_sid:1; - uint64_t reserved_21_23:3; - uint64_t ring_en:1; - uint64_t reserved_17_19:3; - uint64_t ignrs:1; - uint64_t vs_wqe:1; - uint64_t vs_qos:1; - uint64_t l2_mal:1; - uint64_t tcp_flag:1; - uint64_t l4_len:1; - uint64_t l4_chk:1; - uint64_t l4_prt:1; - uint64_t l4_mal:1; - uint64_t reserved_6_7:2; - uint64_t ip6_eext:2; - uint64_t ip4_opts:1; - uint64_t ip_hop:1; - uint64_t ip_mal:1; - uint64_t ip_chk:1; - } s; - struct cvmx_pip_gbl_ctl_cn30xx { - uint64_t reserved_17_63:47; - uint64_t ignrs:1; - uint64_t vs_wqe:1; - uint64_t vs_qos:1; - uint64_t l2_mal:1; - uint64_t tcp_flag:1; - uint64_t l4_len:1; - uint64_t l4_chk:1; - uint64_t l4_prt:1; - uint64_t l4_mal:1; - uint64_t reserved_6_7:2; - uint64_t ip6_eext:2; - uint64_t ip4_opts:1; - uint64_t ip_hop:1; - uint64_t ip_mal:1; - uint64_t ip_chk:1; - } cn30xx; - struct cvmx_pip_gbl_ctl_cn30xx cn31xx; - struct cvmx_pip_gbl_ctl_cn30xx cn38xx; - struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; - struct cvmx_pip_gbl_ctl_cn30xx cn50xx; - struct cvmx_pip_gbl_ctl_s cn52xx; - struct cvmx_pip_gbl_ctl_s cn52xxp1; - struct cvmx_pip_gbl_ctl_s cn56xx; - struct cvmx_pip_gbl_ctl_cn56xxp1 { - uint64_t reserved_21_63:43; - uint64_t ring_en:1; - uint64_t reserved_17_19:3; - uint64_t ignrs:1; - uint64_t vs_wqe:1; - uint64_t vs_qos:1; - uint64_t l2_mal:1; - uint64_t tcp_flag:1; - uint64_t l4_len:1; - uint64_t l4_chk:1; - uint64_t l4_prt:1; - uint64_t l4_mal:1; - uint64_t reserved_6_7:2; - uint64_t ip6_eext:2; - uint64_t ip4_opts:1; - uint64_t ip_hop:1; - uint64_t ip_mal:1; - uint64_t ip_chk:1; - } cn56xxp1; - struct cvmx_pip_gbl_ctl_cn30xx cn58xx; - struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; -}; - -union cvmx_pip_hg_pri_qos { - uint64_t u64; - struct cvmx_pip_hg_pri_qos_s { - uint64_t reserved_11_63:53; - uint64_t qos:3; - uint64_t reserved_6_7:2; - uint64_t pri:6; - } s; - struct cvmx_pip_hg_pri_qos_s cn52xx; - struct cvmx_pip_hg_pri_qos_s cn52xxp1; - struct cvmx_pip_hg_pri_qos_s cn56xx; -}; - -union cvmx_pip_int_en { - uint64_t u64; - struct cvmx_pip_int_en_s { - uint64_t reserved_13_63:51; - uint64_t punyerr:1; - uint64_t lenerr:1; - uint64_t maxerr:1; - uint64_t minerr:1; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t crcerr:1; - uint64_t pktdrp:1; - } s; - struct cvmx_pip_int_en_cn30xx { - uint64_t reserved_9_63:55; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t crcerr:1; - uint64_t pktdrp:1; - } cn30xx; - struct cvmx_pip_int_en_cn30xx cn31xx; - struct cvmx_pip_int_en_cn30xx cn38xx; - struct cvmx_pip_int_en_cn30xx cn38xxp2; - struct cvmx_pip_int_en_cn50xx { - uint64_t reserved_12_63:52; - uint64_t lenerr:1; - uint64_t maxerr:1; - uint64_t minerr:1; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t reserved_1_1:1; - uint64_t pktdrp:1; - } cn50xx; - struct cvmx_pip_int_en_cn52xx { - uint64_t reserved_13_63:51; - uint64_t punyerr:1; - uint64_t lenerr:1; - uint64_t maxerr:1; - uint64_t minerr:1; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t reserved_1_1:1; - uint64_t pktdrp:1; - } cn52xx; - struct cvmx_pip_int_en_cn52xx cn52xxp1; - struct cvmx_pip_int_en_s cn56xx; - struct cvmx_pip_int_en_cn56xxp1 { - uint64_t reserved_12_63:52; - uint64_t lenerr:1; - uint64_t maxerr:1; - uint64_t minerr:1; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t crcerr:1; - uint64_t pktdrp:1; - } cn56xxp1; - struct cvmx_pip_int_en_cn58xx { - uint64_t reserved_13_63:51; - uint64_t punyerr:1; - uint64_t reserved_9_11:3; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t crcerr:1; - uint64_t pktdrp:1; - } cn58xx; - struct cvmx_pip_int_en_cn30xx cn58xxp1; -}; - -union cvmx_pip_int_reg { - uint64_t u64; - struct cvmx_pip_int_reg_s { - uint64_t reserved_13_63:51; - uint64_t punyerr:1; - uint64_t lenerr:1; - uint64_t maxerr:1; - uint64_t minerr:1; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t crcerr:1; - uint64_t pktdrp:1; - } s; - struct cvmx_pip_int_reg_cn30xx { - uint64_t reserved_9_63:55; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t crcerr:1; - uint64_t pktdrp:1; - } cn30xx; - struct cvmx_pip_int_reg_cn30xx cn31xx; - struct cvmx_pip_int_reg_cn30xx cn38xx; - struct cvmx_pip_int_reg_cn30xx cn38xxp2; - struct cvmx_pip_int_reg_cn50xx { - uint64_t reserved_12_63:52; - uint64_t lenerr:1; - uint64_t maxerr:1; - uint64_t minerr:1; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t reserved_1_1:1; - uint64_t pktdrp:1; - } cn50xx; - struct cvmx_pip_int_reg_cn52xx { - uint64_t reserved_13_63:51; - uint64_t punyerr:1; - uint64_t lenerr:1; - uint64_t maxerr:1; - uint64_t minerr:1; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t reserved_1_1:1; - uint64_t pktdrp:1; - } cn52xx; - struct cvmx_pip_int_reg_cn52xx cn52xxp1; - struct cvmx_pip_int_reg_s cn56xx; - struct cvmx_pip_int_reg_cn56xxp1 { - uint64_t reserved_12_63:52; - uint64_t lenerr:1; - uint64_t maxerr:1; - uint64_t minerr:1; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t crcerr:1; - uint64_t pktdrp:1; - } cn56xxp1; - struct cvmx_pip_int_reg_cn58xx { - uint64_t reserved_13_63:51; - uint64_t punyerr:1; - uint64_t reserved_9_11:3; - uint64_t beperr:1; - uint64_t feperr:1; - uint64_t todoovr:1; - uint64_t skprunt:1; - uint64_t badtag:1; - uint64_t prtnxa:1; - uint64_t bckprs:1; - uint64_t crcerr:1; - uint64_t pktdrp:1; - } cn58xx; - struct cvmx_pip_int_reg_cn30xx cn58xxp1; -}; - -union cvmx_pip_ip_offset { - uint64_t u64; - struct cvmx_pip_ip_offset_s { - uint64_t reserved_3_63:61; - uint64_t offset:3; - } s; - struct cvmx_pip_ip_offset_s cn30xx; - struct cvmx_pip_ip_offset_s cn31xx; - struct cvmx_pip_ip_offset_s cn38xx; - struct cvmx_pip_ip_offset_s cn38xxp2; - struct cvmx_pip_ip_offset_s cn50xx; - struct cvmx_pip_ip_offset_s cn52xx; - struct cvmx_pip_ip_offset_s cn52xxp1; - struct cvmx_pip_ip_offset_s cn56xx; - struct cvmx_pip_ip_offset_s cn56xxp1; - struct cvmx_pip_ip_offset_s cn58xx; - struct cvmx_pip_ip_offset_s cn58xxp1; -}; - -union cvmx_pip_prt_cfgx { - uint64_t u64; - struct cvmx_pip_prt_cfgx_s { - uint64_t reserved_53_63:11; - uint64_t pad_len:1; - uint64_t vlan_len:1; - uint64_t lenerr_en:1; - uint64_t maxerr_en:1; - uint64_t minerr_en:1; - uint64_t grp_wat_47:4; - uint64_t qos_wat_47:4; - uint64_t reserved_37_39:3; - uint64_t rawdrp:1; - uint64_t tag_inc:2; - uint64_t dyn_rs:1; - uint64_t inst_hdr:1; - uint64_t grp_wat:4; - uint64_t hg_qos:1; - uint64_t qos:3; - uint64_t qos_wat:4; - uint64_t qos_vsel:1; - uint64_t qos_vod:1; - uint64_t qos_diff:1; - uint64_t qos_vlan:1; - uint64_t reserved_13_15:3; - uint64_t crc_en:1; - uint64_t higig_en:1; - uint64_t dsa_en:1; - uint64_t mode:2; - uint64_t reserved_7_7:1; - uint64_t skip:7; - } s; - struct cvmx_pip_prt_cfgx_cn30xx { - uint64_t reserved_37_63:27; - uint64_t rawdrp:1; - uint64_t tag_inc:2; - uint64_t dyn_rs:1; - uint64_t inst_hdr:1; - uint64_t grp_wat:4; - uint64_t reserved_27_27:1; - uint64_t qos:3; - uint64_t qos_wat:4; - uint64_t reserved_18_19:2; - uint64_t qos_diff:1; - uint64_t qos_vlan:1; - uint64_t reserved_10_15:6; - uint64_t mode:2; - uint64_t reserved_7_7:1; - uint64_t skip:7; - } cn30xx; - struct cvmx_pip_prt_cfgx_cn30xx cn31xx; - struct cvmx_pip_prt_cfgx_cn38xx { - uint64_t reserved_37_63:27; - uint64_t rawdrp:1; - uint64_t tag_inc:2; - uint64_t dyn_rs:1; - uint64_t inst_hdr:1; - uint64_t grp_wat:4; - uint64_t reserved_27_27:1; - uint64_t qos:3; - uint64_t qos_wat:4; - uint64_t reserved_18_19:2; - uint64_t qos_diff:1; - uint64_t qos_vlan:1; - uint64_t reserved_13_15:3; - uint64_t crc_en:1; - uint64_t reserved_10_11:2; - uint64_t mode:2; - uint64_t reserved_7_7:1; - uint64_t skip:7; - } cn38xx; - struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; - struct cvmx_pip_prt_cfgx_cn50xx { - uint64_t reserved_53_63:11; - uint64_t pad_len:1; - uint64_t vlan_len:1; - uint64_t lenerr_en:1; - uint64_t maxerr_en:1; - uint64_t minerr_en:1; - uint64_t grp_wat_47:4; - uint64_t qos_wat_47:4; - uint64_t reserved_37_39:3; - uint64_t rawdrp:1; - uint64_t tag_inc:2; - uint64_t dyn_rs:1; - uint64_t inst_hdr:1; - uint64_t grp_wat:4; - uint64_t reserved_27_27:1; - uint64_t qos:3; - uint64_t qos_wat:4; - uint64_t reserved_19_19:1; - uint64_t qos_vod:1; - uint64_t qos_diff:1; - uint64_t qos_vlan:1; - uint64_t reserved_13_15:3; - uint64_t crc_en:1; - uint64_t reserved_10_11:2; - uint64_t mode:2; - uint64_t reserved_7_7:1; - uint64_t skip:7; - } cn50xx; - struct cvmx_pip_prt_cfgx_s cn52xx; - struct cvmx_pip_prt_cfgx_s cn52xxp1; - struct cvmx_pip_prt_cfgx_s cn56xx; - struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; - struct cvmx_pip_prt_cfgx_cn58xx { - uint64_t reserved_37_63:27; - uint64_t rawdrp:1; - uint64_t tag_inc:2; - uint64_t dyn_rs:1; - uint64_t inst_hdr:1; - uint64_t grp_wat:4; - uint64_t reserved_27_27:1; - uint64_t qos:3; - uint64_t qos_wat:4; - uint64_t reserved_19_19:1; - uint64_t qos_vod:1; - uint64_t qos_diff:1; - uint64_t qos_vlan:1; - uint64_t reserved_13_15:3; - uint64_t crc_en:1; - uint64_t reserved_10_11:2; - uint64_t mode:2; - uint64_t reserved_7_7:1; - uint64_t skip:7; - } cn58xx; - struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; -}; - -union cvmx_pip_prt_tagx { - uint64_t u64; - struct cvmx_pip_prt_tagx_s { - uint64_t reserved_40_63:24; - uint64_t grptagbase:4; - uint64_t grptagmask:4; - uint64_t grptag:1; - uint64_t grptag_mskip:1; - uint64_t tag_mode:2; - uint64_t inc_vs:2; - uint64_t inc_vlan:1; - uint64_t inc_prt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_src_flag:1; - uint64_t tcp6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t non_tag_type:2; - uint64_t grp:4; - } s; - struct cvmx_pip_prt_tagx_cn30xx { - uint64_t reserved_40_63:24; - uint64_t grptagbase:4; - uint64_t grptagmask:4; - uint64_t grptag:1; - uint64_t reserved_30_30:1; - uint64_t tag_mode:2; - uint64_t inc_vs:2; - uint64_t inc_vlan:1; - uint64_t inc_prt_flag:1; - uint64_t ip6_dprt_flag:1; - uint64_t ip4_dprt_flag:1; - uint64_t ip6_sprt_flag:1; - uint64_t ip4_sprt_flag:1; - uint64_t ip6_nxth_flag:1; - uint64_t ip4_pctl_flag:1; - uint64_t ip6_dst_flag:1; - uint64_t ip4_dst_flag:1; - uint64_t ip6_src_flag:1; - uint64_t ip4_src_flag:1; - uint64_t tcp6_tag_type:2; - uint64_t tcp4_tag_type:2; - uint64_t ip6_tag_type:2; - uint64_t ip4_tag_type:2; - uint64_t non_tag_type:2; - uint64_t grp:4; - } cn30xx; - struct cvmx_pip_prt_tagx_cn30xx cn31xx; - struct cvmx_pip_prt_tagx_cn30xx cn38xx; - struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; - struct cvmx_pip_prt_tagx_s cn50xx; - struct cvmx_pip_prt_tagx_s cn52xx; - struct cvmx_pip_prt_tagx_s cn52xxp1; - struct cvmx_pip_prt_tagx_s cn56xx; - struct cvmx_pip_prt_tagx_s cn56xxp1; - struct cvmx_pip_prt_tagx_cn30xx cn58xx; - struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; -}; - -union cvmx_pip_qos_diffx { - uint64_t u64; - struct cvmx_pip_qos_diffx_s { - uint64_t reserved_3_63:61; - uint64_t qos:3; - } s; - struct cvmx_pip_qos_diffx_s cn30xx; - struct cvmx_pip_qos_diffx_s cn31xx; - struct cvmx_pip_qos_diffx_s cn38xx; - struct cvmx_pip_qos_diffx_s cn38xxp2; - struct cvmx_pip_qos_diffx_s cn50xx; - struct cvmx_pip_qos_diffx_s cn52xx; - struct cvmx_pip_qos_diffx_s cn52xxp1; - struct cvmx_pip_qos_diffx_s cn56xx; - struct cvmx_pip_qos_diffx_s cn56xxp1; - struct cvmx_pip_qos_diffx_s cn58xx; - struct cvmx_pip_qos_diffx_s cn58xxp1; -}; - -union cvmx_pip_qos_vlanx { - uint64_t u64; - struct cvmx_pip_qos_vlanx_s { - uint64_t reserved_7_63:57; - uint64_t qos1:3; - uint64_t reserved_3_3:1; - uint64_t qos:3; - } s; - struct cvmx_pip_qos_vlanx_cn30xx { - uint64_t reserved_3_63:61; - uint64_t qos:3; - } cn30xx; - struct cvmx_pip_qos_vlanx_cn30xx cn31xx; - struct cvmx_pip_qos_vlanx_cn30xx cn38xx; - struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2; - struct cvmx_pip_qos_vlanx_cn30xx cn50xx; - struct cvmx_pip_qos_vlanx_s cn52xx; - struct cvmx_pip_qos_vlanx_s cn52xxp1; - struct cvmx_pip_qos_vlanx_s cn56xx; - struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; - struct cvmx_pip_qos_vlanx_cn30xx cn58xx; - struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; -}; - -union cvmx_pip_qos_watchx { - uint64_t u64; - struct cvmx_pip_qos_watchx_s { - uint64_t reserved_48_63:16; - uint64_t mask:16; - uint64_t reserved_28_31:4; - uint64_t grp:4; - uint64_t reserved_23_23:1; - uint64_t qos:3; - uint64_t reserved_19_19:1; - uint64_t match_type:3; - uint64_t match_value:16; - } s; - struct cvmx_pip_qos_watchx_cn30xx { - uint64_t reserved_48_63:16; - uint64_t mask:16; - uint64_t reserved_28_31:4; - uint64_t grp:4; - uint64_t reserved_23_23:1; - uint64_t qos:3; - uint64_t reserved_18_19:2; - uint64_t match_type:2; - uint64_t match_value:16; - } cn30xx; - struct cvmx_pip_qos_watchx_cn30xx cn31xx; - struct cvmx_pip_qos_watchx_cn30xx cn38xx; - struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; - struct cvmx_pip_qos_watchx_s cn50xx; - struct cvmx_pip_qos_watchx_s cn52xx; - struct cvmx_pip_qos_watchx_s cn52xxp1; - struct cvmx_pip_qos_watchx_s cn56xx; - struct cvmx_pip_qos_watchx_s cn56xxp1; - struct cvmx_pip_qos_watchx_cn30xx cn58xx; - struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; -}; - -union cvmx_pip_raw_word { - uint64_t u64; - struct cvmx_pip_raw_word_s { - uint64_t reserved_56_63:8; - uint64_t word:56; - } s; - struct cvmx_pip_raw_word_s cn30xx; - struct cvmx_pip_raw_word_s cn31xx; - struct cvmx_pip_raw_word_s cn38xx; - struct cvmx_pip_raw_word_s cn38xxp2; - struct cvmx_pip_raw_word_s cn50xx; - struct cvmx_pip_raw_word_s cn52xx; - struct cvmx_pip_raw_word_s cn52xxp1; - struct cvmx_pip_raw_word_s cn56xx; - struct cvmx_pip_raw_word_s cn56xxp1; - struct cvmx_pip_raw_word_s cn58xx; - struct cvmx_pip_raw_word_s cn58xxp1; -}; - -union cvmx_pip_sft_rst { - uint64_t u64; - struct cvmx_pip_sft_rst_s { - uint64_t reserved_1_63:63; - uint64_t rst:1; - } s; - struct cvmx_pip_sft_rst_s cn30xx; - struct cvmx_pip_sft_rst_s cn31xx; - struct cvmx_pip_sft_rst_s cn38xx; - struct cvmx_pip_sft_rst_s cn50xx; - struct cvmx_pip_sft_rst_s cn52xx; - struct cvmx_pip_sft_rst_s cn52xxp1; - struct cvmx_pip_sft_rst_s cn56xx; - struct cvmx_pip_sft_rst_s cn56xxp1; - struct cvmx_pip_sft_rst_s cn58xx; - struct cvmx_pip_sft_rst_s cn58xxp1; -}; - -union cvmx_pip_stat0_prtx { - uint64_t u64; - struct cvmx_pip_stat0_prtx_s { - uint64_t drp_pkts:32; - uint64_t drp_octs:32; - } s; - struct cvmx_pip_stat0_prtx_s cn30xx; - struct cvmx_pip_stat0_prtx_s cn31xx; - struct cvmx_pip_stat0_prtx_s cn38xx; - struct cvmx_pip_stat0_prtx_s cn38xxp2; - struct cvmx_pip_stat0_prtx_s cn50xx; - struct cvmx_pip_stat0_prtx_s cn52xx; - struct cvmx_pip_stat0_prtx_s cn52xxp1; - struct cvmx_pip_stat0_prtx_s cn56xx; - struct cvmx_pip_stat0_prtx_s cn56xxp1; - struct cvmx_pip_stat0_prtx_s cn58xx; - struct cvmx_pip_stat0_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat1_prtx { - uint64_t u64; - struct cvmx_pip_stat1_prtx_s { - uint64_t reserved_48_63:16; - uint64_t octs:48; - } s; - struct cvmx_pip_stat1_prtx_s cn30xx; - struct cvmx_pip_stat1_prtx_s cn31xx; - struct cvmx_pip_stat1_prtx_s cn38xx; - struct cvmx_pip_stat1_prtx_s cn38xxp2; - struct cvmx_pip_stat1_prtx_s cn50xx; - struct cvmx_pip_stat1_prtx_s cn52xx; - struct cvmx_pip_stat1_prtx_s cn52xxp1; - struct cvmx_pip_stat1_prtx_s cn56xx; - struct cvmx_pip_stat1_prtx_s cn56xxp1; - struct cvmx_pip_stat1_prtx_s cn58xx; - struct cvmx_pip_stat1_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat2_prtx { - uint64_t u64; - struct cvmx_pip_stat2_prtx_s { - uint64_t pkts:32; - uint64_t raw:32; - } s; - struct cvmx_pip_stat2_prtx_s cn30xx; - struct cvmx_pip_stat2_prtx_s cn31xx; - struct cvmx_pip_stat2_prtx_s cn38xx; - struct cvmx_pip_stat2_prtx_s cn38xxp2; - struct cvmx_pip_stat2_prtx_s cn50xx; - struct cvmx_pip_stat2_prtx_s cn52xx; - struct cvmx_pip_stat2_prtx_s cn52xxp1; - struct cvmx_pip_stat2_prtx_s cn56xx; - struct cvmx_pip_stat2_prtx_s cn56xxp1; - struct cvmx_pip_stat2_prtx_s cn58xx; - struct cvmx_pip_stat2_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat3_prtx { - uint64_t u64; - struct cvmx_pip_stat3_prtx_s { - uint64_t bcst:32; - uint64_t mcst:32; - } s; - struct cvmx_pip_stat3_prtx_s cn30xx; - struct cvmx_pip_stat3_prtx_s cn31xx; - struct cvmx_pip_stat3_prtx_s cn38xx; - struct cvmx_pip_stat3_prtx_s cn38xxp2; - struct cvmx_pip_stat3_prtx_s cn50xx; - struct cvmx_pip_stat3_prtx_s cn52xx; - struct cvmx_pip_stat3_prtx_s cn52xxp1; - struct cvmx_pip_stat3_prtx_s cn56xx; - struct cvmx_pip_stat3_prtx_s cn56xxp1; - struct cvmx_pip_stat3_prtx_s cn58xx; - struct cvmx_pip_stat3_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat4_prtx { - uint64_t u64; - struct cvmx_pip_stat4_prtx_s { - uint64_t h65to127:32; - uint64_t h64:32; - } s; - struct cvmx_pip_stat4_prtx_s cn30xx; - struct cvmx_pip_stat4_prtx_s cn31xx; - struct cvmx_pip_stat4_prtx_s cn38xx; - struct cvmx_pip_stat4_prtx_s cn38xxp2; - struct cvmx_pip_stat4_prtx_s cn50xx; - struct cvmx_pip_stat4_prtx_s cn52xx; - struct cvmx_pip_stat4_prtx_s cn52xxp1; - struct cvmx_pip_stat4_prtx_s cn56xx; - struct cvmx_pip_stat4_prtx_s cn56xxp1; - struct cvmx_pip_stat4_prtx_s cn58xx; - struct cvmx_pip_stat4_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat5_prtx { - uint64_t u64; - struct cvmx_pip_stat5_prtx_s { - uint64_t h256to511:32; - uint64_t h128to255:32; - } s; - struct cvmx_pip_stat5_prtx_s cn30xx; - struct cvmx_pip_stat5_prtx_s cn31xx; - struct cvmx_pip_stat5_prtx_s cn38xx; - struct cvmx_pip_stat5_prtx_s cn38xxp2; - struct cvmx_pip_stat5_prtx_s cn50xx; - struct cvmx_pip_stat5_prtx_s cn52xx; - struct cvmx_pip_stat5_prtx_s cn52xxp1; - struct cvmx_pip_stat5_prtx_s cn56xx; - struct cvmx_pip_stat5_prtx_s cn56xxp1; - struct cvmx_pip_stat5_prtx_s cn58xx; - struct cvmx_pip_stat5_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat6_prtx { - uint64_t u64; - struct cvmx_pip_stat6_prtx_s { - uint64_t h1024to1518:32; - uint64_t h512to1023:32; - } s; - struct cvmx_pip_stat6_prtx_s cn30xx; - struct cvmx_pip_stat6_prtx_s cn31xx; - struct cvmx_pip_stat6_prtx_s cn38xx; - struct cvmx_pip_stat6_prtx_s cn38xxp2; - struct cvmx_pip_stat6_prtx_s cn50xx; - struct cvmx_pip_stat6_prtx_s cn52xx; - struct cvmx_pip_stat6_prtx_s cn52xxp1; - struct cvmx_pip_stat6_prtx_s cn56xx; - struct cvmx_pip_stat6_prtx_s cn56xxp1; - struct cvmx_pip_stat6_prtx_s cn58xx; - struct cvmx_pip_stat6_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat7_prtx { - uint64_t u64; - struct cvmx_pip_stat7_prtx_s { - uint64_t fcs:32; - uint64_t h1519:32; - } s; - struct cvmx_pip_stat7_prtx_s cn30xx; - struct cvmx_pip_stat7_prtx_s cn31xx; - struct cvmx_pip_stat7_prtx_s cn38xx; - struct cvmx_pip_stat7_prtx_s cn38xxp2; - struct cvmx_pip_stat7_prtx_s cn50xx; - struct cvmx_pip_stat7_prtx_s cn52xx; - struct cvmx_pip_stat7_prtx_s cn52xxp1; - struct cvmx_pip_stat7_prtx_s cn56xx; - struct cvmx_pip_stat7_prtx_s cn56xxp1; - struct cvmx_pip_stat7_prtx_s cn58xx; - struct cvmx_pip_stat7_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat8_prtx { - uint64_t u64; - struct cvmx_pip_stat8_prtx_s { - uint64_t frag:32; - uint64_t undersz:32; - } s; - struct cvmx_pip_stat8_prtx_s cn30xx; - struct cvmx_pip_stat8_prtx_s cn31xx; - struct cvmx_pip_stat8_prtx_s cn38xx; - struct cvmx_pip_stat8_prtx_s cn38xxp2; - struct cvmx_pip_stat8_prtx_s cn50xx; - struct cvmx_pip_stat8_prtx_s cn52xx; - struct cvmx_pip_stat8_prtx_s cn52xxp1; - struct cvmx_pip_stat8_prtx_s cn56xx; - struct cvmx_pip_stat8_prtx_s cn56xxp1; - struct cvmx_pip_stat8_prtx_s cn58xx; - struct cvmx_pip_stat8_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat9_prtx { - uint64_t u64; - struct cvmx_pip_stat9_prtx_s { - uint64_t jabber:32; - uint64_t oversz:32; - } s; - struct cvmx_pip_stat9_prtx_s cn30xx; - struct cvmx_pip_stat9_prtx_s cn31xx; - struct cvmx_pip_stat9_prtx_s cn38xx; - struct cvmx_pip_stat9_prtx_s cn38xxp2; - struct cvmx_pip_stat9_prtx_s cn50xx; - struct cvmx_pip_stat9_prtx_s cn52xx; - struct cvmx_pip_stat9_prtx_s cn52xxp1; - struct cvmx_pip_stat9_prtx_s cn56xx; - struct cvmx_pip_stat9_prtx_s cn56xxp1; - struct cvmx_pip_stat9_prtx_s cn58xx; - struct cvmx_pip_stat9_prtx_s cn58xxp1; -}; - -union cvmx_pip_stat_ctl { - uint64_t u64; - struct cvmx_pip_stat_ctl_s { - uint64_t reserved_1_63:63; - uint64_t rdclr:1; - } s; - struct cvmx_pip_stat_ctl_s cn30xx; - struct cvmx_pip_stat_ctl_s cn31xx; - struct cvmx_pip_stat_ctl_s cn38xx; - struct cvmx_pip_stat_ctl_s cn38xxp2; - struct cvmx_pip_stat_ctl_s cn50xx; - struct cvmx_pip_stat_ctl_s cn52xx; - struct cvmx_pip_stat_ctl_s cn52xxp1; - struct cvmx_pip_stat_ctl_s cn56xx; - struct cvmx_pip_stat_ctl_s cn56xxp1; - struct cvmx_pip_stat_ctl_s cn58xx; - struct cvmx_pip_stat_ctl_s cn58xxp1; -}; - -union cvmx_pip_stat_inb_errsx { - uint64_t u64; - struct cvmx_pip_stat_inb_errsx_s { - uint64_t reserved_16_63:48; - uint64_t errs:16; - } s; - struct cvmx_pip_stat_inb_errsx_s cn30xx; - struct cvmx_pip_stat_inb_errsx_s cn31xx; - struct cvmx_pip_stat_inb_errsx_s cn38xx; - struct cvmx_pip_stat_inb_errsx_s cn38xxp2; - struct cvmx_pip_stat_inb_errsx_s cn50xx; - struct cvmx_pip_stat_inb_errsx_s cn52xx; - struct cvmx_pip_stat_inb_errsx_s cn52xxp1; - struct cvmx_pip_stat_inb_errsx_s cn56xx; - struct cvmx_pip_stat_inb_errsx_s cn56xxp1; - struct cvmx_pip_stat_inb_errsx_s cn58xx; - struct cvmx_pip_stat_inb_errsx_s cn58xxp1; -}; - -union cvmx_pip_stat_inb_octsx { - uint64_t u64; - struct cvmx_pip_stat_inb_octsx_s { - uint64_t reserved_48_63:16; - uint64_t octs:48; - } s; - struct cvmx_pip_stat_inb_octsx_s cn30xx; - struct cvmx_pip_stat_inb_octsx_s cn31xx; - struct cvmx_pip_stat_inb_octsx_s cn38xx; - struct cvmx_pip_stat_inb_octsx_s cn38xxp2; - struct cvmx_pip_stat_inb_octsx_s cn50xx; - struct cvmx_pip_stat_inb_octsx_s cn52xx; - struct cvmx_pip_stat_inb_octsx_s cn52xxp1; - struct cvmx_pip_stat_inb_octsx_s cn56xx; - struct cvmx_pip_stat_inb_octsx_s cn56xxp1; - struct cvmx_pip_stat_inb_octsx_s cn58xx; - struct cvmx_pip_stat_inb_octsx_s cn58xxp1; -}; - -union cvmx_pip_stat_inb_pktsx { - uint64_t u64; - struct cvmx_pip_stat_inb_pktsx_s { - uint64_t reserved_32_63:32; - uint64_t pkts:32; - } s; - struct cvmx_pip_stat_inb_pktsx_s cn30xx; - struct cvmx_pip_stat_inb_pktsx_s cn31xx; - struct cvmx_pip_stat_inb_pktsx_s cn38xx; - struct cvmx_pip_stat_inb_pktsx_s cn38xxp2; - struct cvmx_pip_stat_inb_pktsx_s cn50xx; - struct cvmx_pip_stat_inb_pktsx_s cn52xx; - struct cvmx_pip_stat_inb_pktsx_s cn52xxp1; - struct cvmx_pip_stat_inb_pktsx_s cn56xx; - struct cvmx_pip_stat_inb_pktsx_s cn56xxp1; - struct cvmx_pip_stat_inb_pktsx_s cn58xx; - struct cvmx_pip_stat_inb_pktsx_s cn58xxp1; -}; - -union cvmx_pip_tag_incx { - uint64_t u64; - struct cvmx_pip_tag_incx_s { - uint64_t reserved_8_63:56; - uint64_t en:8; - } s; - struct cvmx_pip_tag_incx_s cn30xx; - struct cvmx_pip_tag_incx_s cn31xx; - struct cvmx_pip_tag_incx_s cn38xx; - struct cvmx_pip_tag_incx_s cn38xxp2; - struct cvmx_pip_tag_incx_s cn50xx; - struct cvmx_pip_tag_incx_s cn52xx; - struct cvmx_pip_tag_incx_s cn52xxp1; - struct cvmx_pip_tag_incx_s cn56xx; - struct cvmx_pip_tag_incx_s cn56xxp1; - struct cvmx_pip_tag_incx_s cn58xx; - struct cvmx_pip_tag_incx_s cn58xxp1; -}; - -union cvmx_pip_tag_mask { - uint64_t u64; - struct cvmx_pip_tag_mask_s { - uint64_t reserved_16_63:48; - uint64_t mask:16; - } s; - struct cvmx_pip_tag_mask_s cn30xx; - struct cvmx_pip_tag_mask_s cn31xx; - struct cvmx_pip_tag_mask_s cn38xx; - struct cvmx_pip_tag_mask_s cn38xxp2; - struct cvmx_pip_tag_mask_s cn50xx; - struct cvmx_pip_tag_mask_s cn52xx; - struct cvmx_pip_tag_mask_s cn52xxp1; - struct cvmx_pip_tag_mask_s cn56xx; - struct cvmx_pip_tag_mask_s cn56xxp1; - struct cvmx_pip_tag_mask_s cn58xx; - struct cvmx_pip_tag_mask_s cn58xxp1; -}; - -union cvmx_pip_tag_secret { - uint64_t u64; - struct cvmx_pip_tag_secret_s { - uint64_t reserved_32_63:32; - uint64_t dst:16; - uint64_t src:16; - } s; - struct cvmx_pip_tag_secret_s cn30xx; - struct cvmx_pip_tag_secret_s cn31xx; - struct cvmx_pip_tag_secret_s cn38xx; - struct cvmx_pip_tag_secret_s cn38xxp2; - struct cvmx_pip_tag_secret_s cn50xx; - struct cvmx_pip_tag_secret_s cn52xx; - struct cvmx_pip_tag_secret_s cn52xxp1; - struct cvmx_pip_tag_secret_s cn56xx; - struct cvmx_pip_tag_secret_s cn56xxp1; - struct cvmx_pip_tag_secret_s cn58xx; - struct cvmx_pip_tag_secret_s cn58xxp1; -}; - -union cvmx_pip_todo_entry { - uint64_t u64; - struct cvmx_pip_todo_entry_s { - uint64_t val:1; - uint64_t reserved_62_62:1; - uint64_t entry:62; - } s; - struct cvmx_pip_todo_entry_s cn30xx; - struct cvmx_pip_todo_entry_s cn31xx; - struct cvmx_pip_todo_entry_s cn38xx; - struct cvmx_pip_todo_entry_s cn38xxp2; - struct cvmx_pip_todo_entry_s cn50xx; - struct cvmx_pip_todo_entry_s cn52xx; - struct cvmx_pip_todo_entry_s cn52xxp1; - struct cvmx_pip_todo_entry_s cn56xx; - struct cvmx_pip_todo_entry_s cn56xxp1; - struct cvmx_pip_todo_entry_s cn58xx; - struct cvmx_pip_todo_entry_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-pip.h b/drivers/staging/octeon/cvmx-pip.h deleted file mode 100644 index 78dbce8f2c5e..000000000000 --- a/drivers/staging/octeon/cvmx-pip.h +++ /dev/null @@ -1,524 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Interface to the hardware Packet Input Processing unit. - * - */ - -#ifndef __CVMX_PIP_H__ -#define __CVMX_PIP_H__ - -#include "cvmx-wqe.h" -#include "cvmx-fpa.h" -#include "cvmx-pip-defs.h" - -#define CVMX_PIP_NUM_INPUT_PORTS 40 -#define CVMX_PIP_NUM_WATCHERS 4 - -/* - * Encodes the different error and exception codes - */ -typedef enum { - CVMX_PIP_L4_NO_ERR = 0ull, - /* - * 1 = TCP (UDP) packet not long enough to cover TCP (UDP) - * header - */ - CVMX_PIP_L4_MAL_ERR = 1ull, - /* 2 = TCP/UDP checksum failure */ - CVMX_PIP_CHK_ERR = 2ull, - /* - * 3 = TCP/UDP length check (TCP/UDP length does not match IP - * length). - */ - CVMX_PIP_L4_LENGTH_ERR = 3ull, - /* 4 = illegal TCP/UDP port (either source or dest port is zero) */ - CVMX_PIP_BAD_PRT_ERR = 4ull, - /* 8 = TCP flags = FIN only */ - CVMX_PIP_TCP_FLG8_ERR = 8ull, - /* 9 = TCP flags = 0 */ - CVMX_PIP_TCP_FLG9_ERR = 9ull, - /* 10 = TCP flags = FIN+RST+* */ - CVMX_PIP_TCP_FLG10_ERR = 10ull, - /* 11 = TCP flags = SYN+URG+* */ - CVMX_PIP_TCP_FLG11_ERR = 11ull, - /* 12 = TCP flags = SYN+RST+* */ - CVMX_PIP_TCP_FLG12_ERR = 12ull, - /* 13 = TCP flags = SYN+FIN+* */ - CVMX_PIP_TCP_FLG13_ERR = 13ull -} cvmx_pip_l4_err_t; - -typedef enum { - - CVMX_PIP_IP_NO_ERR = 0ull, - /* 1 = not IPv4 or IPv6 */ - CVMX_PIP_NOT_IP = 1ull, - /* 2 = IPv4 header checksum violation */ - CVMX_PIP_IPV4_HDR_CHK = 2ull, - /* 3 = malformed (packet not long enough to cover IP hdr) */ - CVMX_PIP_IP_MAL_HDR = 3ull, - /* 4 = malformed (packet not long enough to cover len in IP hdr) */ - CVMX_PIP_IP_MAL_PKT = 4ull, - /* 5 = TTL / hop count equal zero */ - CVMX_PIP_TTL_HOP = 5ull, - /* 6 = IPv4 options / IPv6 early extension headers */ - CVMX_PIP_OPTS = 6ull -} cvmx_pip_ip_exc_t; - -/** - * NOTES - * late collision (data received before collision) - * late collisions cannot be detected by the receiver - * they would appear as JAM bits which would appear as bad FCS - * or carrier extend error which is CVMX_PIP_EXTEND_ERR - */ -typedef enum { - /* No error */ - CVMX_PIP_RX_NO_ERR = 0ull, - /* RGM+SPI 1 = partially received packet (buffering/bandwidth - * not adequate) */ - CVMX_PIP_PARTIAL_ERR = 1ull, - /* RGM+SPI 2 = receive packet too large and truncated */ - CVMX_PIP_JABBER_ERR = 2ull, - /* - * RGM 3 = max frame error (pkt len > max frame len) (with FCS - * error) - */ - CVMX_PIP_OVER_FCS_ERR = 3ull, - /* RGM+SPI 4 = max frame error (pkt len > max frame len) */ - CVMX_PIP_OVER_ERR = 4ull, - /* - * RGM 5 = nibble error (data not byte multiple - 100M and 10M - * only) - */ - CVMX_PIP_ALIGN_ERR = 5ull, - /* - * RGM 6 = min frame error (pkt len < min frame len) (with FCS - * error) - */ - CVMX_PIP_UNDER_FCS_ERR = 6ull, - /* RGM 7 = FCS error */ - CVMX_PIP_GMX_FCS_ERR = 7ull, - /* RGM+SPI 8 = min frame error (pkt len < min frame len) */ - CVMX_PIP_UNDER_ERR = 8ull, - /* RGM 9 = Frame carrier extend error */ - CVMX_PIP_EXTEND_ERR = 9ull, - /* - * RGM 10 = length mismatch (len did not match len in L2 - * length/type) - */ - CVMX_PIP_LENGTH_ERR = 10ull, - /* RGM 11 = Frame error (some or all data bits marked err) */ - CVMX_PIP_DAT_ERR = 11ull, - /* SPI 11 = DIP4 error */ - CVMX_PIP_DIP_ERR = 11ull, - /* - * RGM 12 = packet was not large enough to pass the skipper - - * no inspection could occur. - */ - CVMX_PIP_SKIP_ERR = 12ull, - /* - * RGM 13 = studder error (data not repeated - 100M and 10M - * only) - */ - CVMX_PIP_NIBBLE_ERR = 13ull, - /* RGM+SPI 16 = FCS error */ - CVMX_PIP_PIP_FCS = 16L, - /* - * RGM+SPI+PCI 17 = packet was not large enough to pass the - * skipper - no inspection could occur. - */ - CVMX_PIP_PIP_SKIP_ERR = 17L, - /* - * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to - * cover L2 hdr). - */ - CVMX_PIP_PIP_L2_MAL_HDR = 18L - /* - * NOTES: xx = late collision (data received before collision) - * late collisions cannot be detected by the receiver - * they would appear as JAM bits which would appear as - * bad FCS or carrier extend error which is - * CVMX_PIP_EXTEND_ERR - */ -} cvmx_pip_rcv_err_t; - -/** - * This defines the err_code field errors in the work Q entry - */ -typedef union { - cvmx_pip_l4_err_t l4_err; - cvmx_pip_ip_exc_t ip_exc; - cvmx_pip_rcv_err_t rcv_err; -} cvmx_pip_err_t; - -/** - * Status statistics for a port - */ -typedef struct { - /* Inbound octets marked to be dropped by the IPD */ - uint32_t dropped_octets; - /* Inbound packets marked to be dropped by the IPD */ - uint32_t dropped_packets; - /* RAW PCI Packets received by PIP per port */ - uint32_t pci_raw_packets; - /* Number of octets processed by PIP */ - uint32_t octets; - /* Number of packets processed by PIP */ - uint32_t packets; - /* - * Number of indentified L2 multicast packets. Does not - * include broadcast packets. Only includes packets whose - * parse mode is SKIP_TO_L2 - */ - uint32_t multicast_packets; - /* - * Number of indentified L2 broadcast packets. Does not - * include multicast packets. Only includes packets whose - * parse mode is SKIP_TO_L2 - */ - uint32_t broadcast_packets; - /* Number of 64B packets */ - uint32_t len_64_packets; - /* Number of 65-127B packets */ - uint32_t len_65_127_packets; - /* Number of 128-255B packets */ - uint32_t len_128_255_packets; - /* Number of 256-511B packets */ - uint32_t len_256_511_packets; - /* Number of 512-1023B packets */ - uint32_t len_512_1023_packets; - /* Number of 1024-1518B packets */ - uint32_t len_1024_1518_packets; - /* Number of 1519-max packets */ - uint32_t len_1519_max_packets; - /* Number of packets with FCS or Align opcode errors */ - uint32_t fcs_align_err_packets; - /* Number of packets with length < min */ - uint32_t runt_packets; - /* Number of packets with length < min and FCS error */ - uint32_t runt_crc_packets; - /* Number of packets with length > max */ - uint32_t oversize_packets; - /* Number of packets with length > max and FCS error */ - uint32_t oversize_crc_packets; - /* Number of packets without GMX/SPX/PCI errors received by PIP */ - uint32_t inb_packets; - /* - * Total number of octets from all packets received by PIP, - * including CRC - */ - uint64_t inb_octets; - /* Number of packets with GMX/SPX/PCI errors received by PIP */ - uint16_t inb_errors; -} cvmx_pip_port_status_t; - -/** - * Definition of the PIP custom header that can be prepended - * to a packet by external hardware. - */ -typedef union { - uint64_t u64; - struct { - /* - * Documented as R - Set if the Packet is RAWFULL. If - * set, this header must be the full 8 bytes. - */ - uint64_t rawfull:1; - /* Must be zero */ - uint64_t reserved0:5; - /* PIP parse mode for this packet */ - uint64_t parse_mode:2; - /* Must be zero */ - uint64_t reserved1:1; - /* - * Skip amount, including this header, to the - * beginning of the packet - */ - uint64_t skip_len:7; - /* Must be zero */ - uint64_t reserved2:6; - /* POW input queue for this packet */ - uint64_t qos:3; - /* POW input group for this packet */ - uint64_t grp:4; - /* - * Flag to store this packet in the work queue entry, - * if possible - */ - uint64_t rs:1; - /* POW input tag type */ - uint64_t tag_type:2; - /* POW input tag */ - uint64_t tag:32; - } s; -} cvmx_pip_pkt_inst_hdr_t; - -/* CSR typedefs have been moved to cvmx-csr-*.h */ - -/** - * Configure an ethernet input port - * - * @port_num: Port number to configure - * @port_cfg: Port hardware configuration - * @port_tag_cfg: - * Port POW tagging configuration - */ -static inline void cvmx_pip_config_port(uint64_t port_num, - union cvmx_pip_prt_cfgx port_cfg, - union cvmx_pip_prt_tagx port_tag_cfg) -{ - cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64); - cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64); -} -#if 0 -/** - * @deprecated This function is a thin wrapper around the Pass1 version - * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for - * setting the group that is incompatible with this function, - * the preferred upgrade path is to use the CSR directly. - * - * Configure the global QoS packet watchers. Each watcher is - * capable of matching a field in a packet to determine the - * QoS queue for scheduling. - * - * @watcher: Watcher number to configure (0 - 3). - * @match_type: Watcher match type - * @match_value: - * Value the watcher will match against - * @qos: QoS queue for packets matching this watcher - */ -static inline void cvmx_pip_config_watcher(uint64_t watcher, - cvmx_pip_qos_watch_types match_type, - uint64_t match_value, uint64_t qos) -{ - cvmx_pip_port_watcher_cfg_t watcher_config; - - watcher_config.u64 = 0; - watcher_config.s.match_type = match_type; - watcher_config.s.match_value = match_value; - watcher_config.s.qos = qos; - - cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64); -} -#endif -/** - * Configure the VLAN priority to QoS queue mapping. - * - * @vlan_priority: - * VLAN priority (0-7) - * @qos: QoS queue for packets matching this watcher - */ -static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, - uint64_t qos) -{ - union cvmx_pip_qos_vlanx pip_qos_vlanx; - pip_qos_vlanx.u64 = 0; - pip_qos_vlanx.s.qos = qos; - cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64); -} - -/** - * Configure the Diffserv to QoS queue mapping. - * - * @diffserv: Diffserv field value (0-63) - * @qos: QoS queue for packets matching this watcher - */ -static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos) -{ - union cvmx_pip_qos_diffx pip_qos_diffx; - pip_qos_diffx.u64 = 0; - pip_qos_diffx.s.qos = qos; - cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64); -} - -/** - * Get the status counters for a port. - * - * @port_num: Port number to get statistics for. - * @clear: Set to 1 to clear the counters after they are read - * @status: Where to put the results. - */ -static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, - cvmx_pip_port_status_t *status) -{ - union cvmx_pip_stat_ctl pip_stat_ctl; - union cvmx_pip_stat0_prtx stat0; - union cvmx_pip_stat1_prtx stat1; - union cvmx_pip_stat2_prtx stat2; - union cvmx_pip_stat3_prtx stat3; - union cvmx_pip_stat4_prtx stat4; - union cvmx_pip_stat5_prtx stat5; - union cvmx_pip_stat6_prtx stat6; - union cvmx_pip_stat7_prtx stat7; - union cvmx_pip_stat8_prtx stat8; - union cvmx_pip_stat9_prtx stat9; - union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx; - union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx; - union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx; - - pip_stat_ctl.u64 = 0; - pip_stat_ctl.s.rdclr = clear; - cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64); - - stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num)); - stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num)); - stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num)); - stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num)); - stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num)); - stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num)); - stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num)); - stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num)); - stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num)); - stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num)); - pip_stat_inb_pktsx.u64 = - cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num)); - pip_stat_inb_octsx.u64 = - cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num)); - pip_stat_inb_errsx.u64 = - cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num)); - - status->dropped_octets = stat0.s.drp_octs; - status->dropped_packets = stat0.s.drp_pkts; - status->octets = stat1.s.octs; - status->pci_raw_packets = stat2.s.raw; - status->packets = stat2.s.pkts; - status->multicast_packets = stat3.s.mcst; - status->broadcast_packets = stat3.s.bcst; - status->len_64_packets = stat4.s.h64; - status->len_65_127_packets = stat4.s.h65to127; - status->len_128_255_packets = stat5.s.h128to255; - status->len_256_511_packets = stat5.s.h256to511; - status->len_512_1023_packets = stat6.s.h512to1023; - status->len_1024_1518_packets = stat6.s.h1024to1518; - status->len_1519_max_packets = stat7.s.h1519; - status->fcs_align_err_packets = stat7.s.fcs; - status->runt_packets = stat8.s.undersz; - status->runt_crc_packets = stat8.s.frag; - status->oversize_packets = stat9.s.oversz; - status->oversize_crc_packets = stat9.s.jabber; - status->inb_packets = pip_stat_inb_pktsx.s.pkts; - status->inb_octets = pip_stat_inb_octsx.s.octs; - status->inb_errors = pip_stat_inb_errsx.s.errs; - - if (cvmx_octeon_is_pass1()) { - /* - * Kludge to fix Octeon Pass 1 errata - Drop counts - * don't work. - */ - if (status->inb_packets > status->packets) - status->dropped_packets = - status->inb_packets - status->packets; - else - status->dropped_packets = 0; - if (status->inb_octets - status->inb_packets * 4 > - status->octets) - status->dropped_octets = - status->inb_octets - status->inb_packets * 4 - - status->octets; - else - status->dropped_octets = 0; - } -} - -/** - * Configure the hardware CRC engine - * - * @interface: Interface to configure (0 or 1) - * @invert_result: - * Invert the result of the CRC - * @reflect: Reflect - * @initialization_vector: - * CRC initialization vector - */ -static inline void cvmx_pip_config_crc(uint64_t interface, - uint64_t invert_result, uint64_t reflect, - uint32_t initialization_vector) -{ - if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) { - union cvmx_pip_crc_ctlx config; - union cvmx_pip_crc_ivx pip_crc_ivx; - - config.u64 = 0; - config.s.invres = invert_result; - config.s.reflect = reflect; - cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64); - - pip_crc_ivx.u64 = 0; - pip_crc_ivx.s.iv = initialization_vector; - cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64); - } -} - -/** - * Clear all bits in a tag mask. This should be called on - * startup before any calls to cvmx_pip_tag_mask_set. Each bit - * set in the final mask represent a byte used in the packet for - * tag generation. - * - * @mask_index: Which tag mask to clear (0..3) - */ -static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index) -{ - uint64_t index; - union cvmx_pip_tag_incx pip_tag_incx; - pip_tag_incx.u64 = 0; - pip_tag_incx.s.en = 0; - for (index = mask_index * 16; index < (mask_index + 1) * 16; index++) - cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); -} - -/** - * Sets a range of bits in the tag mask. The tag mask is used - * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero. - * There are four separate masks that can be configured. - * - * @mask_index: Which tag mask to modify (0..3) - * @offset: Offset into the bitmask to set bits at. Use the GCC macro - * offsetof() to determine the offsets into packet headers. - * For example, offsetof(ethhdr, protocol) returns the offset - * of the ethernet protocol field. The bitmask selects which - * bytes to include the the tag, with bit offset X selecting - * byte at offset X from the beginning of the packet data. - * @len: Number of bytes to include. Usually this is the sizeof() - * the field. - */ -static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, - uint64_t len) -{ - while (len--) { - union cvmx_pip_tag_incx pip_tag_incx; - uint64_t index = mask_index * 16 + offset / 8; - pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index)); - pip_tag_incx.s.en |= 0x80 >> (offset & 0x7); - cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64); - offset++; - } -} - -#endif /* __CVMX_PIP_H__ */ diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/drivers/staging/octeon/cvmx-pko-defs.h deleted file mode 100644 index 50e779cf1ad8..000000000000 --- a/drivers/staging/octeon/cvmx-pko-defs.h +++ /dev/null @@ -1,1133 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_PKO_DEFS_H__ -#define __CVMX_PKO_DEFS_H__ - -#define CVMX_PKO_MEM_COUNT0 \ - CVMX_ADD_IO_SEG(0x0001180050001080ull) -#define CVMX_PKO_MEM_COUNT1 \ - CVMX_ADD_IO_SEG(0x0001180050001088ull) -#define CVMX_PKO_MEM_DEBUG0 \ - CVMX_ADD_IO_SEG(0x0001180050001100ull) -#define CVMX_PKO_MEM_DEBUG1 \ - CVMX_ADD_IO_SEG(0x0001180050001108ull) -#define CVMX_PKO_MEM_DEBUG10 \ - CVMX_ADD_IO_SEG(0x0001180050001150ull) -#define CVMX_PKO_MEM_DEBUG11 \ - CVMX_ADD_IO_SEG(0x0001180050001158ull) -#define CVMX_PKO_MEM_DEBUG12 \ - CVMX_ADD_IO_SEG(0x0001180050001160ull) -#define CVMX_PKO_MEM_DEBUG13 \ - CVMX_ADD_IO_SEG(0x0001180050001168ull) -#define CVMX_PKO_MEM_DEBUG14 \ - CVMX_ADD_IO_SEG(0x0001180050001170ull) -#define CVMX_PKO_MEM_DEBUG2 \ - CVMX_ADD_IO_SEG(0x0001180050001110ull) -#define CVMX_PKO_MEM_DEBUG3 \ - CVMX_ADD_IO_SEG(0x0001180050001118ull) -#define CVMX_PKO_MEM_DEBUG4 \ - CVMX_ADD_IO_SEG(0x0001180050001120ull) -#define CVMX_PKO_MEM_DEBUG5 \ - CVMX_ADD_IO_SEG(0x0001180050001128ull) -#define CVMX_PKO_MEM_DEBUG6 \ - CVMX_ADD_IO_SEG(0x0001180050001130ull) -#define CVMX_PKO_MEM_DEBUG7 \ - CVMX_ADD_IO_SEG(0x0001180050001138ull) -#define CVMX_PKO_MEM_DEBUG8 \ - CVMX_ADD_IO_SEG(0x0001180050001140ull) -#define CVMX_PKO_MEM_DEBUG9 \ - CVMX_ADD_IO_SEG(0x0001180050001148ull) -#define CVMX_PKO_MEM_PORT_PTRS \ - CVMX_ADD_IO_SEG(0x0001180050001010ull) -#define CVMX_PKO_MEM_PORT_QOS \ - CVMX_ADD_IO_SEG(0x0001180050001018ull) -#define CVMX_PKO_MEM_PORT_RATE0 \ - CVMX_ADD_IO_SEG(0x0001180050001020ull) -#define CVMX_PKO_MEM_PORT_RATE1 \ - CVMX_ADD_IO_SEG(0x0001180050001028ull) -#define CVMX_PKO_MEM_QUEUE_PTRS \ - CVMX_ADD_IO_SEG(0x0001180050001000ull) -#define CVMX_PKO_MEM_QUEUE_QOS \ - CVMX_ADD_IO_SEG(0x0001180050001008ull) -#define CVMX_PKO_REG_BIST_RESULT \ - CVMX_ADD_IO_SEG(0x0001180050000080ull) -#define CVMX_PKO_REG_CMD_BUF \ - CVMX_ADD_IO_SEG(0x0001180050000010ull) -#define CVMX_PKO_REG_CRC_CTLX(offset) \ - CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8)) -#define CVMX_PKO_REG_CRC_ENABLE \ - CVMX_ADD_IO_SEG(0x0001180050000020ull) -#define CVMX_PKO_REG_CRC_IVX(offset) \ - CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8)) -#define CVMX_PKO_REG_DEBUG0 \ - CVMX_ADD_IO_SEG(0x0001180050000098ull) -#define CVMX_PKO_REG_DEBUG1 \ - CVMX_ADD_IO_SEG(0x00011800500000A0ull) -#define CVMX_PKO_REG_DEBUG2 \ - CVMX_ADD_IO_SEG(0x00011800500000A8ull) -#define CVMX_PKO_REG_DEBUG3 \ - CVMX_ADD_IO_SEG(0x00011800500000B0ull) -#define CVMX_PKO_REG_ENGINE_INFLIGHT \ - CVMX_ADD_IO_SEG(0x0001180050000050ull) -#define CVMX_PKO_REG_ENGINE_THRESH \ - CVMX_ADD_IO_SEG(0x0001180050000058ull) -#define CVMX_PKO_REG_ERROR \ - CVMX_ADD_IO_SEG(0x0001180050000088ull) -#define CVMX_PKO_REG_FLAGS \ - CVMX_ADD_IO_SEG(0x0001180050000000ull) -#define CVMX_PKO_REG_GMX_PORT_MODE \ - CVMX_ADD_IO_SEG(0x0001180050000018ull) -#define CVMX_PKO_REG_INT_MASK \ - CVMX_ADD_IO_SEG(0x0001180050000090ull) -#define CVMX_PKO_REG_QUEUE_MODE \ - CVMX_ADD_IO_SEG(0x0001180050000048ull) -#define CVMX_PKO_REG_QUEUE_PTRS1 \ - CVMX_ADD_IO_SEG(0x0001180050000100ull) -#define CVMX_PKO_REG_READ_IDX \ - CVMX_ADD_IO_SEG(0x0001180050000008ull) - -union cvmx_pko_mem_count0 { - uint64_t u64; - struct cvmx_pko_mem_count0_s { - uint64_t reserved_32_63:32; - uint64_t count:32; - } s; - struct cvmx_pko_mem_count0_s cn30xx; - struct cvmx_pko_mem_count0_s cn31xx; - struct cvmx_pko_mem_count0_s cn38xx; - struct cvmx_pko_mem_count0_s cn38xxp2; - struct cvmx_pko_mem_count0_s cn50xx; - struct cvmx_pko_mem_count0_s cn52xx; - struct cvmx_pko_mem_count0_s cn52xxp1; - struct cvmx_pko_mem_count0_s cn56xx; - struct cvmx_pko_mem_count0_s cn56xxp1; - struct cvmx_pko_mem_count0_s cn58xx; - struct cvmx_pko_mem_count0_s cn58xxp1; -}; - -union cvmx_pko_mem_count1 { - uint64_t u64; - struct cvmx_pko_mem_count1_s { - uint64_t reserved_48_63:16; - uint64_t count:48; - } s; - struct cvmx_pko_mem_count1_s cn30xx; - struct cvmx_pko_mem_count1_s cn31xx; - struct cvmx_pko_mem_count1_s cn38xx; - struct cvmx_pko_mem_count1_s cn38xxp2; - struct cvmx_pko_mem_count1_s cn50xx; - struct cvmx_pko_mem_count1_s cn52xx; - struct cvmx_pko_mem_count1_s cn52xxp1; - struct cvmx_pko_mem_count1_s cn56xx; - struct cvmx_pko_mem_count1_s cn56xxp1; - struct cvmx_pko_mem_count1_s cn58xx; - struct cvmx_pko_mem_count1_s cn58xxp1; -}; - -union cvmx_pko_mem_debug0 { - uint64_t u64; - struct cvmx_pko_mem_debug0_s { - uint64_t fau:28; - uint64_t cmd:14; - uint64_t segs:6; - uint64_t size:16; - } s; - struct cvmx_pko_mem_debug0_s cn30xx; - struct cvmx_pko_mem_debug0_s cn31xx; - struct cvmx_pko_mem_debug0_s cn38xx; - struct cvmx_pko_mem_debug0_s cn38xxp2; - struct cvmx_pko_mem_debug0_s cn50xx; - struct cvmx_pko_mem_debug0_s cn52xx; - struct cvmx_pko_mem_debug0_s cn52xxp1; - struct cvmx_pko_mem_debug0_s cn56xx; - struct cvmx_pko_mem_debug0_s cn56xxp1; - struct cvmx_pko_mem_debug0_s cn58xx; - struct cvmx_pko_mem_debug0_s cn58xxp1; -}; - -union cvmx_pko_mem_debug1 { - uint64_t u64; - struct cvmx_pko_mem_debug1_s { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t size:16; - uint64_t ptr:40; - } s; - struct cvmx_pko_mem_debug1_s cn30xx; - struct cvmx_pko_mem_debug1_s cn31xx; - struct cvmx_pko_mem_debug1_s cn38xx; - struct cvmx_pko_mem_debug1_s cn38xxp2; - struct cvmx_pko_mem_debug1_s cn50xx; - struct cvmx_pko_mem_debug1_s cn52xx; - struct cvmx_pko_mem_debug1_s cn52xxp1; - struct cvmx_pko_mem_debug1_s cn56xx; - struct cvmx_pko_mem_debug1_s cn56xxp1; - struct cvmx_pko_mem_debug1_s cn58xx; - struct cvmx_pko_mem_debug1_s cn58xxp1; -}; - -union cvmx_pko_mem_debug10 { - uint64_t u64; - struct cvmx_pko_mem_debug10_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_pko_mem_debug10_cn30xx { - uint64_t fau:28; - uint64_t cmd:14; - uint64_t segs:6; - uint64_t size:16; - } cn30xx; - struct cvmx_pko_mem_debug10_cn30xx cn31xx; - struct cvmx_pko_mem_debug10_cn30xx cn38xx; - struct cvmx_pko_mem_debug10_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug10_cn50xx { - uint64_t reserved_49_63:15; - uint64_t ptrs1:17; - uint64_t reserved_17_31:15; - uint64_t ptrs2:17; - } cn50xx; - struct cvmx_pko_mem_debug10_cn50xx cn52xx; - struct cvmx_pko_mem_debug10_cn50xx cn52xxp1; - struct cvmx_pko_mem_debug10_cn50xx cn56xx; - struct cvmx_pko_mem_debug10_cn50xx cn56xxp1; - struct cvmx_pko_mem_debug10_cn50xx cn58xx; - struct cvmx_pko_mem_debug10_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug11 { - uint64_t u64; - struct cvmx_pko_mem_debug11_s { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t size:16; - uint64_t reserved_0_39:40; - } s; - struct cvmx_pko_mem_debug11_cn30xx { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t size:16; - uint64_t ptr:40; - } cn30xx; - struct cvmx_pko_mem_debug11_cn30xx cn31xx; - struct cvmx_pko_mem_debug11_cn30xx cn38xx; - struct cvmx_pko_mem_debug11_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug11_cn50xx { - uint64_t reserved_23_63:41; - uint64_t maj:1; - uint64_t uid:3; - uint64_t sop:1; - uint64_t len:1; - uint64_t chk:1; - uint64_t cnt:13; - uint64_t mod:3; - } cn50xx; - struct cvmx_pko_mem_debug11_cn50xx cn52xx; - struct cvmx_pko_mem_debug11_cn50xx cn52xxp1; - struct cvmx_pko_mem_debug11_cn50xx cn56xx; - struct cvmx_pko_mem_debug11_cn50xx cn56xxp1; - struct cvmx_pko_mem_debug11_cn50xx cn58xx; - struct cvmx_pko_mem_debug11_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug12 { - uint64_t u64; - struct cvmx_pko_mem_debug12_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_pko_mem_debug12_cn30xx { - uint64_t data:64; - } cn30xx; - struct cvmx_pko_mem_debug12_cn30xx cn31xx; - struct cvmx_pko_mem_debug12_cn30xx cn38xx; - struct cvmx_pko_mem_debug12_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug12_cn50xx { - uint64_t fau:28; - uint64_t cmd:14; - uint64_t segs:6; - uint64_t size:16; - } cn50xx; - struct cvmx_pko_mem_debug12_cn50xx cn52xx; - struct cvmx_pko_mem_debug12_cn50xx cn52xxp1; - struct cvmx_pko_mem_debug12_cn50xx cn56xx; - struct cvmx_pko_mem_debug12_cn50xx cn56xxp1; - struct cvmx_pko_mem_debug12_cn50xx cn58xx; - struct cvmx_pko_mem_debug12_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug13 { - uint64_t u64; - struct cvmx_pko_mem_debug13_s { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t reserved_0_55:56; - } s; - struct cvmx_pko_mem_debug13_cn30xx { - uint64_t reserved_51_63:13; - uint64_t widx:17; - uint64_t ridx2:17; - uint64_t widx2:17; - } cn30xx; - struct cvmx_pko_mem_debug13_cn30xx cn31xx; - struct cvmx_pko_mem_debug13_cn30xx cn38xx; - struct cvmx_pko_mem_debug13_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug13_cn50xx { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t size:16; - uint64_t ptr:40; - } cn50xx; - struct cvmx_pko_mem_debug13_cn50xx cn52xx; - struct cvmx_pko_mem_debug13_cn50xx cn52xxp1; - struct cvmx_pko_mem_debug13_cn50xx cn56xx; - struct cvmx_pko_mem_debug13_cn50xx cn56xxp1; - struct cvmx_pko_mem_debug13_cn50xx cn58xx; - struct cvmx_pko_mem_debug13_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug14 { - uint64_t u64; - struct cvmx_pko_mem_debug14_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_pko_mem_debug14_cn30xx { - uint64_t reserved_17_63:47; - uint64_t ridx:17; - } cn30xx; - struct cvmx_pko_mem_debug14_cn30xx cn31xx; - struct cvmx_pko_mem_debug14_cn30xx cn38xx; - struct cvmx_pko_mem_debug14_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug14_cn52xx { - uint64_t data:64; - } cn52xx; - struct cvmx_pko_mem_debug14_cn52xx cn52xxp1; - struct cvmx_pko_mem_debug14_cn52xx cn56xx; - struct cvmx_pko_mem_debug14_cn52xx cn56xxp1; -}; - -union cvmx_pko_mem_debug2 { - uint64_t u64; - struct cvmx_pko_mem_debug2_s { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t size:16; - uint64_t ptr:40; - } s; - struct cvmx_pko_mem_debug2_s cn30xx; - struct cvmx_pko_mem_debug2_s cn31xx; - struct cvmx_pko_mem_debug2_s cn38xx; - struct cvmx_pko_mem_debug2_s cn38xxp2; - struct cvmx_pko_mem_debug2_s cn50xx; - struct cvmx_pko_mem_debug2_s cn52xx; - struct cvmx_pko_mem_debug2_s cn52xxp1; - struct cvmx_pko_mem_debug2_s cn56xx; - struct cvmx_pko_mem_debug2_s cn56xxp1; - struct cvmx_pko_mem_debug2_s cn58xx; - struct cvmx_pko_mem_debug2_s cn58xxp1; -}; - -union cvmx_pko_mem_debug3 { - uint64_t u64; - struct cvmx_pko_mem_debug3_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_pko_mem_debug3_cn30xx { - uint64_t i:1; - uint64_t back:4; - uint64_t pool:3; - uint64_t size:16; - uint64_t ptr:40; - } cn30xx; - struct cvmx_pko_mem_debug3_cn30xx cn31xx; - struct cvmx_pko_mem_debug3_cn30xx cn38xx; - struct cvmx_pko_mem_debug3_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug3_cn50xx { - uint64_t data:64; - } cn50xx; - struct cvmx_pko_mem_debug3_cn50xx cn52xx; - struct cvmx_pko_mem_debug3_cn50xx cn52xxp1; - struct cvmx_pko_mem_debug3_cn50xx cn56xx; - struct cvmx_pko_mem_debug3_cn50xx cn56xxp1; - struct cvmx_pko_mem_debug3_cn50xx cn58xx; - struct cvmx_pko_mem_debug3_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug4 { - uint64_t u64; - struct cvmx_pko_mem_debug4_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_pko_mem_debug4_cn30xx { - uint64_t data:64; - } cn30xx; - struct cvmx_pko_mem_debug4_cn30xx cn31xx; - struct cvmx_pko_mem_debug4_cn30xx cn38xx; - struct cvmx_pko_mem_debug4_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug4_cn50xx { - uint64_t cmnd_segs:3; - uint64_t cmnd_siz:16; - uint64_t cmnd_off:6; - uint64_t uid:3; - uint64_t dread_sop:1; - uint64_t init_dwrite:1; - uint64_t chk_once:1; - uint64_t chk_mode:1; - uint64_t active:1; - uint64_t static_p:1; - uint64_t qos:3; - uint64_t qcb_ridx:5; - uint64_t qid_off_max:4; - uint64_t qid_off:4; - uint64_t qid_base:8; - uint64_t wait:1; - uint64_t minor:2; - uint64_t major:3; - } cn50xx; - struct cvmx_pko_mem_debug4_cn52xx { - uint64_t curr_siz:8; - uint64_t curr_off:16; - uint64_t cmnd_segs:6; - uint64_t cmnd_siz:16; - uint64_t cmnd_off:6; - uint64_t uid:2; - uint64_t dread_sop:1; - uint64_t init_dwrite:1; - uint64_t chk_once:1; - uint64_t chk_mode:1; - uint64_t wait:1; - uint64_t minor:2; - uint64_t major:3; - } cn52xx; - struct cvmx_pko_mem_debug4_cn52xx cn52xxp1; - struct cvmx_pko_mem_debug4_cn52xx cn56xx; - struct cvmx_pko_mem_debug4_cn52xx cn56xxp1; - struct cvmx_pko_mem_debug4_cn50xx cn58xx; - struct cvmx_pko_mem_debug4_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug5 { - uint64_t u64; - struct cvmx_pko_mem_debug5_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_pko_mem_debug5_cn30xx { - uint64_t dwri_mod:1; - uint64_t dwri_sop:1; - uint64_t dwri_len:1; - uint64_t dwri_cnt:13; - uint64_t cmnd_siz:16; - uint64_t uid:1; - uint64_t xfer_wor:1; - uint64_t xfer_dwr:1; - uint64_t cbuf_fre:1; - uint64_t reserved_27_27:1; - uint64_t chk_mode:1; - uint64_t active:1; - uint64_t qos:3; - uint64_t qcb_ridx:5; - uint64_t qid_off:3; - uint64_t qid_base:7; - uint64_t wait:1; - uint64_t minor:2; - uint64_t major:4; - } cn30xx; - struct cvmx_pko_mem_debug5_cn30xx cn31xx; - struct cvmx_pko_mem_debug5_cn30xx cn38xx; - struct cvmx_pko_mem_debug5_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug5_cn50xx { - uint64_t curr_ptr:29; - uint64_t curr_siz:16; - uint64_t curr_off:16; - uint64_t cmnd_segs:3; - } cn50xx; - struct cvmx_pko_mem_debug5_cn52xx { - uint64_t reserved_54_63:10; - uint64_t nxt_inflt:6; - uint64_t curr_ptr:40; - uint64_t curr_siz:8; - } cn52xx; - struct cvmx_pko_mem_debug5_cn52xx cn52xxp1; - struct cvmx_pko_mem_debug5_cn52xx cn56xx; - struct cvmx_pko_mem_debug5_cn52xx cn56xxp1; - struct cvmx_pko_mem_debug5_cn50xx cn58xx; - struct cvmx_pko_mem_debug5_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug6 { - uint64_t u64; - struct cvmx_pko_mem_debug6_s { - uint64_t reserved_37_63:27; - uint64_t qid_offres:4; - uint64_t qid_offths:4; - uint64_t preempter:1; - uint64_t preemptee:1; - uint64_t preempted:1; - uint64_t active:1; - uint64_t statc:1; - uint64_t qos:3; - uint64_t qcb_ridx:5; - uint64_t qid_offmax:4; - uint64_t reserved_0_11:12; - } s; - struct cvmx_pko_mem_debug6_cn30xx { - uint64_t reserved_11_63:53; - uint64_t qid_offm:3; - uint64_t static_p:1; - uint64_t work_min:3; - uint64_t dwri_chk:1; - uint64_t dwri_uid:1; - uint64_t dwri_mod:2; - } cn30xx; - struct cvmx_pko_mem_debug6_cn30xx cn31xx; - struct cvmx_pko_mem_debug6_cn30xx cn38xx; - struct cvmx_pko_mem_debug6_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug6_cn50xx { - uint64_t reserved_11_63:53; - uint64_t curr_ptr:11; - } cn50xx; - struct cvmx_pko_mem_debug6_cn52xx { - uint64_t reserved_37_63:27; - uint64_t qid_offres:4; - uint64_t qid_offths:4; - uint64_t preempter:1; - uint64_t preemptee:1; - uint64_t preempted:1; - uint64_t active:1; - uint64_t statc:1; - uint64_t qos:3; - uint64_t qcb_ridx:5; - uint64_t qid_offmax:4; - uint64_t qid_off:4; - uint64_t qid_base:8; - } cn52xx; - struct cvmx_pko_mem_debug6_cn52xx cn52xxp1; - struct cvmx_pko_mem_debug6_cn52xx cn56xx; - struct cvmx_pko_mem_debug6_cn52xx cn56xxp1; - struct cvmx_pko_mem_debug6_cn50xx cn58xx; - struct cvmx_pko_mem_debug6_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug7 { - uint64_t u64; - struct cvmx_pko_mem_debug7_s { - uint64_t qos:5; - uint64_t tail:1; - uint64_t reserved_0_57:58; - } s; - struct cvmx_pko_mem_debug7_cn30xx { - uint64_t reserved_58_63:6; - uint64_t dwb:9; - uint64_t start:33; - uint64_t size:16; - } cn30xx; - struct cvmx_pko_mem_debug7_cn30xx cn31xx; - struct cvmx_pko_mem_debug7_cn30xx cn38xx; - struct cvmx_pko_mem_debug7_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug7_cn50xx { - uint64_t qos:5; - uint64_t tail:1; - uint64_t buf_siz:13; - uint64_t buf_ptr:33; - uint64_t qcb_widx:6; - uint64_t qcb_ridx:6; - } cn50xx; - struct cvmx_pko_mem_debug7_cn50xx cn52xx; - struct cvmx_pko_mem_debug7_cn50xx cn52xxp1; - struct cvmx_pko_mem_debug7_cn50xx cn56xx; - struct cvmx_pko_mem_debug7_cn50xx cn56xxp1; - struct cvmx_pko_mem_debug7_cn50xx cn58xx; - struct cvmx_pko_mem_debug7_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug8 { - uint64_t u64; - struct cvmx_pko_mem_debug8_s { - uint64_t reserved_59_63:5; - uint64_t tail:1; - uint64_t buf_siz:13; - uint64_t reserved_0_44:45; - } s; - struct cvmx_pko_mem_debug8_cn30xx { - uint64_t qos:5; - uint64_t tail:1; - uint64_t buf_siz:13; - uint64_t buf_ptr:33; - uint64_t qcb_widx:6; - uint64_t qcb_ridx:6; - } cn30xx; - struct cvmx_pko_mem_debug8_cn30xx cn31xx; - struct cvmx_pko_mem_debug8_cn30xx cn38xx; - struct cvmx_pko_mem_debug8_cn30xx cn38xxp2; - struct cvmx_pko_mem_debug8_cn50xx { - uint64_t reserved_28_63:36; - uint64_t doorbell:20; - uint64_t reserved_6_7:2; - uint64_t static_p:1; - uint64_t s_tail:1; - uint64_t static_q:1; - uint64_t qos:3; - } cn50xx; - struct cvmx_pko_mem_debug8_cn52xx { - uint64_t reserved_29_63:35; - uint64_t preempter:1; - uint64_t doorbell:20; - uint64_t reserved_7_7:1; - uint64_t preemptee:1; - uint64_t static_p:1; - uint64_t s_tail:1; - uint64_t static_q:1; - uint64_t qos:3; - } cn52xx; - struct cvmx_pko_mem_debug8_cn52xx cn52xxp1; - struct cvmx_pko_mem_debug8_cn52xx cn56xx; - struct cvmx_pko_mem_debug8_cn52xx cn56xxp1; - struct cvmx_pko_mem_debug8_cn50xx cn58xx; - struct cvmx_pko_mem_debug8_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_debug9 { - uint64_t u64; - struct cvmx_pko_mem_debug9_s { - uint64_t reserved_49_63:15; - uint64_t ptrs0:17; - uint64_t reserved_0_31:32; - } s; - struct cvmx_pko_mem_debug9_cn30xx { - uint64_t reserved_28_63:36; - uint64_t doorbell:20; - uint64_t reserved_5_7:3; - uint64_t s_tail:1; - uint64_t static_q:1; - uint64_t qos:3; - } cn30xx; - struct cvmx_pko_mem_debug9_cn30xx cn31xx; - struct cvmx_pko_mem_debug9_cn38xx { - uint64_t reserved_28_63:36; - uint64_t doorbell:20; - uint64_t reserved_6_7:2; - uint64_t static_p:1; - uint64_t s_tail:1; - uint64_t static_q:1; - uint64_t qos:3; - } cn38xx; - struct cvmx_pko_mem_debug9_cn38xx cn38xxp2; - struct cvmx_pko_mem_debug9_cn50xx { - uint64_t reserved_49_63:15; - uint64_t ptrs0:17; - uint64_t reserved_17_31:15; - uint64_t ptrs3:17; - } cn50xx; - struct cvmx_pko_mem_debug9_cn50xx cn52xx; - struct cvmx_pko_mem_debug9_cn50xx cn52xxp1; - struct cvmx_pko_mem_debug9_cn50xx cn56xx; - struct cvmx_pko_mem_debug9_cn50xx cn56xxp1; - struct cvmx_pko_mem_debug9_cn50xx cn58xx; - struct cvmx_pko_mem_debug9_cn50xx cn58xxp1; -}; - -union cvmx_pko_mem_port_ptrs { - uint64_t u64; - struct cvmx_pko_mem_port_ptrs_s { - uint64_t reserved_62_63:2; - uint64_t static_p:1; - uint64_t qos_mask:8; - uint64_t reserved_16_52:37; - uint64_t bp_port:6; - uint64_t eid:4; - uint64_t pid:6; - } s; - struct cvmx_pko_mem_port_ptrs_s cn52xx; - struct cvmx_pko_mem_port_ptrs_s cn52xxp1; - struct cvmx_pko_mem_port_ptrs_s cn56xx; - struct cvmx_pko_mem_port_ptrs_s cn56xxp1; -}; - -union cvmx_pko_mem_port_qos { - uint64_t u64; - struct cvmx_pko_mem_port_qos_s { - uint64_t reserved_61_63:3; - uint64_t qos_mask:8; - uint64_t reserved_10_52:43; - uint64_t eid:4; - uint64_t pid:6; - } s; - struct cvmx_pko_mem_port_qos_s cn52xx; - struct cvmx_pko_mem_port_qos_s cn52xxp1; - struct cvmx_pko_mem_port_qos_s cn56xx; - struct cvmx_pko_mem_port_qos_s cn56xxp1; -}; - -union cvmx_pko_mem_port_rate0 { - uint64_t u64; - struct cvmx_pko_mem_port_rate0_s { - uint64_t reserved_51_63:13; - uint64_t rate_word:19; - uint64_t rate_pkt:24; - uint64_t reserved_6_7:2; - uint64_t pid:6; - } s; - struct cvmx_pko_mem_port_rate0_s cn52xx; - struct cvmx_pko_mem_port_rate0_s cn52xxp1; - struct cvmx_pko_mem_port_rate0_s cn56xx; - struct cvmx_pko_mem_port_rate0_s cn56xxp1; -}; - -union cvmx_pko_mem_port_rate1 { - uint64_t u64; - struct cvmx_pko_mem_port_rate1_s { - uint64_t reserved_32_63:32; - uint64_t rate_lim:24; - uint64_t reserved_6_7:2; - uint64_t pid:6; - } s; - struct cvmx_pko_mem_port_rate1_s cn52xx; - struct cvmx_pko_mem_port_rate1_s cn52xxp1; - struct cvmx_pko_mem_port_rate1_s cn56xx; - struct cvmx_pko_mem_port_rate1_s cn56xxp1; -}; - -union cvmx_pko_mem_queue_ptrs { - uint64_t u64; - struct cvmx_pko_mem_queue_ptrs_s { - uint64_t s_tail:1; - uint64_t static_p:1; - uint64_t static_q:1; - uint64_t qos_mask:8; - uint64_t buf_ptr:36; - uint64_t tail:1; - uint64_t index:3; - uint64_t port:6; - uint64_t queue:7; - } s; - struct cvmx_pko_mem_queue_ptrs_s cn30xx; - struct cvmx_pko_mem_queue_ptrs_s cn31xx; - struct cvmx_pko_mem_queue_ptrs_s cn38xx; - struct cvmx_pko_mem_queue_ptrs_s cn38xxp2; - struct cvmx_pko_mem_queue_ptrs_s cn50xx; - struct cvmx_pko_mem_queue_ptrs_s cn52xx; - struct cvmx_pko_mem_queue_ptrs_s cn52xxp1; - struct cvmx_pko_mem_queue_ptrs_s cn56xx; - struct cvmx_pko_mem_queue_ptrs_s cn56xxp1; - struct cvmx_pko_mem_queue_ptrs_s cn58xx; - struct cvmx_pko_mem_queue_ptrs_s cn58xxp1; -}; - -union cvmx_pko_mem_queue_qos { - uint64_t u64; - struct cvmx_pko_mem_queue_qos_s { - uint64_t reserved_61_63:3; - uint64_t qos_mask:8; - uint64_t reserved_13_52:40; - uint64_t pid:6; - uint64_t qid:7; - } s; - struct cvmx_pko_mem_queue_qos_s cn30xx; - struct cvmx_pko_mem_queue_qos_s cn31xx; - struct cvmx_pko_mem_queue_qos_s cn38xx; - struct cvmx_pko_mem_queue_qos_s cn38xxp2; - struct cvmx_pko_mem_queue_qos_s cn50xx; - struct cvmx_pko_mem_queue_qos_s cn52xx; - struct cvmx_pko_mem_queue_qos_s cn52xxp1; - struct cvmx_pko_mem_queue_qos_s cn56xx; - struct cvmx_pko_mem_queue_qos_s cn56xxp1; - struct cvmx_pko_mem_queue_qos_s cn58xx; - struct cvmx_pko_mem_queue_qos_s cn58xxp1; -}; - -union cvmx_pko_reg_bist_result { - uint64_t u64; - struct cvmx_pko_reg_bist_result_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_pko_reg_bist_result_cn30xx { - uint64_t reserved_27_63:37; - uint64_t psb2:5; - uint64_t count:1; - uint64_t rif:1; - uint64_t wif:1; - uint64_t ncb:1; - uint64_t out:1; - uint64_t crc:1; - uint64_t chk:1; - uint64_t qsb:2; - uint64_t qcb:2; - uint64_t pdb:4; - uint64_t psb:7; - } cn30xx; - struct cvmx_pko_reg_bist_result_cn30xx cn31xx; - struct cvmx_pko_reg_bist_result_cn30xx cn38xx; - struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2; - struct cvmx_pko_reg_bist_result_cn50xx { - uint64_t reserved_33_63:31; - uint64_t csr:1; - uint64_t iob:1; - uint64_t out_crc:1; - uint64_t out_ctl:3; - uint64_t out_sta:1; - uint64_t out_wif:1; - uint64_t prt_chk:3; - uint64_t prt_nxt:1; - uint64_t prt_psb:6; - uint64_t ncb_inb:2; - uint64_t prt_qcb:2; - uint64_t prt_qsb:3; - uint64_t dat_dat:4; - uint64_t dat_ptr:4; - } cn50xx; - struct cvmx_pko_reg_bist_result_cn52xx { - uint64_t reserved_35_63:29; - uint64_t csr:1; - uint64_t iob:1; - uint64_t out_dat:1; - uint64_t out_ctl:3; - uint64_t out_sta:1; - uint64_t out_wif:1; - uint64_t prt_chk:3; - uint64_t prt_nxt:1; - uint64_t prt_psb:8; - uint64_t ncb_inb:2; - uint64_t prt_qcb:2; - uint64_t prt_qsb:3; - uint64_t prt_ctl:2; - uint64_t dat_dat:2; - uint64_t dat_ptr:4; - } cn52xx; - struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1; - struct cvmx_pko_reg_bist_result_cn52xx cn56xx; - struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1; - struct cvmx_pko_reg_bist_result_cn50xx cn58xx; - struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1; -}; - -union cvmx_pko_reg_cmd_buf { - uint64_t u64; - struct cvmx_pko_reg_cmd_buf_s { - uint64_t reserved_23_63:41; - uint64_t pool:3; - uint64_t reserved_13_19:7; - uint64_t size:13; - } s; - struct cvmx_pko_reg_cmd_buf_s cn30xx; - struct cvmx_pko_reg_cmd_buf_s cn31xx; - struct cvmx_pko_reg_cmd_buf_s cn38xx; - struct cvmx_pko_reg_cmd_buf_s cn38xxp2; - struct cvmx_pko_reg_cmd_buf_s cn50xx; - struct cvmx_pko_reg_cmd_buf_s cn52xx; - struct cvmx_pko_reg_cmd_buf_s cn52xxp1; - struct cvmx_pko_reg_cmd_buf_s cn56xx; - struct cvmx_pko_reg_cmd_buf_s cn56xxp1; - struct cvmx_pko_reg_cmd_buf_s cn58xx; - struct cvmx_pko_reg_cmd_buf_s cn58xxp1; -}; - -union cvmx_pko_reg_crc_ctlx { - uint64_t u64; - struct cvmx_pko_reg_crc_ctlx_s { - uint64_t reserved_2_63:62; - uint64_t invres:1; - uint64_t refin:1; - } s; - struct cvmx_pko_reg_crc_ctlx_s cn38xx; - struct cvmx_pko_reg_crc_ctlx_s cn38xxp2; - struct cvmx_pko_reg_crc_ctlx_s cn58xx; - struct cvmx_pko_reg_crc_ctlx_s cn58xxp1; -}; - -union cvmx_pko_reg_crc_enable { - uint64_t u64; - struct cvmx_pko_reg_crc_enable_s { - uint64_t reserved_32_63:32; - uint64_t enable:32; - } s; - struct cvmx_pko_reg_crc_enable_s cn38xx; - struct cvmx_pko_reg_crc_enable_s cn38xxp2; - struct cvmx_pko_reg_crc_enable_s cn58xx; - struct cvmx_pko_reg_crc_enable_s cn58xxp1; -}; - -union cvmx_pko_reg_crc_ivx { - uint64_t u64; - struct cvmx_pko_reg_crc_ivx_s { - uint64_t reserved_32_63:32; - uint64_t iv:32; - } s; - struct cvmx_pko_reg_crc_ivx_s cn38xx; - struct cvmx_pko_reg_crc_ivx_s cn38xxp2; - struct cvmx_pko_reg_crc_ivx_s cn58xx; - struct cvmx_pko_reg_crc_ivx_s cn58xxp1; -}; - -union cvmx_pko_reg_debug0 { - uint64_t u64; - struct cvmx_pko_reg_debug0_s { - uint64_t asserts:64; - } s; - struct cvmx_pko_reg_debug0_cn30xx { - uint64_t reserved_17_63:47; - uint64_t asserts:17; - } cn30xx; - struct cvmx_pko_reg_debug0_cn30xx cn31xx; - struct cvmx_pko_reg_debug0_cn30xx cn38xx; - struct cvmx_pko_reg_debug0_cn30xx cn38xxp2; - struct cvmx_pko_reg_debug0_s cn50xx; - struct cvmx_pko_reg_debug0_s cn52xx; - struct cvmx_pko_reg_debug0_s cn52xxp1; - struct cvmx_pko_reg_debug0_s cn56xx; - struct cvmx_pko_reg_debug0_s cn56xxp1; - struct cvmx_pko_reg_debug0_s cn58xx; - struct cvmx_pko_reg_debug0_s cn58xxp1; -}; - -union cvmx_pko_reg_debug1 { - uint64_t u64; - struct cvmx_pko_reg_debug1_s { - uint64_t asserts:64; - } s; - struct cvmx_pko_reg_debug1_s cn50xx; - struct cvmx_pko_reg_debug1_s cn52xx; - struct cvmx_pko_reg_debug1_s cn52xxp1; - struct cvmx_pko_reg_debug1_s cn56xx; - struct cvmx_pko_reg_debug1_s cn56xxp1; - struct cvmx_pko_reg_debug1_s cn58xx; - struct cvmx_pko_reg_debug1_s cn58xxp1; -}; - -union cvmx_pko_reg_debug2 { - uint64_t u64; - struct cvmx_pko_reg_debug2_s { - uint64_t asserts:64; - } s; - struct cvmx_pko_reg_debug2_s cn50xx; - struct cvmx_pko_reg_debug2_s cn52xx; - struct cvmx_pko_reg_debug2_s cn52xxp1; - struct cvmx_pko_reg_debug2_s cn56xx; - struct cvmx_pko_reg_debug2_s cn56xxp1; - struct cvmx_pko_reg_debug2_s cn58xx; - struct cvmx_pko_reg_debug2_s cn58xxp1; -}; - -union cvmx_pko_reg_debug3 { - uint64_t u64; - struct cvmx_pko_reg_debug3_s { - uint64_t asserts:64; - } s; - struct cvmx_pko_reg_debug3_s cn50xx; - struct cvmx_pko_reg_debug3_s cn52xx; - struct cvmx_pko_reg_debug3_s cn52xxp1; - struct cvmx_pko_reg_debug3_s cn56xx; - struct cvmx_pko_reg_debug3_s cn56xxp1; - struct cvmx_pko_reg_debug3_s cn58xx; - struct cvmx_pko_reg_debug3_s cn58xxp1; -}; - -union cvmx_pko_reg_engine_inflight { - uint64_t u64; - struct cvmx_pko_reg_engine_inflight_s { - uint64_t reserved_40_63:24; - uint64_t engine9:4; - uint64_t engine8:4; - uint64_t engine7:4; - uint64_t engine6:4; - uint64_t engine5:4; - uint64_t engine4:4; - uint64_t engine3:4; - uint64_t engine2:4; - uint64_t engine1:4; - uint64_t engine0:4; - } s; - struct cvmx_pko_reg_engine_inflight_s cn52xx; - struct cvmx_pko_reg_engine_inflight_s cn52xxp1; - struct cvmx_pko_reg_engine_inflight_s cn56xx; - struct cvmx_pko_reg_engine_inflight_s cn56xxp1; -}; - -union cvmx_pko_reg_engine_thresh { - uint64_t u64; - struct cvmx_pko_reg_engine_thresh_s { - uint64_t reserved_10_63:54; - uint64_t mask:10; - } s; - struct cvmx_pko_reg_engine_thresh_s cn52xx; - struct cvmx_pko_reg_engine_thresh_s cn52xxp1; - struct cvmx_pko_reg_engine_thresh_s cn56xx; - struct cvmx_pko_reg_engine_thresh_s cn56xxp1; -}; - -union cvmx_pko_reg_error { - uint64_t u64; - struct cvmx_pko_reg_error_s { - uint64_t reserved_3_63:61; - uint64_t currzero:1; - uint64_t doorbell:1; - uint64_t parity:1; - } s; - struct cvmx_pko_reg_error_cn30xx { - uint64_t reserved_2_63:62; - uint64_t doorbell:1; - uint64_t parity:1; - } cn30xx; - struct cvmx_pko_reg_error_cn30xx cn31xx; - struct cvmx_pko_reg_error_cn30xx cn38xx; - struct cvmx_pko_reg_error_cn30xx cn38xxp2; - struct cvmx_pko_reg_error_s cn50xx; - struct cvmx_pko_reg_error_s cn52xx; - struct cvmx_pko_reg_error_s cn52xxp1; - struct cvmx_pko_reg_error_s cn56xx; - struct cvmx_pko_reg_error_s cn56xxp1; - struct cvmx_pko_reg_error_s cn58xx; - struct cvmx_pko_reg_error_s cn58xxp1; -}; - -union cvmx_pko_reg_flags { - uint64_t u64; - struct cvmx_pko_reg_flags_s { - uint64_t reserved_4_63:60; - uint64_t reset:1; - uint64_t store_be:1; - uint64_t ena_dwb:1; - uint64_t ena_pko:1; - } s; - struct cvmx_pko_reg_flags_s cn30xx; - struct cvmx_pko_reg_flags_s cn31xx; - struct cvmx_pko_reg_flags_s cn38xx; - struct cvmx_pko_reg_flags_s cn38xxp2; - struct cvmx_pko_reg_flags_s cn50xx; - struct cvmx_pko_reg_flags_s cn52xx; - struct cvmx_pko_reg_flags_s cn52xxp1; - struct cvmx_pko_reg_flags_s cn56xx; - struct cvmx_pko_reg_flags_s cn56xxp1; - struct cvmx_pko_reg_flags_s cn58xx; - struct cvmx_pko_reg_flags_s cn58xxp1; -}; - -union cvmx_pko_reg_gmx_port_mode { - uint64_t u64; - struct cvmx_pko_reg_gmx_port_mode_s { - uint64_t reserved_6_63:58; - uint64_t mode1:3; - uint64_t mode0:3; - } s; - struct cvmx_pko_reg_gmx_port_mode_s cn30xx; - struct cvmx_pko_reg_gmx_port_mode_s cn31xx; - struct cvmx_pko_reg_gmx_port_mode_s cn38xx; - struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2; - struct cvmx_pko_reg_gmx_port_mode_s cn50xx; - struct cvmx_pko_reg_gmx_port_mode_s cn52xx; - struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1; - struct cvmx_pko_reg_gmx_port_mode_s cn56xx; - struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1; - struct cvmx_pko_reg_gmx_port_mode_s cn58xx; - struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1; -}; - -union cvmx_pko_reg_int_mask { - uint64_t u64; - struct cvmx_pko_reg_int_mask_s { - uint64_t reserved_3_63:61; - uint64_t currzero:1; - uint64_t doorbell:1; - uint64_t parity:1; - } s; - struct cvmx_pko_reg_int_mask_cn30xx { - uint64_t reserved_2_63:62; - uint64_t doorbell:1; - uint64_t parity:1; - } cn30xx; - struct cvmx_pko_reg_int_mask_cn30xx cn31xx; - struct cvmx_pko_reg_int_mask_cn30xx cn38xx; - struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2; - struct cvmx_pko_reg_int_mask_s cn50xx; - struct cvmx_pko_reg_int_mask_s cn52xx; - struct cvmx_pko_reg_int_mask_s cn52xxp1; - struct cvmx_pko_reg_int_mask_s cn56xx; - struct cvmx_pko_reg_int_mask_s cn56xxp1; - struct cvmx_pko_reg_int_mask_s cn58xx; - struct cvmx_pko_reg_int_mask_s cn58xxp1; -}; - -union cvmx_pko_reg_queue_mode { - uint64_t u64; - struct cvmx_pko_reg_queue_mode_s { - uint64_t reserved_2_63:62; - uint64_t mode:2; - } s; - struct cvmx_pko_reg_queue_mode_s cn30xx; - struct cvmx_pko_reg_queue_mode_s cn31xx; - struct cvmx_pko_reg_queue_mode_s cn38xx; - struct cvmx_pko_reg_queue_mode_s cn38xxp2; - struct cvmx_pko_reg_queue_mode_s cn50xx; - struct cvmx_pko_reg_queue_mode_s cn52xx; - struct cvmx_pko_reg_queue_mode_s cn52xxp1; - struct cvmx_pko_reg_queue_mode_s cn56xx; - struct cvmx_pko_reg_queue_mode_s cn56xxp1; - struct cvmx_pko_reg_queue_mode_s cn58xx; - struct cvmx_pko_reg_queue_mode_s cn58xxp1; -}; - -union cvmx_pko_reg_queue_ptrs1 { - uint64_t u64; - struct cvmx_pko_reg_queue_ptrs1_s { - uint64_t reserved_2_63:62; - uint64_t idx3:1; - uint64_t qid7:1; - } s; - struct cvmx_pko_reg_queue_ptrs1_s cn50xx; - struct cvmx_pko_reg_queue_ptrs1_s cn52xx; - struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1; - struct cvmx_pko_reg_queue_ptrs1_s cn56xx; - struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1; - struct cvmx_pko_reg_queue_ptrs1_s cn58xx; - struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1; -}; - -union cvmx_pko_reg_read_idx { - uint64_t u64; - struct cvmx_pko_reg_read_idx_s { - uint64_t reserved_16_63:48; - uint64_t inc:8; - uint64_t index:8; - } s; - struct cvmx_pko_reg_read_idx_s cn30xx; - struct cvmx_pko_reg_read_idx_s cn31xx; - struct cvmx_pko_reg_read_idx_s cn38xx; - struct cvmx_pko_reg_read_idx_s cn38xxp2; - struct cvmx_pko_reg_read_idx_s cn50xx; - struct cvmx_pko_reg_read_idx_s cn52xx; - struct cvmx_pko_reg_read_idx_s cn52xxp1; - struct cvmx_pko_reg_read_idx_s cn56xx; - struct cvmx_pko_reg_read_idx_s cn56xxp1; - struct cvmx_pko_reg_read_idx_s cn58xx; - struct cvmx_pko_reg_read_idx_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-pko.c b/drivers/staging/octeon/cvmx-pko.c deleted file mode 100644 index 50a2c9bd5a55..000000000000 --- a/drivers/staging/octeon/cvmx-pko.c +++ /dev/null @@ -1,506 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * Support library for the hardware Packet Output unit. - */ - -#include - -#include "cvmx-config.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" - -/** - * Internal state of packet output - */ - -/** - * Call before any other calls to initialize the packet - * output system. This does chip global config, and should only be - * done by one core. - */ - -void cvmx_pko_initialize_global(void) -{ - int i; - uint64_t priority = 8; - union cvmx_pko_reg_cmd_buf config; - - /* - * Set the size of the PKO command buffers to an odd number of - * 64bit words. This allows the normal two word send to stay - * aligned and never span a command word buffer. - */ - config.u64 = 0; - config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL; - config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1; - - cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64); - - for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++) - cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, - &priority); - - /* - * If we aren't using all of the queues optimize PKO's - * internal memory. - */ - if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) - || OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) { - int num_interfaces = cvmx_helper_get_number_of_interfaces(); - int last_port = - cvmx_helper_get_last_ipd_port(num_interfaces - 1); - int max_queues = - cvmx_pko_get_base_queue(last_port) + - cvmx_pko_get_num_queues(last_port); - if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { - if (max_queues <= 32) - cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); - else if (max_queues <= 64) - cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); - } else { - if (max_queues <= 64) - cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2); - else if (max_queues <= 128) - cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1); - } - } -} - -/** - * This function does per-core initialization required by the PKO routines. - * This must be called on all cores that will do packet output, and must - * be called after the FPA has been initialized and filled with pages. - * - * Returns 0 on success - * !0 on failure - */ -int cvmx_pko_initialize_local(void) -{ - /* Nothing to do */ - return 0; -} - -/** - * Enables the packet output hardware. It must already be - * configured. - */ -void cvmx_pko_enable(void) -{ - union cvmx_pko_reg_flags flags; - - flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); - if (flags.s.ena_pko) - cvmx_dprintf - ("Warning: Enabling PKO when PKO already enabled.\n"); - - flags.s.ena_dwb = 1; - flags.s.ena_pko = 1; - /* - * always enable big endian for 3-word command. Does nothing - * for 2-word. - */ - flags.s.store_be = 1; - cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64); -} - -/** - * Disables the packet output. Does not affect any configuration. - */ -void cvmx_pko_disable(void) -{ - union cvmx_pko_reg_flags pko_reg_flags; - pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); - pko_reg_flags.s.ena_pko = 0; - cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); -} - - -/** - * Reset the packet output. - */ -static void __cvmx_pko_reset(void) -{ - union cvmx_pko_reg_flags pko_reg_flags; - pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS); - pko_reg_flags.s.reset = 1; - cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); -} - -/** - * Shutdown and free resources required by packet output. - */ -void cvmx_pko_shutdown(void) -{ - union cvmx_pko_mem_queue_ptrs config; - int queue; - - cvmx_pko_disable(); - - for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) { - config.u64 = 0; - config.s.tail = 1; - config.s.index = 0; - config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID; - config.s.queue = queue & 0x7f; - config.s.qos_mask = 0; - config.s.buf_ptr = 0; - if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { - union cvmx_pko_reg_queue_ptrs1 config1; - config1.u64 = 0; - config1.s.qid7 = queue >> 7; - cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); - } - cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); - cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue)); - } - __cvmx_pko_reset(); -} - -/** - * Configure a output port and the associated queues for use. - * - * @port: Port to configure. - * @base_queue: First queue number to associate with this port. - * @num_queues: Number of queues to associate with this port - * @priority: Array of priority levels for each queue. Values are - * allowed to be 0-8. A value of 8 get 8 times the traffic - * of a value of 1. A value of 0 indicates that no rounds - * will be participated in. These priorities can be changed - * on the fly while the pko is enabled. A priority of 9 - * indicates that static priority should be used. If static - * priority is used all queues with static priority must be - * contiguous starting at the base_queue, and lower numbered - * queues have higher priority than higher numbered queues. - * There must be num_queues elements in the array. - */ -cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, - uint64_t num_queues, - const uint64_t priority[]) -{ - cvmx_pko_status_t result_code; - uint64_t queue; - union cvmx_pko_mem_queue_ptrs config; - union cvmx_pko_reg_queue_ptrs1 config1; - int static_priority_base = -1; - int static_priority_end = -1; - - if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) - && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) { - cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", - (unsigned long long)port); - return CVMX_PKO_INVALID_PORT; - } - - if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES) { - cvmx_dprintf - ("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n", - (unsigned long long)(base_queue + num_queues)); - return CVMX_PKO_INVALID_QUEUE; - } - - if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) { - /* - * Validate the static queue priority setup and set - * static_priority_base and static_priority_end - * accordingly. - */ - for (queue = 0; queue < num_queues; queue++) { - /* Find first queue of static priority */ - if (static_priority_base == -1 - && priority[queue] == - CVMX_PKO_QUEUE_STATIC_PRIORITY) - static_priority_base = queue; - /* Find last queue of static priority */ - if (static_priority_base != -1 - && static_priority_end == -1 - && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY - && queue) - static_priority_end = queue - 1; - else if (static_priority_base != -1 - && static_priority_end == -1 - && queue == num_queues - 1) - /* all queues are static priority */ - static_priority_end = queue; - /* - * Check to make sure all static priority - * queues are contiguous. Also catches some - * cases of static priorites not starting at - * queue 0. - */ - if (static_priority_end != -1 - && (int)queue > static_priority_end - && priority[queue] == - CVMX_PKO_QUEUE_STATIC_PRIORITY) { - cvmx_dprintf("ERROR: cvmx_pko_config_port: " - "Static priority queues aren't " - "contiguous or don't start at " - "base queue. q: %d, eq: %d\n", - (int)queue, static_priority_end); - return CVMX_PKO_INVALID_PRIORITY; - } - } - if (static_priority_base > 0) { - cvmx_dprintf("ERROR: cvmx_pko_config_port: Static " - "priority queues don't start at base " - "queue. sq: %d\n", - static_priority_base); - return CVMX_PKO_INVALID_PRIORITY; - } -#if 0 - cvmx_dprintf("Port %d: Static priority queue base: %d, " - "end: %d\n", port, - static_priority_base, static_priority_end); -#endif - } - /* - * At this point, static_priority_base and static_priority_end - * are either both -1, or are valid start/end queue - * numbers. - */ - - result_code = CVMX_PKO_SUCCESS; - -#ifdef PKO_DEBUG - cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues, - CVMX_PKO_QUEUES_PER_PORT_INTERFACE0, - CVMX_PKO_QUEUES_PER_PORT_INTERFACE1); -#endif - - for (queue = 0; queue < num_queues; queue++) { - uint64_t *buf_ptr = NULL; - - config1.u64 = 0; - config1.s.idx3 = queue >> 3; - config1.s.qid7 = (base_queue + queue) >> 7; - - config.u64 = 0; - config.s.tail = queue == (num_queues - 1); - config.s.index = queue; - config.s.port = port; - config.s.queue = base_queue + queue; - - if (!cvmx_octeon_is_pass1()) { - config.s.static_p = static_priority_base >= 0; - config.s.static_q = (int)queue <= static_priority_end; - config.s.s_tail = (int)queue == static_priority_end; - } - /* - * Convert the priority into an enable bit field. Try - * to space the bits out evenly so the packet don't - * get grouped up - */ - switch ((int)priority[queue]) { - case 0: - config.s.qos_mask = 0x00; - break; - case 1: - config.s.qos_mask = 0x01; - break; - case 2: - config.s.qos_mask = 0x11; - break; - case 3: - config.s.qos_mask = 0x49; - break; - case 4: - config.s.qos_mask = 0x55; - break; - case 5: - config.s.qos_mask = 0x57; - break; - case 6: - config.s.qos_mask = 0x77; - break; - case 7: - config.s.qos_mask = 0x7f; - break; - case 8: - config.s.qos_mask = 0xff; - break; - case CVMX_PKO_QUEUE_STATIC_PRIORITY: - /* Pass 1 will fall through to the error case */ - if (!cvmx_octeon_is_pass1()) { - config.s.qos_mask = 0xff; - break; - } - default: - cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid " - "priority %llu\n", - (unsigned long long)priority[queue]); - config.s.qos_mask = 0xff; - result_code = CVMX_PKO_INVALID_PRIORITY; - break; - } - - if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) { - cvmx_cmd_queue_result_t cmd_res = - cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO - (base_queue + queue), - CVMX_PKO_MAX_QUEUE_DEPTH, - CVMX_FPA_OUTPUT_BUFFER_POOL, - CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - - - CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST - * 8); - if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) { - switch (cmd_res) { - case CVMX_CMD_QUEUE_NO_MEMORY: - cvmx_dprintf("ERROR: " - "cvmx_pko_config_port: " - "Unable to allocate " - "output buffer.\n"); - return CVMX_PKO_NO_MEMORY; - case CVMX_CMD_QUEUE_ALREADY_SETUP: - cvmx_dprintf - ("ERROR: cvmx_pko_config_port: Port already setup.\n"); - return CVMX_PKO_PORT_ALREADY_SETUP; - case CVMX_CMD_QUEUE_INVALID_PARAM: - default: - cvmx_dprintf - ("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n"); - return CVMX_PKO_CMD_QUEUE_INIT_ERROR; - } - } - - buf_ptr = - (uint64_t *) - cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO - (base_queue + queue)); - config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr); - } else - config.s.buf_ptr = 0; - - CVMX_SYNCWS; - - if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) - cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); - cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); - } - - return result_code; -} - -#ifdef PKO_DEBUG -/** - * Show map of ports -> queues for different cores. - */ -void cvmx_pko_show_queue_map() -{ - int core, port; - int pko_output_ports = 36; - - cvmx_dprintf("port"); - for (port = 0; port < pko_output_ports; port++) - cvmx_dprintf("%3d ", port); - cvmx_dprintf("\n"); - - for (core = 0; core < CVMX_MAX_CORES; core++) { - cvmx_dprintf("\n%2d: ", core); - for (port = 0; port < pko_output_ports; port++) { - cvmx_dprintf("%3d ", - cvmx_pko_get_base_queue_per_core(port, - core)); - } - } - cvmx_dprintf("\n"); -} -#endif - -/** - * Rate limit a PKO port to a max packets/sec. This function is only - * supported on CN51XX and higher, excluding CN58XX. - * - * @port: Port to rate limit - * @packets_s: Maximum packet/sec - * @burst: Maximum number of packets to burst in a row before rate - * limiting cuts in. - * - * Returns Zero on success, negative on failure - */ -int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst) -{ - union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; - union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; - - pko_mem_port_rate0.u64 = 0; - pko_mem_port_rate0.s.pid = port; - pko_mem_port_rate0.s.rate_pkt = - cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16; - /* No cost per word since we are limited by packets/sec, not bits/sec */ - pko_mem_port_rate0.s.rate_word = 0; - - pko_mem_port_rate1.u64 = 0; - pko_mem_port_rate1.s.pid = port; - pko_mem_port_rate1.s.rate_lim = - ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8; - - cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); - cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); - return 0; -} - -/** - * Rate limit a PKO port to a max bits/sec. This function is only - * supported on CN51XX and higher, excluding CN58XX. - * - * @port: Port to rate limit - * @bits_s: PKO rate limit in bits/sec - * @burst: Maximum number of bits to burst before rate - * limiting cuts in. - * - * Returns Zero on success, negative on failure - */ -int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst) -{ - union cvmx_pko_mem_port_rate0 pko_mem_port_rate0; - union cvmx_pko_mem_port_rate1 pko_mem_port_rate1; - uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz; - uint64_t tokens_per_bit = clock_rate * 16 / bits_s; - - pko_mem_port_rate0.u64 = 0; - pko_mem_port_rate0.s.pid = port; - /* - * Each packet has a 12 bytes of interframe gap, an 8 byte - * preamble, and a 4 byte CRC. These are not included in the - * per word count. Multiply by 8 to covert to bits and divide - * by 256 for limit granularity. - */ - pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256; - /* Each 8 byte word has 64bits */ - pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit; - - pko_mem_port_rate1.u64 = 0; - pko_mem_port_rate1.s.pid = port; - pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256; - - cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64); - cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64); - return 0; -} diff --git a/drivers/staging/octeon/cvmx-pko.h b/drivers/staging/octeon/cvmx-pko.h deleted file mode 100644 index de3412aada5d..000000000000 --- a/drivers/staging/octeon/cvmx-pko.h +++ /dev/null @@ -1,610 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * Interface to the hardware Packet Output unit. - * - * Starting with SDK 1.7.0, the PKO output functions now support - * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to - * function similarly to previous SDKs by using POW atomic tags - * to preserve ordering and exclusivity. As a new option, you - * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc - * memory based locking instead. This locking has the advantage - * of not affecting the tag state but doesn't preserve packet - * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most - * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used - * with hand tuned fast path code. - * - * Some of other SDK differences visible to the command command - * queuing: - * - PKO indexes are no longer stored in the FAU. A large - * percentage of the FAU register block used to be tied up - * maintaining PKO queue pointers. These are now stored in a - * global named block. - * - The PKO use_locking parameter can now have a global - * effect. Since all application use the same named block, - * queue locking correctly applies across all operating - * systems when using CVMX_PKO_LOCK_CMD_QUEUE. - * - PKO 3 word commands are now supported. Use - * cvmx_pko_send_packet_finish3(). - * - */ - -#ifndef __CVMX_PKO_H__ -#define __CVMX_PKO_H__ - -#include "cvmx-fpa.h" -#include "cvmx-pow.h" -#include "cvmx-cmd-queue.h" -#include "cvmx-pko-defs.h" - -/* Adjust the command buffer size by 1 word so that in the case of using only - * two word PKO commands no command words stradle buffers. The useful values - * for this are 0 and 1. */ -#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1) - -#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256 -#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ - OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \ - OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \ - (OCTEON_IS_MODEL(OCTEON_CN58XX) || \ - OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128) -#define CVMX_PKO_NUM_OUTPUT_PORTS 40 -/* use this for queues that are not used */ -#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 -#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 -#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF -#define CVMX_PKO_MAX_QUEUE_DEPTH 0 - -typedef enum { - CVMX_PKO_SUCCESS, - CVMX_PKO_INVALID_PORT, - CVMX_PKO_INVALID_QUEUE, - CVMX_PKO_INVALID_PRIORITY, - CVMX_PKO_NO_MEMORY, - CVMX_PKO_PORT_ALREADY_SETUP, - CVMX_PKO_CMD_QUEUE_INIT_ERROR -} cvmx_pko_status_t; - -/** - * This enumeration represents the differnet locking modes supported by PKO. - */ -typedef enum { - /* - * PKO doesn't do any locking. It is the responsibility of the - * application to make sure that no other core is accessing - * the same queue at the same time - */ - CVMX_PKO_LOCK_NONE = 0, - /* - * PKO performs an atomic tagswitch to insure exclusive access - * to the output queue. This will maintain packet ordering on - * output. - */ - CVMX_PKO_LOCK_ATOMIC_TAG = 1, - /* - * PKO uses the common command queue locks to insure exclusive - * access to the output queue. This is a memory based - * ll/sc. This is the most portable locking mechanism. - */ - CVMX_PKO_LOCK_CMD_QUEUE = 2, -} cvmx_pko_lock_t; - -typedef struct { - uint32_t packets; - uint64_t octets; - uint64_t doorbell; -} cvmx_pko_port_status_t; - -/** - * This structure defines the address to use on a packet enqueue - */ -typedef union { - uint64_t u64; - struct { - /* Must CVMX_IO_SEG */ - uint64_t mem_space:2; - /* Must be zero */ - uint64_t reserved:13; - /* Must be one */ - uint64_t is_io:1; - /* The ID of the device on the non-coherent bus */ - uint64_t did:8; - /* Must be zero */ - uint64_t reserved2:4; - /* Must be zero */ - uint64_t reserved3:18; - /* - * The hardware likes to have the output port in - * addition to the output queue, - */ - uint64_t port:6; - /* - * The output queue to send the packet to (0-127 are - * legal) - */ - uint64_t queue:9; - /* Must be zero */ - uint64_t reserved4:3; - } s; -} cvmx_pko_doorbell_address_t; - -/** - * Structure of the first packet output command word. - */ -typedef union { - uint64_t u64; - struct { - /* - * The size of the reg1 operation - could be 8, 16, - * 32, or 64 bits. - */ - uint64_t size1:2; - /* - * The size of the reg0 operation - could be 8, 16, - * 32, or 64 bits. - */ - uint64_t size0:2; - /* - * If set, subtract 1, if clear, subtract packet - * size. - */ - uint64_t subone1:1; - /* - * The register, subtract will be done if reg1 is - * non-zero. - */ - uint64_t reg1:11; - /* If set, subtract 1, if clear, subtract packet size */ - uint64_t subone0:1; - /* The register, subtract will be done if reg0 is non-zero */ - uint64_t reg0:11; - /* - * When set, interpret segment pointer and segment - * bytes in little endian order. - */ - uint64_t le:1; - /* - * When set, packet data not allocated in L2 cache by - * PKO. - */ - uint64_t n2:1; - /* - * If set and rsp is set, word3 contains a pointer to - * a work queue entry. - */ - uint64_t wqp:1; - /* If set, the hardware will send a response when done */ - uint64_t rsp:1; - /* - * If set, the supplied pkt_ptr is really a pointer to - * a list of pkt_ptr's. - */ - uint64_t gather:1; - /* - * If ipoffp1 is non zero, (ipoffp1-1) is the number - * of bytes to IP header, and the hardware will - * calculate and insert the UDP/TCP checksum. - */ - uint64_t ipoffp1:7; - /* - * If set, ignore the I bit (force to zero) from all - * pointer structures. - */ - uint64_t ignore_i:1; - /* - * If clear, the hardware will attempt to free the - * buffers containing the packet. - */ - uint64_t dontfree:1; - /* - * The total number of segs in the packet, if gather - * set, also gather list length. - */ - uint64_t segs:6; - /* Including L2, but no trailing CRC */ - uint64_t total_bytes:16; - } s; -} cvmx_pko_command_word0_t; - -/* CSR typedefs have been moved to cvmx-csr-*.h */ - -/** - * Definition of internal state for Packet output processing - */ -typedef struct { - /* ptr to start of buffer, offset kept in FAU reg */ - uint64_t *start_ptr; -} cvmx_pko_state_elem_t; - -/** - * Call before any other calls to initialize the packet - * output system. - */ -extern void cvmx_pko_initialize_global(void); -extern int cvmx_pko_initialize_local(void); - -/** - * Enables the packet output hardware. It must already be - * configured. - */ -extern void cvmx_pko_enable(void); - -/** - * Disables the packet output. Does not affect any configuration. - */ -extern void cvmx_pko_disable(void); - -/** - * Shutdown and free resources required by packet output. - */ - -extern void cvmx_pko_shutdown(void); - -/** - * Configure a output port and the associated queues for use. - * - * @port: Port to configure. - * @base_queue: First queue number to associate with this port. - * @num_queues: Number of queues t oassociate with this port - * @priority: Array of priority levels for each queue. Values are - * allowed to be 1-8. A value of 8 get 8 times the traffic - * of a value of 1. There must be num_queues elements in the - * array. - */ -extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, - uint64_t base_queue, - uint64_t num_queues, - const uint64_t priority[]); - -/** - * Ring the packet output doorbell. This tells the packet - * output hardware that "len" command words have been added - * to its pending list. This command includes the required - * CVMX_SYNCWS before the doorbell ring. - * - * @port: Port the packet is for - * @queue: Queue the packet is for - * @len: Length of the command in 64 bit words - */ -static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, - uint64_t len) -{ - cvmx_pko_doorbell_address_t ptr; - - ptr.u64 = 0; - ptr.s.mem_space = CVMX_IO_SEG; - ptr.s.did = CVMX_OCT_DID_PKT_SEND; - ptr.s.is_io = 1; - ptr.s.port = port; - ptr.s.queue = queue; - /* - * Need to make sure output queue data is in DRAM before - * doorbell write. - */ - CVMX_SYNCWS; - cvmx_write_io(ptr.u64, len); -} - -/** - * Prepare to send a packet. This may initiate a tag switch to - * get exclusive access to the output queue structure, and - * performs other prep work for the packet send operation. - * - * cvmx_pko_send_packet_finish() MUST be called after this function is called, - * and must be called with the same port/queue/use_locking arguments. - * - * The use_locking parameter allows the caller to use three - * possible locking modes. - * - CVMX_PKO_LOCK_NONE - * - PKO doesn't do any locking. It is the responsibility - * of the application to make sure that no other core - * is accessing the same queue at the same time. - * - CVMX_PKO_LOCK_ATOMIC_TAG - * - PKO performs an atomic tagswitch to insure exclusive - * access to the output queue. This will maintain - * packet ordering on output. - * - CVMX_PKO_LOCK_CMD_QUEUE - * - PKO uses the common command queue locks to insure - * exclusive access to the output queue. This is a - * memory based ll/sc. This is the most portable - * locking mechanism. - * - * NOTE: If atomic locking is used, the POW entry CANNOT be - * descheduled, as it does not contain a valid WQE pointer. - * - * @port: Port to send it on - * @queue: Queue to use - * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE - */ - -static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, - cvmx_pko_lock_t use_locking) -{ - if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) { - /* - * Must do a full switch here to handle all cases. We - * use a fake WQE pointer, as the POW does not access - * this memory. The WQE pointer and group are only - * used if this work is descheduled, which is not - * supported by the - * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish - * combination. Note that this is a special case in - * which these fake values can be used - this is not a - * general technique. - */ - uint32_t tag = - CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT | - CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT | - (CVMX_TAG_SUBGROUP_MASK & queue); - cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag, - CVMX_POW_TAG_TYPE_ATOMIC, 0); - } -} - -/** - * Complete packet output. cvmx_pko_send_packet_prepare() must be - * called exactly once before this, and the same parameters must be - * passed to both cvmx_pko_send_packet_prepare() and - * cvmx_pko_send_packet_finish(). - * - * @port: Port to send it on - * @queue: Queue to use - * @pko_command: - * PKO HW command word - * @packet: Packet to send - * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE - * - * Returns returns CVMX_PKO_SUCCESS on success, or error code on - * failure of output - */ -static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( - uint64_t port, - uint64_t queue, - cvmx_pko_command_word0_t pko_command, - union cvmx_buf_ptr packet, - cvmx_pko_lock_t use_locking) -{ - cvmx_cmd_queue_result_t result; - if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) - cvmx_pow_tag_sw_wait(); - result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue), - (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), - pko_command.u64, packet.u64); - if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { - cvmx_pko_doorbell(port, queue, 2); - return CVMX_PKO_SUCCESS; - } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) - || (result == CVMX_CMD_QUEUE_FULL)) { - return CVMX_PKO_NO_MEMORY; - } else { - return CVMX_PKO_INVALID_QUEUE; - } -} - -/** - * Complete packet output. cvmx_pko_send_packet_prepare() must be - * called exactly once before this, and the same parameters must be - * passed to both cvmx_pko_send_packet_prepare() and - * cvmx_pko_send_packet_finish(). - * - * @port: Port to send it on - * @queue: Queue to use - * @pko_command: - * PKO HW command word - * @packet: Packet to send - * @addr: Plysical address of a work queue entry or physical address - * to zero on complete. - * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or - * CVMX_PKO_LOCK_CMD_QUEUE - * - * Returns returns CVMX_PKO_SUCCESS on success, or error code on - * failure of output - */ -static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3( - uint64_t port, - uint64_t queue, - cvmx_pko_command_word0_t pko_command, - union cvmx_buf_ptr packet, - uint64_t addr, - cvmx_pko_lock_t use_locking) -{ - cvmx_cmd_queue_result_t result; - if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) - cvmx_pow_tag_sw_wait(); - result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue), - (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), - pko_command.u64, packet.u64, addr); - if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { - cvmx_pko_doorbell(port, queue, 3); - return CVMX_PKO_SUCCESS; - } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) - || (result == CVMX_CMD_QUEUE_FULL)) { - return CVMX_PKO_NO_MEMORY; - } else { - return CVMX_PKO_INVALID_QUEUE; - } -} - -/** - * Return the pko output queue associated with a port and a specific core. - * In normal mode (PKO lockless operation is disabled), the value returned - * is the base queue. - * - * @port: Port number - * @core: Core to get queue for - * - * Returns Core-specific output queue - */ -static inline int cvmx_pko_get_base_queue_per_core(int port, int core) -{ -#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 -#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16 -#endif -#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 -#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16 -#endif - - if (port < CVMX_PKO_MAX_PORTS_INTERFACE0) - return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core; - else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1) - return CVMX_PKO_MAX_PORTS_INTERFACE0 * - CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port - - 16) * - CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core; - else if ((port >= 32) && (port < 36)) - return CVMX_PKO_MAX_PORTS_INTERFACE0 * - CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + - CVMX_PKO_MAX_PORTS_INTERFACE1 * - CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port - - 32) * - CVMX_PKO_QUEUES_PER_PORT_PCI; - else if ((port >= 36) && (port < 40)) - return CVMX_PKO_MAX_PORTS_INTERFACE0 * - CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + - CVMX_PKO_MAX_PORTS_INTERFACE1 * - CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + - 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port - - 36) * - CVMX_PKO_QUEUES_PER_PORT_LOOP; - else - /* Given the limit on the number of ports we can map to - * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256, - * divided among all cores), the remaining unmapped ports - * are assigned an illegal queue number */ - return CVMX_PKO_ILLEGAL_QUEUE; -} - -/** - * For a given port number, return the base pko output queue - * for the port. - * - * @port: Port number - * Returns Base output queue - */ -static inline int cvmx_pko_get_base_queue(int port) -{ - return cvmx_pko_get_base_queue_per_core(port, 0); -} - -/** - * For a given port number, return the number of pko output queues. - * - * @port: Port number - * Returns Number of output queues - */ -static inline int cvmx_pko_get_num_queues(int port) -{ - if (port < 16) - return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0; - else if (port < 32) - return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1; - else if (port < 36) - return CVMX_PKO_QUEUES_PER_PORT_PCI; - else if (port < 40) - return CVMX_PKO_QUEUES_PER_PORT_LOOP; - else - return 0; -} - -/** - * Get the status counters for a port. - * - * @port_num: Port number to get statistics for. - * @clear: Set to 1 to clear the counters after they are read - * @status: Where to put the results. - */ -static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, - cvmx_pko_port_status_t *status) -{ - union cvmx_pko_reg_read_idx pko_reg_read_idx; - union cvmx_pko_mem_count0 pko_mem_count0; - union cvmx_pko_mem_count1 pko_mem_count1; - - pko_reg_read_idx.u64 = 0; - pko_reg_read_idx.s.index = port_num; - cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); - - pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0); - status->packets = pko_mem_count0.s.count; - if (clear) { - pko_mem_count0.s.count = port_num; - cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64); - } - - pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1); - status->octets = pko_mem_count1.s.count; - if (clear) { - pko_mem_count1.s.count = port_num; - cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64); - } - - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { - union cvmx_pko_mem_debug9 debug9; - pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); - cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); - debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); - status->doorbell = debug9.cn38xx.doorbell; - } else { - union cvmx_pko_mem_debug8 debug8; - pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); - cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); - debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); - status->doorbell = debug8.cn58xx.doorbell; - } -} - -/** - * Rate limit a PKO port to a max packets/sec. This function is only - * supported on CN57XX, CN56XX, CN55XX, and CN54XX. - * - * @port: Port to rate limit - * @packets_s: Maximum packet/sec - * @burst: Maximum number of packets to burst in a row before rate - * limiting cuts in. - * - * Returns Zero on success, negative on failure - */ -extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst); - -/** - * Rate limit a PKO port to a max bits/sec. This function is only - * supported on CN57XX, CN56XX, CN55XX, and CN54XX. - * - * @port: Port to rate limit - * @bits_s: PKO rate limit in bits/sec - * @burst: Maximum number of bits to burst before rate - * limiting cuts in. - * - * Returns Zero on success, negative on failure - */ -extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst); - -#endif /* __CVMX_PKO_H__ */ diff --git a/drivers/staging/octeon/cvmx-pow.h b/drivers/staging/octeon/cvmx-pow.h deleted file mode 100644 index 999aefe3274c..000000000000 --- a/drivers/staging/octeon/cvmx-pow.h +++ /dev/null @@ -1,1982 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * Interface to the hardware Packet Order / Work unit. - * - * New, starting with SDK 1.7.0, cvmx-pow supports a number of - * extended consistency checks. The define - * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW - * internal state checks to find common programming errors. If - * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default - * enabled. For example, cvmx-pow will check for the following - * program errors or POW state inconsistency. - * - Requesting a POW operation with an active tag switch in - * progress. - * - Waiting for a tag switch to complete for an excessively - * long period. This is normally a sign of an error in locking - * causing deadlock. - * - Illegal tag switches from NULL_NULL. - * - Illegal tag switches from NULL. - * - Illegal deschedule request. - * - WQE pointer not matching the one attached to the core by - * the POW. - * - */ - -#ifndef __CVMX_POW_H__ -#define __CVMX_POW_H__ - -#include - -#include "cvmx-scratch.h" -#include "cvmx-wqe.h" - -/* Default to having all POW constancy checks turned on */ -#ifndef CVMX_ENABLE_POW_CHECKS -#define CVMX_ENABLE_POW_CHECKS 1 -#endif - -enum cvmx_pow_tag_type { - /* Tag ordering is maintained */ - CVMX_POW_TAG_TYPE_ORDERED = 0L, - /* Tag ordering is maintained, and at most one PP has the tag */ - CVMX_POW_TAG_TYPE_ATOMIC = 1L, - /* - * The work queue entry from the order - NEVER tag switch from - * NULL to NULL - */ - CVMX_POW_TAG_TYPE_NULL = 2L, - /* A tag switch to NULL, and there is no space reserved in POW - * - NEVER tag switch to NULL_NULL - * - NEVER tag switch from NULL_NULL - * - NULL_NULL is entered at the beginning of time and on a deschedule. - * - NULL_NULL can be exited by a new work request. A NULL_SWITCH - * load can also switch the state to NULL - */ - CVMX_POW_TAG_TYPE_NULL_NULL = 3L -}; - -/** - * Wait flag values for pow functions. - */ -typedef enum { - CVMX_POW_WAIT = 1, - CVMX_POW_NO_WAIT = 0, -} cvmx_pow_wait_t; - -/** - * POW tag operations. These are used in the data stored to the POW. - */ -typedef enum { - /* - * switch the tag (only) for this PP - * - the previous tag should be non-NULL in this case - * - tag switch response required - * - fields used: op, type, tag - */ - CVMX_POW_TAG_OP_SWTAG = 0L, - /* - * switch the tag for this PP, with full information - * - this should be used when the previous tag is NULL - * - tag switch response required - * - fields used: address, op, grp, type, tag - */ - CVMX_POW_TAG_OP_SWTAG_FULL = 1L, - /* - * switch the tag (and/or group) for this PP and de-schedule - * - OK to keep the tag the same and only change the group - * - fields used: op, no_sched, grp, type, tag - */ - CVMX_POW_TAG_OP_SWTAG_DESCH = 2L, - /* - * just de-schedule - * - fields used: op, no_sched - */ - CVMX_POW_TAG_OP_DESCH = 3L, - /* - * create an entirely new work queue entry - * - fields used: address, op, qos, grp, type, tag - */ - CVMX_POW_TAG_OP_ADDWQ = 4L, - /* - * just update the work queue pointer and grp for this PP - * - fields used: address, op, grp - */ - CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L, - /* - * set the no_sched bit on the de-schedule list - * - * - does nothing if the selected entry is not on the - * de-schedule list - * - * - does nothing if the stored work queue pointer does not - * match the address field - * - * - fields used: address, index, op - * - * Before issuing a *_NSCHED operation, SW must guarantee - * that all prior deschedules and set/clr NSCHED operations - * are complete and all prior switches are complete. The - * hardware provides the opsdone bit and swdone bit for SW - * polling. After issuing a *_NSCHED operation, SW must - * guarantee that the set/clr NSCHED is complete before any - * subsequent operations. - */ - CVMX_POW_TAG_OP_SET_NSCHED = 6L, - /* - * clears the no_sched bit on the de-schedule list - * - * - does nothing if the selected entry is not on the - * de-schedule list - * - * - does nothing if the stored work queue pointer does not - * match the address field - * - * - fields used: address, index, op - * - * Before issuing a *_NSCHED operation, SW must guarantee that - * all prior deschedules and set/clr NSCHED operations are - * complete and all prior switches are complete. The hardware - * provides the opsdone bit and swdone bit for SW - * polling. After issuing a *_NSCHED operation, SW must - * guarantee that the set/clr NSCHED is complete before any - * subsequent operations. - */ - CVMX_POW_TAG_OP_CLR_NSCHED = 7L, - /* do nothing */ - CVMX_POW_TAG_OP_NOP = 15L -} cvmx_pow_tag_op_t; - -/** - * This structure defines the store data on a store to POW - */ -typedef union { - uint64_t u64; - struct { - /* - * Don't reschedule this entry. no_sched is used for - * CVMX_POW_TAG_OP_SWTAG_DESCH and - * CVMX_POW_TAG_OP_DESCH - */ - uint64_t no_sched:1; - uint64_t unused:2; - /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */ - uint64_t index:13; - /* The operation to perform */ - cvmx_pow_tag_op_t op:4; - uint64_t unused2:2; - /* - * The QOS level for the packet. qos is only used for - * CVMX_POW_TAG_OP_ADDWQ - */ - uint64_t qos:3; - /* - * The group that the work queue entry will be - * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ, - * CVMX_POW_TAG_OP_SWTAG_FULL, - * CVMX_POW_TAG_OP_SWTAG_DESCH, and - * CVMX_POW_TAG_OP_UPDATE_WQP_GRP - */ - uint64_t grp:4; - /* - * The type of the tag. type is used for everything - * except CVMX_POW_TAG_OP_DESCH, - * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and - * CVMX_POW_TAG_OP_*_NSCHED - */ - uint64_t type:3; - /* - * The actual tag. tag is used for everything except - * CVMX_POW_TAG_OP_DESCH, - * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and - * CVMX_POW_TAG_OP_*_NSCHED - */ - uint64_t tag:32; - } s; -} cvmx_pow_tag_req_t; - -/** - * This structure describes the address to load stuff from POW - */ -typedef union { - uint64_t u64; - - /** - * Address for new work request loads (did<2:0> == 0) - */ - struct { - /* Mips64 address region. Should be CVMX_IO_SEG */ - uint64_t mem_region:2; - /* Must be zero */ - uint64_t reserved_49_61:13; - /* Must be one */ - uint64_t is_io:1; - /* the ID of POW -- did<2:0> == 0 in this case */ - uint64_t did:8; - /* Must be zero */ - uint64_t reserved_4_39:36; - /* - * If set, don't return load response until work is - * available. - */ - uint64_t wait:1; - /* Must be zero */ - uint64_t reserved_0_2:3; - } swork; - - /** - * Address for loads to get POW internal status - */ - struct { - /* Mips64 address region. Should be CVMX_IO_SEG */ - uint64_t mem_region:2; - /* Must be zero */ - uint64_t reserved_49_61:13; - /* Must be one */ - uint64_t is_io:1; - /* the ID of POW -- did<2:0> == 1 in this case */ - uint64_t did:8; - /* Must be zero */ - uint64_t reserved_10_39:30; - /* The core id to get status for */ - uint64_t coreid:4; - /* - * If set and get_cur is set, return reverse tag-list - * pointer rather than forward tag-list pointer. - */ - uint64_t get_rev:1; - /* - * If set, return current status rather than pending - * status. - */ - uint64_t get_cur:1; - /* - * If set, get the work-queue pointer rather than - * tag/type. - */ - uint64_t get_wqp:1; - /* Must be zero */ - uint64_t reserved_0_2:3; - } sstatus; - - /** - * Address for memory loads to get POW internal state - */ - struct { - /* Mips64 address region. Should be CVMX_IO_SEG */ - uint64_t mem_region:2; - /* Must be zero */ - uint64_t reserved_49_61:13; - /* Must be one */ - uint64_t is_io:1; - /* the ID of POW -- did<2:0> == 2 in this case */ - uint64_t did:8; - /* Must be zero */ - uint64_t reserved_16_39:24; - /* POW memory index */ - uint64_t index:11; - /* - * If set, return deschedule information rather than - * the standard response for work-queue index (invalid - * if the work-queue entry is not on the deschedule - * list). - */ - uint64_t get_des:1; - /* - * If set, get the work-queue pointer rather than - * tag/type (no effect when get_des set). - */ - uint64_t get_wqp:1; - /* Must be zero */ - uint64_t reserved_0_2:3; - } smemload; - - /** - * Address for index/pointer loads - */ - struct { - /* Mips64 address region. Should be CVMX_IO_SEG */ - uint64_t mem_region:2; - /* Must be zero */ - uint64_t reserved_49_61:13; - /* Must be one */ - uint64_t is_io:1; - /* the ID of POW -- did<2:0> == 3 in this case */ - uint64_t did:8; - /* Must be zero */ - uint64_t reserved_9_39:31; - /* - * when {get_rmt ==0 AND get_des_get_tail == 0}, this - * field selects one of eight POW internal-input - * queues (0-7), one per QOS level; values 8-15 are - * illegal in this case; when {get_rmt ==0 AND - * get_des_get_tail == 1}, this field selects one of - * 16 deschedule lists (per group); when get_rmt ==1, - * this field selects one of 16 memory-input queue - * lists. The two memory-input queue lists associated - * with each QOS level are: - * - * - qosgrp = 0, qosgrp = 8: QOS0 - * - qosgrp = 1, qosgrp = 9: QOS1 - * - qosgrp = 2, qosgrp = 10: QOS2 - * - qosgrp = 3, qosgrp = 11: QOS3 - * - qosgrp = 4, qosgrp = 12: QOS4 - * - qosgrp = 5, qosgrp = 13: QOS5 - * - qosgrp = 6, qosgrp = 14: QOS6 - * - qosgrp = 7, qosgrp = 15: QOS7 - */ - uint64_t qosgrp:4; - /* - * If set and get_rmt is clear, return deschedule list - * indexes rather than indexes for the specified qos - * level; if set and get_rmt is set, return the tail - * pointer rather than the head pointer for the - * specified qos level. - */ - uint64_t get_des_get_tail:1; - /* - * If set, return remote pointers rather than the - * local indexes for the specified qos level. - */ - uint64_t get_rmt:1; - /* Must be zero */ - uint64_t reserved_0_2:3; - } sindexload; - - /** - * address for NULL_RD request (did<2:0> == 4) when this is read, - * HW attempts to change the state to NULL if it is NULL_NULL (the - * hardware cannot switch from NULL_NULL to NULL if a POW entry is - * not available - software may need to recover by finishing - * another piece of work before a POW entry can ever become - * available.) - */ - struct { - /* Mips64 address region. Should be CVMX_IO_SEG */ - uint64_t mem_region:2; - /* Must be zero */ - uint64_t reserved_49_61:13; - /* Must be one */ - uint64_t is_io:1; - /* the ID of POW -- did<2:0> == 4 in this case */ - uint64_t did:8; - /* Must be zero */ - uint64_t reserved_0_39:40; - } snull_rd; -} cvmx_pow_load_addr_t; - -/** - * This structure defines the response to a load/SENDSINGLE to POW - * (except CSR reads) - */ -typedef union { - uint64_t u64; - - /** - * Response to new work request loads - */ - struct { - /* - * Set when no new work queue entry was returned. * - * If there was de-scheduled work, the HW will - * definitely return it. When this bit is set, it - * could mean either mean: - * - * - There was no work, or - * - * - There was no work that the HW could find. This - * case can happen, regardless of the wait bit value - * in the original request, when there is work in - * the IQ's that is too deep down the list. - */ - uint64_t no_work:1; - /* Must be zero */ - uint64_t reserved_40_62:23; - /* 36 in O1 -- the work queue pointer */ - uint64_t addr:40; - } s_work; - - /** - * Result for a POW Status Load (when get_cur==0 and get_wqp==0) - */ - struct { - uint64_t reserved_62_63:2; - /* Set when there is a pending non-NULL SWTAG or - * SWTAG_FULL, and the POW entry has not left the list - * for the original tag. */ - uint64_t pend_switch:1; - /* Set when SWTAG_FULL and pend_switch is set. */ - uint64_t pend_switch_full:1; - /* - * Set when there is a pending NULL SWTAG, or an - * implicit switch to NULL. - */ - uint64_t pend_switch_null:1; - /* Set when there is a pending DESCHED or SWTAG_DESCHED. */ - uint64_t pend_desched:1; - /* - * Set when there is a pending SWTAG_DESCHED and - * pend_desched is set. - */ - uint64_t pend_desched_switch:1; - /* Set when nosched is desired and pend_desched is set. */ - uint64_t pend_nosched:1; - /* Set when there is a pending GET_WORK. */ - uint64_t pend_new_work:1; - /* - * When pend_new_work is set, this bit indicates that - * the wait bit was set. - */ - uint64_t pend_new_work_wait:1; - /* Set when there is a pending NULL_RD. */ - uint64_t pend_null_rd:1; - /* Set when there is a pending CLR_NSCHED. */ - uint64_t pend_nosched_clr:1; - uint64_t reserved_51:1; - /* This is the index when pend_nosched_clr is set. */ - uint64_t pend_index:11; - /* - * This is the new_grp when (pend_desched AND - * pend_desched_switch) is set. - */ - uint64_t pend_grp:4; - uint64_t reserved_34_35:2; - /* - * This is the tag type when pend_switch or - * (pend_desched AND pend_desched_switch) are set. - */ - uint64_t pend_type:2; - /* - * - this is the tag when pend_switch or (pend_desched - * AND pend_desched_switch) are set. - */ - uint64_t pend_tag:32; - } s_sstatus0; - - /** - * Result for a POW Status Load (when get_cur==0 and get_wqp==1) - */ - struct { - uint64_t reserved_62_63:2; - /* - * Set when there is a pending non-NULL SWTAG or - * SWTAG_FULL, and the POW entry has not left the list - * for the original tag. - */ - uint64_t pend_switch:1; - /* Set when SWTAG_FULL and pend_switch is set. */ - uint64_t pend_switch_full:1; - /* - * Set when there is a pending NULL SWTAG, or an - * implicit switch to NULL. - */ - uint64_t pend_switch_null:1; - /* - * Set when there is a pending DESCHED or - * SWTAG_DESCHED. - */ - uint64_t pend_desched:1; - /* - * Set when there is a pending SWTAG_DESCHED and - * pend_desched is set. - */ - uint64_t pend_desched_switch:1; - /* Set when nosched is desired and pend_desched is set. */ - uint64_t pend_nosched:1; - /* Set when there is a pending GET_WORK. */ - uint64_t pend_new_work:1; - /* - * When pend_new_work is set, this bit indicates that - * the wait bit was set. - */ - uint64_t pend_new_work_wait:1; - /* Set when there is a pending NULL_RD. */ - uint64_t pend_null_rd:1; - /* Set when there is a pending CLR_NSCHED. */ - uint64_t pend_nosched_clr:1; - uint64_t reserved_51:1; - /* This is the index when pend_nosched_clr is set. */ - uint64_t pend_index:11; - /* - * This is the new_grp when (pend_desched AND - * pend_desched_switch) is set. - */ - uint64_t pend_grp:4; - /* This is the wqp when pend_nosched_clr is set. */ - uint64_t pend_wqp:36; - } s_sstatus1; - - /** - * Result for a POW Status Load (when get_cur==1, get_wqp==0, and - * get_rev==0) - */ - struct { - uint64_t reserved_62_63:2; - /* - * Points to the next POW entry in the tag list when - * tail == 0 (and tag_type is not NULL or NULL_NULL). - */ - uint64_t link_index:11; - /* The POW entry attached to the core. */ - uint64_t index:11; - /* - * The group attached to the core (updated when new - * tag list entered on SWTAG_FULL). - */ - uint64_t grp:4; - /* - * Set when this POW entry is at the head of its tag - * list (also set when in the NULL or NULL_NULL - * state). - */ - uint64_t head:1; - /* - * Set when this POW entry is at the tail of its tag - * list (also set when in the NULL or NULL_NULL - * state). - */ - uint64_t tail:1; - /* - * The tag type attached to the core (updated when new - * tag list entered on SWTAG, SWTAG_FULL, or - * SWTAG_DESCHED). - */ - uint64_t tag_type:2; - /* - * The tag attached to the core (updated when new tag - * list entered on SWTAG, SWTAG_FULL, or - * SWTAG_DESCHED). - */ - uint64_t tag:32; - } s_sstatus2; - - /** - * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1) - */ - struct { - uint64_t reserved_62_63:2; - /* - * Points to the prior POW entry in the tag list when - * head == 0 (and tag_type is not NULL or - * NULL_NULL). This field is unpredictable when the - * core's state is NULL or NULL_NULL. - */ - uint64_t revlink_index:11; - /* The POW entry attached to the core. */ - uint64_t index:11; - /* - * The group attached to the core (updated when new - * tag list entered on SWTAG_FULL). - */ - uint64_t grp:4; - /* Set when this POW entry is at the head of its tag - * list (also set when in the NULL or NULL_NULL - * state). - */ - uint64_t head:1; - /* - * Set when this POW entry is at the tail of its tag - * list (also set when in the NULL or NULL_NULL - * state). - */ - uint64_t tail:1; - /* - * The tag type attached to the core (updated when new - * tag list entered on SWTAG, SWTAG_FULL, or - * SWTAG_DESCHED). - */ - uint64_t tag_type:2; - /* - * The tag attached to the core (updated when new tag - * list entered on SWTAG, SWTAG_FULL, or - * SWTAG_DESCHED). - */ - uint64_t tag:32; - } s_sstatus3; - - /** - * Result for a POW Status Load (when get_cur==1, get_wqp==1, and - * get_rev==0) - */ - struct { - uint64_t reserved_62_63:2; - /* - * Points to the next POW entry in the tag list when - * tail == 0 (and tag_type is not NULL or NULL_NULL). - */ - uint64_t link_index:11; - /* The POW entry attached to the core. */ - uint64_t index:11; - /* - * The group attached to the core (updated when new - * tag list entered on SWTAG_FULL). - */ - uint64_t grp:4; - /* - * The wqp attached to the core (updated when new tag - * list entered on SWTAG_FULL). - */ - uint64_t wqp:36; - } s_sstatus4; - - /** - * Result for a POW Status Load (when get_cur==1, get_wqp==1, and - * get_rev==1) - */ - struct { - uint64_t reserved_62_63:2; - /* - * Points to the prior POW entry in the tag list when - * head == 0 (and tag_type is not NULL or - * NULL_NULL). This field is unpredictable when the - * core's state is NULL or NULL_NULL. - */ - uint64_t revlink_index:11; - /* The POW entry attached to the core. */ - uint64_t index:11; - /* - * The group attached to the core (updated when new - * tag list entered on SWTAG_FULL). - */ - uint64_t grp:4; - /* - * The wqp attached to the core (updated when new tag - * list entered on SWTAG_FULL). - */ - uint64_t wqp:36; - } s_sstatus5; - - /** - * Result For POW Memory Load (get_des == 0 and get_wqp == 0) - */ - struct { - uint64_t reserved_51_63:13; - /* - * The next entry in the input, free, descheduled_head - * list (unpredictable if entry is the tail of the - * list). - */ - uint64_t next_index:11; - /* The group of the POW entry. */ - uint64_t grp:4; - uint64_t reserved_35:1; - /* - * Set when this POW entry is at the tail of its tag - * list (also set when in the NULL or NULL_NULL - * state). - */ - uint64_t tail:1; - /* The tag type of the POW entry. */ - uint64_t tag_type:2; - /* The tag of the POW entry. */ - uint64_t tag:32; - } s_smemload0; - - /** - * Result For POW Memory Load (get_des == 0 and get_wqp == 1) - */ - struct { - uint64_t reserved_51_63:13; - /* - * The next entry in the input, free, descheduled_head - * list (unpredictable if entry is the tail of the - * list). - */ - uint64_t next_index:11; - /* The group of the POW entry. */ - uint64_t grp:4; - /* The WQP held in the POW entry. */ - uint64_t wqp:36; - } s_smemload1; - - /** - * Result For POW Memory Load (get_des == 1) - */ - struct { - uint64_t reserved_51_63:13; - /* - * The next entry in the tag list connected to the - * descheduled head. - */ - uint64_t fwd_index:11; - /* The group of the POW entry. */ - uint64_t grp:4; - /* The nosched bit for the POW entry. */ - uint64_t nosched:1; - /* There is a pending tag switch */ - uint64_t pend_switch:1; - /* - * The next tag type for the new tag list when - * pend_switch is set. - */ - uint64_t pend_type:2; - /* - * The next tag for the new tag list when pend_switch - * is set. - */ - uint64_t pend_tag:32; - } s_smemload2; - - /** - * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0) - */ - struct { - uint64_t reserved_52_63:12; - /* - * set when there is one or more POW entries on the - * free list. - */ - uint64_t free_val:1; - /* - * set when there is exactly one POW entry on the free - * list. - */ - uint64_t free_one:1; - uint64_t reserved_49:1; - /* - * when free_val is set, indicates the first entry on - * the free list. - */ - uint64_t free_head:11; - uint64_t reserved_37:1; - /* - * when free_val is set, indicates the last entry on - * the free list. - */ - uint64_t free_tail:11; - /* - * set when there is one or more POW entries on the - * input Q list selected by qosgrp. - */ - uint64_t loc_val:1; - /* - * set when there is exactly one POW entry on the - * input Q list selected by qosgrp. - */ - uint64_t loc_one:1; - uint64_t reserved_23:1; - /* - * when loc_val is set, indicates the first entry on - * the input Q list selected by qosgrp. - */ - uint64_t loc_head:11; - uint64_t reserved_11:1; - /* - * when loc_val is set, indicates the last entry on - * the input Q list selected by qosgrp. - */ - uint64_t loc_tail:11; - } sindexload0; - - /** - * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1) - */ - struct { - uint64_t reserved_52_63:12; - /* - * set when there is one or more POW entries on the - * nosched list. - */ - uint64_t nosched_val:1; - /* - * set when there is exactly one POW entry on the - * nosched list. - */ - uint64_t nosched_one:1; - uint64_t reserved_49:1; - /* - * when nosched_val is set, indicates the first entry - * on the nosched list. - */ - uint64_t nosched_head:11; - uint64_t reserved_37:1; - /* - * when nosched_val is set, indicates the last entry - * on the nosched list. - */ - uint64_t nosched_tail:11; - /* - * set when there is one or more descheduled heads on - * the descheduled list selected by qosgrp. - */ - uint64_t des_val:1; - /* - * set when there is exactly one descheduled head on - * the descheduled list selected by qosgrp. - */ - uint64_t des_one:1; - uint64_t reserved_23:1; - /* - * when des_val is set, indicates the first - * descheduled head on the descheduled list selected - * by qosgrp. - */ - uint64_t des_head:11; - uint64_t reserved_11:1; - /* - * when des_val is set, indicates the last descheduled - * head on the descheduled list selected by qosgrp. - */ - uint64_t des_tail:11; - } sindexload1; - - /** - * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0) - */ - struct { - uint64_t reserved_39_63:25; - /* - * Set when this DRAM list is the current head - * (i.e. is the next to be reloaded when the POW - * hardware reloads a POW entry from DRAM). The POW - * hardware alternates between the two DRAM lists - * associated with a QOS level when it reloads work - * from DRAM into the POW unit. - */ - uint64_t rmt_is_head:1; - /* - * Set when the DRAM portion of the input Q list - * selected by qosgrp contains one or more pieces of - * work. - */ - uint64_t rmt_val:1; - /* - * Set when the DRAM portion of the input Q list - * selected by qosgrp contains exactly one piece of - * work. - */ - uint64_t rmt_one:1; - /* - * When rmt_val is set, indicates the first piece of - * work on the DRAM input Q list selected by - * qosgrp. - */ - uint64_t rmt_head:36; - } sindexload2; - - /** - * Result For POW Index/Pointer Load (get_rmt == - * 1/get_des_get_tail == 1) - */ - struct { - uint64_t reserved_39_63:25; - /* - * set when this DRAM list is the current head - * (i.e. is the next to be reloaded when the POW - * hardware reloads a POW entry from DRAM). The POW - * hardware alternates between the two DRAM lists - * associated with a QOS level when it reloads work - * from DRAM into the POW unit. - */ - uint64_t rmt_is_head:1; - /* - * set when the DRAM portion of the input Q list - * selected by qosgrp contains one or more pieces of - * work. - */ - uint64_t rmt_val:1; - /* - * set when the DRAM portion of the input Q list - * selected by qosgrp contains exactly one piece of - * work. - */ - uint64_t rmt_one:1; - /* - * when rmt_val is set, indicates the last piece of - * work on the DRAM input Q list selected by - * qosgrp. - */ - uint64_t rmt_tail:36; - } sindexload3; - - /** - * Response to NULL_RD request loads - */ - struct { - uint64_t unused:62; - /* of type cvmx_pow_tag_type_t. state is one of the - * following: - * - * - CVMX_POW_TAG_TYPE_ORDERED - * - CVMX_POW_TAG_TYPE_ATOMIC - * - CVMX_POW_TAG_TYPE_NULL - * - CVMX_POW_TAG_TYPE_NULL_NULL - */ - uint64_t state:2; - } s_null_rd; - -} cvmx_pow_tag_load_resp_t; - -/** - * This structure describes the address used for stores to the POW. - * The store address is meaningful on stores to the POW. The - * hardware assumes that an aligned 64-bit store was used for all - * these stores. Note the assumption that the work queue entry is - * aligned on an 8-byte boundary (since the low-order 3 address bits - * must be zero). Note that not all fields are used by all - * operations. - * - * NOTE: The following is the behavior of the pending switch bit at the PP - * for POW stores (i.e. when did<7:3> == 0xc) - * - did<2:0> == 0 => pending switch bit is set - * - did<2:0> == 1 => no affect on the pending switch bit - * - did<2:0> == 3 => pending switch bit is cleared - * - did<2:0> == 7 => no affect on the pending switch bit - * - did<2:0> == others => must not be used - * - No other loads/stores have an affect on the pending switch bit - * - The switch bus from POW can clear the pending switch bit - * - * NOTE: did<2:0> == 2 is used by the HW for a special single-cycle - * ADDWQ command that only contains the pointer). SW must never use - * did<2:0> == 2. - */ -typedef union { - /** - * Unsigned 64 bit integer representation of store address - */ - uint64_t u64; - - struct { - /* Memory region. Should be CVMX_IO_SEG in most cases */ - uint64_t mem_reg:2; - uint64_t reserved_49_61:13; /* Must be zero */ - uint64_t is_io:1; /* Must be one */ - /* Device ID of POW. Note that different sub-dids are used. */ - uint64_t did:8; - uint64_t reserved_36_39:4; /* Must be zero */ - /* Address field. addr<2:0> must be zero */ - uint64_t addr:36; - } stag; -} cvmx_pow_tag_store_addr_t; - -/** - * decode of the store data when an IOBDMA SENDSINGLE is sent to POW - */ -typedef union { - uint64_t u64; - - struct { - /* - * the (64-bit word) location in scratchpad to write - * to (if len != 0) - */ - uint64_t scraddr:8; - /* the number of words in the response (0 => no response) */ - uint64_t len:8; - /* the ID of the device on the non-coherent bus */ - uint64_t did:8; - uint64_t unused:36; - /* if set, don't return load response until work is available */ - uint64_t wait:1; - uint64_t unused2:3; - } s; - -} cvmx_pow_iobdma_store_t; - -/* CSR typedefs have been moved to cvmx-csr-*.h */ - -/** - * Get the POW tag for this core. This returns the current - * tag type, tag, group, and POW entry index associated with - * this core. Index is only valid if the tag type isn't NULL_NULL. - * If a tag switch is pending this routine returns the tag before - * the tag switch, not after. - * - * Returns Current tag - */ -static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void) -{ - cvmx_pow_load_addr_t load_addr; - cvmx_pow_tag_load_resp_t load_resp; - cvmx_pow_tag_req_t result; - - load_addr.u64 = 0; - load_addr.sstatus.mem_region = CVMX_IO_SEG; - load_addr.sstatus.is_io = 1; - load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1; - load_addr.sstatus.coreid = cvmx_get_core_num(); - load_addr.sstatus.get_cur = 1; - load_resp.u64 = cvmx_read_csr(load_addr.u64); - result.u64 = 0; - result.s.grp = load_resp.s_sstatus2.grp; - result.s.index = load_resp.s_sstatus2.index; - result.s.type = load_resp.s_sstatus2.tag_type; - result.s.tag = load_resp.s_sstatus2.tag; - return result; -} - -/** - * Get the POW WQE for this core. This returns the work queue - * entry currently associated with this core. - * - * Returns WQE pointer - */ -static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void) -{ - cvmx_pow_load_addr_t load_addr; - cvmx_pow_tag_load_resp_t load_resp; - - load_addr.u64 = 0; - load_addr.sstatus.mem_region = CVMX_IO_SEG; - load_addr.sstatus.is_io = 1; - load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1; - load_addr.sstatus.coreid = cvmx_get_core_num(); - load_addr.sstatus.get_cur = 1; - load_addr.sstatus.get_wqp = 1; - load_resp.u64 = cvmx_read_csr(load_addr.u64); - return (cvmx_wqe_t *) cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp); -} - -#ifndef CVMX_MF_CHORD -#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30) -#endif - -/** - * Print a warning if a tag switch is pending for this core - * - * @function: Function name checking for a pending tag switch - */ -static inline void __cvmx_pow_warn_if_pending_switch(const char *function) -{ - uint64_t switch_complete; - CVMX_MF_CHORD(switch_complete); - if (!switch_complete) - pr_warning("%s called with tag switch in progress\n", function); -} - -/** - * Waits for a tag switch to complete by polling the completion bit. - * Note that switches to NULL complete immediately and do not need - * to be waited for. - */ -static inline void cvmx_pow_tag_sw_wait(void) -{ - const uint64_t MAX_CYCLES = 1ull << 31; - uint64_t switch_complete; - uint64_t start_cycle = cvmx_get_cycle(); - while (1) { - CVMX_MF_CHORD(switch_complete); - if (unlikely(switch_complete)) - break; - if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) { - pr_warning("Tag switch is taking a long time, " - "possible deadlock\n"); - start_cycle = -MAX_CYCLES - 1; - } - } -} - -/** - * Synchronous work request. Requests work from the POW. - * This function does NOT wait for previous tag switches to complete, - * so the caller must ensure that there is not a pending tag switch. - * - * @wait: When set, call stalls until work becomes avaiable, or times out. - * If not set, returns immediately. - * - * Returns Returns the WQE pointer from POW. Returns NULL if no work - * was available. - */ -static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t - wait) -{ - cvmx_pow_load_addr_t ptr; - cvmx_pow_tag_load_resp_t result; - - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - ptr.u64 = 0; - ptr.swork.mem_region = CVMX_IO_SEG; - ptr.swork.is_io = 1; - ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG; - ptr.swork.wait = wait; - - result.u64 = cvmx_read_csr(ptr.u64); - - if (result.s_work.no_work) - return NULL; - else - return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr); -} - -/** - * Synchronous work request. Requests work from the POW. - * This function waits for any previous tag switch to complete before - * requesting the new work. - * - * @wait: When set, call stalls until work becomes avaiable, or times out. - * If not set, returns immediately. - * - * Returns Returns the WQE pointer from POW. Returns NULL if no work - * was available. - */ -static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait) -{ - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - /* Must not have a switch pending when requesting work */ - cvmx_pow_tag_sw_wait(); - return cvmx_pow_work_request_sync_nocheck(wait); - -} - -/** - * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state. - * This function waits for any previous tag switch to complete before - * requesting the null_rd. - * - * Returns Returns the POW state of type cvmx_pow_tag_type_t. - */ -static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void) -{ - cvmx_pow_load_addr_t ptr; - cvmx_pow_tag_load_resp_t result; - - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - /* Must not have a switch pending when requesting work */ - cvmx_pow_tag_sw_wait(); - - ptr.u64 = 0; - ptr.snull_rd.mem_region = CVMX_IO_SEG; - ptr.snull_rd.is_io = 1; - ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD; - - result.u64 = cvmx_read_csr(ptr.u64); - - return (enum cvmx_pow_tag_type) result.s_null_rd.state; -} - -/** - * Asynchronous work request. Work is requested from the POW unit, - * and should later be checked with function - * cvmx_pow_work_response_async. This function does NOT wait for - * previous tag switches to complete, so the caller must ensure that - * there is not a pending tag switch. - * - * @scr_addr: Scratch memory address that response will be returned - * to, which is either a valid WQE, or a response with the - * invalid bit set. Byte address, must be 8 byte aligned. - * - * @wait: 1 to cause response to wait for work to become available (or - * timeout), 0 to cause response to return immediately - */ -static inline void cvmx_pow_work_request_async_nocheck(int scr_addr, - cvmx_pow_wait_t wait) -{ - cvmx_pow_iobdma_store_t data; - - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - /* scr_addr must be 8 byte aligned */ - data.s.scraddr = scr_addr >> 3; - data.s.len = 1; - data.s.did = CVMX_OCT_DID_TAG_SWTAG; - data.s.wait = wait; - cvmx_send_single(data.u64); -} - -/** - * Asynchronous work request. Work is requested from the POW unit, - * and should later be checked with function - * cvmx_pow_work_response_async. This function waits for any previous - * tag switch to complete before requesting the new work. - * - * @scr_addr: Scratch memory address that response will be returned - * to, which is either a valid WQE, or a response with the - * invalid bit set. Byte address, must be 8 byte aligned. - * - * @wait: 1 to cause response to wait for work to become available (or - * timeout), 0 to cause response to return immediately - */ -static inline void cvmx_pow_work_request_async(int scr_addr, - cvmx_pow_wait_t wait) -{ - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - /* Must not have a switch pending when requesting work */ - cvmx_pow_tag_sw_wait(); - cvmx_pow_work_request_async_nocheck(scr_addr, wait); -} - -/** - * Gets result of asynchronous work request. Performs a IOBDMA sync - * to wait for the response. - * - * @scr_addr: Scratch memory address to get result from Byte address, - * must be 8 byte aligned. - * - * Returns Returns the WQE from the scratch register, or NULL if no - * work was available. - */ -static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr) -{ - cvmx_pow_tag_load_resp_t result; - - CVMX_SYNCIOBDMA; - result.u64 = cvmx_scratch_read64(scr_addr); - - if (result.s_work.no_work) - return NULL; - else - return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr); -} - -/** - * Checks if a work queue entry pointer returned by a work - * request is valid. It may be invalid due to no work - * being available or due to a timeout. - * - * @wqe_ptr: pointer to a work queue entry returned by the POW - * - * Returns 0 if pointer is valid - * 1 if invalid (no work was returned) - */ -static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr) -{ - return wqe_ptr == NULL; -} - -/** - * Starts a tag switch to the provided tag value and tag type. - * Completion for the tag switch must be checked for separately. This - * function does NOT update the work queue entry in dram to match tag - * value and type, so the application must keep track of these if they - * are important to the application. This tag switch command must not - * be used for switches to NULL, as the tag switch pending bit will be - * set by the switch request, but never cleared by the hardware. - * - * NOTE: This should not be used when switching from a NULL tag. Use - * cvmx_pow_tag_sw_full() instead. - * - * This function does no checks, so the caller must ensure that any - * previous tag switch has completed. - * - * @tag: new tag value - * @tag_type: new tag type (ordered or atomic) - */ -static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag, - enum cvmx_pow_tag_type tag_type) -{ - cvmx_addr_t ptr; - cvmx_pow_tag_req_t tag_req; - - if (CVMX_ENABLE_POW_CHECKS) { - cvmx_pow_tag_req_t current_tag; - __cvmx_pow_warn_if_pending_switch(__func__); - current_tag = cvmx_pow_get_current_tag(); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) - pr_warning("%s called with NULL_NULL tag\n", - __func__); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) - pr_warning("%s called with NULL tag\n", __func__); - if ((current_tag.s.type == tag_type) - && (current_tag.s.tag == tag)) - pr_warning("%s called to perform a tag switch to the " - "same tag\n", - __func__); - if (tag_type == CVMX_POW_TAG_TYPE_NULL) - pr_warning("%s called to perform a tag switch to " - "NULL. Use cvmx_pow_tag_sw_null() instead\n", - __func__); - } - - /* - * Note that WQE in DRAM is not updated here, as the POW does - * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's - * responsibility to keep track of the current tag value if - * that is important. - */ - - tag_req.u64 = 0; - tag_req.s.op = CVMX_POW_TAG_OP_SWTAG; - tag_req.s.tag = tag; - tag_req.s.type = tag_type; - - ptr.u64 = 0; - ptr.sio.mem_region = CVMX_IO_SEG; - ptr.sio.is_io = 1; - ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; - - /* once this store arrives at POW, it will attempt the switch - software must wait for the switch to complete separately */ - cvmx_write_io(ptr.u64, tag_req.u64); -} - -/** - * Starts a tag switch to the provided tag value and tag type. - * Completion for the tag switch must be checked for separately. This - * function does NOT update the work queue entry in dram to match tag - * value and type, so the application must keep track of these if they - * are important to the application. This tag switch command must not - * be used for switches to NULL, as the tag switch pending bit will be - * set by the switch request, but never cleared by the hardware. - * - * NOTE: This should not be used when switching from a NULL tag. Use - * cvmx_pow_tag_sw_full() instead. - * - * This function waits for any previous tag switch to complete, and also - * displays an error on tag switches to NULL. - * - * @tag: new tag value - * @tag_type: new tag type (ordered or atomic) - */ -static inline void cvmx_pow_tag_sw(uint32_t tag, - enum cvmx_pow_tag_type tag_type) -{ - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - /* - * Note that WQE in DRAM is not updated here, as the POW does - * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's - * responsibility to keep track of the current tag value if - * that is important. - */ - - /* - * Ensure that there is not a pending tag switch, as a tag - * switch cannot be started if a previous switch is still - * pending. - */ - cvmx_pow_tag_sw_wait(); - cvmx_pow_tag_sw_nocheck(tag, tag_type); -} - -/** - * Starts a tag switch to the provided tag value and tag type. - * Completion for the tag switch must be checked for separately. This - * function does NOT update the work queue entry in dram to match tag - * value and type, so the application must keep track of these if they - * are important to the application. This tag switch command must not - * be used for switches to NULL, as the tag switch pending bit will be - * set by the switch request, but never cleared by the hardware. - * - * This function must be used for tag switches from NULL. - * - * This function does no checks, so the caller must ensure that any - * previous tag switch has completed. - * - * @wqp: pointer to work queue entry to submit. This entry is - * updated to match the other parameters - * @tag: tag value to be assigned to work queue entry - * @tag_type: type of tag - * @group: group value for the work queue entry. - */ -static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag, - enum cvmx_pow_tag_type tag_type, - uint64_t group) -{ - cvmx_addr_t ptr; - cvmx_pow_tag_req_t tag_req; - - if (CVMX_ENABLE_POW_CHECKS) { - cvmx_pow_tag_req_t current_tag; - __cvmx_pow_warn_if_pending_switch(__func__); - current_tag = cvmx_pow_get_current_tag(); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) - pr_warning("%s called with NULL_NULL tag\n", - __func__); - if ((current_tag.s.type == tag_type) - && (current_tag.s.tag == tag)) - pr_warning("%s called to perform a tag switch to " - "the same tag\n", - __func__); - if (tag_type == CVMX_POW_TAG_TYPE_NULL) - pr_warning("%s called to perform a tag switch to " - "NULL. Use cvmx_pow_tag_sw_null() instead\n", - __func__); - if (wqp != cvmx_phys_to_ptr(0x80)) - if (wqp != cvmx_pow_get_current_wqp()) - pr_warning("%s passed WQE(%p) doesn't match " - "the address in the POW(%p)\n", - __func__, wqp, - cvmx_pow_get_current_wqp()); - } - - /* - * Note that WQE in DRAM is not updated here, as the POW does - * not read from DRAM once the WQE is in flight. See hardware - * manual for complete details. It is the application's - * responsibility to keep track of the current tag value if - * that is important. - */ - - tag_req.u64 = 0; - tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL; - tag_req.s.tag = tag; - tag_req.s.type = tag_type; - tag_req.s.grp = group; - - ptr.u64 = 0; - ptr.sio.mem_region = CVMX_IO_SEG; - ptr.sio.is_io = 1; - ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG; - ptr.sio.offset = CAST64(wqp); - - /* - * once this store arrives at POW, it will attempt the switch - * software must wait for the switch to complete separately. - */ - cvmx_write_io(ptr.u64, tag_req.u64); -} - -/** - * Starts a tag switch to the provided tag value and tag type. - * Completion for the tag switch must be checked for separately. This - * function does NOT update the work queue entry in dram to match tag - * value and type, so the application must keep track of these if they - * are important to the application. This tag switch command must not - * be used for switches to NULL, as the tag switch pending bit will be - * set by the switch request, but never cleared by the hardware. - * - * This function must be used for tag switches from NULL. - * - * This function waits for any pending tag switches to complete - * before requesting the tag switch. - * - * @wqp: pointer to work queue entry to submit. This entry is updated - * to match the other parameters - * @tag: tag value to be assigned to work queue entry - * @tag_type: type of tag - * @group: group value for the work queue entry. - */ -static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag, - enum cvmx_pow_tag_type tag_type, - uint64_t group) -{ - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - /* - * Ensure that there is not a pending tag switch, as a tag - * switch cannot be started if a previous switch is still - * pending. - */ - cvmx_pow_tag_sw_wait(); - cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group); -} - -/** - * Switch to a NULL tag, which ends any ordering or - * synchronization provided by the POW for the current - * work queue entry. This operation completes immediately, - * so completion should not be waited for. - * This function does NOT wait for previous tag switches to complete, - * so the caller must ensure that any previous tag switches have completed. - */ -static inline void cvmx_pow_tag_sw_null_nocheck(void) -{ - cvmx_addr_t ptr; - cvmx_pow_tag_req_t tag_req; - - if (CVMX_ENABLE_POW_CHECKS) { - cvmx_pow_tag_req_t current_tag; - __cvmx_pow_warn_if_pending_switch(__func__); - current_tag = cvmx_pow_get_current_tag(); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) - pr_warning("%s called with NULL_NULL tag\n", - __func__); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) - pr_warning("%s called when we already have a " - "NULL tag\n", - __func__); - } - - tag_req.u64 = 0; - tag_req.s.op = CVMX_POW_TAG_OP_SWTAG; - tag_req.s.type = CVMX_POW_TAG_TYPE_NULL; - - ptr.u64 = 0; - ptr.sio.mem_region = CVMX_IO_SEG; - ptr.sio.is_io = 1; - ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; - - cvmx_write_io(ptr.u64, tag_req.u64); - - /* switch to NULL completes immediately */ -} - -/** - * Switch to a NULL tag, which ends any ordering or - * synchronization provided by the POW for the current - * work queue entry. This operation completes immediately, - * so completion should not be waited for. - * This function waits for any pending tag switches to complete - * before requesting the switch to NULL. - */ -static inline void cvmx_pow_tag_sw_null(void) -{ - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - /* - * Ensure that there is not a pending tag switch, as a tag - * switch cannot be started if a previous switch is still - * pending. - */ - cvmx_pow_tag_sw_wait(); - cvmx_pow_tag_sw_null_nocheck(); - - /* switch to NULL completes immediately */ -} - -/** - * Submits work to an input queue. This function updates the work - * queue entry in DRAM to match the arguments given. Note that the - * tag provided is for the work queue entry submitted, and is - * unrelated to the tag that the core currently holds. - * - * @wqp: pointer to work queue entry to submit. This entry is - * updated to match the other parameters - * @tag: tag value to be assigned to work queue entry - * @tag_type: type of tag - * @qos: Input queue to add to. - * @grp: group value for the work queue entry. - */ -static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag, - enum cvmx_pow_tag_type tag_type, - uint64_t qos, uint64_t grp) -{ - cvmx_addr_t ptr; - cvmx_pow_tag_req_t tag_req; - - wqp->qos = qos; - wqp->tag = tag; - wqp->tag_type = tag_type; - wqp->grp = grp; - - tag_req.u64 = 0; - tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ; - tag_req.s.type = tag_type; - tag_req.s.tag = tag; - tag_req.s.qos = qos; - tag_req.s.grp = grp; - - ptr.u64 = 0; - ptr.sio.mem_region = CVMX_IO_SEG; - ptr.sio.is_io = 1; - ptr.sio.did = CVMX_OCT_DID_TAG_TAG1; - ptr.sio.offset = cvmx_ptr_to_phys(wqp); - - /* - * SYNC write to memory before the work submit. This is - * necessary as POW may read values from DRAM at this time. - */ - CVMX_SYNCWS; - cvmx_write_io(ptr.u64, tag_req.u64); -} - -/** - * This function sets the group mask for a core. The group mask - * indicates which groups each core will accept work from. There are - * 16 groups. - * - * @core_num: core to apply mask to - * @mask: Group mask. There are 16 groups, so only bits 0-15 are valid, - * representing groups 0-15. - * Each 1 bit in the mask enables the core to accept work from - * the corresponding group. - */ -static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask) -{ - union cvmx_pow_pp_grp_mskx grp_msk; - - grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); - grp_msk.s.grp_msk = mask; - cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); -} - -/** - * This function sets POW static priorities for a core. Each input queue has - * an associated priority value. - * - * @core_num: core to apply priorities to - * @priority: Vector of 8 priorities, one per POW Input Queue (0-7). - * Highest priority is 0 and lowest is 7. A priority value - * of 0xF instructs POW to skip the Input Queue when - * scheduling to this specific core. - * NOTE: priorities should not have gaps in values, meaning - * {0,1,1,1,1,1,1,1} is a valid configuration while - * {0,2,2,2,2,2,2,2} is not. - */ -static inline void cvmx_pow_set_priority(uint64_t core_num, - const uint8_t priority[]) -{ - /* POW priorities are supported on CN5xxx and later */ - if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { - union cvmx_pow_pp_grp_mskx grp_msk; - - grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num)); - grp_msk.s.qos0_pri = priority[0]; - grp_msk.s.qos1_pri = priority[1]; - grp_msk.s.qos2_pri = priority[2]; - grp_msk.s.qos3_pri = priority[3]; - grp_msk.s.qos4_pri = priority[4]; - grp_msk.s.qos5_pri = priority[5]; - grp_msk.s.qos6_pri = priority[6]; - grp_msk.s.qos7_pri = priority[7]; - - /* Detect gaps between priorities and flag error */ - { - int i; - uint32_t prio_mask = 0; - - for (i = 0; i < 8; i++) - if (priority[i] != 0xF) - prio_mask |= 1 << priority[i]; - - if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) { - pr_err("POW static priorities should be " - "contiguous (0x%llx)\n", - (unsigned long long)prio_mask); - return; - } - } - - cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64); - } -} - -/** - * Performs a tag switch and then an immediate deschedule. This completes - * immediately, so completion must not be waited for. This function does NOT - * update the wqe in DRAM to match arguments. - * - * This function does NOT wait for any prior tag switches to complete, so the - * calling code must do this. - * - * Note the following CAVEAT of the Octeon HW behavior when - * re-scheduling DE-SCHEDULEd items whose (next) state is - * ORDERED: - * - If there are no switches pending at the time that the - * HW executes the de-schedule, the HW will only re-schedule - * the head of the FIFO associated with the given tag. This - * means that in many respects, the HW treats this ORDERED - * tag as an ATOMIC tag. Note that in the SWTAG_DESCH - * case (to an ORDERED tag), the HW will do the switch - * before the deschedule whenever it is possible to do - * the switch immediately, so it may often look like - * this case. - * - If there is a pending switch to ORDERED at the time - * the HW executes the de-schedule, the HW will perform - * the switch at the time it re-schedules, and will be - * able to reschedule any/all of the entries with the - * same tag. - * Due to this behavior, the RECOMMENDATION to software is - * that they have a (next) state of ATOMIC when they - * DE-SCHEDULE. If an ORDERED tag is what was really desired, - * SW can choose to immediately switch to an ORDERED tag - * after the work (that has an ATOMIC tag) is re-scheduled. - * Note that since there are never any tag switches pending - * when the HW re-schedules, this switch can be IMMEDIATE upon - * the reception of the pointer during the re-schedule. - * - * @tag: New tag value - * @tag_type: New tag type - * @group: New group value - * @no_sched: Control whether this work queue entry will be rescheduled. - * - 1 : don't schedule this work - * - 0 : allow this work to be scheduled. - */ -static inline void cvmx_pow_tag_sw_desched_nocheck( - uint32_t tag, - enum cvmx_pow_tag_type tag_type, - uint64_t group, - uint64_t no_sched) -{ - cvmx_addr_t ptr; - cvmx_pow_tag_req_t tag_req; - - if (CVMX_ENABLE_POW_CHECKS) { - cvmx_pow_tag_req_t current_tag; - __cvmx_pow_warn_if_pending_switch(__func__); - current_tag = cvmx_pow_get_current_tag(); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) - pr_warning("%s called with NULL_NULL tag\n", - __func__); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) - pr_warning("%s called with NULL tag. Deschedule not " - "allowed from NULL state\n", - __func__); - if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC) - && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC)) - pr_warning("%s called where neither the before or " - "after tag is ATOMIC\n", - __func__); - } - - tag_req.u64 = 0; - tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH; - tag_req.s.tag = tag; - tag_req.s.type = tag_type; - tag_req.s.grp = group; - tag_req.s.no_sched = no_sched; - - ptr.u64 = 0; - ptr.sio.mem_region = CVMX_IO_SEG; - ptr.sio.is_io = 1; - ptr.sio.did = CVMX_OCT_DID_TAG_TAG3; - /* - * since TAG3 is used, this store will clear the local pending - * switch bit. - */ - cvmx_write_io(ptr.u64, tag_req.u64); -} - -/** - * Performs a tag switch and then an immediate deschedule. This completes - * immediately, so completion must not be waited for. This function does NOT - * update the wqe in DRAM to match arguments. - * - * This function waits for any prior tag switches to complete, so the - * calling code may call this function with a pending tag switch. - * - * Note the following CAVEAT of the Octeon HW behavior when - * re-scheduling DE-SCHEDULEd items whose (next) state is - * ORDERED: - * - If there are no switches pending at the time that the - * HW executes the de-schedule, the HW will only re-schedule - * the head of the FIFO associated with the given tag. This - * means that in many respects, the HW treats this ORDERED - * tag as an ATOMIC tag. Note that in the SWTAG_DESCH - * case (to an ORDERED tag), the HW will do the switch - * before the deschedule whenever it is possible to do - * the switch immediately, so it may often look like - * this case. - * - If there is a pending switch to ORDERED at the time - * the HW executes the de-schedule, the HW will perform - * the switch at the time it re-schedules, and will be - * able to reschedule any/all of the entries with the - * same tag. - * Due to this behavior, the RECOMMENDATION to software is - * that they have a (next) state of ATOMIC when they - * DE-SCHEDULE. If an ORDERED tag is what was really desired, - * SW can choose to immediately switch to an ORDERED tag - * after the work (that has an ATOMIC tag) is re-scheduled. - * Note that since there are never any tag switches pending - * when the HW re-schedules, this switch can be IMMEDIATE upon - * the reception of the pointer during the re-schedule. - * - * @tag: New tag value - * @tag_type: New tag type - * @group: New group value - * @no_sched: Control whether this work queue entry will be rescheduled. - * - 1 : don't schedule this work - * - 0 : allow this work to be scheduled. - */ -static inline void cvmx_pow_tag_sw_desched(uint32_t tag, - enum cvmx_pow_tag_type tag_type, - uint64_t group, uint64_t no_sched) -{ - if (CVMX_ENABLE_POW_CHECKS) - __cvmx_pow_warn_if_pending_switch(__func__); - - /* Need to make sure any writes to the work queue entry are complete */ - CVMX_SYNCWS; - /* - * Ensure that there is not a pending tag switch, as a tag - * switch cannot be started if a previous switch is still - * pending. - */ - cvmx_pow_tag_sw_wait(); - cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched); -} - -/** - * Descchedules the current work queue entry. - * - * @no_sched: no schedule flag value to be set on the work queue - * entry. If this is set the entry will not be - * rescheduled. - */ -static inline void cvmx_pow_desched(uint64_t no_sched) -{ - cvmx_addr_t ptr; - cvmx_pow_tag_req_t tag_req; - - if (CVMX_ENABLE_POW_CHECKS) { - cvmx_pow_tag_req_t current_tag; - __cvmx_pow_warn_if_pending_switch(__func__); - current_tag = cvmx_pow_get_current_tag(); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL) - pr_warning("%s called with NULL_NULL tag\n", - __func__); - if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL) - pr_warning("%s called with NULL tag. Deschedule not " - "expected from NULL state\n", - __func__); - } - - /* Need to make sure any writes to the work queue entry are complete */ - CVMX_SYNCWS; - - tag_req.u64 = 0; - tag_req.s.op = CVMX_POW_TAG_OP_DESCH; - tag_req.s.no_sched = no_sched; - - ptr.u64 = 0; - ptr.sio.mem_region = CVMX_IO_SEG; - ptr.sio.is_io = 1; - ptr.sio.did = CVMX_OCT_DID_TAG_TAG3; - /* - * since TAG3 is used, this store will clear the local pending - * switch bit. - */ - cvmx_write_io(ptr.u64, tag_req.u64); -} - -/**************************************************** -* Define usage of bits within the 32 bit tag values. -*****************************************************/ - -/* - * Number of bits of the tag used by software. The SW bits are always - * a contiguous block of the high starting at bit 31. The hardware - * bits are always the low bits. By default, the top 8 bits of the - * tag are reserved for software, and the low 24 are set by the IPD - * unit. - */ -#define CVMX_TAG_SW_BITS (8) -#define CVMX_TAG_SW_SHIFT (32 - CVMX_TAG_SW_BITS) - -/* Below is the list of values for the top 8 bits of the tag. */ -/* - * Tag values with top byte of this value are reserved for internal - * executive uses. - */ -#define CVMX_TAG_SW_BITS_INTERNAL 0x1 -/* The executive divides the remaining 24 bits as follows: - * - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup - * - * - the lower 16 bits (bits 15 - 0 of the tag) define are the value - * with the subgroup - * - * Note that this section describes the format of tags generated by - * software - refer to the hardware documentation for a description of - * the tags values generated by the packet input hardware. Subgroups - * are defined here. - */ -/* Mask for the value portion of the tag */ -#define CVMX_TAG_SUBGROUP_MASK 0xFFFF -#define CVMX_TAG_SUBGROUP_SHIFT 16 -#define CVMX_TAG_SUBGROUP_PKO 0x1 - -/* End of executive tag subgroup definitions */ - -/* - * The remaining values software bit values 0x2 - 0xff are available - * for application use. - */ - -/** - * This function creates a 32 bit tag value from the two values provided. - * - * @sw_bits: The upper bits (number depends on configuration) are set - * to this value. The remainder of bits are set by the - * hw_bits parameter. - * - * @hw_bits: The lower bits (number depends on configuration) are set - * to this value. The remainder of bits are set by the - * sw_bits parameter. - * - * Returns 32 bit value of the combined hw and sw bits. - */ -static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits) -{ - return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) << - CVMX_TAG_SW_SHIFT) | - (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS)); -} - -/** - * Extracts the bits allocated for software use from the tag - * - * @tag: 32 bit tag value - * - * Returns N bit software tag value, where N is configurable with the - * CVMX_TAG_SW_BITS define - */ -static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag) -{ - return (tag >> (32 - CVMX_TAG_SW_BITS)) & - cvmx_build_mask(CVMX_TAG_SW_BITS); -} - -/** - * - * Extracts the bits allocated for hardware use from the tag - * - * @tag: 32 bit tag value - * - * Returns (32 - N) bit software tag value, where N is configurable - * with the CVMX_TAG_SW_BITS define - */ -static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag) -{ - return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS); -} - -/** - * Store the current POW internal state into the supplied - * buffer. It is recommended that you pass a buffer of at least - * 128KB. The format of the capture may change based on SDK - * version and Octeon chip. - * - * @buffer: Buffer to store capture into - * @buffer_size: - * The size of the supplied buffer - * - * Returns Zero on success, negative on failure - */ -extern int cvmx_pow_capture(void *buffer, int buffer_size); - -/** - * Dump a POW capture to the console in a human readable format. - * - * @buffer: POW capture from cvmx_pow_capture() - * @buffer_size: - * Size of the buffer - */ -extern void cvmx_pow_display(void *buffer, int buffer_size); - -/** - * Return the number of POW entries supported by this chip - * - * Returns Number of POW entries - */ -extern int cvmx_pow_get_num_entries(void); - -#endif /* __CVMX_POW_H__ */ diff --git a/drivers/staging/octeon/cvmx-scratch.h b/drivers/staging/octeon/cvmx-scratch.h deleted file mode 100644 index 96b70cfd6245..000000000000 --- a/drivers/staging/octeon/cvmx-scratch.h +++ /dev/null @@ -1,139 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * This file provides support for the processor local scratch memory. - * Scratch memory is byte addressable - all addresses are byte addresses. - * - */ - -#ifndef __CVMX_SCRATCH_H__ -#define __CVMX_SCRATCH_H__ - -/* - * Note: This define must be a long, not a long long in order to - * compile without warnings for both 32bit and 64bit. - */ -#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */ - -/** - * Reads an 8 bit value from the processor local scratchpad memory. - * - * @address: byte address to read from - * - * Returns value read - */ -static inline uint8_t cvmx_scratch_read8(uint64_t address) -{ - return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address); -} - -/** - * Reads a 16 bit value from the processor local scratchpad memory. - * - * @address: byte address to read from - * - * Returns value read - */ -static inline uint16_t cvmx_scratch_read16(uint64_t address) -{ - return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address); -} - -/** - * Reads a 32 bit value from the processor local scratchpad memory. - * - * @address: byte address to read from - * - * Returns value read - */ -static inline uint32_t cvmx_scratch_read32(uint64_t address) -{ - return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address); -} - -/** - * Reads a 64 bit value from the processor local scratchpad memory. - * - * @address: byte address to read from - * - * Returns value read - */ -static inline uint64_t cvmx_scratch_read64(uint64_t address) -{ - return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address); -} - -/** - * Writes an 8 bit value to the processor local scratchpad memory. - * - * @address: byte address to write to - * @value: value to write - */ -static inline void cvmx_scratch_write8(uint64_t address, uint64_t value) -{ - *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) = - (uint8_t) value; -} - -/** - * Writes a 32 bit value to the processor local scratchpad memory. - * - * @address: byte address to write to - * @value: value to write - */ -static inline void cvmx_scratch_write16(uint64_t address, uint64_t value) -{ - *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) = - (uint16_t) value; -} - -/** - * Writes a 16 bit value to the processor local scratchpad memory. - * - * @address: byte address to write to - * @value: value to write - */ -static inline void cvmx_scratch_write32(uint64_t address, uint64_t value) -{ - *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) = - (uint32_t) value; -} - -/** - * Writes a 64 bit value to the processor local scratchpad memory. - * - * @address: byte address to write to - * @value: value to write - */ -static inline void cvmx_scratch_write64(uint64_t address, uint64_t value) -{ - *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value; -} - -#endif /* __CVMX_SCRATCH_H__ */ diff --git a/drivers/staging/octeon/cvmx-smix-defs.h b/drivers/staging/octeon/cvmx-smix-defs.h deleted file mode 100644 index 9ae45fcbe3e3..000000000000 --- a/drivers/staging/octeon/cvmx-smix-defs.h +++ /dev/null @@ -1,178 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_SMIX_DEFS_H__ -#define __CVMX_SMIX_DEFS_H__ - -#define CVMX_SMIX_CLK(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_CMD(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_EN(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_RD_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_WR_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256)) - -union cvmx_smix_clk { - uint64_t u64; - struct cvmx_smix_clk_s { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t sample_mode:1; - uint64_t reserved_14_14:1; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } s; - struct cvmx_smix_clk_cn30xx { - uint64_t reserved_21_63:43; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn30xx; - struct cvmx_smix_clk_cn30xx cn31xx; - struct cvmx_smix_clk_cn30xx cn38xx; - struct cvmx_smix_clk_cn30xx cn38xxp2; - struct cvmx_smix_clk_cn50xx { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn50xx; - struct cvmx_smix_clk_s cn52xx; - struct cvmx_smix_clk_cn50xx cn52xxp1; - struct cvmx_smix_clk_s cn56xx; - struct cvmx_smix_clk_cn50xx cn56xxp1; - struct cvmx_smix_clk_cn30xx cn58xx; - struct cvmx_smix_clk_cn30xx cn58xxp1; -}; - -union cvmx_smix_cmd { - uint64_t u64; - struct cvmx_smix_cmd_s { - uint64_t reserved_18_63:46; - uint64_t phy_op:2; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } s; - struct cvmx_smix_cmd_cn30xx { - uint64_t reserved_17_63:47; - uint64_t phy_op:1; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } cn30xx; - struct cvmx_smix_cmd_cn30xx cn31xx; - struct cvmx_smix_cmd_cn30xx cn38xx; - struct cvmx_smix_cmd_cn30xx cn38xxp2; - struct cvmx_smix_cmd_s cn50xx; - struct cvmx_smix_cmd_s cn52xx; - struct cvmx_smix_cmd_s cn52xxp1; - struct cvmx_smix_cmd_s cn56xx; - struct cvmx_smix_cmd_s cn56xxp1; - struct cvmx_smix_cmd_cn30xx cn58xx; - struct cvmx_smix_cmd_cn30xx cn58xxp1; -}; - -union cvmx_smix_en { - uint64_t u64; - struct cvmx_smix_en_s { - uint64_t reserved_1_63:63; - uint64_t en:1; - } s; - struct cvmx_smix_en_s cn30xx; - struct cvmx_smix_en_s cn31xx; - struct cvmx_smix_en_s cn38xx; - struct cvmx_smix_en_s cn38xxp2; - struct cvmx_smix_en_s cn50xx; - struct cvmx_smix_en_s cn52xx; - struct cvmx_smix_en_s cn52xxp1; - struct cvmx_smix_en_s cn56xx; - struct cvmx_smix_en_s cn56xxp1; - struct cvmx_smix_en_s cn58xx; - struct cvmx_smix_en_s cn58xxp1; -}; - -union cvmx_smix_rd_dat { - uint64_t u64; - struct cvmx_smix_rd_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_rd_dat_s cn30xx; - struct cvmx_smix_rd_dat_s cn31xx; - struct cvmx_smix_rd_dat_s cn38xx; - struct cvmx_smix_rd_dat_s cn38xxp2; - struct cvmx_smix_rd_dat_s cn50xx; - struct cvmx_smix_rd_dat_s cn52xx; - struct cvmx_smix_rd_dat_s cn52xxp1; - struct cvmx_smix_rd_dat_s cn56xx; - struct cvmx_smix_rd_dat_s cn56xxp1; - struct cvmx_smix_rd_dat_s cn58xx; - struct cvmx_smix_rd_dat_s cn58xxp1; -}; - -union cvmx_smix_wr_dat { - uint64_t u64; - struct cvmx_smix_wr_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_wr_dat_s cn30xx; - struct cvmx_smix_wr_dat_s cn31xx; - struct cvmx_smix_wr_dat_s cn38xx; - struct cvmx_smix_wr_dat_s cn38xxp2; - struct cvmx_smix_wr_dat_s cn50xx; - struct cvmx_smix_wr_dat_s cn52xx; - struct cvmx_smix_wr_dat_s cn52xxp1; - struct cvmx_smix_wr_dat_s cn56xx; - struct cvmx_smix_wr_dat_s cn56xxp1; - struct cvmx_smix_wr_dat_s cn58xx; - struct cvmx_smix_wr_dat_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-spi.c b/drivers/staging/octeon/cvmx-spi.c deleted file mode 100644 index 82794d920cec..000000000000 --- a/drivers/staging/octeon/cvmx-spi.c +++ /dev/null @@ -1,667 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * Support library for the SPI - */ -#include - -#include "cvmx-config.h" - -#include "cvmx-pko.h" -#include "cvmx-spi.h" - -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" -#include "cvmx-srxx-defs.h" - -#define INVOKE_CB(function_p, args...) \ - do { \ - if (function_p) { \ - res = function_p(args); \ - if (res) \ - return res; \ - } \ - } while (0) - -#if CVMX_ENABLE_DEBUG_PRINTS -static const char *modes[] = - { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" }; -#endif - -/* Default callbacks, can be overridden - * using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks - */ -static cvmx_spi_callbacks_t cvmx_spi_callbacks = { - .reset_cb = cvmx_spi_reset_cb, - .calendar_setup_cb = cvmx_spi_calendar_setup_cb, - .clock_detect_cb = cvmx_spi_clock_detect_cb, - .training_cb = cvmx_spi_training_cb, - .calendar_sync_cb = cvmx_spi_calendar_sync_cb, - .interface_up_cb = cvmx_spi_interface_up_cb -}; - -/** - * Get current SPI4 initialization callbacks - * - * @callbacks: Pointer to the callbacks structure.to fill - * - * Returns Pointer to cvmx_spi_callbacks_t structure. - */ -void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks) -{ - memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks)); -} - -/** - * Set new SPI4 initialization callbacks - * - * @new_callbacks: Pointer to an updated callbacks structure. - */ -void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks) -{ - memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks)); -} - -/** - * Initialize and start the SPI interface. - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * @num_ports: Number of SPI ports to configure - * - * Returns Zero on success, negative of failure. - */ -int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, - int num_ports) -{ - int res = -1; - - if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) - return res; - - /* Callback to perform SPI4 reset */ - INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); - - /* Callback to perform calendar setup */ - INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode, - num_ports); - - /* Callback to perform clock detection */ - INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); - - /* Callback to perform SPI4 link training */ - INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); - - /* Callback to perform calendar sync */ - INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, - timeout); - - /* Callback to handle interface coming up */ - INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); - - return res; -} - -/** - * This routine restarts the SPI interface after it has lost synchronization - * with its correspondent system. - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * - * Returns Zero on success, negative of failure. - */ -int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout) -{ - int res = -1; - - if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) - return res; - - cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]); - - /* Callback to perform SPI4 reset */ - INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); - - /* NOTE: Calendar setup is not performed during restart */ - /* Refer to cvmx_spi_start_interface() for the full sequence */ - - /* Callback to perform clock detection */ - INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); - - /* Callback to perform SPI4 link training */ - INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); - - /* Callback to perform calendar sync */ - INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, - timeout); - - /* Callback to handle interface coming up */ - INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); - - return res; -} - -/** - * Callback to perform SPI4 reset - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) -{ - union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl; - union cvmx_spxx_clk_ctl spxx_clk_ctl; - union cvmx_spxx_bist_stat spxx_bist_stat; - union cvmx_spxx_int_msk spxx_int_msk; - union cvmx_stxx_int_msk stxx_int_msk; - union cvmx_spxx_trn4_ctl spxx_trn4_ctl; - int index; - uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; - - /* Disable SPI error events while we run BIST */ - spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); - cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); - stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); - cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); - - /* Run BIST in the SPI interface */ - cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); - cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); - spxx_clk_ctl.u64 = 0; - spxx_clk_ctl.s.runbist = 1; - cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); - cvmx_wait(10 * MS); - spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface)); - if (spxx_bist_stat.s.stat0) - cvmx_dprintf - ("ERROR SPI%d: BIST failed on receive datapath FIFO\n", - interface); - if (spxx_bist_stat.s.stat1) - cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n", - interface); - if (spxx_bist_stat.s.stat2) - cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n", - interface); - - /* Clear the calendar table after BIST to fix parity errors */ - for (index = 0; index < 32; index++) { - union cvmx_srxx_spi4_calx srxx_spi4_calx; - union cvmx_stxx_spi4_calx stxx_spi4_calx; - - srxx_spi4_calx.u64 = 0; - srxx_spi4_calx.s.oddpar = 1; - cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), - srxx_spi4_calx.u64); - - stxx_spi4_calx.u64 = 0; - stxx_spi4_calx.s.oddpar = 1; - cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), - stxx_spi4_calx.u64); - } - - /* Re enable reporting of error interrupts */ - cvmx_write_csr(CVMX_SPXX_INT_REG(interface), - cvmx_read_csr(CVMX_SPXX_INT_REG(interface))); - cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); - cvmx_write_csr(CVMX_STXX_INT_REG(interface), - cvmx_read_csr(CVMX_STXX_INT_REG(interface))); - cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); - - /* Setup the CLKDLY right in the middle */ - spxx_clk_ctl.u64 = 0; - spxx_clk_ctl.s.seetrn = 0; - spxx_clk_ctl.s.clkdly = 0x10; - spxx_clk_ctl.s.runbist = 0; - spxx_clk_ctl.s.statdrv = 0; - /* This should always be on the opposite edge as statdrv */ - spxx_clk_ctl.s.statrcv = 1; - spxx_clk_ctl.s.sndtrn = 0; - spxx_clk_ctl.s.drptrn = 0; - spxx_clk_ctl.s.rcvtrn = 0; - spxx_clk_ctl.s.srxdlck = 0; - cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); - cvmx_wait(100 * MS); - - /* Reset SRX0 DLL */ - spxx_clk_ctl.s.srxdlck = 1; - cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); - - /* Waiting for Inf0 Spi4 RX DLL to lock */ - cvmx_wait(100 * MS); - - /* Enable dynamic alignment */ - spxx_trn4_ctl.s.trntest = 0; - spxx_trn4_ctl.s.jitter = 1; - spxx_trn4_ctl.s.clr_boot = 1; - spxx_trn4_ctl.s.set_boot = 0; - if (OCTEON_IS_MODEL(OCTEON_CN58XX)) - spxx_trn4_ctl.s.maxdist = 3; - else - spxx_trn4_ctl.s.maxdist = 8; - spxx_trn4_ctl.s.macro_en = 1; - spxx_trn4_ctl.s.mux_en = 1; - cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); - - spxx_dbg_deskew_ctl.u64 = 0; - cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface), - spxx_dbg_deskew_ctl.u64); - - return 0; -} - -/** - * Callback to setup calendar and miscellaneous settings before clock detection - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @num_ports: Number of ports to configure on SPI - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, - int num_ports) -{ - int port; - int index; - if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { - union cvmx_srxx_com_ctl srxx_com_ctl; - union cvmx_srxx_spi4_stat srxx_spi4_stat; - - /* SRX0 number of Ports */ - srxx_com_ctl.u64 = 0; - srxx_com_ctl.s.prts = num_ports - 1; - srxx_com_ctl.s.st_en = 0; - srxx_com_ctl.s.inf_en = 0; - cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); - - /* SRX0 Calendar Table. This round robbins through all ports */ - port = 0; - index = 0; - while (port < num_ports) { - union cvmx_srxx_spi4_calx srxx_spi4_calx; - srxx_spi4_calx.u64 = 0; - srxx_spi4_calx.s.prt0 = port++; - srxx_spi4_calx.s.prt1 = port++; - srxx_spi4_calx.s.prt2 = port++; - srxx_spi4_calx.s.prt3 = port++; - srxx_spi4_calx.s.oddpar = - ~(cvmx_dpop(srxx_spi4_calx.u64) & 1); - cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), - srxx_spi4_calx.u64); - index++; - } - srxx_spi4_stat.u64 = 0; - srxx_spi4_stat.s.len = num_ports; - srxx_spi4_stat.s.m = 1; - cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface), - srxx_spi4_stat.u64); - } - - if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { - union cvmx_stxx_arb_ctl stxx_arb_ctl; - union cvmx_gmxx_tx_spi_max gmxx_tx_spi_max; - union cvmx_gmxx_tx_spi_thresh gmxx_tx_spi_thresh; - union cvmx_gmxx_tx_spi_ctl gmxx_tx_spi_ctl; - union cvmx_stxx_spi4_stat stxx_spi4_stat; - union cvmx_stxx_spi4_dat stxx_spi4_dat; - - /* STX0 Config */ - stxx_arb_ctl.u64 = 0; - stxx_arb_ctl.s.igntpa = 0; - stxx_arb_ctl.s.mintrn = 0; - cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64); - - gmxx_tx_spi_max.u64 = 0; - gmxx_tx_spi_max.s.max1 = 8; - gmxx_tx_spi_max.s.max2 = 4; - gmxx_tx_spi_max.s.slice = 0; - cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface), - gmxx_tx_spi_max.u64); - - gmxx_tx_spi_thresh.u64 = 0; - gmxx_tx_spi_thresh.s.thresh = 4; - cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface), - gmxx_tx_spi_thresh.u64); - - gmxx_tx_spi_ctl.u64 = 0; - gmxx_tx_spi_ctl.s.tpa_clr = 0; - gmxx_tx_spi_ctl.s.cont_pkt = 0; - cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface), - gmxx_tx_spi_ctl.u64); - - /* STX0 Training Control */ - stxx_spi4_dat.u64 = 0; - /*Minimum needed by dynamic alignment */ - stxx_spi4_dat.s.alpha = 32; - stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */ - cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), - stxx_spi4_dat.u64); - - /* STX0 Calendar Table. This round robbins through all ports */ - port = 0; - index = 0; - while (port < num_ports) { - union cvmx_stxx_spi4_calx stxx_spi4_calx; - stxx_spi4_calx.u64 = 0; - stxx_spi4_calx.s.prt0 = port++; - stxx_spi4_calx.s.prt1 = port++; - stxx_spi4_calx.s.prt2 = port++; - stxx_spi4_calx.s.prt3 = port++; - stxx_spi4_calx.s.oddpar = - ~(cvmx_dpop(stxx_spi4_calx.u64) & 1); - cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), - stxx_spi4_calx.u64); - index++; - } - stxx_spi4_stat.u64 = 0; - stxx_spi4_stat.s.len = num_ports; - stxx_spi4_stat.s.m = 1; - cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface), - stxx_spi4_stat.u64); - } - - return 0; -} - -/** - * Callback to perform clock detection - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout) -{ - int clock_transitions; - union cvmx_spxx_clk_stat stat; - uint64_t timeout_time; - uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; - - /* - * Regardless of operating mode, both Tx and Rx clocks must be - * present for the SPI interface to operate. - */ - cvmx_dprintf("SPI%d: Waiting to see TsClk...\n", interface); - timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; - /* - * Require 100 clock transitions in order to avoid any noise - * in the beginning. - */ - clock_transitions = 100; - do { - stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); - if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) { - /* - * We've seen a clock transition, so decrement - * the number we still need. - */ - clock_transitions--; - cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); - stat.s.s4clk0 = 0; - stat.s.s4clk1 = 0; - } - if (cvmx_get_cycle() > timeout_time) { - cvmx_dprintf("SPI%d: Timeout\n", interface); - return -1; - } - } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0); - - cvmx_dprintf("SPI%d: Waiting to see RsClk...\n", interface); - timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; - /* - * Require 100 clock transitions in order to avoid any noise in the - * beginning. - */ - clock_transitions = 100; - do { - stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); - if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) { - /* - * We've seen a clock transition, so decrement - * the number we still need - */ - clock_transitions--; - cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); - stat.s.d4clk0 = 0; - stat.s.d4clk1 = 0; - } - if (cvmx_get_cycle() > timeout_time) { - cvmx_dprintf("SPI%d: Timeout\n", interface); - return -1; - } - } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0); - - return 0; -} - -/** - * Callback to perform link training - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for link to be trained (in seconds) - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) -{ - union cvmx_spxx_trn4_ctl spxx_trn4_ctl; - union cvmx_spxx_clk_stat stat; - uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; - uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; - int rx_training_needed; - - /* SRX0 & STX0 Inf0 Links are configured - begin training */ - union cvmx_spxx_clk_ctl spxx_clk_ctl; - spxx_clk_ctl.u64 = 0; - spxx_clk_ctl.s.seetrn = 0; - spxx_clk_ctl.s.clkdly = 0x10; - spxx_clk_ctl.s.runbist = 0; - spxx_clk_ctl.s.statdrv = 0; - /* This should always be on the opposite edge as statdrv */ - spxx_clk_ctl.s.statrcv = 1; - spxx_clk_ctl.s.sndtrn = 1; - spxx_clk_ctl.s.drptrn = 1; - spxx_clk_ctl.s.rcvtrn = 1; - spxx_clk_ctl.s.srxdlck = 1; - cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); - cvmx_wait(1000 * MS); - - /* SRX0 clear the boot bit */ - spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface)); - spxx_trn4_ctl.s.clr_boot = 1; - cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); - - /* Wait for the training sequence to complete */ - cvmx_dprintf("SPI%d: Waiting for training\n", interface); - cvmx_wait(1000 * MS); - /* Wait a really long time here */ - timeout_time = cvmx_get_cycle() + 1000ull * MS * 600; - /* - * The HRM says we must wait for 34 + 16 * MAXDIST training sequences. - * We'll be pessimistic and wait for a lot more. - */ - rx_training_needed = 500; - do { - stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); - if (stat.s.srxtrn && rx_training_needed) { - rx_training_needed--; - cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); - stat.s.srxtrn = 0; - } - if (cvmx_get_cycle() > timeout_time) { - cvmx_dprintf("SPI%d: Timeout\n", interface); - return -1; - } - } while (stat.s.srxtrn == 0); - - return 0; -} - -/** - * Callback to perform calendar data synchronization - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for calendar data in seconds - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout) -{ - uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; - if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { - /* SRX0 interface should be good, send calendar data */ - union cvmx_srxx_com_ctl srxx_com_ctl; - cvmx_dprintf - ("SPI%d: Rx is synchronized, start sending calendar data\n", - interface); - srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); - srxx_com_ctl.s.inf_en = 1; - srxx_com_ctl.s.st_en = 1; - cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); - } - - if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { - /* STX0 has achieved sync */ - /* The corespondant board should be sending calendar data */ - /* Enable the STX0 STAT receiver. */ - union cvmx_spxx_clk_stat stat; - uint64_t timeout_time; - union cvmx_stxx_com_ctl stxx_com_ctl; - stxx_com_ctl.u64 = 0; - stxx_com_ctl.s.st_en = 1; - cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); - - /* Waiting for calendar sync on STX0 STAT */ - cvmx_dprintf("SPI%d: Waiting to sync on STX[%d] STAT\n", - interface, interface); - timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; - /* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */ - do { - stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); - if (cvmx_get_cycle() > timeout_time) { - cvmx_dprintf("SPI%d: Timeout\n", interface); - return -1; - } - } while (stat.s.stxcal == 0); - } - - return 0; -} - -/** - * Callback to handle interface up - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode) -{ - union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min; - union cvmx_gmxx_rxx_frm_max gmxx_rxx_frm_max; - union cvmx_gmxx_rxx_jabber gmxx_rxx_jabber; - - if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { - union cvmx_srxx_com_ctl srxx_com_ctl; - srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); - srxx_com_ctl.s.inf_en = 1; - cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); - cvmx_dprintf("SPI%d: Rx is now up\n", interface); - } - - if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { - union cvmx_stxx_com_ctl stxx_com_ctl; - stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface)); - stxx_com_ctl.s.inf_en = 1; - cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); - cvmx_dprintf("SPI%d: Tx is now up\n", interface); - } - - gmxx_rxx_frm_min.u64 = 0; - gmxx_rxx_frm_min.s.len = 64; - cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface), - gmxx_rxx_frm_min.u64); - gmxx_rxx_frm_max.u64 = 0; - gmxx_rxx_frm_max.s.len = 64 * 1024 - 4; - cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface), - gmxx_rxx_frm_max.u64); - gmxx_rxx_jabber.u64 = 0; - gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4; - cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64); - - return 0; -} diff --git a/drivers/staging/octeon/cvmx-spi.h b/drivers/staging/octeon/cvmx-spi.h deleted file mode 100644 index e814648953a5..000000000000 --- a/drivers/staging/octeon/cvmx-spi.h +++ /dev/null @@ -1,269 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/* - * - * This file contains defines for the SPI interface - */ -#ifndef __CVMX_SPI_H__ -#define __CVMX_SPI_H__ - -#include "cvmx-gmxx-defs.h" - -/* CSR typedefs have been moved to cvmx-csr-*.h */ - -typedef enum { - CVMX_SPI_MODE_UNKNOWN = 0, - CVMX_SPI_MODE_TX_HALFPLEX = 1, - CVMX_SPI_MODE_RX_HALFPLEX = 2, - CVMX_SPI_MODE_DUPLEX = 3 -} cvmx_spi_mode_t; - -/** Callbacks structure to customize SPI4 initialization sequence */ -typedef struct { - /** Called to reset SPI4 DLL */ - int (*reset_cb) (int interface, cvmx_spi_mode_t mode); - - /** Called to setup calendar */ - int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode, - int num_ports); - - /** Called for Tx and Rx clock detection */ - int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode, - int timeout); - - /** Called to perform link training */ - int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout); - - /** Called for calendar data synchronization */ - int (*calendar_sync_cb) (int interface, cvmx_spi_mode_t mode, - int timeout); - - /** Called when interface is up */ - int (*interface_up_cb) (int interface, cvmx_spi_mode_t mode); - -} cvmx_spi_callbacks_t; - -/** - * Return true if the supplied interface is configured for SPI - * - * @interface: Interface to check - * Returns True if interface is SPI - */ -static inline int cvmx_spi_is_spi_interface(int interface) -{ - uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); - return (gmxState & 0x2) && (gmxState & 0x1); -} - -/** - * Initialize and start the SPI interface. - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * @num_ports: Number of SPI ports to configure - * - * Returns Zero on success, negative of failure. - */ -extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, - int timeout, int num_ports); - -/** - * This routine restarts the SPI interface after it has lost synchronization - * with its corespondant system. - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * Returns Zero on success, negative of failure. - */ -extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, - int timeout); - -/** - * Return non-zero if the SPI interface has a SPI4000 attached - * - * @interface: SPI interface the SPI4000 is connected to - * - * Returns - */ -static inline int cvmx_spi4000_is_present(int interface) -{ - return 0; -} - -/** - * Initialize the SPI4000 for use - * - * @interface: SPI interface the SPI4000 is connected to - */ -static inline int cvmx_spi4000_initialize(int interface) -{ - return 0; -} - -/** - * Poll all the SPI4000 port and check its speed - * - * @interface: Interface the SPI4000 is on - * @port: Port to poll (0-9) - * Returns Status of the port. 0=down. All other values the port is up. - */ -static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed( - int interface, - int port) -{ - union cvmx_gmxx_rxx_rx_inbnd r; - r.u64 = 0; - return r; -} - -/** - * Get current SPI4 initialization callbacks - * - * @callbacks: Pointer to the callbacks structure.to fill - * - * Returns Pointer to cvmx_spi_callbacks_t structure. - */ -extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks); - -/** - * Set new SPI4 initialization callbacks - * - * @new_callbacks: Pointer to an updated callbacks structure. - */ -extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks); - -/** - * Callback to perform SPI4 reset - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode); - -/** - * Callback to setup calendar and miscellaneous settings before clock - * detection - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @num_ports: Number of ports to configure on SPI - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, - int num_ports); - -/** - * Callback to perform clock detection - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for clock synchronization in seconds - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, - int timeout); - -/** - * Callback to perform link training - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for link to be trained (in seconds) - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, - int timeout); - -/** - * Callback to perform calendar data synchronization - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * @timeout: Timeout to wait for calendar data in seconds - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, - int timeout); - -/** - * Callback to handle interface up - * - * @interface: The identifier of the packet interface to configure and - * use as a SPI interface. - * @mode: The operating mode for the SPI interface. The interface - * can operate as a full duplex (both Tx and Rx data paths - * active) or as a halfplex (either the Tx data path is - * active or the Rx data path is active, but not both). - * - * Returns Zero on success, non-zero error code on failure (will cause - * SPI initialization to abort) - */ -extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode); - -#endif /* __CVMX_SPI_H__ */ diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/drivers/staging/octeon/cvmx-spxx-defs.h deleted file mode 100644 index b16940e32c83..000000000000 --- a/drivers/staging/octeon/cvmx-spxx-defs.h +++ /dev/null @@ -1,347 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_SPXX_DEFS_H__ -#define __CVMX_SPXX_DEFS_H__ - -#define CVMX_SPXX_BCKPRS_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_BIST_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_CLK_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_CLK_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_DRV_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_ERR_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_INT_SYNC(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_ACC(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_MAX(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TPA_SEL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SPXX_TRN4_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull)) - -union cvmx_spxx_bckprs_cnt { - uint64_t u64; - struct cvmx_spxx_bckprs_cnt_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_spxx_bckprs_cnt_s cn38xx; - struct cvmx_spxx_bckprs_cnt_s cn38xxp2; - struct cvmx_spxx_bckprs_cnt_s cn58xx; - struct cvmx_spxx_bckprs_cnt_s cn58xxp1; -}; - -union cvmx_spxx_bist_stat { - uint64_t u64; - struct cvmx_spxx_bist_stat_s { - uint64_t reserved_3_63:61; - uint64_t stat2:1; - uint64_t stat1:1; - uint64_t stat0:1; - } s; - struct cvmx_spxx_bist_stat_s cn38xx; - struct cvmx_spxx_bist_stat_s cn38xxp2; - struct cvmx_spxx_bist_stat_s cn58xx; - struct cvmx_spxx_bist_stat_s cn58xxp1; -}; - -union cvmx_spxx_clk_ctl { - uint64_t u64; - struct cvmx_spxx_clk_ctl_s { - uint64_t reserved_17_63:47; - uint64_t seetrn:1; - uint64_t reserved_12_15:4; - uint64_t clkdly:5; - uint64_t runbist:1; - uint64_t statdrv:1; - uint64_t statrcv:1; - uint64_t sndtrn:1; - uint64_t drptrn:1; - uint64_t rcvtrn:1; - uint64_t srxdlck:1; - } s; - struct cvmx_spxx_clk_ctl_s cn38xx; - struct cvmx_spxx_clk_ctl_s cn38xxp2; - struct cvmx_spxx_clk_ctl_s cn58xx; - struct cvmx_spxx_clk_ctl_s cn58xxp1; -}; - -union cvmx_spxx_clk_stat { - uint64_t u64; - struct cvmx_spxx_clk_stat_s { - uint64_t reserved_11_63:53; - uint64_t stxcal:1; - uint64_t reserved_9_9:1; - uint64_t srxtrn:1; - uint64_t s4clk1:1; - uint64_t s4clk0:1; - uint64_t d4clk1:1; - uint64_t d4clk0:1; - uint64_t reserved_0_3:4; - } s; - struct cvmx_spxx_clk_stat_s cn38xx; - struct cvmx_spxx_clk_stat_s cn38xxp2; - struct cvmx_spxx_clk_stat_s cn58xx; - struct cvmx_spxx_clk_stat_s cn58xxp1; -}; - -union cvmx_spxx_dbg_deskew_ctl { - uint64_t u64; - struct cvmx_spxx_dbg_deskew_ctl_s { - uint64_t reserved_30_63:34; - uint64_t fallnop:1; - uint64_t fall8:1; - uint64_t reserved_26_27:2; - uint64_t sstep_go:1; - uint64_t sstep:1; - uint64_t reserved_22_23:2; - uint64_t clrdly:1; - uint64_t dec:1; - uint64_t inc:1; - uint64_t mux:1; - uint64_t offset:5; - uint64_t bitsel:5; - uint64_t offdly:6; - uint64_t dllfrc:1; - uint64_t dlldis:1; - } s; - struct cvmx_spxx_dbg_deskew_ctl_s cn38xx; - struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2; - struct cvmx_spxx_dbg_deskew_ctl_s cn58xx; - struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1; -}; - -union cvmx_spxx_dbg_deskew_state { - uint64_t u64; - struct cvmx_spxx_dbg_deskew_state_s { - uint64_t reserved_9_63:55; - uint64_t testres:1; - uint64_t unxterm:1; - uint64_t muxsel:2; - uint64_t offset:5; - } s; - struct cvmx_spxx_dbg_deskew_state_s cn38xx; - struct cvmx_spxx_dbg_deskew_state_s cn38xxp2; - struct cvmx_spxx_dbg_deskew_state_s cn58xx; - struct cvmx_spxx_dbg_deskew_state_s cn58xxp1; -}; - -union cvmx_spxx_drv_ctl { - uint64_t u64; - struct cvmx_spxx_drv_ctl_s { - uint64_t reserved_0_63:64; - } s; - struct cvmx_spxx_drv_ctl_cn38xx { - uint64_t reserved_16_63:48; - uint64_t stx4ncmp:4; - uint64_t stx4pcmp:4; - uint64_t srx4cmp:8; - } cn38xx; - struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2; - struct cvmx_spxx_drv_ctl_cn58xx { - uint64_t reserved_24_63:40; - uint64_t stx4ncmp:4; - uint64_t stx4pcmp:4; - uint64_t reserved_10_15:6; - uint64_t srx4cmp:10; - } cn58xx; - struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1; -}; - -union cvmx_spxx_err_ctl { - uint64_t u64; - struct cvmx_spxx_err_ctl_s { - uint64_t reserved_9_63:55; - uint64_t prtnxa:1; - uint64_t dipcls:1; - uint64_t dippay:1; - uint64_t reserved_4_5:2; - uint64_t errcnt:4; - } s; - struct cvmx_spxx_err_ctl_s cn38xx; - struct cvmx_spxx_err_ctl_s cn38xxp2; - struct cvmx_spxx_err_ctl_s cn58xx; - struct cvmx_spxx_err_ctl_s cn58xxp1; -}; - -union cvmx_spxx_int_dat { - uint64_t u64; - struct cvmx_spxx_int_dat_s { - uint64_t reserved_32_63:32; - uint64_t mul:1; - uint64_t reserved_14_30:17; - uint64_t calbnk:2; - uint64_t rsvop:4; - uint64_t prt:8; - } s; - struct cvmx_spxx_int_dat_s cn38xx; - struct cvmx_spxx_int_dat_s cn38xxp2; - struct cvmx_spxx_int_dat_s cn58xx; - struct cvmx_spxx_int_dat_s cn58xxp1; -}; - -union cvmx_spxx_int_msk { - uint64_t u64; - struct cvmx_spxx_int_msk_s { - uint64_t reserved_12_63:52; - uint64_t calerr:1; - uint64_t syncerr:1; - uint64_t diperr:1; - uint64_t tpaovr:1; - uint64_t rsverr:1; - uint64_t drwnng:1; - uint64_t clserr:1; - uint64_t spiovr:1; - uint64_t reserved_2_3:2; - uint64_t abnorm:1; - uint64_t prtnxa:1; - } s; - struct cvmx_spxx_int_msk_s cn38xx; - struct cvmx_spxx_int_msk_s cn38xxp2; - struct cvmx_spxx_int_msk_s cn58xx; - struct cvmx_spxx_int_msk_s cn58xxp1; -}; - -union cvmx_spxx_int_reg { - uint64_t u64; - struct cvmx_spxx_int_reg_s { - uint64_t reserved_32_63:32; - uint64_t spf:1; - uint64_t reserved_12_30:19; - uint64_t calerr:1; - uint64_t syncerr:1; - uint64_t diperr:1; - uint64_t tpaovr:1; - uint64_t rsverr:1; - uint64_t drwnng:1; - uint64_t clserr:1; - uint64_t spiovr:1; - uint64_t reserved_2_3:2; - uint64_t abnorm:1; - uint64_t prtnxa:1; - } s; - struct cvmx_spxx_int_reg_s cn38xx; - struct cvmx_spxx_int_reg_s cn38xxp2; - struct cvmx_spxx_int_reg_s cn58xx; - struct cvmx_spxx_int_reg_s cn58xxp1; -}; - -union cvmx_spxx_int_sync { - uint64_t u64; - struct cvmx_spxx_int_sync_s { - uint64_t reserved_12_63:52; - uint64_t calerr:1; - uint64_t syncerr:1; - uint64_t diperr:1; - uint64_t tpaovr:1; - uint64_t rsverr:1; - uint64_t drwnng:1; - uint64_t clserr:1; - uint64_t spiovr:1; - uint64_t reserved_2_3:2; - uint64_t abnorm:1; - uint64_t prtnxa:1; - } s; - struct cvmx_spxx_int_sync_s cn38xx; - struct cvmx_spxx_int_sync_s cn38xxp2; - struct cvmx_spxx_int_sync_s cn58xx; - struct cvmx_spxx_int_sync_s cn58xxp1; -}; - -union cvmx_spxx_tpa_acc { - uint64_t u64; - struct cvmx_spxx_tpa_acc_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_spxx_tpa_acc_s cn38xx; - struct cvmx_spxx_tpa_acc_s cn38xxp2; - struct cvmx_spxx_tpa_acc_s cn58xx; - struct cvmx_spxx_tpa_acc_s cn58xxp1; -}; - -union cvmx_spxx_tpa_max { - uint64_t u64; - struct cvmx_spxx_tpa_max_s { - uint64_t reserved_32_63:32; - uint64_t max:32; - } s; - struct cvmx_spxx_tpa_max_s cn38xx; - struct cvmx_spxx_tpa_max_s cn38xxp2; - struct cvmx_spxx_tpa_max_s cn58xx; - struct cvmx_spxx_tpa_max_s cn58xxp1; -}; - -union cvmx_spxx_tpa_sel { - uint64_t u64; - struct cvmx_spxx_tpa_sel_s { - uint64_t reserved_4_63:60; - uint64_t prtsel:4; - } s; - struct cvmx_spxx_tpa_sel_s cn38xx; - struct cvmx_spxx_tpa_sel_s cn38xxp2; - struct cvmx_spxx_tpa_sel_s cn58xx; - struct cvmx_spxx_tpa_sel_s cn58xxp1; -}; - -union cvmx_spxx_trn4_ctl { - uint64_t u64; - struct cvmx_spxx_trn4_ctl_s { - uint64_t reserved_13_63:51; - uint64_t trntest:1; - uint64_t jitter:3; - uint64_t clr_boot:1; - uint64_t set_boot:1; - uint64_t maxdist:5; - uint64_t macro_en:1; - uint64_t mux_en:1; - } s; - struct cvmx_spxx_trn4_ctl_s cn38xx; - struct cvmx_spxx_trn4_ctl_s cn38xxp2; - struct cvmx_spxx_trn4_ctl_s cn58xx; - struct cvmx_spxx_trn4_ctl_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/drivers/staging/octeon/cvmx-srxx-defs.h deleted file mode 100644 index d82b366c279f..000000000000 --- a/drivers/staging/octeon/cvmx-srxx-defs.h +++ /dev/null @@ -1,126 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_SRXX_DEFS_H__ -#define __CVMX_SRXX_DEFS_H__ - -#define CVMX_SRXX_COM_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_IGN_RX_FULL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SPI4_CALX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SPI4_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SW_TICK_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_SRXX_SW_TICK_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull)) - -union cvmx_srxx_com_ctl { - uint64_t u64; - struct cvmx_srxx_com_ctl_s { - uint64_t reserved_8_63:56; - uint64_t prts:4; - uint64_t st_en:1; - uint64_t reserved_1_2:2; - uint64_t inf_en:1; - } s; - struct cvmx_srxx_com_ctl_s cn38xx; - struct cvmx_srxx_com_ctl_s cn38xxp2; - struct cvmx_srxx_com_ctl_s cn58xx; - struct cvmx_srxx_com_ctl_s cn58xxp1; -}; - -union cvmx_srxx_ign_rx_full { - uint64_t u64; - struct cvmx_srxx_ign_rx_full_s { - uint64_t reserved_16_63:48; - uint64_t ignore:16; - } s; - struct cvmx_srxx_ign_rx_full_s cn38xx; - struct cvmx_srxx_ign_rx_full_s cn38xxp2; - struct cvmx_srxx_ign_rx_full_s cn58xx; - struct cvmx_srxx_ign_rx_full_s cn58xxp1; -}; - -union cvmx_srxx_spi4_calx { - uint64_t u64; - struct cvmx_srxx_spi4_calx_s { - uint64_t reserved_17_63:47; - uint64_t oddpar:1; - uint64_t prt3:4; - uint64_t prt2:4; - uint64_t prt1:4; - uint64_t prt0:4; - } s; - struct cvmx_srxx_spi4_calx_s cn38xx; - struct cvmx_srxx_spi4_calx_s cn38xxp2; - struct cvmx_srxx_spi4_calx_s cn58xx; - struct cvmx_srxx_spi4_calx_s cn58xxp1; -}; - -union cvmx_srxx_spi4_stat { - uint64_t u64; - struct cvmx_srxx_spi4_stat_s { - uint64_t reserved_16_63:48; - uint64_t m:8; - uint64_t reserved_7_7:1; - uint64_t len:7; - } s; - struct cvmx_srxx_spi4_stat_s cn38xx; - struct cvmx_srxx_spi4_stat_s cn38xxp2; - struct cvmx_srxx_spi4_stat_s cn58xx; - struct cvmx_srxx_spi4_stat_s cn58xxp1; -}; - -union cvmx_srxx_sw_tick_ctl { - uint64_t u64; - struct cvmx_srxx_sw_tick_ctl_s { - uint64_t reserved_14_63:50; - uint64_t eop:1; - uint64_t sop:1; - uint64_t mod:4; - uint64_t opc:4; - uint64_t adr:4; - } s; - struct cvmx_srxx_sw_tick_ctl_s cn38xx; - struct cvmx_srxx_sw_tick_ctl_s cn58xx; - struct cvmx_srxx_sw_tick_ctl_s cn58xxp1; -}; - -union cvmx_srxx_sw_tick_dat { - uint64_t u64; - struct cvmx_srxx_sw_tick_dat_s { - uint64_t dat:64; - } s; - struct cvmx_srxx_sw_tick_dat_s cn38xx; - struct cvmx_srxx_sw_tick_dat_s cn58xx; - struct cvmx_srxx_sw_tick_dat_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/drivers/staging/octeon/cvmx-stxx-defs.h deleted file mode 100644 index 4f209b62cae1..000000000000 --- a/drivers/staging/octeon/cvmx-stxx-defs.h +++ /dev/null @@ -1,292 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_STXX_DEFS_H__ -#define __CVMX_STXX_DEFS_H__ - -#define CVMX_STXX_ARB_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_BCKPRS_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_COM_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_DIP_CNT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_IGN_CAL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_MSK(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_REG(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_INT_SYNC(block_id) \ - CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_MIN_BST(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_CALX(offset, block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_DAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_SPI4_STAT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_BYTES_HI(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_BYTES_LO(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_CTL(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull)) -#define CVMX_STXX_STAT_PKT_XMT(block_id) \ - CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull)) - -union cvmx_stxx_arb_ctl { - uint64_t u64; - struct cvmx_stxx_arb_ctl_s { - uint64_t reserved_6_63:58; - uint64_t mintrn:1; - uint64_t reserved_4_4:1; - uint64_t igntpa:1; - uint64_t reserved_0_2:3; - } s; - struct cvmx_stxx_arb_ctl_s cn38xx; - struct cvmx_stxx_arb_ctl_s cn38xxp2; - struct cvmx_stxx_arb_ctl_s cn58xx; - struct cvmx_stxx_arb_ctl_s cn58xxp1; -}; - -union cvmx_stxx_bckprs_cnt { - uint64_t u64; - struct cvmx_stxx_bckprs_cnt_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_stxx_bckprs_cnt_s cn38xx; - struct cvmx_stxx_bckprs_cnt_s cn38xxp2; - struct cvmx_stxx_bckprs_cnt_s cn58xx; - struct cvmx_stxx_bckprs_cnt_s cn58xxp1; -}; - -union cvmx_stxx_com_ctl { - uint64_t u64; - struct cvmx_stxx_com_ctl_s { - uint64_t reserved_4_63:60; - uint64_t st_en:1; - uint64_t reserved_1_2:2; - uint64_t inf_en:1; - } s; - struct cvmx_stxx_com_ctl_s cn38xx; - struct cvmx_stxx_com_ctl_s cn38xxp2; - struct cvmx_stxx_com_ctl_s cn58xx; - struct cvmx_stxx_com_ctl_s cn58xxp1; -}; - -union cvmx_stxx_dip_cnt { - uint64_t u64; - struct cvmx_stxx_dip_cnt_s { - uint64_t reserved_8_63:56; - uint64_t frmmax:4; - uint64_t dipmax:4; - } s; - struct cvmx_stxx_dip_cnt_s cn38xx; - struct cvmx_stxx_dip_cnt_s cn38xxp2; - struct cvmx_stxx_dip_cnt_s cn58xx; - struct cvmx_stxx_dip_cnt_s cn58xxp1; -}; - -union cvmx_stxx_ign_cal { - uint64_t u64; - struct cvmx_stxx_ign_cal_s { - uint64_t reserved_16_63:48; - uint64_t igntpa:16; - } s; - struct cvmx_stxx_ign_cal_s cn38xx; - struct cvmx_stxx_ign_cal_s cn38xxp2; - struct cvmx_stxx_ign_cal_s cn58xx; - struct cvmx_stxx_ign_cal_s cn58xxp1; -}; - -union cvmx_stxx_int_msk { - uint64_t u64; - struct cvmx_stxx_int_msk_s { - uint64_t reserved_8_63:56; - uint64_t frmerr:1; - uint64_t unxfrm:1; - uint64_t nosync:1; - uint64_t diperr:1; - uint64_t datovr:1; - uint64_t ovrbst:1; - uint64_t calpar1:1; - uint64_t calpar0:1; - } s; - struct cvmx_stxx_int_msk_s cn38xx; - struct cvmx_stxx_int_msk_s cn38xxp2; - struct cvmx_stxx_int_msk_s cn58xx; - struct cvmx_stxx_int_msk_s cn58xxp1; -}; - -union cvmx_stxx_int_reg { - uint64_t u64; - struct cvmx_stxx_int_reg_s { - uint64_t reserved_9_63:55; - uint64_t syncerr:1; - uint64_t frmerr:1; - uint64_t unxfrm:1; - uint64_t nosync:1; - uint64_t diperr:1; - uint64_t datovr:1; - uint64_t ovrbst:1; - uint64_t calpar1:1; - uint64_t calpar0:1; - } s; - struct cvmx_stxx_int_reg_s cn38xx; - struct cvmx_stxx_int_reg_s cn38xxp2; - struct cvmx_stxx_int_reg_s cn58xx; - struct cvmx_stxx_int_reg_s cn58xxp1; -}; - -union cvmx_stxx_int_sync { - uint64_t u64; - struct cvmx_stxx_int_sync_s { - uint64_t reserved_8_63:56; - uint64_t frmerr:1; - uint64_t unxfrm:1; - uint64_t nosync:1; - uint64_t diperr:1; - uint64_t datovr:1; - uint64_t ovrbst:1; - uint64_t calpar1:1; - uint64_t calpar0:1; - } s; - struct cvmx_stxx_int_sync_s cn38xx; - struct cvmx_stxx_int_sync_s cn38xxp2; - struct cvmx_stxx_int_sync_s cn58xx; - struct cvmx_stxx_int_sync_s cn58xxp1; -}; - -union cvmx_stxx_min_bst { - uint64_t u64; - struct cvmx_stxx_min_bst_s { - uint64_t reserved_9_63:55; - uint64_t minb:9; - } s; - struct cvmx_stxx_min_bst_s cn38xx; - struct cvmx_stxx_min_bst_s cn38xxp2; - struct cvmx_stxx_min_bst_s cn58xx; - struct cvmx_stxx_min_bst_s cn58xxp1; -}; - -union cvmx_stxx_spi4_calx { - uint64_t u64; - struct cvmx_stxx_spi4_calx_s { - uint64_t reserved_17_63:47; - uint64_t oddpar:1; - uint64_t prt3:4; - uint64_t prt2:4; - uint64_t prt1:4; - uint64_t prt0:4; - } s; - struct cvmx_stxx_spi4_calx_s cn38xx; - struct cvmx_stxx_spi4_calx_s cn38xxp2; - struct cvmx_stxx_spi4_calx_s cn58xx; - struct cvmx_stxx_spi4_calx_s cn58xxp1; -}; - -union cvmx_stxx_spi4_dat { - uint64_t u64; - struct cvmx_stxx_spi4_dat_s { - uint64_t reserved_32_63:32; - uint64_t alpha:16; - uint64_t max_t:16; - } s; - struct cvmx_stxx_spi4_dat_s cn38xx; - struct cvmx_stxx_spi4_dat_s cn38xxp2; - struct cvmx_stxx_spi4_dat_s cn58xx; - struct cvmx_stxx_spi4_dat_s cn58xxp1; -}; - -union cvmx_stxx_spi4_stat { - uint64_t u64; - struct cvmx_stxx_spi4_stat_s { - uint64_t reserved_16_63:48; - uint64_t m:8; - uint64_t reserved_7_7:1; - uint64_t len:7; - } s; - struct cvmx_stxx_spi4_stat_s cn38xx; - struct cvmx_stxx_spi4_stat_s cn38xxp2; - struct cvmx_stxx_spi4_stat_s cn58xx; - struct cvmx_stxx_spi4_stat_s cn58xxp1; -}; - -union cvmx_stxx_stat_bytes_hi { - uint64_t u64; - struct cvmx_stxx_stat_bytes_hi_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_stxx_stat_bytes_hi_s cn38xx; - struct cvmx_stxx_stat_bytes_hi_s cn38xxp2; - struct cvmx_stxx_stat_bytes_hi_s cn58xx; - struct cvmx_stxx_stat_bytes_hi_s cn58xxp1; -}; - -union cvmx_stxx_stat_bytes_lo { - uint64_t u64; - struct cvmx_stxx_stat_bytes_lo_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_stxx_stat_bytes_lo_s cn38xx; - struct cvmx_stxx_stat_bytes_lo_s cn38xxp2; - struct cvmx_stxx_stat_bytes_lo_s cn58xx; - struct cvmx_stxx_stat_bytes_lo_s cn58xxp1; -}; - -union cvmx_stxx_stat_ctl { - uint64_t u64; - struct cvmx_stxx_stat_ctl_s { - uint64_t reserved_5_63:59; - uint64_t clr:1; - uint64_t bckprs:4; - } s; - struct cvmx_stxx_stat_ctl_s cn38xx; - struct cvmx_stxx_stat_ctl_s cn38xxp2; - struct cvmx_stxx_stat_ctl_s cn58xx; - struct cvmx_stxx_stat_ctl_s cn58xxp1; -}; - -union cvmx_stxx_stat_pkt_xmt { - uint64_t u64; - struct cvmx_stxx_stat_pkt_xmt_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_stxx_stat_pkt_xmt_s cn38xx; - struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2; - struct cvmx_stxx_stat_pkt_xmt_s cn58xx; - struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1; -}; - -#endif diff --git a/drivers/staging/octeon/cvmx-wqe.h b/drivers/staging/octeon/cvmx-wqe.h deleted file mode 100644 index 653610953d28..000000000000 --- a/drivers/staging/octeon/cvmx-wqe.h +++ /dev/null @@ -1,397 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -/** - * - * This header file defines the work queue entry (wqe) data structure. - * Since this is a commonly used structure that depends on structures - * from several hardware blocks, those definitions have been placed - * in this file to create a single point of definition of the wqe - * format. - * Data structures are still named according to the block that they - * relate to. - * - */ - -#ifndef __CVMX_WQE_H__ -#define __CVMX_WQE_H__ - -#include "cvmx-packet.h" - - -#define OCT_TAG_TYPE_STRING(x) \ - (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \ - (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \ - (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \ - "NULL_NULL"))) - -/** - * HW decode / err_code in work queue entry - */ -typedef union { - uint64_t u64; - - /* Use this struct if the hardware determines that the packet is IP */ - struct { - /* HW sets this to the number of buffers used by this packet */ - uint64_t bufs:8; - /* HW sets to the number of L2 bytes prior to the IP */ - uint64_t ip_offset:8; - /* set to 1 if we found DSA/VLAN in the L2 */ - uint64_t vlan_valid:1; - /* Set to 1 if the DSA/VLAN tag is stacked */ - uint64_t vlan_stacked:1; - uint64_t unassigned:1; - /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */ - uint64_t vlan_cfi:1; - /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */ - uint64_t vlan_id:12; - /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */ - uint64_t pr:4; - uint64_t unassigned2:8; - /* the packet needs to be decompressed */ - uint64_t dec_ipcomp:1; - /* the packet is either TCP or UDP */ - uint64_t tcp_or_udp:1; - /* the packet needs to be decrypted (ESP or AH) */ - uint64_t dec_ipsec:1; - /* the packet is IPv6 */ - uint64_t is_v6:1; - - /* - * (rcv_error, not_IP, IP_exc, is_frag, L4_error, - * software, etc.). - */ - - /* - * reserved for software use, hardware will clear on - * packet creation. - */ - uint64_t software:1; - /* exceptional conditions below */ - /* the receive interface hardware detected an L4 error - * (only applies if !is_frag) (only applies if - * !rcv_error && !not_IP && !IP_exc && !is_frag) - * failure indicated in err_code below, decode: - * - * - 1 = Malformed L4 - * - 2 = L4 Checksum Error: the L4 checksum value is - * - 3 = UDP Length Error: The UDP length field would - * make the UDP data longer than what remains in - * the IP packet (as defined by the IP header - * length field). - * - 4 = Bad L4 Port: either the source or destination - * TCP/UDP port is 0. - * - 8 = TCP FIN Only: the packet is TCP and only the - * FIN flag set. - * - 9 = TCP No Flags: the packet is TCP and no flags - * are set. - * - 10 = TCP FIN RST: the packet is TCP and both FIN - * and RST are set. - * - 11 = TCP SYN URG: the packet is TCP and both SYN - * and URG are set. - * - 12 = TCP SYN RST: the packet is TCP and both SYN - * and RST are set. - * - 13 = TCP SYN FIN: the packet is TCP and both SYN - * and FIN are set. - */ - uint64_t L4_error:1; - /* set if the packet is a fragment */ - uint64_t is_frag:1; - /* the receive interface hardware detected an IP error - * / exception (only applies if !rcv_error && !not_IP) - * failure indicated in err_code below, decode: - * - * - 1 = Not IP: the IP version field is neither 4 nor - * 6. - * - 2 = IPv4 Header Checksum Error: the IPv4 header - * has a checksum violation. - * - 3 = IP Malformed Header: the packet is not long - * enough to contain the IP header. - * - 4 = IP Malformed: the packet is not long enough - * to contain the bytes indicated by the IP - * header. Pad is allowed. - * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 - * Hop Count field are zero. - * - 6 = IP Options - */ - uint64_t IP_exc:1; - /* - * Set if the hardware determined that the packet is a - * broadcast. - */ - uint64_t is_bcast:1; - /* - * St if the hardware determined that the packet is a - * multi-cast. - */ - uint64_t is_mcast:1; - /* - * Set if the packet may not be IP (must be zero in - * this case). - */ - uint64_t not_IP:1; - /* - * The receive interface hardware detected a receive - * error (must be zero in this case). - */ - uint64_t rcv_error:1; - /* lower err_code = first-level descriptor of the - * work */ - /* zero for packet submitted by hardware that isn't on - * the slow path */ - /* type is cvmx_pip_err_t */ - uint64_t err_code:8; - } s; - - /* use this to get at the 16 vlan bits */ - struct { - uint64_t unused1:16; - uint64_t vlan:16; - uint64_t unused2:32; - } svlan; - - /* - * use this struct if the hardware could not determine that - * the packet is ip. - */ - struct { - /* - * HW sets this to the number of buffers used by this - * packet. - */ - uint64_t bufs:8; - uint64_t unused:8; - /* set to 1 if we found DSA/VLAN in the L2 */ - uint64_t vlan_valid:1; - /* Set to 1 if the DSA/VLAN tag is stacked */ - uint64_t vlan_stacked:1; - uint64_t unassigned:1; - /* - * HW sets to the DSA/VLAN CFI flag (valid when - * vlan_valid) - */ - uint64_t vlan_cfi:1; - /* - * HW sets to the DSA/VLAN_ID field (valid when - * vlan_valid). - */ - uint64_t vlan_id:12; - /* - * Ring Identifier (if PCIe). Requires - * PIP_GBL_CTL[RING_EN]=1 - */ - uint64_t pr:4; - uint64_t unassigned2:12; - /* - * reserved for software use, hardware will clear on - * packet creation. - */ - uint64_t software:1; - uint64_t unassigned3:1; - /* - * set if the hardware determined that the packet is - * rarp. - */ - uint64_t is_rarp:1; - /* - * set if the hardware determined that the packet is - * arp - */ - uint64_t is_arp:1; - /* - * set if the hardware determined that the packet is a - * broadcast. - */ - uint64_t is_bcast:1; - /* - * set if the hardware determined that the packet is a - * multi-cast - */ - uint64_t is_mcast:1; - /* - * set if the packet may not be IP (must be one in - * this case) - */ - uint64_t not_IP:1; - /* The receive interface hardware detected a receive - * error. Failure indicated in err_code below, - * decode: - * - * - 1 = partial error: a packet was partially - * received, but internal buffering / bandwidth - * was not adequate to receive the entire - * packet. - * - 2 = jabber error: the RGMII packet was too large - * and is truncated. - * - 3 = overrun error: the RGMII packet is longer - * than allowed and had an FCS error. - * - 4 = oversize error: the RGMII packet is longer - * than allowed. - * - 5 = alignment error: the RGMII packet is not an - * integer number of bytes - * and had an FCS error (100M and 10M only). - * - 6 = fragment error: the RGMII packet is shorter - * than allowed and had an FCS error. - * - 7 = GMX FCS error: the RGMII packet had an FCS - * error. - * - 8 = undersize error: the RGMII packet is shorter - * than allowed. - * - 9 = extend error: the RGMII packet had an extend - * error. - * - 10 = length mismatch error: the RGMII packet had - * a length that did not match the length field - * in the L2 HDR. - * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII - * packet had one or more data reception errors - * (RXERR) or the SPI4 packet had one or more - * DIP4 errors. - * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII - * packet was not large enough to cover the - * skipped bytes or the SPI4 packet was - * terminated with an About EOPS. - * - 13 = RGMII nibble error/SPI4 Port NXA Error: the - * RGMII packet had a studder error (data not - * repeated - 10/100M only) or the SPI4 packet - * was sent to an NXA. - * - 16 = FCS error: a SPI4.2 packet had an FCS error. - * - 17 = Skip error: a packet was not large enough to - * cover the skipped bytes. - * - 18 = L2 header malformed: the packet is not long - * enough to contain the L2. - */ - - uint64_t rcv_error:1; - /* - * lower err_code = first-level descriptor of the - * work - */ - /* - * zero for packet submitted by hardware that isn't on - * the slow path - */ - /* type is cvmx_pip_err_t (union, so can't use directly */ - uint64_t err_code:8; - } snoip; - -} cvmx_pip_wqe_word2; - -/** - * Work queue entry format - * - * must be 8-byte aligned - */ -typedef struct { - - /***************************************************************** - * WORD 0 - * HW WRITE: the following 64 bits are filled by HW when a packet arrives - */ - - /** - * raw chksum result generated by the HW - */ - uint16_t hw_chksum; - /** - * Field unused by hardware - available for software - */ - uint8_t unused; - /** - * Next pointer used by hardware for list maintenance. - * May be written/read by HW before the work queue - * entry is scheduled to a PP - * (Only 36 bits used in Octeon 1) - */ - uint64_t next_ptr:40; - - /***************************************************************** - * WORD 1 - * HW WRITE: the following 64 bits are filled by HW when a packet arrives - */ - - /** - * HW sets to the total number of bytes in the packet - */ - uint64_t len:16; - /** - * HW sets this to input physical port - */ - uint64_t ipprt:6; - - /** - * HW sets this to what it thought the priority of the input packet was - */ - uint64_t qos:3; - - /** - * the group that the work queue entry will be scheduled to - */ - uint64_t grp:4; - /** - * the type of the tag (ORDERED, ATOMIC, NULL) - */ - uint64_t tag_type:3; - /** - * the synchronization/ordering tag - */ - uint64_t tag:32; - - /** - * WORD 2 HW WRITE: the following 64-bits are filled in by - * hardware when a packet arrives This indicates a variety of - * status and error conditions. - */ - cvmx_pip_wqe_word2 word2; - - /** - * Pointer to the first segment of the packet. - */ - union cvmx_buf_ptr packet_ptr; - - /** - * HW WRITE: octeon will fill in a programmable amount from the - * packet, up to (at most, but perhaps less) the amount - * needed to fill the work queue entry to 128 bytes - * - * If the packet is recognized to be IP, the hardware starts - * (except that the IPv4 header is padded for appropriate - * alignment) writing here where the IP header starts. If the - * packet is not recognized to be IP, the hardware starts - * writing the beginning of the packet here. - */ - uint8_t packet_data[96]; - - /** - * If desired, SW can make the work Q entry any length. For the - * purposes of discussion here, Assume 128B always, as this is all that - * the hardware deals with. - * - */ - -} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t; - -#endif /* __CVMX_WQE_H__ */ diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h index 6a2cd50a17df..bdaec8d2ca0c 100644 --- a/drivers/staging/octeon/ethernet-defines.h +++ b/drivers/staging/octeon/ethernet-defines.h @@ -59,7 +59,7 @@ #ifndef __ETHERNET_DEFINES_H__ #define __ETHERNET_DEFINES_H__ -#include "cvmx-config.h" +#include #define OCTEON_ETHERNET_VERSION "1.9" diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index f18e3e140413..63800ba71d06 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -38,9 +38,9 @@ #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "cvmx-helper-board.h" +#include -#include "cvmx-smix-defs.h" +#include static void cvm_oct_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c index 635bb86cdcff..78b6cb743769 100644 --- a/drivers/staging/octeon/ethernet-mem.c +++ b/drivers/staging/octeon/ethernet-mem.c @@ -32,7 +32,7 @@ #include "ethernet-defines.h" -#include "cvmx-fpa.h" +#include /** * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c index c3d73f8431ae..d8f5f694ec35 100644 --- a/drivers/staging/octeon/ethernet-rgmii.c +++ b/drivers/staging/octeon/ethernet-rgmii.c @@ -37,11 +37,11 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include #include #include -#include "cvmx-gmxx-defs.h" +#include DEFINE_SPINLOCK(global_register_lock); diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c index 8b307b428791..400df8cbee53 100644 --- a/drivers/staging/octeon/ethernet-rx.c +++ b/drivers/staging/octeon/ethernet-rx.c @@ -52,14 +52,14 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" -#include "cvmx-wqe.h" -#include "cvmx-fau.h" -#include "cvmx-pow.h" -#include "cvmx-pip.h" -#include "cvmx-scratch.h" - -#include "cvmx-gmxx-defs.h" +#include +#include +#include +#include +#include +#include + +#include struct cvm_napi_wrapper { struct napi_struct napi; diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h index a0743b85d54e..9240c85ce241 100644 --- a/drivers/staging/octeon/ethernet-rx.h +++ b/drivers/staging/octeon/ethernet-rx.h @@ -24,7 +24,7 @@ * This file may also be available under a different license from Cavium. * Contact Cavium Networks for more information *********************************************************************/ -#include "cvmx-fau.h" +#include void cvm_oct_poll_controller(struct net_device *dev); void cvm_oct_rx_initialize(void); diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c index 5e148b512c97..d3e82430eba6 100644 --- a/drivers/staging/octeon/ethernet-sgmii.c +++ b/drivers/staging/octeon/ethernet-sgmii.c @@ -35,9 +35,9 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include -#include "cvmx-gmxx-defs.h" +#include int cvm_oct_sgmii_open(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c index d0e2d514968a..af8d62818f13 100644 --- a/drivers/staging/octeon/ethernet-spi.c +++ b/drivers/staging/octeon/ethernet-spi.c @@ -35,11 +35,11 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-spi.h" +#include #include -#include "cvmx-spxx-defs.h" -#include "cvmx-stxx-defs.h" +#include +#include static int number_spi_ports; static int need_retrain[2] = { 0, 0 }; diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c index 2542c3743904..56d74dc2fbd5 100644 --- a/drivers/staging/octeon/ethernet-tx.c +++ b/drivers/staging/octeon/ethernet-tx.c @@ -47,13 +47,13 @@ #include "ethernet-tx.h" #include "ethernet-util.h" -#include "cvmx-wqe.h" -#include "cvmx-fau.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-helper.h" +#include +#include +#include +#include +#include -#include "cvmx-gmxx-defs.h" +#include #define CVM_OCT_SKB_CB(skb) ((u64 *)((skb)->cb)) diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c index 861a4b3fe857..419f8c34ecdf 100644 --- a/drivers/staging/octeon/ethernet-xaui.c +++ b/drivers/staging/octeon/ethernet-xaui.c @@ -35,9 +35,9 @@ #include "octeon-ethernet.h" #include "ethernet-util.h" -#include "cvmx-helper.h" +#include -#include "cvmx-gmxx-defs.h" +#include int cvm_oct_xaui_open(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 076f86675ce6..9112cd882154 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -44,14 +44,14 @@ #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "cvmx-pip.h" -#include "cvmx-pko.h" -#include "cvmx-fau.h" -#include "cvmx-ipd.h" -#include "cvmx-helper.h" - -#include "cvmx-gmxx-defs.h" -#include "cvmx-smix-defs.h" +#include +#include +#include +#include +#include + +#include +#include #if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \ && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS -- cgit v1.2.3 From e84de0c61905030a0fe66b7210b6f1bb7c3e1eab Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Tue, 22 Nov 2011 14:38:02 +0000 Subject: MIPS: GIO bus support for SGI IP22/28 SGI IP22/IP28 machines have GIO busses for adding graphics and other extension cards. This patch adds support for GIO driver/device handling and converts the newport console driver to a GIO driver. [ralf@linux-mips.org: Fixed build error caused by the modules.h -> export.h changes.] Signed-off-by: Thomas Bogendoerfer Acked-by: Florian Tobias Schandinat To: linux-fbdev@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2886/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/gio_device.h | 56 +++++ arch/mips/sgi-ip22/Makefile | 2 +- arch/mips/sgi-ip22/ip22-gio.c | 428 ++++++++++++++++++++++++++++++++++++ arch/mips/sgi-ip22/ip22-mc.c | 10 +- arch/mips/sgi-ip22/ip22-setup.c | 21 -- drivers/video/console/newport_con.c | 63 ++++-- 6 files changed, 534 insertions(+), 46 deletions(-) create mode 100644 arch/mips/include/asm/gio_device.h create mode 100644 arch/mips/sgi-ip22/ip22-gio.c (limited to 'drivers') diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h new file mode 100644 index 000000000000..5437c84664bf --- /dev/null +++ b/arch/mips/include/asm/gio_device.h @@ -0,0 +1,56 @@ +#include +#include + +struct gio_device_id { + __u8 id; +}; + +struct gio_device { + struct device dev; + struct resource resource; + unsigned int irq; + unsigned int slotno; + + const char *name; + struct gio_device_id id; + unsigned id32:1; + unsigned gio64:1; +}; +#define to_gio_device(d) container_of(d, struct gio_device, dev) + +struct gio_driver { + const char *name; + struct module *owner; + const struct gio_device_id *id_table; + + int (*probe)(struct gio_device *, const struct gio_device_id *); + void (*remove)(struct gio_device *); + int (*suspend)(struct gio_device *, pm_message_t); + int (*resume)(struct gio_device *); + void (*shutdown)(struct gio_device *); + + struct device_driver driver; +}; +#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver) + +extern const struct gio_device_id *gio_match_device(const struct gio_device_id *, + const struct gio_device *); +extern struct gio_device *gio_dev_get(struct gio_device *); +extern void gio_dev_put(struct gio_device *); + +extern int gio_device_register(struct gio_device *); +extern void gio_device_unregister(struct gio_device *); +extern void gio_release_dev(struct device *); + +static inline void gio_device_free(struct gio_device *dev) +{ + gio_release_dev(&dev->dev); +} + +extern int gio_register_driver(struct gio_driver *); +extern void gio_unregister_driver(struct gio_driver *); + +#define gio_get_drvdata(_dev) drv_get_drvdata(&(_dev)->dev) +#define gio_set_drvdata(_dev, data) drv_set_drvdata(&(_dev)->dev, (data)) + +extern void gio_set_master(struct gio_device *); diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile index cc538493cae1..411cda9ee030 100644 --- a/arch/mips/sgi-ip22/Makefile +++ b/arch/mips/sgi-ip22/Makefile @@ -4,7 +4,7 @@ # obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \ - ip22-platform.o ip22-reset.o ip22-setup.o + ip22-platform.o ip22-reset.o ip22-setup.o ip22-gio.o obj-$(CONFIG_SGI_IP22) += ip22-berr.o obj-$(CONFIG_SGI_IP28) += ip28-berr.o diff --git a/arch/mips/sgi-ip22/ip22-gio.c b/arch/mips/sgi-ip22/ip22-gio.c new file mode 100644 index 000000000000..f5ebc092aed5 --- /dev/null +++ b/arch/mips/sgi-ip22/ip22-gio.c @@ -0,0 +1,428 @@ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +static struct bus_type gio_bus_type; + +static struct { + const char *name; + __u8 id; +} gio_name_table[] = { + { .name = "SGI Impact", .id = 0x10 }, + { .name = "Phobos G160", .id = 0x35 }, + /* fake IDs */ + { .name = "SGI Newport", .id = 0x7e }, + { .name = "SGI GR2/GR3", .id = 0x7f }, +}; + +static struct device gio_bus = { + .init_name = "gio", +}; + +/** + * gio_match_device - Tell if an of_device structure has a matching + * gio_match structure + * @ids: array of of device match structures to search in + * @dev: the of device structure to match against + * + * Used by a driver to check whether an of_device present in the + * system is in its list of supported devices. + */ +const struct gio_device_id *gio_match_device(const struct gio_device_id *match, + const struct gio_device *dev) +{ + const struct gio_device_id *ids; + + for (ids = match; ids->id != 0xff; ids++) + if (ids->id == dev->id.id) + return ids; + + return NULL; +} +EXPORT_SYMBOL_GPL(gio_match_device); + +struct gio_device *gio_dev_get(struct gio_device *dev) +{ + struct device *tmp; + + if (!dev) + return NULL; + tmp = get_device(&dev->dev); + if (tmp) + return to_gio_device(tmp); + else + return NULL; +} +EXPORT_SYMBOL_GPL(gio_dev_get); + +void gio_dev_put(struct gio_device *dev) +{ + if (dev) + put_device(&dev->dev); +} +EXPORT_SYMBOL_GPL(gio_dev_put); + +/** + * gio_release_dev - free an gio device structure when all users of it are finished. + * @dev: device that's been disconnected + * + * Will be called only by the device core when all users of this gio device are + * done. + */ +void gio_release_dev(struct device *dev) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + kfree(giodev); +} +EXPORT_SYMBOL_GPL(gio_release_dev); + +int gio_device_register(struct gio_device *giodev) +{ + giodev->dev.bus = &gio_bus_type; + giodev->dev.parent = &gio_bus; + return device_register(&giodev->dev); +} +EXPORT_SYMBOL_GPL(gio_device_register); + +void gio_device_unregister(struct gio_device *giodev) +{ + device_unregister(&giodev->dev); +} +EXPORT_SYMBOL_GPL(gio_device_unregister); + +static int gio_bus_match(struct device *dev, struct device_driver *drv) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *gio_drv = to_gio_driver(drv); + + return gio_match_device(gio_drv->id_table, gio_dev) != NULL; +} + +static int gio_device_probe(struct device *dev) +{ + int error = -ENODEV; + struct gio_driver *drv; + struct gio_device *gio_dev; + const struct gio_device_id *match; + + drv = to_gio_driver(dev->driver); + gio_dev = to_gio_device(dev); + + if (!drv->probe) + return error; + + gio_dev_get(gio_dev); + + match = gio_match_device(drv->id_table, gio_dev); + if (match) + error = drv->probe(gio_dev, match); + if (error) + gio_dev_put(gio_dev); + + return error; +} + +static int gio_device_remove(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + + if (dev->driver && drv->remove) + drv->remove(gio_dev); + return 0; +} + +static int gio_device_suspend(struct device *dev, pm_message_t state) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + int error = 0; + + if (dev->driver && drv->suspend) + error = drv->suspend(gio_dev, state); + return error; +} + +static int gio_device_resume(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + int error = 0; + + if (dev->driver && drv->resume) + error = drv->resume(gio_dev); + return error; +} + +static void gio_device_shutdown(struct device *dev) +{ + struct gio_device *gio_dev = to_gio_device(dev); + struct gio_driver *drv = to_gio_driver(dev->driver); + + if (dev->driver && drv->shutdown) + drv->shutdown(gio_dev); +} + +static ssize_t modalias_show(struct device *dev, struct device_attribute *a, + char *buf) +{ + struct gio_device *gio_dev = to_gio_device(dev); + int len = snprintf(buf, PAGE_SIZE, "gio:%x\n", gio_dev->id.id); + + return (len >= PAGE_SIZE) ? (PAGE_SIZE - 1) : len; +} + +static ssize_t name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + return sprintf(buf, "%s", giodev->name); +} + +static ssize_t id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gio_device *giodev; + + giodev = to_gio_device(dev); + return sprintf(buf, "%x", giodev->id.id); +} + +static struct device_attribute gio_dev_attrs[] = { + __ATTR_RO(modalias), + __ATTR_RO(name), + __ATTR_RO(id), + __ATTR_NULL, +}; + +static int gio_device_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct gio_device *gio_dev = to_gio_device(dev); + + add_uevent_var(env, "MODALIAS=gio:%x", gio_dev->id.id); + return 0; +} + +int gio_register_driver(struct gio_driver *drv) +{ + /* initialize common driver fields */ + if (!drv->driver.name) + drv->driver.name = drv->name; + if (!drv->driver.owner) + drv->driver.owner = drv->owner; + drv->driver.bus = &gio_bus_type; + + /* register with core */ + return driver_register(&drv->driver); +} +EXPORT_SYMBOL_GPL(gio_register_driver); + +void gio_unregister_driver(struct gio_driver *drv) +{ + driver_unregister(&drv->driver); +} +EXPORT_SYMBOL_GPL(gio_unregister_driver); + +void gio_set_master(struct gio_device *dev) +{ + u32 tmp = sgimc->giopar; + + switch (dev->slotno) { + case 0: + tmp |= SGIMC_GIOPAR_MASTERGFX; + break; + case 1: + tmp |= SGIMC_GIOPAR_MASTEREXP0; + break; + case 2: + tmp |= SGIMC_GIOPAR_MASTEREXP1; + break; + } + sgimc->giopar = tmp; +} +EXPORT_SYMBOL_GPL(gio_set_master); + +void ip22_gio_set_64bit(int slotno) +{ + u32 tmp = sgimc->giopar; + + switch (slotno) { + case 0: + tmp |= SGIMC_GIOPAR_GFX64; + break; + case 1: + tmp |= SGIMC_GIOPAR_EXP064; + break; + case 2: + tmp |= SGIMC_GIOPAR_EXP164; + break; + } + sgimc->giopar = tmp; +} + +static int ip22_gio_id(unsigned long addr, u32 *res) +{ + u8 tmp8; + u8 tmp16; + u32 tmp32; + u8 *ptr8; + u16 *ptr16; + u32 *ptr32; + + ptr32 = (void *)CKSEG1ADDR(addr); + if (!get_dbe(tmp32, ptr32)) { + /* + * We got no DBE, but this doesn't mean anything. + * If GIO is pipelined (which can't be disabled + * for GFX slot) we don't get a DBE, but we see + * the transfer size as data. So we do an 8bit + * and a 16bit access and check whether the common + * data matches + */ + ptr8 = (void *)CKSEG1ADDR(addr + 3); + get_dbe(tmp8, ptr8); + ptr16 = (void *)CKSEG1ADDR(addr + 2); + get_dbe(tmp16, ptr16); + if (tmp8 == (tmp16 & 0xff) && + tmp8 == (tmp32 & 0xff) && + tmp16 == (tmp32 & 0xffff)) { + *res = tmp32; + return 1; + } + } + return 0; /* nothing here */ +} + +#define HQ2_MYSTERY_OFFS 0x6A07C +#define NEWPORT_USTATUS_OFFS 0xF133C + +static int ip22_is_gr2(unsigned long addr) +{ + u32 tmp; + u32 *ptr; + + /* HQ2 only allows 32bit accesses */ + ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS); + if (!get_dbe(tmp, ptr)) { + if (tmp == 0xdeadbeef) + return 1; + } + return 0; +} + + +static void ip22_check_gio(int slotno, unsigned long addr) +{ + const char *name = "Unknown"; + struct gio_device *gio_dev; + u32 tmp; + __u8 id; + int i; + + /* first look for GR2/GR3 by checking mystery register */ + if (ip22_is_gr2(addr)) + tmp = 0x7f; + else { + if (!ip22_gio_id(addr, &tmp)) { + /* + * no GIO signature at start address of slot, but + * Newport doesn't have one, so let's check usea + * status register + */ + if (ip22_gio_id(addr + NEWPORT_USTATUS_OFFS, &tmp)) + tmp = 0x7e; + else + tmp = 0; + } + } + if (tmp) { + id = GIO_ID(tmp); + if (tmp & GIO_32BIT_ID) { + if (tmp & GIO_64BIT_IFACE) + ip22_gio_set_64bit(slotno); + } + for (i = 0; i < ARRAY_SIZE(gio_name_table); i++) { + if (id == gio_name_table[i].id) { + name = gio_name_table[i].name; + break; + } + } + printk(KERN_INFO "GIO: slot %d : %s (id %x)\n", + slotno, name, id); + gio_dev = kzalloc(sizeof *gio_dev, GFP_KERNEL); + gio_dev->name = name; + gio_dev->slotno = slotno; + gio_dev->id.id = id; + gio_dev->resource.start = addr; + gio_dev->resource.end = addr + 0x3fffff; + gio_dev->resource.flags = IORESOURCE_MEM; + dev_set_name(&gio_dev->dev, "%d", slotno); + gio_device_register(gio_dev); + } else + printk(KERN_INFO "GIO: slot %d : Empty\n", slotno); +} + +static struct bus_type gio_bus_type = { + .name = "gio", + .dev_attrs = gio_dev_attrs, + .match = gio_bus_match, + .probe = gio_device_probe, + .remove = gio_device_remove, + .suspend = gio_device_suspend, + .resume = gio_device_resume, + .shutdown = gio_device_shutdown, + .uevent = gio_device_uevent, +}; + +static struct resource gio_bus_resource = { + .start = GIO_SLOT_GFX_BASE, + .end = GIO_SLOT_GFX_BASE + 0x9fffff, + .name = "GIO Bus", + .flags = IORESOURCE_MEM, +}; + +int __init ip22_gio_init(void) +{ + unsigned int pbdma __maybe_unused; + int ret; + + ret = device_register(&gio_bus); + if (ret) + return ret; + + ret = bus_register(&gio_bus_type); + if (!ret) { + request_resource(&iomem_resource, &gio_bus_resource); + printk(KERN_INFO "GIO: Probing bus...\n"); + + if (ip22_is_fullhouse() || + !get_dbe(pbdma, (unsigned int *)&hpc3c1->pbdma[1])) { + /* Indigo2 and ChallengeS */ + ip22_check_gio(0, GIO_SLOT_GFX_BASE); + ip22_check_gio(1, GIO_SLOT_EXP0_BASE); + } else { + /* Indy */ + ip22_check_gio(0, GIO_SLOT_GFX_BASE); + ip22_check_gio(1, GIO_SLOT_EXP0_BASE); + ip22_check_gio(2, GIO_SLOT_EXP1_BASE); + } + } else + device_unregister(&gio_bus); + + return ret; +} + +subsys_initcall(ip22_gio_init); diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c index d22262ee6853..75ada8a9713b 100644 --- a/arch/mips/sgi-ip22/ip22-mc.c +++ b/arch/mips/sgi-ip22/ip22-mc.c @@ -139,11 +139,11 @@ void __init sgimc_init(void) * zero. */ /* don't touch parity settings for IP28 */ -#ifndef CONFIG_SGI_IP28 tmp = sgimc->cpuctrl0; - tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | - SGIMC_CCTRL0_R4KNOCHKPARR); +#ifndef CONFIG_SGI_IP28 + tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM; #endif + tmp |= SGIMC_CCTRL0_R4KNOCHKPARR; sgimc->cpuctrl0 = tmp; /* Step 3: Setup the MC write buffer depth, this is controlled @@ -178,7 +178,8 @@ void __init sgimc_init(void) */ /* First the basic invariants across all GIO64 implementations. */ - tmp = SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ + tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */ + tmp |= SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */ tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */ if (ip22_is_fullhouse()) { @@ -193,7 +194,6 @@ void __init sgimc_init(void) tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */ tmp |= SGIMC_GIOPAR_PLINEEXP1; tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */ - tmp |= SGIMC_GIOPAR_GFX64; /* GFX at 64 bits */ } } else { /* Guiness specific settings. */ diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 5e6621349471..c7bdfe43df5b 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -26,9 +26,6 @@ #include #include -unsigned long sgi_gfxaddr; -EXPORT_SYMBOL_GPL(sgi_gfxaddr); - extern void ip22_be_init(void) __init; void __init plat_mem_setup(void) @@ -78,22 +75,4 @@ void __init plat_mem_setup(void) prom_flags |= PROM_FLAG_USE_AS_CONSOLE; add_preferred_console("arc", 0, NULL); } - -#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE) - { - ULONG *gfxinfo; - ULONG * (*__vec)(void) = (void *) (long) - *((_PULONG *)(long)((PROMBLOCK)->pvector + 0x20)); - - gfxinfo = __vec(); - sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000 - && gfxinfo[1] <= 0xc0000000) - ? gfxinfo[1] - 0xa0000000 : 0); - - /* newport addresses? */ - if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) { - conswitchp = &newport_con; - } - } -#endif } diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c index 93317b5b8740..a122d9287d16 100644 --- a/drivers/video/console/newport_con.c +++ b/drivers/video/console/newport_con.c @@ -25,14 +25,13 @@ #include #include #include +#include + #include