From 6f259bf1619bbff6118c1e556044c0cb4020bbb6 Mon Sep 17 00:00:00 2001 From: kartik Date: Mon, 6 Dec 2021 17:22:45 +0530 Subject: soc/tegra: fuse: Update nvmem cell list Update tegra_fuse_cells with below entries: - gcplex-config-fuse: Configuration bits for GPU, used to enable/disable write protected region used for storing GPU firmware. - pdi0: Unique per chip public identifier. - pdi1: Unique per chip public identifier. Signed-off-by: Prathamesh Shete Signed-off-by: Kartik Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'drivers/soc/tegra') diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 913103ee5432..10d2ae99babd 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved. */ #include @@ -161,6 +161,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bytes = 4, .bit_offset = 0, .nbits = 32, + }, { + .name = "gcplex-config-fuse", + .offset = 0x1c8, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, }, { .name = "tsensor-realignment", .offset = 0x1fc, @@ -179,6 +185,18 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bytes = 4, .bit_offset = 0, .nbits = 32, + }, { + .name = "pdi0", + .offset = 0x300, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "pdi1", + .offset = 0x304, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, }, }; -- cgit v1.2.3