From cd4ed0ab802b5aa171015dae40ac2418e1f7f720 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:10 +0300 Subject: power: reset: at91-reset: document structures and enums Document structures and enums. Signed-off-by: Claudiu Beznea Signed-off-by: Sebastian Reichel --- drivers/power/reset/at91-reset.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/power/reset') diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 64def79d557a..e62798750b6b 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -39,6 +39,17 @@ #define AT91_RSTC_URSTIEN BIT(4) /* User Reset Interrupt Enable */ #define AT91_RSTC_ERSTL GENMASK(11, 8) /* External Reset Length */ +/** + * enum reset_type - reset types + * @RESET_TYPE_GENERAL: first power-up reset + * @RESET_TYPE_WAKEUP: return from backup mode + * @RESET_TYPE_WATCHDOG: watchdog fault + * @RESET_TYPE_SOFTWARE: processor reset required by software + * @RESET_TYPE_USER: NRST pin detected low + * @RESET_TYPE_CPU_FAIL: CPU clock failure detection + * @RESET_TYPE_XTAL_FAIL: 32KHz crystal failure dectection fault + * @RESET_TYPE_ULP2: ULP2 reset + */ enum reset_type { RESET_TYPE_GENERAL = 0, RESET_TYPE_WAKEUP = 1, @@ -50,6 +61,15 @@ enum reset_type { RESET_TYPE_ULP2 = 8, }; +/** + * struct at91_reset - AT91 reset specific data structure + * @rstc_base: base address for system reset + * @ramc_base: array with base addresses of RAM controllers + * @sclk: slow clock + * @nb: reset notifier block + * @args: SoC specific system reset arguments + * @ramc_lpr: SDRAM Controller Low Power Register + */ struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; -- cgit v1.2.3 From e17ad25bc31a3565c1adab924316d72935eef4a2 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:11 +0300 Subject: power: reset: at91-reset: add at91_reset_data Add struct at91_reset_data to keep per platform related information. This is a prerequisite for adding reset_controller_dev support. Signed-off-by: Claudiu Beznea Signed-off-by: Sebastian Reichel --- drivers/power/reset/at91-reset.c | 45 ++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 11 deletions(-) (limited to 'drivers/power/reset') diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index e62798750b6b..bb073aba816f 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -66,6 +66,7 @@ enum reset_type { * @rstc_base: base address for system reset * @ramc_base: array with base addresses of RAM controllers * @sclk: slow clock + * @data: platform specific reset data * @nb: reset notifier block * @args: SoC specific system reset arguments * @ramc_lpr: SDRAM Controller Low Power Register @@ -74,11 +75,26 @@ struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; struct clk *sclk; + const struct at91_reset_data *data; struct notifier_block nb; u32 args; u32 ramc_lpr; }; +/** + * struct at91_reset_data - AT91 reset data + * @reset_args: SoC specific system reset arguments + * @n_device_reset: number of device resets + * @device_reset_min_id: min id for device reset + * @device_reset_max_id: max id for device reset + */ +struct at91_reset_data { + u32 reset_args; + u32 n_device_reset; + u8 device_reset_min_id; + u8 device_reset_max_id; +}; + /* * unless the SDRAM is cleanly shutdown before we hit the * reset register it can be left driving the data bus and @@ -115,7 +131,7 @@ static int at91_reset(struct notifier_block *this, unsigned long mode, "r" (reset->rstc_base), "r" (1), "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN), - "r" (reset->args), + "r" (reset->data->reset_args), "r" (reset->ramc_lpr) : "r4"); @@ -173,29 +189,34 @@ static const struct of_device_id at91_ramc_of_match[] = { { /* sentinel */ } }; +static const struct at91_reset_data sam9260 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST, +}; + +static const struct at91_reset_data samx7 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, +}; + static const struct of_device_id at91_reset_of_match[] = { { .compatible = "atmel,at91sam9260-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST), + .data = &sam9260, }, { .compatible = "atmel,at91sam9g45-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST) + .data = &sam9260, }, { .compatible = "atmel,sama5d3-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST | - AT91_RSTC_PROCRST) + .data = &sam9260, }, { .compatible = "atmel,samx7-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) + .data = &samx7, }, { .compatible = "microchip,sam9x60-rstc", - .data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST) + .data = &samx7, }, { /* sentinel */ } }; @@ -232,10 +253,12 @@ static int __init at91_reset_probe(struct platform_device *pdev) } } - match = of_match_node(at91_reset_of_match, pdev->dev.of_node); + reset->data = device_get_match_data(&pdev->dev); + if (!reset->data) + return -ENODEV; + reset->nb.notifier_call = at91_reset; reset->nb.priority = 192; - reset->args = (u32)match->data; reset->sclk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(reset->sclk)) -- cgit v1.2.3 From 5f37c797a4df2a3a5b6406af48cc565020c01d98 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:12 +0300 Subject: power: reset: at91-reset: add reset_controller_dev support SAMA7G5 reset controller has 5 extra lines that goes to different devices (3 lines to USB PHYs, 1 line to DDR controller, 1 line to DDR PHY controller). These reset lines could be requested by different controller drivers (e.g. USB PHY driver) and these controllers' drivers could assert/deassert these lines when necessary. Thus add support for reset_controller_dev which brings this functionality. Signed-off-by: Claudiu Beznea Reviewed-by: Philipp Zabel Signed-off-by: Sebastian Reichel --- drivers/power/reset/at91-reset.c | 106 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 102 insertions(+), 4 deletions(-) (limited to 'drivers/power/reset') diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index bb073aba816f..bc9f1d9e7867 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -65,8 +66,11 @@ enum reset_type { * struct at91_reset - AT91 reset specific data structure * @rstc_base: base address for system reset * @ramc_base: array with base addresses of RAM controllers + * @dev_base: base address for devices reset * @sclk: slow clock * @data: platform specific reset data + * @rcdev: reset controller device + * @lock: lock for devices reset register access * @nb: reset notifier block * @args: SoC specific system reset arguments * @ramc_lpr: SDRAM Controller Low Power Register @@ -74,13 +78,18 @@ enum reset_type { struct at91_reset { void __iomem *rstc_base; void __iomem *ramc_base[2]; + void __iomem *dev_base; struct clk *sclk; const struct at91_reset_data *data; + struct reset_controller_dev rcdev; + spinlock_t lock; struct notifier_block nb; u32 args; u32 ramc_lpr; }; +#define to_at91_reset(r) container_of(r, struct at91_reset, rcdev) + /** * struct at91_reset_data - AT91 reset data * @reset_args: SoC specific system reset arguments @@ -222,6 +231,89 @@ static const struct of_device_id at91_reset_of_match[] = { }; MODULE_DEVICE_TABLE(of, at91_reset_of_match); +static int at91_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&reset->lock, flags); + val = readl_relaxed(reset->dev_base); + if (assert) + val |= BIT(id); + else + val &= ~BIT(id); + writel_relaxed(val, reset->dev_base); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static int at91_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return at91_reset_update(rcdev, id, true); +} + +static int at91_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return at91_reset_update(rcdev, id, false); +} + +static int at91_reset_dev_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + u32 val; + + val = readl_relaxed(reset->dev_base); + + return !!(val & BIT(id)); +} + +static const struct reset_control_ops at91_reset_ops = { + .assert = at91_reset_assert, + .deassert = at91_reset_deassert, + .status = at91_reset_dev_status, +}; + +static int at91_reset_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct at91_reset *reset = to_at91_reset(rcdev); + + if (!reset->data->n_device_reset || + (reset_spec->args[0] < reset->data->device_reset_min_id || + reset_spec->args[0] > reset->data->device_reset_max_id)) + return -EINVAL; + + return reset_spec->args[0]; +} + +static int at91_rcdev_init(struct at91_reset *reset, + struct platform_device *pdev) +{ + if (!reset->data->n_device_reset) + return 0; + + reset->dev_base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 1, + NULL); + if (IS_ERR(reset->dev_base)) + return -ENODEV; + + spin_lock_init(&reset->lock); + reset->rcdev.ops = &at91_reset_ops; + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.nr_resets = reset->data->n_device_reset; + reset->rcdev.of_reset_n_cells = 1; + reset->rcdev.of_xlate = at91_reset_of_xlate; + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + static int __init at91_reset_probe(struct platform_device *pdev) { const struct of_device_id *match; @@ -272,6 +364,10 @@ static int __init at91_reset_probe(struct platform_device *pdev) platform_set_drvdata(pdev, reset); + ret = at91_rcdev_init(reset, pdev); + if (ret) + goto disable_clk; + if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) { u32 val = readl(reset->rstc_base + AT91_RSTC_MR); @@ -280,14 +376,16 @@ static int __init at91_reset_probe(struct platform_device *pdev) } ret = register_restart_handler(&reset->nb); - if (ret) { - clk_disable_unprepare(reset->sclk); - return ret; - } + if (ret) + goto disable_clk; at91_reset_status(pdev, reset->rstc_base); return 0; + +disable_clk: + clk_disable_unprepare(reset->sclk); + return ret; } static int __exit at91_reset_remove(struct platform_device *pdev) -- cgit v1.2.3 From a22c8e8834bcc55e44d0bae738f0915df7e6f573 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 10 Jun 2022 12:24:13 +0300 Subject: power: reset: at91-reset: add support for SAMA7G5 Add support for SAMA7G5 including reset_controller_dev support for 3 lines (which are USB PHYs). Signed-off-by: Claudiu Beznea Signed-off-by: Sebastian Reichel --- drivers/power/reset/at91-reset.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/power/reset') diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index bc9f1d9e7867..741e44a017c3 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -22,6 +22,8 @@ #include #include +#include + #define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */ #define AT91_RSTC_PROCRST BIT(0) /* Processor Reset */ #define AT91_RSTC_PERRST BIT(2) /* Peripheral Reset */ @@ -206,6 +208,13 @@ static const struct at91_reset_data samx7 = { .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, }; +static const struct at91_reset_data sama7g5 = { + .reset_args = AT91_RSTC_KEY | AT91_RSTC_PROCRST, + .n_device_reset = 3, + .device_reset_min_id = SAMA7G5_RESET_USB_PHY1, + .device_reset_max_id = SAMA7G5_RESET_USB_PHY3, +}; + static const struct of_device_id at91_reset_of_match[] = { { .compatible = "atmel,at91sam9260-rstc", @@ -227,6 +236,10 @@ static const struct of_device_id at91_reset_of_match[] = { .compatible = "microchip,sam9x60-rstc", .data = &samx7, }, + { + .compatible = "microchip,sama7g5-rstc", + .data = &sama7g5, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, at91_reset_of_match); -- cgit v1.2.3