From afb8d5f4311585a9d79ca45da3e53c382e826e7b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 5 Oct 2022 16:33:37 +0300 Subject: pinctrl: actions: make irq_chip immutable Since recently, the kernel is nagging about mutable irq_chips: "not an immutable chip, please consider fixing it!" Drop the unneeded copy, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221005133337.19245-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-owl.c | 39 +++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 15 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index ed46abc15d72..0898d178f4e5 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -38,7 +38,6 @@ * @clk: clock control * @soc: reference to soc_data * @base: pinctrl register base address - * @irq_chip: IRQ chip information * @num_irq: number of possible interrupts * @irq: interrupt numbers */ @@ -50,7 +49,6 @@ struct owl_pinctrl { struct clk *clk; const struct owl_pinctrl_soc_data *soc; void __iomem *base; - struct irq_chip irq_chip; unsigned int num_irq; unsigned int *irq; }; @@ -722,10 +720,11 @@ static void owl_gpio_irq_mask(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct owl_pinctrl *pctrl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(data); const struct owl_gpio_port *port; + unsigned int gpio = hwirq; void __iomem *gpio_base; unsigned long flags; - unsigned int gpio = data->hwirq; u32 val; port = owl_gpio_get_port(pctrl, &gpio); @@ -745,22 +744,27 @@ static void owl_gpio_irq_mask(struct irq_data *data) OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false); raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + gpiochip_disable_irq(gc, hwirq); } static void owl_gpio_irq_unmask(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct owl_pinctrl *pctrl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(data); const struct owl_gpio_port *port; + unsigned int gpio = hwirq; void __iomem *gpio_base; unsigned long flags; - unsigned int gpio = data->hwirq; u32 value; port = owl_gpio_get_port(pctrl, &gpio); if (WARN_ON(port == NULL)) return; + gpiochip_enable_irq(gc, hwirq); + gpio_base = pctrl->base + port->offset; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -780,20 +784,21 @@ static void owl_gpio_irq_ack(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct owl_pinctrl *pctrl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(data); const struct owl_gpio_port *port; + unsigned int gpio = hwirq; void __iomem *gpio_base; unsigned long flags; - unsigned int gpio = data->hwirq; /* * Switch the interrupt edge to the opposite edge of the interrupt * which got triggered for the case of emulating both edges */ if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) { - if (owl_gpio_get(gc, gpio)) - irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING); + if (owl_gpio_get(gc, hwirq)) + irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_FALLING); else - irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING); + irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_RISING); } port = owl_gpio_get_port(pctrl, &gpio); @@ -825,6 +830,16 @@ static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type) return 0; } +static const struct irq_chip owl_gpio_irqchip = { + .name = "owl-irq", + .irq_ack = owl_gpio_irq_ack, + .irq_mask = owl_gpio_irq_mask, + .irq_unmask = owl_gpio_irq_unmask, + .irq_set_type = owl_gpio_irq_set_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static void owl_gpio_irq_handler(struct irq_desc *desc) { struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc); @@ -875,14 +890,8 @@ static int owl_gpio_init(struct owl_pinctrl *pctrl) chip->parent = pctrl->dev; chip->owner = THIS_MODULE; - pctrl->irq_chip.name = chip->of_node->name; - pctrl->irq_chip.irq_ack = owl_gpio_irq_ack; - pctrl->irq_chip.irq_mask = owl_gpio_irq_mask; - pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask; - pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type; - gpio_irq = &chip->irq; - gpio_irq->chip = &pctrl->irq_chip; + gpio_irq_chip_set_chip(gpio_irq, &owl_gpio_irqchip); gpio_irq->handler = handle_simple_irq; gpio_irq->default_type = IRQ_TYPE_NONE; gpio_irq->parent_handler = owl_gpio_irq_handler; -- cgit v1.2.3 From 8ada020ade3bc4125b639a1dca50a6df687dd986 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Sun, 25 Sep 2022 10:12:58 +0800 Subject: pinctrl: ocelot: add missing destroy_workqueue() in error path in ocelot_pinctrl_probe() Using devm_add_action_or_reset() to make workqueue device-managed, so it can be destroy whenever the driver is unbound. Fixes: c297561bc98a ("pinctrl: ocelot: Fix interrupt controller") Signed-off-by: Yang Yingliang Reviewed-by: Horatiu Vultur Link: https://lore.kernel.org/r/20220925021258.1492905-1-yangyingliang@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 62ce3957abe4..266fbc957273 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -2038,6 +2038,11 @@ static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); } +static void ocelot_destroy_workqueue(void *data) +{ + destroy_workqueue(data); +} + static int ocelot_pinctrl_probe(struct platform_device *pdev) { const struct ocelot_match_data *data; @@ -2069,6 +2074,11 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) if (!info->wq) return -ENOMEM; + ret = devm_add_action_or_reset(dev, ocelot_destroy_workqueue, + info->wq); + if (ret) + return ret; + info->pincfg_data = &data->pincfg_data; reset = devm_reset_control_get_optional_shared(dev, "switch"); @@ -2110,15 +2120,6 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) return 0; } -static int ocelot_pinctrl_remove(struct platform_device *pdev) -{ - struct ocelot_pinctrl *info = platform_get_drvdata(pdev); - - destroy_workqueue(info->wq); - - return 0; -} - static struct platform_driver ocelot_pinctrl_driver = { .driver = { .name = "pinctrl-ocelot", @@ -2126,7 +2127,6 @@ static struct platform_driver ocelot_pinctrl_driver = { .suppress_bind_attrs = true, }, .probe = ocelot_pinctrl_probe, - .remove = ocelot_pinctrl_remove, }; module_platform_driver(ocelot_pinctrl_driver); -- cgit v1.2.3 From f764b84848e81508d65bac69c77ed2ed165eb511 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 13 Oct 2022 20:19:33 -0400 Subject: pinctrl: qcom: do not reinitialize gpio valid mask It may be necessary for some devices to specify reserved gpios in the device-specific DTS, in addition to the reserved gpios common to all devices with a given SoC. Remove this bitmap_fill() call so that the settings applied to the gpio valid mask by DTS are not overridden by the driver's reserved gpios. Signed-off-by: Richard Acayan Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221014001934.4995-3-mailingradian@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index a2abfe987ab1..c5c9e588fb13 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -687,9 +687,8 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc, const int *reserved = pctrl->soc->reserved_gpios; u16 *tmp; - /* Driver provided reserved list overrides DT and ACPI */ + /* Remove driver-provided reserved GPIOs from valid_mask */ if (reserved) { - bitmap_fill(valid_mask, ngpios); for (i = 0; reserved[i] >= 0; i++) { if (i >= ngpios || reserved[i] >= ngpios) { dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); -- cgit v1.2.3 From 61164d220f524945d4006263bb4946a023f0dbb4 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 13 Oct 2022 20:19:34 -0400 Subject: pinctrl: qcom: add sdm670 pinctrl The Snapdragon 670 has a Top-Level Mode Multiplexer (TLMM) for various features. Add a driver to support it. Link: https://android.googlesource.com/kernel/msm/+/de5a12173c7fa6d65bedee9ad36af55b2dbfeb36%5E%21/#F6 Link: https://android.googlesource.com/kernel/msm/+/04f083156d9b9f3bfcf204c1c6da88632fbb3863%5E%21/#F22 Link: https://android.googlesource.com/kernel/msm/+/54837652e3400ecc63ccc78b2193faf4f349a32e%5E%21/#F0 Link: https://android.googlesource.com/kernel/msm/+/f0409b07174ceca217f8b7fd255418feff06092d%5E%21/#F0 Signed-off-by: Richard Acayan Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221014001934.4995-4-mailingradian@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sdm670.c | 1345 +++++++++++++++++++++++++++++++++ 3 files changed, 1356 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm670.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 9dc2d803a586..1378ddca084f 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -308,6 +308,16 @@ config PINCTRL_SDM660 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM660 platform. +config PINCTRL_SDM670 + tristate "Qualcomm Technologies Inc SDM670 pin controller driver" + depends on OF + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDM670 platform. + config PINCTRL_SDM845 tristate "Qualcomm Technologies Inc SDM845 pin controller driver" depends on (OF || ACPI) diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 8269a1db8794..a5c40f552e5c 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c new file mode 100644 index 000000000000..4c3c3782fef8 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c @@ -0,0 +1,1345 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define NORTH 0x00500000 +#define SOUTH 0x00900000 +#define WEST 0x00100000 + +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +/* + * A dummy pingroup is a pin group that cannot be assigned a function and has + * no registers to control or monitor it. + */ +#define PINGROUP_DUMMY(id) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .ctl_reg = 0, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = -1, \ + .drv_bit = -1, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdm670_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "UFS_RESET"), + PINCTRL_PIN(151, "SDC1_RCLK"), + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), + PINCTRL_PIN(155, "SDC2_CLK"), + PINCTRL_PIN(156, "SDC2_CMD"), + PINCTRL_PIN(157, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int ufs_reset_pins[] = { 150 }; +static const unsigned int sdc1_rclk_pins[] = { 151 }; +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; +static const unsigned int sdc2_clk_pins[] = { 155 }; +static const unsigned int sdc2_cmd_pins[] = { 156 }; +static const unsigned int sdc2_data_pins[] = { 157 }; + +enum sdm670_functions { + msm_mux_gpio, + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_copy_gp, + msm_mux_copy_phase, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gps_tx, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qua_mi2s, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sec_mi2s, + msm_mux_ter_mi2s, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_tsif2_clk, + msm_mux_tsif2_data, + msm_mux_tsif2_en, + msm_mux_tsif2_error, + msm_mux_tsif2_sync, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux_wsa_clk, + msm_mux_wsa_data, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio65", "gpio66", "gpio67", "gpio68", "gpio75", "gpio76", + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", +}; +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup9_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const qdss_cti_groups[] = { + "gpio4", "gpio5", "gpio51", "gpio52", "gpio90", "gpio91", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const vsense_trigger_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const qup_l4_groups[] = { + "gpio8", "gpio35", "gpio75", "gpio105", "gpio123", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio66", +}; +static const char * const qup_l5_groups[] = { + "gpio9", "gpio36", "gpio76", "gpio106", "gpio124", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio97", "gpio98", +}; +static const char * const qup_l6_groups[] = { + "gpio10", "gpio37", "gpio77", "gpio107", "gpio125", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio10", "gpio11", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const tsif1_sync_groups[] = { + "gpio12", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio13", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const qup1_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const jitter_bist_groups[] = { + "gpio26", "gpio35", +}; +static const char * const qup2_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", +}; +static const char * const pll_bist_groups[] = { + "gpio27", "gpio36", +}; +static const char * const agera_pll_groups[] = { + "gpio28", "gpio37", +}; +static const char * const atest_tsens_groups[] = { + "gpio29", +}; +static const char * const phase_flag_groups[] = { + "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", "gpio96", + "gpio99", "gpio100", "gpio101", "gpio137", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142", "gpio143", +}; +static const char * const qup11_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const qup14_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; +static const char * const usb_phy_groups[] = { + "gpio38", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio39", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const tsif1_error_groups[] = { + "gpio40", +}; +static const char * const qup3_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const qup6_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const qup12_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const qup10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const gp_pdm0_groups[] = { + "gpio54", "gpio95", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio54", +}; +static const char * const atest_usb13_groups[] = { + "gpio54", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio54", "gpio55", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio55", +}; +static const char * const atest_usb12_groups[] = { + "gpio55", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const pri_mi2s_groups[] = { + "gpio65", "gpio67", "gpio68", +}; +static const char * const qup8_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const wsa_clk_groups[] = { + "gpio65", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio66", +}; +static const char * const wsa_data_groups[] = { + "gpio66", +}; +static const char * const atest_usb2_groups[] = { + "gpio67", +}; +static const char * const atest_usb23_groups[] = { + "gpio68", +}; +static const char * const ter_mi2s_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const atest_usb22_groups[] = { + "gpio75", +}; +static const char * const atest_usb21_groups[] = { + "gpio76", +}; +static const char * const atest_usb20_groups[] = { + "gpio77", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const gp_pdm2_groups[] = { + "gpio79", +}; +static const char * const qup15_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const qup5_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const copy_gp_groups[] = { + "gpio86", +}; +static const char * const tsif1_clk_groups[] = { + "gpio89", +}; +static const char * const qup4_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; +static const char * const tgu_ch3_groups[] = { + "gpio89", +}; +static const char * const tsif1_en_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio90", +}; +static const char * const tgu_ch0_groups[] = { + "gpio90", +}; +static const char * const tsif1_data_groups[] = { + "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const tgu_ch1_groups[] = { + "gpio91", +}; +static const char * const tsif2_error_groups[] = { + "gpio92", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const tgu_ch2_groups[] = { + "gpio92", +}; +static const char * const sdc4_data_groups[] = { + "gpio92", "gpio94", "gpio95", "gpio96", +}; +static const char * const tsif2_clk_groups[] = { + "gpio93", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const qup7_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96", +}; +static const char * const tsif2_en_groups[] = { + "gpio94", +}; +static const char * const tsif2_data_groups[] = { + "gpio95", +}; +static const char * const tsif2_sync_groups[] = { + "gpio96", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const prng_rosc_groups[] = { + "gpio99", "gpio102", +}; +static const char * const pci_e1_groups[] = { + "gpio102", "gpio103", +}; +static const char * const copy_phase_groups[] = { + "gpio103", +}; +static const char * const uim2_data_groups[] = { + "gpio105", +}; +static const char * const qup13_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; +static const char * const uim2_clk_groups[] = { + "gpio106", +}; +static const char * const uim2_reset_groups[] = { + "gpio107", +}; +static const char * const uim2_present_groups[] = { + "gpio108", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const edp_hot_groups[] = { + "gpio113", +}; +static const char * const nav_pps_groups[] = { + "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128", + "gpio129", "gpio129", "gpio143", "gpio143", +}; +static const char * const gps_tx_groups[] = { + "gpio114", "gpio115", "gpio128", "gpio129", "gpio143", "gpio145", +}; +static const char * const atest_char_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const qlink_request_groups[] = { + "gpio130", +}; +static const char * const qlink_enable_groups[] = { + "gpio131", +}; +static const char * const pa_indicator_groups[] = { + "gpio135", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; + +static const struct msm_function sdm670_functions[] = { + FUNCTION(gpio), + FUNCTION(adsp_ext), + FUNCTION(agera_pll), + FUNCTION(atest_char), + FUNCTION(atest_tsens), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(atest_usb10), + FUNCTION(atest_usb11), + FUNCTION(atest_usb12), + FUNCTION(atest_usb13), + FUNCTION(atest_usb2), + FUNCTION(atest_usb20), + FUNCTION(atest_usb21), + FUNCTION(atest_usb22), + FUNCTION(atest_usb23), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(copy_gp), + FUNCTION(copy_phase), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(edp_hot), + FUNCTION(edp_lcd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gps_tx), + FUNCTION(jitter_bist), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(lpass_slimbus), + FUNCTION(m_voc), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mss_lte), + FUNCTION(nav_pps), + FUNCTION(pa_indicator), + FUNCTION(pci_e0), + FUNCTION(pci_e1), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_bypassnl), + FUNCTION(pll_reset), + FUNCTION(pri_mi2s), + FUNCTION(pri_mi2s_ws), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss), + FUNCTION(qlink_enable), + FUNCTION(qlink_request), + FUNCTION(qua_mi2s), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup_l4), + FUNCTION(qup_l5), + FUNCTION(qup_l6), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sdc4_data), + FUNCTION(sd_write), + FUNCTION(sec_mi2s), + FUNCTION(ter_mi2s), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tsif1_clk), + FUNCTION(tsif1_data), + FUNCTION(tsif1_en), + FUNCTION(tsif1_error), + FUNCTION(tsif1_sync), + FUNCTION(tsif2_clk), + FUNCTION(tsif2_data), + FUNCTION(tsif2_en), + FUNCTION(tsif2_error), + FUNCTION(tsif2_sync), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(uim_batt), + FUNCTION(usb_phy), + FUNCTION(vfr_1), + FUNCTION(vsense_trigger), + FUNCTION(wlan1_adc0), + FUNCTION(wlan1_adc1), + FUNCTION(wlan2_adc0), + FUNCTION(wlan2_adc1), + FUNCTION(wsa_clk), + FUNCTION(wsa_data), +}; + +/* + * Each pin is individually controlled by its own group and gpios that cannot + * be requested are represented by the PINGROUP_DUMMY macro so that the group + * numbers and names correspond to their respective gpio. These dummy pins do + * not have a valid set of pinfuncs or a valid ctl_reg and should not be + * requested. + */ +static const struct msm_pingroup sdm670_groups[] = { + PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _), + PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _), + PINGROUP(8, WEST, qup_l4, gp_pdm1, ddr_bist, _, _, _, _, _, _), + PINGROUP(9, WEST, qup_l5, ddr_bist, _, _, _, _, _, _, _), + PINGROUP(10, NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _), + PINGROUP(11, NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _), + PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _), + PINGROUP(13, WEST, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _), + PINGROUP(14, WEST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), + PINGROUP(15, WEST, cam_mclk, qdss, _, _, _, _, _, _, _), + PINGROUP(16, WEST, cam_mclk, qdss, _, _, _, _, _, _, _), + PINGROUP(17, WEST, cci_i2c, qup1, qdss, _, _, _, _, _, _), + PINGROUP(18, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(19, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(20, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(21, WEST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _), + PINGROUP(22, WEST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _), + PINGROUP(23, WEST, cci_timer2, qdss, _, _, _, _, _, _, _), + PINGROUP(24, WEST, cci_timer3, cci_async, qdss, _, _, _, _, _, _), + PINGROUP(25, WEST, cci_timer4, cci_async, qdss, _, _, _, _, _, _), + PINGROUP(26, WEST, cci_async, qdss, jitter_bist, _, _, _, _, _, _), + PINGROUP(27, WEST, qup2, qdss, pll_bist, _, _, _, _, _, _), + PINGROUP(28, WEST, qup2, qdss, agera_pll, _, _, _, _, _, _), + PINGROUP(29, WEST, qup2, _, phase_flag, qdss, atest_tsens, _, _, _, _), + PINGROUP(30, WEST, qup2, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(31, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(32, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(33, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(34, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(35, NORTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _), + PINGROUP(36, NORTH, pci_e0, qup_l5, pll_bist, _, _, _, _, _, _), + PINGROUP(37, NORTH, qup_l6, agera_pll, _, _, _, _, _, _, _), + PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _), + PINGROUP(39, NORTH, lpass_slimbus, _, _, _, _, _, _, _, _), + PINGROUP(40, NORTH, sd_write, tsif1_error, _, _, _, _, _, _, _), + PINGROUP(41, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(42, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(43, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(44, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(45, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(46, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(47, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(48, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _), + PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _), + PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _), + PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _), + PINGROUP(54, NORTH, qup10, gp_pdm0, phase_flag, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), + PINGROUP(55, NORTH, qup10, phase_flag, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _), + PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _), + PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _), + PINGROUP_DUMMY(58), + PINGROUP_DUMMY(59), + PINGROUP_DUMMY(60), + PINGROUP_DUMMY(61), + PINGROUP_DUMMY(62), + PINGROUP_DUMMY(63), + PINGROUP_DUMMY(64), + PINGROUP(65, NORTH, pri_mi2s, qup8, wsa_clk, _, _, _, _, _, _), + PINGROUP(66, NORTH, pri_mi2s_ws, qup8, wsa_data, gp_pdm1, _, _, _, _, _), + PINGROUP(67, NORTH, pri_mi2s, qup8, _, atest_usb2, _, _, _, _, _), + PINGROUP(68, NORTH, pri_mi2s, qup8, _, atest_usb23, _, _, _, _, _), + PINGROUP_DUMMY(69), + PINGROUP_DUMMY(70), + PINGROUP_DUMMY(71), + PINGROUP_DUMMY(72), + PINGROUP_DUMMY(73), + PINGROUP_DUMMY(74), + PINGROUP(75, NORTH, ter_mi2s, phase_flag, qdss, atest_usb22, qup_l4, _, _, _, _), + PINGROUP(76, NORTH, ter_mi2s, phase_flag, qdss, atest_usb21, qup_l5, _, _, _, _), + PINGROUP(77, NORTH, ter_mi2s, phase_flag, qdss, atest_usb20, qup_l6, _, _, _, _), + PINGROUP(78, NORTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _), + PINGROUP(79, NORTH, sec_mi2s, gp_pdm2, _, qdss, _, _, _, _, _), + PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _), + PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _), + PINGROUP(85, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(86, SOUTH, qup5, copy_gp, _, _, _, _, _, _, _), + PINGROUP(87, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(88, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(89, SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag, _, _, _, _, _), + PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti), + PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, _, qdss_cti, _, _, _), + PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, vfr_1, tgu_ch2, _, _, _, _), + PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, _, qdss, _, _, _, _), + PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, _, _, _, _, _, _), + PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, gp_pdm0, _, _, _, _, _), + PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _), + PINGROUP(97, WEST, _, _, mdp_vsync, ldo_en, _, _, _, _, _), + PINGROUP(98, WEST, _, mdp_vsync, ldo_update, _, _, _, _, _, _), + PINGROUP(99, NORTH, phase_flag, prng_rosc, _, _, _, _, _, _, _), + PINGROUP(100, WEST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(101, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(102, WEST, pci_e1, prng_rosc, _, _, _, _, _, _, _), + PINGROUP(103, WEST, pci_e1, copy_phase, _, _, _, _, _, _, _), + PINGROUP_DUMMY(104), + PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _), + PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _), + PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _), + PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _), + PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _), + PINGROUP(114, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + PINGROUP(115, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + PINGROUP(116, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _), + PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(122, NORTH, _, qdss, _, _, _, _, _, _, _), + PINGROUP(123, NORTH, qup_l4, _, qdss, _, _, _, _, _, _), + PINGROUP(124, NORTH, qup_l5, _, qdss, _, _, _, _, _, _), + PINGROUP(125, NORTH, qup_l6, _, _, _, _, _, _, _, _), + PINGROUP(126, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(128, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _), + PINGROUP(129, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _), + PINGROUP(130, WEST, qlink_request, _, _, _, _, _, _, _, _), + PINGROUP(131, WEST, qlink_enable, _, _, _, _, _, _, _, _), + PINGROUP(132, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _), + PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(137, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(138, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(139, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(140, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(141, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(142, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(143, WEST, _, nav_pps, nav_pps, gps_tx, phase_flag, _, _, _, _), + PINGROUP(144, SOUTH, mss_lte, _, _, _, _, _, _, _, _), + PINGROUP(145, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _), + PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), + UFS_RESET(ufs_reset, 0x99d000), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x99000, 15, 0), + SDC_QDSD_PINGROUP(sdc1_clk, 0x99000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x99000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x99000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x9a000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x9a000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x9a000, 9, 0), +}; + +const int sdm670_reserved_gpios[] = { + 58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1 +}; + +static const struct msm_pinctrl_soc_data sdm670_pinctrl = { + .pins = sdm670_pins, + .npins = ARRAY_SIZE(sdm670_pins), + .functions = sdm670_functions, + .nfunctions = ARRAY_SIZE(sdm670_functions), + .groups = sdm670_groups, + .ngroups = ARRAY_SIZE(sdm670_groups), + .ngpios = 151, + .reserved_gpios = sdm670_reserved_gpios, +}; + +static int sdm670_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdm670_pinctrl); +} + +static const struct of_device_id sdm670_pinctrl_of_match[] = { + { .compatible = "qcom,sdm670-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sdm670_pinctrl_of_match); + +static struct platform_driver sdm670_pinctrl_driver = { + .driver = { + .name = "sdm670-pinctrl", + .of_match_table = sdm670_pinctrl_of_match, + }, + .probe = sdm670_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdm670_pinctrl_init(void) +{ + return platform_driver_register(&sdm670_pinctrl_driver); +} +arch_initcall(sdm670_pinctrl_init); + +static void __exit sdm670_pinctrl_exit(void) +{ + platform_driver_unregister(&sdm670_pinctrl_driver); +} +module_exit(sdm670_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm SDM670 TLMM pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From aef1bef2dfdd6e1bf003cb745eb3941bca01b714 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Sat, 8 Oct 2022 18:48:06 +0200 Subject: pinctrl: mt7986: allow configuring uart rx/tx and rts/cts separately Some mt7986 boards use uart rts/cts pins as gpio, This patch allows to change rts/cts to gpio mode, but keep rx/tx as UART function. Signed-off-by: Frank Wunderlich Signed-off-by: Sam Shih Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index f26869f1a367..95f32e62e02f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; -static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; -static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; +static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; +static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; -static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; -static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; +static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; +static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; + +static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; +static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; + +static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; +static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; @@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = { 1, }; static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; +static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; +static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; + +static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; +static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; + static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; @@ -749,6 +761,8 @@ static const struct group_desc mt7986_groups[] = { PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), PINCTRL_PIN_GROUP("i2c", mt7986_i2c), PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), + PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), + PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), @@ -760,8 +774,10 @@ static const struct group_desc mt7986_groups[] = { PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), - PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), - PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), + PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), + PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), + PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), + PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), PINCTRL_PIN_GROUP("spi0", mt7986_spi0), PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), @@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", }; static const char *mt7986_spi_groups[] = { "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; static const char *mt7986_uart_groups[] = { - "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", + "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", + "uart1_2_rx_tx", "uart1_2_cts_rts", + "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", "uart2_0", "uart2_1", "uart0", "uart1", "uart2", }; static const char *mt7986_wdt_groups[] = { "watchdog", }; -- cgit v1.2.3 From fcd7631748575706210ef05a787fccbeb4d79898 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Fri, 7 Oct 2022 08:16:46 -0700 Subject: pinctrl: at91-pio4: Add configuration to userspace Adding support for line bias flags that have been implented in gpio API. There are functions in the gpiod library that can control line bias from userspace this adds that functionality to this driver. Adding .pin_config_set allows the driver's pin configuration to be accessed from userspace. The general idea for this as been taken from stm32, intel, and rockchip drivers that have userspace access for bias flags. Signed-off-by: Ryan Wanner Tested-by: Nicolas Ferre # on sama5d27 som1 ek Acked-by: Nicolas Ferre Tested-by: Nicolas Ferre Link: https://lore.kernel.org/r/20221007151647.98222-2-Ryan.Wanner@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91-pio4.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 82b921fd630d..a7383b9a309e 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -897,6 +897,25 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, return 0; } +static int atmel_conf_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin); + + return atmel_conf_pin_config_group_set(pctldev, grp->pin, configs, num_configs); +} + +static int atmel_conf_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs) +{ + struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin); + + return atmel_conf_pin_config_group_get(pctldev, grp->pin, configs); +} + static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin_id) @@ -944,6 +963,8 @@ static const struct pinconf_ops atmel_confops = { .pin_config_group_get = atmel_conf_pin_config_group_get, .pin_config_group_set = atmel_conf_pin_config_group_set, .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, + .pin_config_set = atmel_conf_pin_config_set, + .pin_config_get = atmel_conf_pin_config_get, }; static struct pinctrl_desc atmel_pinctrl_desc = { @@ -1134,6 +1155,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) atmel_pioctrl->gpio_chip->label = dev_name(dev); atmel_pioctrl->gpio_chip->parent = dev; atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; + atmel_pioctrl->gpio_chip->set_config = gpiochip_generic_config; atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev, atmel_pioctrl->nbanks, -- cgit v1.2.3 From eaa4c8f953ba1d2eafb1c961aa9321beb71f21c9 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Fri, 7 Oct 2022 08:16:47 -0700 Subject: pinctrl: at91-pio4: Add persist state case in config Adding persist state case to atmel_conf_pin_config_group_set() function. After adding configuration support for userspace gpiod api, there was an extra flag PIN_CONFIG_PERSIST_STATE that was not passed in before. Based on other drivers like TI drivers, added a switch case and return ENOTSUPP in that case. Signed-off-by: Ryan Wanner Acked-by: Nicolas Ferre Tested-by: Nicolas Ferre Link: https://lore.kernel.org/r/20221007151647.98222-3-Ryan.Wanner@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91-pio4.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index a7383b9a309e..2287e3fa64bf 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -775,6 +775,8 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, return -EINVAL; arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET; break; + case PIN_CONFIG_PERSIST_STATE: + return -ENOTSUPP; default: return -ENOTSUPP; } @@ -883,6 +885,8 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n"); } break; + case PIN_CONFIG_PERSIST_STATE: + return -ENOTSUPP; default: dev_warn(pctldev->dev, "unsupported configuration parameter: %u\n", -- cgit v1.2.3 From 9b3148d6d626d484fd038d25409602190d89eee7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 10 Oct 2022 15:52:20 +0300 Subject: pinctrl: cy8c95x0: Extract cy8c95x0_set_mode() helper The code in newly introduced cy8c95x0_set_mode() helper may be used later on by another function. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221010125221.28275-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 68509a2301b8..33eba7ad87f4 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1124,9 +1124,7 @@ static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned in return 0; } -static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip, - unsigned int val, - unsigned long off) +static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) { u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); @@ -1137,7 +1135,20 @@ static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip, if (ret < 0) return ret; - ret = regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, val ? bit : 0); + return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0); +} + +static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, + unsigned int selector, unsigned int group) +{ + u8 port = cypress_get_port(chip, group); + u8 bit = cypress_get_pin_mask(chip, group); + int ret; + + if (selector == 0) + return cy8c95x0_set_mode(chip, group, false); + + ret = cy8c95x0_set_mode(chip, group, true); if (ret < 0) return ret; @@ -1156,7 +1167,7 @@ static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, int ret; mutex_lock(&chip->i2c_lock); - ret = cy8c95x0_pinmux_cfg(chip, selector, group); + ret = cy8c95x0_pinmux_mode(chip, selector, group); mutex_unlock(&chip->i2c_lock); return ret; -- cgit v1.2.3 From a039dfb96ad24666d6947b8ab631449441152efe Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 10 Oct 2022 15:52:21 +0300 Subject: pinctrl: cy8c95x0: Implement ->gpio_request_enable() and ->gpio_set_direction() Without ->gpio_request_enable() and ->gpio_set_direction() callbacks it's not possible to mux GPIO via standard GPIO interfaces (like `gpioget` or `gpioset` tools in user space). Implement those functions to fill the above mentioned gap. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221010125221.28275-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 112 ++++++++++++++++++++++--------------- 1 file changed, 68 insertions(+), 44 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 33eba7ad87f4..b44b36be54b3 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -21,9 +21,10 @@ #include #include -#include +#include #include #include +#include #include /* Fast access registers */ @@ -551,36 +552,7 @@ out: static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) { - struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); - u8 port = cypress_get_port(chip, off); - u8 bit = cypress_get_pin_mask(chip, off); - int ret; - - mutex_lock(&chip->i2c_lock); - ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); - if (ret) - goto out; - - ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit); - if (ret) - goto out; - - if (test_bit(off, chip->push_pull)) { - /* - * Disable driving the pin by forcing it to HighZ. Only setting the - * direction register isn't sufficient in Push-Pull mode. - */ - ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); - if (ret) - goto out; - - __clear_bit(off, chip->push_pull); - } - -out: - mutex_unlock(&chip->i2c_lock); - - return ret; + return pinctrl_gpio_direction_input(gc->base + off); } static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, @@ -597,19 +569,7 @@ static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, if (ret) return ret; - mutex_lock(&chip->i2c_lock); - /* Select port... */ - ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); - if (ret) - goto out; - - /* ...then direction */ - ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, 0); - -out: - mutex_unlock(&chip->i2c_lock); - - return ret; + return pinctrl_gpio_direction_output(gc->base + off); } static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) @@ -850,6 +810,8 @@ static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) { struct gpio_chip *gc = &chip->gpio_chip; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; gc->direction_input = cy8c95x0_gpio_direction_input; gc->direction_output = cy8c95x0_gpio_direction_output; gc->get = cy8c95x0_gpio_get_value; @@ -1173,11 +1135,73 @@ static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, return ret; } +static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); + int ret; + + mutex_lock(&chip->i2c_lock); + ret = cy8c95x0_set_mode(chip, pin, false); + mutex_unlock(&chip->i2c_lock); + + return ret; +} + +static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, + unsigned int pin, bool input) +{ + u8 port = cypress_get_port(chip, pin); + u8 bit = cypress_get_pin_mask(chip, pin); + int ret; + + /* Select port... */ + ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); + if (ret) + return ret; + + /* ...then direction */ + ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0); + if (ret) + return ret; + + /* + * Disable driving the pin by forcing it to HighZ. Only setting + * the direction register isn't sufficient in Push-Pull mode. + */ + if (input && test_bit(pin, chip->push_pull)) { + ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); + if (ret) + return ret; + + __clear_bit(pin, chip->push_pull); + } + + return 0; +} + +static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); + int ret; + + mutex_lock(&chip->i2c_lock); + ret = cy8c95x0_pinmux_direction(chip, pin, input); + mutex_unlock(&chip->i2c_lock); + + return ret; +} + static const struct pinmux_ops cy8c95x0_pmxops = { .get_functions_count = cy8c95x0_get_functions_count, .get_function_name = cy8c95x0_get_function_name, .get_function_groups = cy8c95x0_get_function_groups, .set_mux = cy8c95x0_set_mux, + .gpio_request_enable = cy8c95x0_gpio_request_enable, + .gpio_set_direction = cy8c95x0_gpio_set_direction, .strict = true, }; -- cgit v1.2.3 From 1d81689d9f3f77a7272dfd1670ad4ebd029ed22a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 10 Oct 2022 10:56:15 +0300 Subject: pinctrl: st: Switch to use fwnode instead of of_node The OF node in the GPIO library is deprecated and soon will be removed. GPIO library now accepts fwnode as a firmware node, so switch the driver to use it. Signed-off-by: Andy Shevchenko Reviewed-by: Patrice Chotard Reviewed-by: Dmitry Torokhov Link: https://lore.kernel.org/r/20221010075615.43244-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index cf7f9cbe6044..987878c83349 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1175,7 +1175,7 @@ static int st_pctl_dt_calculate_pin(struct st_pinctrl *info, for (i = 0; i < info->nbanks; i++) { chip = &info->banks[i].gpio_chip; - if (chip->of_node == np) { + if (chip->fwnode == of_fwnode_handle(np)) { if (offset < chip->ngpio) retval = chip->base + offset; break; @@ -1518,7 +1518,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, bank->gpio_chip = st_gpio_template; bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; - bank->gpio_chip.of_node = np; + bank->gpio_chip.fwnode = of_fwnode_handle(np); bank->gpio_chip.parent = dev; spin_lock_init(&bank->lock); -- cgit v1.2.3 From 1d66e379731f79ae5039a869c0fde22a4f6a6a91 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 13 Oct 2022 08:47:29 -0500 Subject: pinctrl: amd: Add dynamic debugging for active GPIOs Some laptops have been reported to wake up from s2idle when plugging in the AC adapter or by closing the lid. This is a surprising behavior that is further clarified by commit cb3e7d624c3ff ("PM: wakeup: Add extra debugging statement for multiple active IRQs"). With that commit in place the following interaction can be seen when the lid is closed: [ 28.946038] PM: suspend-to-idle [ 28.946083] ACPI: EC: ACPI EC GPE status set [ 28.946101] ACPI: PM: Rearming ACPI SCI for wakeup [ 28.950152] Timekeeping suspended for 3.320 seconds [ 28.950152] PM: Triggering wakeup from IRQ 9 [ 28.950152] ACPI: EC: ACPI EC GPE status set [ 28.950152] ACPI: EC: ACPI EC GPE dispatched [ 28.995057] ACPI: EC: ACPI EC work flushed [ 28.995075] ACPI: PM: Rearming ACPI SCI for wakeup [ 28.995131] PM: Triggering wakeup from IRQ 9 [ 28.995271] ACPI: EC: ACPI EC GPE status set [ 28.995291] ACPI: EC: ACPI EC GPE dispatched [ 29.098556] ACPI: EC: ACPI EC work flushed [ 29.207020] ACPI: EC: ACPI EC work flushed [ 29.207037] ACPI: PM: Rearming ACPI SCI for wakeup [ 29.211095] Timekeeping suspended for 0.739 seconds [ 29.211095] PM: Triggering wakeup from IRQ 9 [ 29.211079] PM: Triggering wakeup from IRQ 7 [ 29.211095] ACPI: PM: ACPI non-EC GPE wakeup [ 29.211095] PM: resume from suspend-to-idle * IRQ9 on this laptop is used for the ACPI SCI. * IRQ7 on this laptop is used for the GPIO controller. What has occurred is when the lid was closed the EC woke up the SoC from it's deepest sleep state and the kernel's s2idle loop processed all EC events. When it was finished processing EC events, it checked for any other reasons to wake (break the s2idle loop). The IRQ for the GPIO controller was active so the loop broke, and then this IRQ was processed. This is not a kernel bug but it is certainly a surprising behavior, and to better debug it we should have a dynamic debugging message that we can enact to catch it. Acked-by: Basavaraj Natikar Acked-by: Kai-Heng Feng Acked-by: Mark Pearson Signed-off-by: Mario Limonciello Link: https://lore.kernel.org/r/20221013134729.5592-2-mario.limonciello@amd.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 6be896871718..9bc6e3922e78 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -628,13 +628,15 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) /* Each status bit covers four pins */ for (i = 0; i < 4; i++) { regval = readl(regs + i); - /* caused wake on resume context for shared IRQ */ - if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) { + + if (regval & PIN_IRQ_PENDING) dev_dbg(&gpio_dev->pdev->dev, - "Waking due to GPIO %d: 0x%x", + "GPIO %d is active: 0x%x", irqnr + i, regval); + + /* caused wake on resume context for shared IRQ */ + if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) return true; - } if (!(regval & PIN_IRQ_PENDING) || !(regval & BIT(INTERRUPT_MASK_OFF))) -- cgit v1.2.3 From 417c326091b06eadb93511e638e8c36230dae2e6 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 18 Oct 2022 18:12:23 +0300 Subject: pinctrl: cy8c95x0: Don't use cy8c95x0_set_mode() twice Instead, call it once in cy8c95x0_pinmux_mode() and if selector is 0, shortcut the flow by returning 0 immediately. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221018151223.80846-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-cy8c95x0.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index b44b36be54b3..ee753e080481 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1107,13 +1107,13 @@ static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, u8 bit = cypress_get_pin_mask(chip, group); int ret; - if (selector == 0) - return cy8c95x0_set_mode(chip, group, false); - - ret = cy8c95x0_set_mode(chip, group, true); + ret = cy8c95x0_set_mode(chip, group, selector); if (ret < 0) return ret; + if (selector == 0) + return 0; + /* Set direction to output & set output to 1 so that PWM can work */ ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit); if (ret < 0) -- cgit v1.2.3 From dbbd909eeb26037fc38a4d29d6d94f7c39631a5e Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 20 Oct 2022 15:56:50 +0800 Subject: pinctrl: qcom: sdm670: change sdm670_reserved_gpios to static sdm670_reserved_gpios is only used in pinctrl-sdm670.c now, change it to static. Fixes: 61164d220f52 ("pinctrl: qcom: add sdm670 pinctrl") Signed-off-by: Yang Yingliang Link: https://lore.kernel.org/r/20221020075650.1031228-1-yangyingliang@huawei.com Acked-by: Richard Acayan [Fix up subject] Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-sdm670.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c index 4c3c3782fef8..b888bca7ecd7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c @@ -1294,7 +1294,7 @@ static const struct msm_pingroup sdm670_groups[] = { SDC_QDSD_PINGROUP(sdc2_data, 0x9a000, 9, 0), }; -const int sdm670_reserved_gpios[] = { +static const int sdm670_reserved_gpios[] = { 58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1 }; -- cgit v1.2.3 From 4c0c5bbc89cda1c57ce0fb36d917693396b8b065 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: actions: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-owl.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index ed46abc15d72..a84ace6e451e 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -17,13 +17,15 @@ #include #include #include +#include +#include +#include + #include +#include +#include #include #include -#include -#include -#include -#include #include "../core.h" #include "../pinctrl-utils.h" -- cgit v1.2.3 From fb0ca836f9b8c61e6a01b58f4979d3c421dd1eb6 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: apple-gpio: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-apple-gpio.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 2490384ef1b8..3751c7de37aa 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -11,6 +11,8 @@ */ #include + +#include #include #include #include @@ -18,11 +20,12 @@ #include #include #include -#include -#include #include #include +#include +#include + #include "pinctrl-utils.h" #include "core.h" #include "pinmux.h" -- cgit v1.2.3 From 52240f91f71725782ed79391efb861db5ff68174 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: aspeed: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index a30912a92f05..3945612900e6 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include "../core.h" -- cgit v1.2.3 From 9ace1002c854a3df07dde113c614c7c1ebe5e18f Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: at91: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij Reviewed-by: Claudiu Beznea --- drivers/pinctrl/pinctrl-at91-pio4.c | 10 +++++++--- drivers/pinctrl/pinctrl-at91.c | 16 +++++++++------- 2 files changed, 16 insertions(+), 10 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 82b921fd630d..e38c683aba09 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -7,18 +7,22 @@ */ #include + #include #include +#include #include #include -#include #include #include -#include +#include +#include + #include +#include #include #include -#include + #include "core.h" #include "pinconf.h" #include "pinctrl-utils.h" diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 81dbffab621f..1e1813d7c550 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -7,22 +7,24 @@ #include #include +#include #include +#include +#include #include -#include #include +#include #include +#include +#include #include -#include -#include -#include + +/* Since we request GPIOs from ourself */ +#include #include #include #include #include -/* Since we request GPIOs from ourself */ -#include -#include #include "pinctrl-at91.h" #include "core.h" -- cgit v1.2.3 From 20ce95528f73ded5b80c202b40be86fe0d2af4eb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: axp209: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij Acked-by: Chen-Yu Tsai --- drivers/pinctrl/pinctrl-axp209.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 7ab20ac15391..0bc1b381a2b8 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -16,13 +16,15 @@ #include #include #include -#include -#include -#include #include #include #include +#include +#include +#include +#include + #define AXP20X_GPIO_FUNCTIONS 0x7 #define AXP20X_GPIO_FUNCTION_OUT_LOW 0 #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1 -- cgit v1.2.3 From eebefdd0b7796c4be5c87fa2ab51aca2568835b1 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: bcm: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm281xx.c | 13 ++++++++----- drivers/pinctrl/bcm/pinctrl-cygnus-mux.c | 9 ++++++--- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 12 +++++++----- drivers/pinctrl/bcm/pinctrl-ns2-mux.c | 8 +++++--- drivers/pinctrl/bcm/pinctrl-nsp-mux.c | 8 +++++--- 5 files changed, 31 insertions(+), 19 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index fd52a83387ef..73dbf29c002f 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -2,16 +2,19 @@ // Copyright (C) 2013-2017 Broadcom #include -#include #include +#include #include #include -#include -#include -#include -#include #include +#include #include + +#include +#include +#include +#include + #include "../core.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c index 5251460f6327..bf9597800954 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c @@ -13,12 +13,15 @@ #include #include #include -#include #include +#include +#include + +#include +#include #include #include -#include -#include + #include "../core.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 52fa2f4cd618..3df56a4ea510 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -16,17 +16,19 @@ * SoCs IOMUX controller. */ -#include -#include +#include #include #include -#include #include +#include #include #include -#include -#include +#include + +#include #include +#include +#include #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c index 960e253f0be4..04f4fca854cc 100644 --- a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c @@ -9,12 +9,14 @@ #include #include #include -#include +#include +#include +#include + #include +#include #include #include -#include -#include #include "../core.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c index db8f79920ff0..eb6298507c1d 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c @@ -20,12 +20,14 @@ #include #include #include -#include +#include +#include +#include + #include +#include #include #include -#include -#include #include "../core.h" #include "../pinctrl-utils.h" -- cgit v1.2.3 From 810644cc7cceba03ca4f762ae12c51879743a9f2 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: bm1880: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-bm1880.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index a8e267237435..b0000fe5b31d 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -9,10 +9,12 @@ #include #include #include +#include + +#include +#include #include #include -#include -#include #include "core.h" #include "pinctrl-utils.h" -- cgit v1.2.3 From 65f9d85880480b01982d0a97b7a0d5cda25ca489 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: cirrus: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/cirrus/pinctrl-madera-core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c index e1cfbee3643a..bb589922d8c5 100644 --- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c +++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c @@ -10,13 +10,14 @@ #include #include #include +#include #include #include +#include +#include #include #include -#include -#include #include #include -- cgit v1.2.3 From 9c0c752591923769b60f899e2f3d8d20e277213b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: cy8c95x0: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 68509a2301b8..5eb5521636fe 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From b7348441f7e28359f3d0cef033caf800a032a041 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: gemini: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-gemini.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index 5870956a993a..631612539af7 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -10,14 +10,16 @@ #include #include #include +#include +#include +#include +#include + #include +#include +#include #include #include -#include -#include -#include -#include -#include #include "pinctrl-utils.h" -- cgit v1.2.3 From 6e8bc379033348ac296ba81fb60cb61ae60c85aa Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: imx: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 8 +++++--- drivers/pinctrl/freescale/pinctrl-imx1-core.c | 4 +++- drivers/pinctrl/freescale/pinctrl-mxs.c | 7 +++++-- 3 files changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 3a7d2de10b13..e9aef764138f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -13,14 +13,16 @@ #include #include #include -#include #include +#include +#include +#include +#include + #include #include #include #include -#include -#include #include "../core.h" #include "../pinconf.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index 70186448d2f4..3726c0ac2560 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -16,11 +16,13 @@ #include #include #include +#include +#include + #include #include #include #include -#include #include "../core.h" #include "pinctrl-imx1.h" diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c index 735cedd0958a..9f78c9b29ddd 100644 --- a/drivers/pinctrl/freescale/pinctrl-mxs.c +++ b/drivers/pinctrl/freescale/pinctrl-mxs.c @@ -7,12 +7,15 @@ #include #include #include +#include +#include +#include + #include #include #include #include -#include -#include + #include "../core.h" #include "pinctrl-mxs.h" -- cgit v1.2.3 From 9b69b7d721f0aa3245c2a48650a3045ba59f9b66 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: ingenic: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Acked-by: Linus Walleij Reviewed-by: Paul Cercueil --- drivers/pinctrl/pinctrl-ingenic.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 7e732076dedf..dbc25a60fbff 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -14,16 +14,18 @@ #include #include #include -#include -#include -#include -#include #include #include #include #include #include +#include +#include +#include +#include +#include + #include "core.h" #include "pinconf.h" #include "pinmux.h" -- cgit v1.2.3 From 93c9dc90f991ce3660f5ed0daf40d3c54b3e0dd4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: k210: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Damien Le Moal --- drivers/pinctrl/pinctrl-k210.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index ecab6bf63dc6..288e44457fec 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -3,18 +3,20 @@ * Copyright (C) 2020 Sean Anderson * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ -#include -#include +#include #include +#include #include +#include #include -#include #include +#include #include + +#include +#include #include #include -#include -#include #include -- cgit v1.2.3 From d854028a1f642fc89ffb54bea838e424657ed89a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: lantiq: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-falcon.c | 9 +++++---- drivers/pinctrl/pinctrl-lantiq.c | 5 +++-- drivers/pinctrl/pinctrl-lantiq.h | 7 ++++--- 3 files changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index 7521a924dffb..2eab14f86fa3 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -7,17 +7,18 @@ * Copyright (C) 2012 John Crispin */ +#include +#include #include #include -#include -#include -#include #include #include -#include #include #include +#include #include +#include +#include #include "pinctrl-lantiq.h" diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index 626e02d7a1ba..7145b8b0dfd4 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -6,12 +6,13 @@ * Copyright (C) 2012 John Crispin */ -#include #include #include +#include +#include #include +#include #include -#include #include "pinctrl-lantiq.h" diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h index c1f80886d1a8..efb25fc34f14 100644 --- a/drivers/pinctrl/pinctrl-lantiq.h +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -10,11 +10,12 @@ #define __PINCTRL_LANTIQ_H #include -#include -#include -#include + #include #include +#include +#include +#include #include "core.h" -- cgit v1.2.3 From b2fd05c7f746f58bc98516c7668f80e6f96477b5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: lochnagar: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Acked-by: Charles Keepax --- drivers/pinctrl/cirrus/pinctrl-lochnagar.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c index 3fda4446d70b..0b78cf611afe 100644 --- a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c +++ b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c @@ -15,10 +15,12 @@ #include #include #include + +#include +#include +#include #include #include -#include -#include #include #include -- cgit v1.2.3 From c2ecb0273c2026844c8921375c42ddbac8bec16a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: lpc18xx: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-lpc18xx.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index ed9bf2c89998..13c041dd2ce0 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -10,13 +10,15 @@ #include #include -#include #include +#include #include #include + +#include +#include #include #include -#include #include "core.h" #include "pinctrl-utils.h" -- cgit v1.2.3 From 9abef9f2edde2fca79fd0cffb0771727defce6b3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: mediatek: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-moore.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-paris.c | 5 +++++ 2 files changed, 8 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 526faaebaf77..9474ada5addb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -9,6 +9,9 @@ */ #include + +#include + #include "pinctrl-moore.h" #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 74517e810958..475f4172d508 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -11,7 +11,12 @@ #include #include +#include + +#include + #include + #include "pinctrl-paris.h" #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME -- cgit v1.2.3 From 54da3e1be32d4cab06e19afad36ef315782d2bdc Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: microchip-sgpio: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-microchip-sgpio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index af27b72c8958..4794602316e7 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -15,13 +15,15 @@ #include #include #include -#include #include #include #include #include #include +#include +#include + #include "core.h" #include "pinconf.h" -- cgit v1.2.3 From b1a3bd1c67c77d2daf0ed6d8cae8b0c9f5e86128 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: mvebu: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/mvebu/pinctrl-mvebu.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 8ef0a97d2bf5..8e6aac4164df 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -6,20 +6,22 @@ * Thomas Petazzoni */ -#include -#include +#include +#include #include +#include #include #include #include -#include -#include +#include +#include +#include +#include + #include #include #include #include -#include -#include #include "pinctrl-mvebu.h" -- cgit v1.2.3 From 6272cc50bfb70ccffd385364a301d4730d2fe64f Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: npcm7xx: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 1c4e89b046de..ff5bcea172e8 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -11,14 +11,17 @@ #include #include #include +#include +#include +#include +#include + +#include #include -#include #include +#include #include #include -#include -#include -#include /* GCR registers */ #define NPCM7XX_GCR_PDID 0x00 -- cgit v1.2.3 From 8be7f6c8d1aaf5cf5138121e7081b33155da0256 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: ocelot: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Acked-by: Horatiu Vultur --- drivers/pinctrl/pinctrl-ocelot.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 62ce3957abe4..35087059cd82 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -14,15 +14,17 @@ #include #include #include -#include -#include -#include -#include #include #include #include #include +#include +#include +#include +#include +#include + #include "core.h" #include "pinconf.h" #include "pinmux.h" -- cgit v1.2.3 From aa9430f8a6de9b56247b9d0316801d87c20b6779 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: qcom: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 4 ++++ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 9 +++++++-- drivers/pinctrl/qcom/pinctrl-msm.c | 25 ++++++++++++++----------- drivers/pinctrl/qcom/pinctrl-msm.h | 5 +++++ drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 8 +++++--- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 8 +++++--- drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 18 ++++++++++-------- drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 18 ++++++++++-------- 8 files changed, 60 insertions(+), 35 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index e97ce45b6d53..d5cfa91e2eff 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -8,10 +8,14 @@ #include #include #include +#include + #include #include #include + #include "../pinctrl-utils.h" + #include "pinctrl-lpass-lpi.h" #define MAX_LPI_NUM_CLKS 2 diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index afbac2a6c82c..29047bb80bb8 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -6,10 +6,15 @@ #ifndef __PINCTRL_LPASS_LPI_H__ #define __PINCTRL_LPASS_LPI_H__ -#include -#include +#include +#include + #include "../core.h" +struct platform_device; + +struct pinctrl_pin_desc; + #define LPI_SLEW_RATE_CTL_REG 0xa000 #define LPI_TLMM_REG_OFFSET 0x1000 #define LPI_SLEW_RATE_MAX 0x03 diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index a2abfe987ab1..1cbd2593af47 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -6,31 +6,34 @@ #include #include +#include +#include #include +#include #include #include #include +#include +#include +#include +#include +#include +#include + #include +#include +#include #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include #include "../core.h" #include "../pinconf.h" -#include "pinctrl-msm.h" #include "../pinctrl-utils.h" +#include "pinctrl-msm.h" + #define MAX_NR_GPIO 300 #define MAX_NR_TILES 4 #define PS_HOLD_OFFSET 0x820 diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index dd0d949f7a9e..05a1209bf9ae 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -5,6 +5,11 @@ #ifndef __PINCTRL_MSM_H__ #define __PINCTRL_MSM_H__ +#include +#include + +struct platform_device; + struct pinctrl_pin_desc; /** diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 8c31a8f6b7e4..89695b5a2ce7 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -9,15 +9,17 @@ #include #include #include -#include -#include -#include #include #include +#include #include #include #include +#include +#include +#include + #include #include "../core.h" diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 6937157f50b3..063177b79927 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -7,14 +7,16 @@ #include #include #include -#include -#include -#include #include #include +#include #include #include +#include +#include +#include + #include #include "../core.h" diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 1b41adda8129..b1748791a01e 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -4,18 +4,20 @@ * Copyright (c) 2013, The Linux Foundation. All rights reserved. */ -#include -#include -#include -#include -#include -#include -#include -#include #include #include +#include #include #include +#include +#include +#include +#include + +#include +#include +#include +#include #include diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 49893a5133a8..30a934245c1b 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -4,18 +4,20 @@ * Copyright (c) 2013, The Linux Foundation. All rights reserved. */ -#include -#include -#include -#include -#include -#include -#include -#include #include #include +#include #include #include +#include +#include +#include +#include + +#include +#include +#include +#include #include -- cgit v1.2.3 From 2fb98ab403720f2ddd731cdebdf706c5be3b3c24 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: renesas: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 7 +++++-- drivers/pinctrl/renesas/pinctrl-rzn1.c | 8 ++++++-- drivers/pinctrl/renesas/pinctrl-rzv2m.c | 4 +++- drivers/pinctrl/renesas/pinctrl.c | 8 +++++--- 4 files changed, 19 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a43824fd9505..a08eee092430 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -8,16 +8,19 @@ #include #include #include -#include #include +#include #include #include #include +#include +#include + +#include #include #include #include #include -#include #include diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c index 849d091205d4..9158c1757492 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzn1.c +++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c @@ -7,16 +7,20 @@ */ #include + #include #include #include #include #include +#include +#include + #include +#include #include #include -#include -#include + #include "../core.h" #include "../pinconf.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index e8c18198bebd..061f16c77304 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -15,11 +15,13 @@ #include #include #include +#include + +#include #include #include #include #include -#include #include diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index b438d24c13b5..b74147800319 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -12,14 +12,16 @@ #include #include #include +#include +#include +#include + #include #include -#include #include +#include #include #include -#include -#include #include "core.h" #include "../core.h" -- cgit v1.2.3 From 2420cd5f7e01674e664e07eaa826107cbdff3da9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: samsung: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-samsung.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index bd13b5ef246d..5736761927cb 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -15,15 +15,16 @@ // but provides extensions to which platform specific implementation of the gpio // and wakeup interrupts can be hooked to. -#include -#include -#include -#include -#include #include #include +#include +#include #include #include +#include +#include +#include +#include #include #include "../core.h" -- cgit v1.2.3 From 486e0d876db2f21c204cb31a076e602b25dde6c3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: single: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-single.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 67bec7ea0f8b..3a515414927e 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -16,17 +16,17 @@ #include #include #include - #include - #include #include #include #include +#include +#include +#include #include #include -#include #include -- cgit v1.2.3 From f993216dd2448c9c627416fd873663baf7be2288 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: spear: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko Acked-by: Viresh Kumar --- drivers/pinctrl/spear/pinctrl-spear.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index e0543c1ad641..18de2e70ea50 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -19,11 +19,13 @@ #include #include #include +#include +#include +#include + #include #include #include -#include -#include #include "pinctrl-spear.h" -- cgit v1.2.3 From 82a045ab274df4d5039f17f6ec547c5fcda6d07a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: sprd: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Baolin Wang --- drivers/pinctrl/sprd/pinctrl-sprd.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index dca7a505d413..ca9659f4e4b1 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -13,12 +13,15 @@ #include #include #include +#include +#include + +#include #include -#include #include +#include #include #include -#include #include "../core.h" #include "../pinmux.h" -- cgit v1.2.3 From 1635b1d8126e2d7c4030b3c5ef37e00344b88ff6 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: st: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Patrice Chotard --- drivers/pinctrl/pinctrl-st.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index cf7f9cbe6044..985dfceb127d 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -5,21 +5,26 @@ * Srinivas Kandagatla */ -#include -#include -#include #include +#include +#include #include +#include +#include #include -#include #include -#include +#include +#include #include -#include +#include +#include +#include + +#include +#include #include #include -#include -#include + #include "core.h" /* PIO Block registers */ -- cgit v1.2.3 From 042b93c9b6662b9336f1642eccd56796ff7ac56a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: starfive: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko Acked-by: Emil Renner Berthing --- drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c index 5b544fb7f3d8..a90b770821d6 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c @@ -15,8 +15,11 @@ #include #include #include +#include #include +#include +#include #include #include -- cgit v1.2.3 From 7338faa4ed0b5ec511ede43a6d4fdae52ed5851a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: stm32: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/stm32/pinctrl-stm32.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index e485506ea599..cc9472b28404 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -13,22 +13,24 @@ #include #include #include -#include #include #include +#include #include -#include -#include -#include -#include -#include -#include #include #include #include #include +#include #include +#include +#include +#include +#include +#include +#include + #include "../core.h" #include "../pinconf.h" #include "../pinctrl-utils.h" -- cgit v1.2.3 From 8f27fb48a26bff360675320fbc227ba39f559a58 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: stmfx: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-stmfx.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index ab4dde40d3ed..1181c4b506b1 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -10,6 +10,8 @@ #include #include #include +#include + #include #include -- cgit v1.2.3 From 1fe030494ebd02858d89cb13af258b3608f77af1 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: sunxi: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 6c04027d0dd9..f35179eceb4e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -10,26 +10,28 @@ * warranty of any kind, whether express or implied. */ -#include #include +#include #include #include -#include +#include #include -#include +#include #include -#include #include +#include #include #include +#include +#include +#include + #include #include -#include #include +#include +#include #include -#include -#include -#include #include -- cgit v1.2.3 From eebeeb53c580f0aeddebfc20c93ce70b7b8a5300 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: tegra: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/tegra/pinctrl-tegra-xusb.c | 7 +++++-- drivers/pinctrl/tegra/pinctrl-tegra.c | 6 ++++-- 2 files changed, 9 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index 43922ab81666..7641848be4de 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -8,12 +8,15 @@ #include #include #include -#include -#include #include #include +#include #include +#include +#include +#include + #include #include "../core.h" diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 50bd26a30ac0..834a2d50f89b 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -15,11 +15,13 @@ #include #include #include +#include +#include + #include +#include #include #include -#include -#include #include "../core.h" #include "../pinctrl-utils.h" -- cgit v1.2.3 From 2188191f7febe3fcc15e17f428f39c79c118f8f4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: ti-iodelay: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/ti/pinctrl-ti-iodelay.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 4e2382778d38..53abddaebce1 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -15,12 +15,14 @@ #include #include #include -#include -#include -#include #include +#include #include +#include +#include +#include + #include "../core.h" #include "../devicetree.h" -- cgit v1.2.3 From 24b4d76a5a2d7cf0b8b1f059da6b2accd339b7e7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: uniphier: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index ade348b49b31..18d3a4f69e63 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -6,12 +6,14 @@ #include #include #include -#include +#include +#include +#include + #include +#include #include #include -#include -#include #include "../core.h" #include "../pinctrl-utils.h" -- cgit v1.2.3 From e9d10adcd469806b6d85ee0b1c9081c79c893098 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: zynqmp: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-zynqmp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 7d2fbf8a02cd..f2be341f73e1 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -14,10 +14,13 @@ #include #include #include + #include -#include #include +#include +#include +#include #include "core.h" #include "pinctrl-utils.h" -- cgit v1.2.3 From 414fb9f290e09e72c5e3e100d3a2c0a8f8aa8ae1 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: cherryview: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 5c4fd16e5b01..11b81213922d 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -16,12 +16,14 @@ #include #include #include +#include #include +#include +#include +#include #include #include -#include -#include #include "pinctrl-intel.h" -- cgit v1.2.3 From c4168db7c8172711c1dcdcc952da2980e1533cca Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: lynxpoint: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 5d1abee30f8f..8d05dad38556 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -16,13 +16,15 @@ #include #include #include +#include #include #include +#include +#include +#include #include #include -#include -#include #include "pinctrl-intel.h" -- cgit v1.2.3 From cc994a0a76a87108ec3fac10bb906ff9d934c3c9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: merrifield: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-merrifield.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index 5e752818adb4..527957ea35b7 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -12,8 +12,10 @@ #include #include #include -#include +#include + #include +#include #include #include -- cgit v1.2.3 From de23ccb1edc84f0f59f09b157b082110fb40789c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 16:44:44 +0300 Subject: pinctrl: intel: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 52ecd66ce357..b85140eaa9c4 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -14,12 +14,14 @@ #include #include #include +#include #include -#include -#include +#include #include #include +#include +#include #include "../core.h" #include "pinctrl-intel.h" -- cgit v1.2.3 From e5530adc17a79f2a93e8b35e0ce673fc33f5f663 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 7 Oct 2022 12:53:44 +0300 Subject: pinctrl: Clean up headers There is a few things done: - include only the headers we are direct user of - when pointer is in use, provide a forward declaration - add missing headers - group generic headers and subsystem headers - sort each group alphabetically While at it, fix some awkward indentations. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/core.c | 19 ++++++++++--------- drivers/pinctrl/core.h | 12 +++++++++++- drivers/pinctrl/devicetree.h | 6 ++++++ drivers/pinctrl/pinconf.h | 10 ++++++++++ drivers/pinctrl/pinctrl-utils.h | 5 +++++ drivers/pinctrl/pinmux.c | 17 ++++++++++------- drivers/pinctrl/pinmux.h | 11 +++++++++++ include/linux/pinctrl/consumer.h | 31 ++++++++++++++----------------- include/linux/pinctrl/devinfo.h | 6 ++++-- include/linux/pinctrl/machine.h | 8 +++++--- include/linux/pinctrl/pinconf-generic.h | 23 +++++++++++++---------- include/linux/pinctrl/pinctrl.h | 18 +++++++++--------- include/linux/pinctrl/pinmux.h | 5 ++--- 13 files changed, 110 insertions(+), 61 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 9e57f4c62e60..655f9502e73f 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -12,19 +12,21 @@ */ #define pr_fmt(fmt) "pinctrl core: " fmt -#include -#include -#include -#include +#include #include -#include #include +#include +#include +#include +#include #include -#include #include +#include + #include -#include +#include #include +#include #ifdef CONFIG_GPIOLIB #include "../gpio/gpiolib.h" @@ -33,9 +35,8 @@ #include "core.h" #include "devicetree.h" -#include "pinmux.h" #include "pinconf.h" - +#include "pinmux.h" static bool pinctrl_dummy_state; diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 840103c40c14..4d0bdb9fb99b 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -9,12 +9,22 @@ */ #include +#include #include #include -#include +#include + #include +struct dentry; +struct device; +struct device_node; +struct module; + +struct pinctrl; +struct pinctrl_desc; struct pinctrl_gpio_range; +struct pinctrl_state; /** * struct pinctrl_dev - pin control class device diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h index efa80779de4f..def76aba99d1 100644 --- a/drivers/pinctrl/devicetree.h +++ b/drivers/pinctrl/devicetree.h @@ -5,8 +5,14 @@ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ +#include + +struct device_node; struct of_phandle_args; +struct pinctrl; +struct pinctrl_dev; + #ifdef CONFIG_OF void pinctrl_dt_free_maps(struct pinctrl *p); diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index be7311373299..694bfc9961fa 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -10,6 +10,16 @@ * Author: Linus Walleij */ +#include + +struct dentry; +struct device_node; +struct seq_file; + +struct pinctrl_dev; +struct pinctrl_map; +struct pinctrl_setting; + #ifdef CONFIG_PINCONF int pinconf_check_ops(struct pinctrl_dev *pctldev); diff --git a/drivers/pinctrl/pinctrl-utils.h b/drivers/pinctrl/pinctrl-utils.h index cec407a8cc4e..4108ee2dd6d0 100644 --- a/drivers/pinctrl/pinctrl-utils.h +++ b/drivers/pinctrl/pinctrl-utils.h @@ -9,6 +9,11 @@ #ifndef __PINCTRL_UTILS_H__ #define __PINCTRL_UTILS_H__ +#include + +struct pinctrl_dev; +struct pinctrl_map; + int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev, struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps, unsigned reserve); diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index f94d43b082d9..6bd7ac37a0e0 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -13,19 +13,22 @@ #define pr_fmt(fmt) "pinmux core: " fmt #include -#include -#include -#include +#include #include -#include -#include #include +#include +#include #include -#include -#include +#include +#include #include +#include +#include + #include +#include #include + #include "core.h" #include "pinmux.h" diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index 72fcf03eaa43..ea6f99c24aa5 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -9,6 +9,17 @@ * * Author: Linus Walleij */ + +#include + +struct dentry; +struct seq_file; + +struct pinctrl_dev; +struct pinctrl_gpio_range; +struct pinctrl_map; +struct pinctrl_setting; + #ifdef CONFIG_PINMUX int pinmux_check_ops(struct pinctrl_dev *pctldev); diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 019fecd75d0c..4729d54e8995 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -12,14 +12,15 @@ #define __LINUX_PINCTRL_CONSUMER_H #include -#include -#include +#include + #include +struct device; + /* This struct is private to the core and should be regarded as a cookie */ struct pinctrl; struct pinctrl_state; -struct device; #ifdef CONFIG_PINCTRL @@ -33,9 +34,8 @@ extern int pinctrl_gpio_set_config(unsigned gpio, unsigned long config); extern struct pinctrl * __must_check pinctrl_get(struct device *dev); extern void pinctrl_put(struct pinctrl *p); -extern struct pinctrl_state * __must_check pinctrl_lookup_state( - struct pinctrl *p, - const char *name); +extern struct pinctrl_state * __must_check pinctrl_lookup_state(struct pinctrl *p, + const char *name); extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s); extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev); @@ -101,9 +101,8 @@ static inline void pinctrl_put(struct pinctrl *p) { } -static inline struct pinctrl_state * __must_check pinctrl_lookup_state( - struct pinctrl *p, - const char *name) +static inline struct pinctrl_state * __must_check pinctrl_lookup_state(struct pinctrl *p, + const char *name) { return NULL; } @@ -145,8 +144,8 @@ static inline int pinctrl_pm_select_idle_state(struct device *dev) #endif /* CONFIG_PINCTRL */ -static inline struct pinctrl * __must_check pinctrl_get_select( - struct device *dev, const char *name) +static inline struct pinctrl * __must_check pinctrl_get_select(struct device *dev, + const char *name) { struct pinctrl *p; struct pinctrl_state *s; @@ -171,14 +170,13 @@ static inline struct pinctrl * __must_check pinctrl_get_select( return p; } -static inline struct pinctrl * __must_check pinctrl_get_select_default( - struct device *dev) +static inline struct pinctrl * __must_check pinctrl_get_select_default(struct device *dev) { return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); } -static inline struct pinctrl * __must_check devm_pinctrl_get_select( - struct device *dev, const char *name) +static inline struct pinctrl * __must_check devm_pinctrl_get_select(struct device *dev, + const char *name) { struct pinctrl *p; struct pinctrl_state *s; @@ -203,8 +201,7 @@ static inline struct pinctrl * __must_check devm_pinctrl_get_select( return p; } -static inline struct pinctrl * __must_check devm_pinctrl_get_select_default( - struct device *dev) +static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(struct device *dev) { return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); } diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h index a48ff69acddd..9e8b559e1253 100644 --- a/include/linux/pinctrl/devinfo.h +++ b/include/linux/pinctrl/devinfo.h @@ -14,11 +14,15 @@ #ifndef PINCTRL_DEVINFO_H #define PINCTRL_DEVINFO_H +struct device; + #ifdef CONFIG_PINCTRL /* The device core acts as a consumer toward pinctrl */ #include +struct pinctrl; + /** * struct dev_pin_info - pin state container for devices * @p: pinctrl handle for the containing device @@ -42,8 +46,6 @@ extern int pinctrl_init_done(struct device *dev); #else -struct device; - /* Stubs if we're not using pinctrl */ static inline int pinctrl_bind_pins(struct device *dev) diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h index e987dc9fd2af..0639b36f43c5 100644 --- a/include/linux/pinctrl/machine.h +++ b/include/linux/pinctrl/machine.h @@ -11,7 +11,7 @@ #ifndef __LINUX_PINCTRL_MACHINE_H #define __LINUX_PINCTRL_MACHINE_H -#include +#include /* ARRAY_SIZE() */ #include @@ -149,16 +149,18 @@ struct pinctrl_map { #define PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(dev, grp, cfgs) \ PIN_MAP_CONFIGS_GROUP(dev, PINCTRL_STATE_DEFAULT, dev, grp, cfgs) +struct pinctrl_map; + #ifdef CONFIG_PINCTRL extern int pinctrl_register_mappings(const struct pinctrl_map *map, - unsigned num_maps); + unsigned num_maps); extern void pinctrl_unregister_mappings(const struct pinctrl_map *map); extern void pinctrl_provide_dummies(void); #else static inline int pinctrl_register_mappings(const struct pinctrl_map *map, - unsigned num_maps) + unsigned num_maps) { return 0; } diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 2422211d6a5a..940fc4e9e17c 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -11,9 +11,12 @@ #ifndef __LINUX_PINCTRL_PINCONF_GENERIC_H #define __LINUX_PINCTRL_PINCONF_GENERIC_H -#include +#include + #include +struct device_node; + struct pinctrl_dev; struct pinctrl_map; @@ -196,25 +199,25 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, void pinconf_generic_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps); -static inline int pinconf_generic_dt_node_to_map_group( - struct pinctrl_dev *pctldev, struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) +static inline int pinconf_generic_dt_node_to_map_group(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps) { return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps, PIN_MAP_TYPE_CONFIGS_GROUP); } -static inline int pinconf_generic_dt_node_to_map_pin( - struct pinctrl_dev *pctldev, struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) +static inline int pinconf_generic_dt_node_to_map_pin(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps) { return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps, PIN_MAP_TYPE_CONFIGS_PIN); } -static inline int pinconf_generic_dt_node_to_map_all( - struct pinctrl_dev *pctldev, struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) +static inline int pinconf_generic_dt_node_to_map_all(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps) { /* * passing the type as PIN_MAP_TYPE_INVALID causes the underlying parser diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 487117ccb1bc..31fe992412f0 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -11,20 +11,20 @@ #ifndef __LINUX_PINCTRL_PINCTRL_H #define __LINUX_PINCTRL_PINCTRL_H -#include -#include -#include -#include -#include +#include struct device; +struct device_node; +struct gpio_chip; +struct module; +struct seq_file; + +struct pin_config_item; +struct pinconf_generic_params; +struct pinconf_ops; struct pinctrl_dev; struct pinctrl_map; struct pinmux_ops; -struct pinconf_ops; -struct pin_config_item; -struct gpio_chip; -struct device_node; /** * struct pingroup - provides information on pingroup diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h index 9a647fa5c8f1..a7e370965c53 100644 --- a/include/linux/pinctrl/pinmux.h +++ b/include/linux/pinctrl/pinmux.h @@ -11,11 +11,10 @@ #ifndef __LINUX_PINCTRL_PINMUX_H #define __LINUX_PINCTRL_PINMUX_H -#include -#include -#include +#include struct pinctrl_dev; +struct pinctrl_gpio_range; /** * struct pinmux_ops - pinmux operations, to be implemented by pin controller -- cgit v1.2.3 From de1fabef28e09dedfc1fb6b75a23f5851ce78658 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 19 Oct 2022 01:00:55 +0300 Subject: pinctrl: alderlake: Deduplicate COMMUNITY macro code Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-alderlake.c | 40 +++++++++++++------------------ 1 file changed, 16 insertions(+), 24 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c index 62dbd1e67513..427febe09b69 100644 --- a/drivers/pinctrl/intel/pinctrl-alderlake.c +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -34,33 +34,25 @@ .gpio_base = (g), \ } -#define ADL_N_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = ADL_N_PAD_OWN, \ - .padcfglock_offset = ADL_N_PADCFGLOCK, \ - .hostown_offset = ADL_N_HOSTSW_OWN, \ - .is_offset = ADL_N_GPI_IS, \ - .ie_offset = ADL_N_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ +#define ADL_COMMUNITY(b, s, e, g, v) \ + { \ + .barno = (b), \ + .padown_offset = ADL_##v##_PAD_OWN, \ + .padcfglock_offset = ADL_##v##_PADCFGLOCK, \ + .hostown_offset = ADL_##v##_HOSTSW_OWN, \ + .is_offset = ADL_##v##_GPI_IS, \ + .ie_offset = ADL_##v##_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ } +#define ADL_N_COMMUNITY(b, s, e, g) \ + ADL_COMMUNITY(b, s, e, g, N) + #define ADL_S_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = ADL_S_PAD_OWN, \ - .padcfglock_offset = ADL_S_PADCFGLOCK, \ - .hostown_offset = ADL_S_HOSTSW_OWN, \ - .is_offset = ADL_S_GPI_IS, \ - .ie_offset = ADL_S_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } + ADL_COMMUNITY(b, s, e, g, S) /* Alder Lake-N */ static const struct pinctrl_pin_desc adln_pins[] = { -- cgit v1.2.3 From b62241545ba12735438342874aa2aa67c68bfd22 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 19 Oct 2022 01:00:55 +0300 Subject: pinctrl: cannonlake: Deduplicate COMMUNITY macro code Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cannonlake.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index 8078c7739d6a..f8a8b9b14de9 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -30,12 +30,12 @@ .gpio_base = (g), \ } -#define CNL_COMMUNITY(b, s, e, ho, g) \ +#define CNL_COMMUNITY(b, s, e, g, v) \ { \ .barno = (b), \ .padown_offset = CNL_PAD_OWN, \ .padcfglock_offset = CNL_PADCFGLOCK, \ - .hostown_offset = (ho), \ + .hostown_offset = CNL_##v##_HOSTSW_OWN, \ .is_offset = CNL_GPI_IS, \ .ie_offset = CNL_GPI_IE, \ .pin_base = (s), \ @@ -45,10 +45,10 @@ } #define CNL_LP_COMMUNITY(b, s, e, g) \ - CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g) + CNL_COMMUNITY(b, s, e, g, LP) #define CNL_H_COMMUNITY(b, s, e, g) \ - CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g) + CNL_COMMUNITY(b, s, e, g, H) /* Cannon Lake-H */ static const struct pinctrl_pin_desc cnlh_pins[] = { -- cgit v1.2.3 From ac51b59dff2c8f92292347126cd6d24201e73b89 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 19 Oct 2022 01:00:55 +0300 Subject: pinctrl: icelake: Deduplicate COMMUNITY macro code Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-icelake.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 27c248cc16f7..84a56d9ae47e 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -30,14 +30,14 @@ .gpio_base = (g), \ } -#define ICL_COMMUNITY(b, s, e, ie, g) \ +#define ICL_COMMUNITY(b, s, e, g, v) \ { \ .barno = (b), \ .padown_offset = ICL_PAD_OWN, \ .padcfglock_offset = ICL_PADCFGLOCK, \ .hostown_offset = ICL_HOSTSW_OWN, \ .is_offset = ICL_GPI_IS, \ - .ie_offset = (ie), \ + .ie_offset = ICL_##v##_GPI_IE, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ .gpps = (g), \ @@ -45,10 +45,10 @@ } #define ICL_LP_COMMUNITY(b, s, e, g) \ - ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g) + ICL_COMMUNITY(b, s, e, g, LP) #define ICL_N_COMMUNITY(b, s, e, g) \ - ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g) + ICL_COMMUNITY(b, s, e, g, N) /* Ice Lake-LP */ static const struct pinctrl_pin_desc icllp_pins[] = { -- cgit v1.2.3 From 2d145b8bd3eb72ed577550355430930ec1057d15 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 19 Oct 2022 01:00:55 +0300 Subject: pinctrl: sunrisepoint: Deduplicate COMMUNITY macro code Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 32 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 14eac924d43d..292b660067e9 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -22,24 +22,24 @@ #define SPT_GPI_IS 0x100 #define SPT_GPI_IE 0x120 -#define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \ - { \ - .barno = (b), \ - .padown_offset = SPT_PAD_OWN, \ - .padcfglock_offset = (pl), \ - .hostown_offset = SPT_HOSTSW_OWN, \ - .is_offset = SPT_GPI_IS, \ - .ie_offset = SPT_GPI_IE, \ - .gpp_size = (gs), \ - .gpp_num_padown_regs = (gn), \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = (n), \ +#define SPT_COMMUNITY(b, s, e, g, n, v, gs, gn) \ + { \ + .barno = (b), \ + .padown_offset = SPT_PAD_OWN, \ + .padcfglock_offset = SPT_##v##_PADCFGLOCK, \ + .hostown_offset = SPT_HOSTSW_OWN, \ + .is_offset = SPT_GPI_IS, \ + .ie_offset = SPT_GPI_IE, \ + .gpp_size = (gs), \ + .gpp_num_padown_regs = (gn), \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = (n), \ } #define SPT_LP_COMMUNITY(b, s, e) \ - SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0) + SPT_COMMUNITY(b, s, e, NULL, 0, LP, 24, 4) #define SPT_H_GPP(r, s, e, g) \ { \ @@ -50,7 +50,7 @@ } #define SPT_H_COMMUNITY(b, s, e, g) \ - SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g)) + SPT_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), H, 0, 0) /* Sunrisepoint-LP */ static const struct pinctrl_pin_desc sptlp_pins[] = { -- cgit v1.2.3 From 1177ca3a0b53bdfb1438e33a5546527de728ec10 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 19 Oct 2022 01:00:55 +0300 Subject: pinctrl: tigerlake: Deduplicate COMMUNITY macro code Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 3ddaeffc0415..431352fa2ab5 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -31,25 +31,25 @@ .gpio_base = (g), \ } -#define TGL_COMMUNITY(b, s, e, pl, ho, g) \ - { \ - .barno = (b), \ - .padown_offset = TGL_PAD_OWN, \ - .padcfglock_offset = (pl), \ - .hostown_offset = (ho), \ - .is_offset = TGL_GPI_IS, \ - .ie_offset = TGL_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ +#define TGL_COMMUNITY(b, s, e, g, v) \ + { \ + .barno = (b), \ + .padown_offset = TGL_PAD_OWN, \ + .padcfglock_offset = TGL_##v##_PADCFGLOCK, \ + .hostown_offset = TGL_##v##_HOSTSW_OWN, \ + .is_offset = TGL_GPI_IS, \ + .ie_offset = TGL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ } #define TGL_LP_COMMUNITY(b, s, e, g) \ - TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g) + TGL_COMMUNITY(b, s, e, g, LP) #define TGL_H_COMMUNITY(b, s, e, g) \ - TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g) + TGL_COMMUNITY(b, s, e, g, H) /* Tiger Lake-LP */ static const struct pinctrl_pin_desc tgllp_pins[] = { -- cgit v1.2.3 From 98e63c1140a458d6795018ff30e1b259c0e1131c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 17 Oct 2022 20:15:06 +0300 Subject: pinctrl: intel: Use str_enable_disable() helper Use str_enable_disable() helper instead of open coding the same. Signed-off-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-intel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index b85140eaa9c4..b97657e4792e 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -1167,7 +1168,7 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on) else disable_irq_wake(pctrl->irq); - dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin); + dev_dbg(pctrl->dev, "%s wake for pin %u\n", str_enable_disable(on), pin); return 0; } -- cgit v1.2.3 From 03e9491fff252a7435e109333ec51ca2d619b759 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 27 Oct 2022 21:41:45 +0300 Subject: pinctrl: qcom: lpass-lpi: Add missed bitfield.h Previously the cleanup change dropped the bitfield.h from the pinctrl-lpass-lpi.h, since it's not used there, but forgot to re-instantiate it in the C-file, where users are located. Fix this by adding missed bitfield.h to the C-file. Fixes: aa9430f8a6de ("pinctrl: qcom: Add missing header(s)") Reported-by: kernel test robot Reported-by: Nathan Chancellor Signed-off-by: Andy Shevchenko --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index d5cfa91e2eff..3dc670faa59e 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -4,6 +4,7 @@ * Copyright (c) 2020 Linaro Ltd. */ +#include #include #include #include -- cgit v1.2.3 From 12b44105c0ca7c250d4f00c42482c5eaab2e8bd5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 2 Nov 2022 17:29:14 +0200 Subject: pinctrl: intel: Use temporary variable for struct device Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index b97657e4792e..6e630e87fed6 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1505,14 +1505,15 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) static int intel_pinctrl_probe(struct platform_device *pdev, const struct intel_pinctrl_soc_data *soc_data) { + struct device *dev = &pdev->dev; struct intel_pinctrl *pctrl; int i, ret, irq; - pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; - pctrl->dev = &pdev->dev; + pctrl->dev = dev; pctrl->soc = soc_data; raw_spin_lock_init(&pctrl->lock); @@ -1521,8 +1522,8 @@ static int intel_pinctrl_probe(struct platform_device *pdev, * to the registers. */ pctrl->ncommunities = pctrl->soc->ncommunities; - pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities, - sizeof(*pctrl->communities), GFP_KERNEL); + pctrl->communities = devm_kcalloc(dev, pctrl->ncommunities, + sizeof(*pctrl->communities), GFP_KERNEL); if (!pctrl->communities) return -ENOMEM; @@ -1573,7 +1574,7 @@ static int intel_pinctrl_probe(struct platform_device *pdev, offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT; } while (offset); - dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features); + dev_dbg(dev, "Community%d features: %#08x\n", i, community->features); /* Read offset of the pad configuration registers */ offset = readl(regs + PADBAR); @@ -1598,14 +1599,13 @@ static int intel_pinctrl_probe(struct platform_device *pdev, return ret; pctrl->pctldesc = intel_pinctrl_desc; - pctrl->pctldesc.name = dev_name(&pdev->dev); + pctrl->pctldesc.name = dev_name(dev); pctrl->pctldesc.pins = pctrl->soc->pins; pctrl->pctldesc.npins = pctrl->soc->npins; - pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, - pctrl); + pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); if (IS_ERR(pctrl->pctldev)) { - dev_err(&pdev->dev, "failed to register pinctrl driver\n"); + dev_err(dev, "failed to register pinctrl driver\n"); return PTR_ERR(pctrl->pctldev); } @@ -1646,10 +1646,11 @@ const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_ { const struct intel_pinctrl_soc_data * const *table; const struct intel_pinctrl_soc_data *data = NULL; + struct device *dev = &pdev->dev; - table = device_get_match_data(&pdev->dev); + table = device_get_match_data(dev); if (table) { - struct acpi_device *adev = ACPI_COMPANION(&pdev->dev); + struct acpi_device *adev = ACPI_COMPANION(dev); unsigned int i; for (i = 0; table[i]; i++) { -- cgit v1.2.3 From 3886bc3523db24814c98c57d74fe66d7a21bf40b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 2 Nov 2022 17:29:15 +0200 Subject: pinctrl: merrifield: Use temporary variable for struct device Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-merrifield.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index 527957ea35b7..c0845bb1e9e3 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -897,17 +897,18 @@ static const struct pinctrl_desc mrfld_pinctrl_desc = { static int mrfld_pinctrl_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct mrfld_family *families; struct mrfld_pinctrl *mp; void __iomem *regs; size_t nfamilies; unsigned int i; - mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL); + mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); if (!mp) return -ENOMEM; - mp->dev = &pdev->dev; + mp->dev = dev; raw_spin_lock_init(&mp->lock); regs = devm_platform_ioremap_resource(pdev, 0); @@ -919,9 +920,7 @@ static int mrfld_pinctrl_probe(struct platform_device *pdev) * to the registers. */ nfamilies = ARRAY_SIZE(mrfld_families), - families = devm_kmemdup(&pdev->dev, mrfld_families, - sizeof(mrfld_families), - GFP_KERNEL); + families = devm_kmemdup(dev, mrfld_families, sizeof(mrfld_families), GFP_KERNEL); if (!families) return -ENOMEM; @@ -939,13 +938,13 @@ static int mrfld_pinctrl_probe(struct platform_device *pdev) mp->groups = mrfld_groups; mp->ngroups = ARRAY_SIZE(mrfld_groups); mp->pctldesc = mrfld_pinctrl_desc; - mp->pctldesc.name = dev_name(&pdev->dev); + mp->pctldesc.name = dev_name(dev); mp->pctldesc.pins = mrfld_pins; mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins); - mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp); + mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp); if (IS_ERR(mp->pctldev)) { - dev_err(&pdev->dev, "failed to register pinctrl driver\n"); + dev_err(dev, "failed to register pinctrl driver\n"); return PTR_ERR(mp->pctldev); } -- cgit v1.2.3 From d459a2352211bf01c532def4f85eb8c2545c610a Mon Sep 17 00:00:00 2001 From: Balsam CHIHI Date: Fri, 21 Oct 2022 10:47:07 +0200 Subject: pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken SET/CLR modes On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Add mt8365_set_clr_mode() callback for such SoCs, so that instead of using the SET/CLR register, use the main R/W register to read/update/write the modes. Co-developed-by: Fabien Parent Signed-off-by: Fabien Parent Signed-off-by: Balsam CHIHI Link: https://lore.kernel.org/r/20221021084708.1109986-2-bchihi@baylibre.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 15 +++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 +++++++- 2 files changed, 22 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index f25b3e09386b..076ae0b38e3d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -330,6 +330,21 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, return -EINVAL; } + if (pctl->devdata->mt8365_set_clr_mode) { + bit = pin & pctl->devdata->mode_mask; + reg_pullen = mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset; + reg_pullsel = mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset; + ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin), + bit, reg_pullen, reg_pullsel, + enable, isup); + if (ret) + return -EINVAL; + + return 0; + } + bit = BIT(pin & pctl->devdata->mode_mask); if (enable) reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 6fe8564334c9..11afa12a96cb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -216,7 +216,10 @@ struct mtk_eint_offsets { * @spec_dir_set: In very few SoCs, direction control registers are not * arranged continuously, they may be cut to parts. So they need special * dir setting. - + * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they + * need to use the main R/W register to read/update/write the modes instead of + * the SET/CLR register. + * * @dir_offset: The direction register offset. * @pullen_offset: The pull-up/pull-down enable register offset. * @pinmux_offset: The pinmux register offset. @@ -252,6 +255,9 @@ struct mtk_pinctrl_devdata { void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, unsigned int mode); void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); + int (*mt8365_set_clr_mode)(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup); unsigned int dir_offset; unsigned int ies_offset; unsigned int smt_offset; -- cgit v1.2.3 From cdb6f424e93cec2c9d19d59c56ee448d63cb0146 Mon Sep 17 00:00:00 2001 From: Balsam CHIHI Date: Fri, 21 Oct 2022 10:47:08 +0200 Subject: pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callback On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Use the mt8365_set_clr_mode() callback to fix the issue. Co-developed-by: Fabien Parent Signed-off-by: Fabien Parent Signed-off-by: Balsam CHIHI Link: https://lore.kernel.org/r/20221021084708.1109986-3-bchihi@baylibre.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt8365.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 57f37a294063..42b48136ab77 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -416,6 +416,23 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), }; +static int mt8365_set_clr_mode(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup) +{ + int ret; + + ret = regmap_update_bits(regmap, reg_pullen, BIT(bit), enable << bit); + if (ret) + return -EINVAL; + + ret = regmap_update_bits(regmap, reg_pullsel, BIT(bit), isup << bit); + if (ret) + return -EINVAL; + + return 0; +} + static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .pins = mtk_pins_mt8365, .npins = ARRAY_SIZE(mtk_pins_mt8365), @@ -431,6 +448,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd), .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, + .mt8365_set_clr_mode = mt8365_set_clr_mode, .dir_offset = 0x0140, .dout_offset = 0x00A0, .din_offset = 0x0000, -- cgit v1.2.3 From 7c3ccedaf7a7b0260e8ac128f14d6564da8393fd Mon Sep 17 00:00:00 2001 From: Shenwei Wang Date: Thu, 27 Oct 2022 08:08:58 -0500 Subject: pinctrl: freescale: add pad wakeup config add the logic to configure the pad wakeup function via the pin_config_set handler. Signed-off-by: Shenwei Wang Reported-by: kernel test robot Reviewed-by: Peng Fan Acked-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20221027130859.1444412-5-shenwei.wang@nxp.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-scu.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c index 59b5f8a35111..ea261b6e7458 100644 --- a/drivers/pinctrl/freescale/pinctrl-scu.c +++ b/drivers/pinctrl/freescale/pinctrl-scu.c @@ -15,6 +15,11 @@ #include "../core.h" #include "pinctrl-imx.h" +#define IMX_SC_PAD_FUNC_GET_WAKEUP 9 +#define IMX_SC_PAD_FUNC_SET_WAKEUP 4 +#define IMX_SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */ +#define IMX_SC_IRQ_PAD 2 /* Pad wakeup */ + enum pad_func_e { IMX_SC_PAD_FUNC_SET = 15, IMX_SC_PAD_FUNC_GET = 16, @@ -36,10 +41,18 @@ struct imx_sc_msg_resp_pad_get { u32 val; } __packed; +struct imx_sc_msg_gpio_set_pad_wakeup { + struct imx_sc_rpc_msg hdr; + u16 pad; + u8 wakeup; +} __packed __aligned(4); + static struct imx_sc_ipc *pinctrl_ipc_handle; int imx_pinctrl_sc_ipc_init(struct platform_device *pdev) { + imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_WAKE, + IMX_SC_IRQ_PAD, true); return imx_scu_get_handle(&pinctrl_ipc_handle); } EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init); @@ -81,6 +94,23 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned int val; int ret; + if (num_configs == 1) { + struct imx_sc_msg_gpio_set_pad_wakeup wmsg; + + hdr = &wmsg.hdr; + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_PAD; + hdr->func = IMX_SC_PAD_FUNC_SET_WAKEUP; + hdr->size = 2; + wmsg.pad = pin_id; + wmsg.wakeup = *configs; + ret = imx_scu_call_rpc(pinctrl_ipc_handle, &wmsg, true); + + dev_dbg(ipctl->dev, "wakeup pin_id: %d type: %ld\n", + pin_id, *configs); + return ret; + } + /* * Set mux and conf together in one IPC call */ -- cgit v1.2.3 From b14ef61314b37a4a720a1f5686627d5061387480 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 8 Nov 2022 16:09:31 +0200 Subject: pinctrl: intel: Add Intel Moorefield pin controller support This driver adds pinctrl support for Intel Moorefield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver, which supports this pinctrl interface, will be submitted separately. Signed-off-by: Andy Shevchenko Reviewed-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/Kconfig | 11 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl-moorefield.c | 916 +++++++++++++++++++++++++++++ 3 files changed, 928 insertions(+) create mode 100644 drivers/pinctrl/intel/pinctrl-moorefield.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 078eec8af4a4..b3ec00624416 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -47,6 +47,17 @@ config PINCTRL_MERRIFIELD interface that allows configuring of SoC pins and using them as GPIOs. +config PINCTRL_MOOREFIELD + tristate "Intel Moorefield pinctrl driver" + depends on X86_INTEL_MID + select PINMUX + select PINCONF + select GENERIC_PINCONF + help + Moorefield Family-Level Interface Shim (FLIS) driver provides an + interface that allows configuring of SoC pins and using them as + GPIOs. + config PINCTRL_INTEL tristate select PINMUX diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index bb87e7bc7b20..906dd6c8d837 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o +obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o obj-$(CONFIG_PINCTRL_ALDERLAKE) += pinctrl-alderlake.o obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o diff --git a/drivers/pinctrl/intel/pinctrl-moorefield.c b/drivers/pinctrl/intel/pinctrl-moorefield.c new file mode 100644 index 000000000000..e3eec671e15d --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-moorefield.c @@ -0,0 +1,916 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Moorefield SoC pinctrl driver + * + * Copyright (C) 2022, Intel Corporation + * Author: Andy Shevchenko + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "pinctrl-intel.h" + +#define MOFLD_FAMILY_NR 64 +#define MOFLD_FAMILY_LEN 0x400 + +#define SLEW_OFFSET 0x000 +#define BUFCFG_OFFSET 0x100 +#define MISC_OFFSET 0x300 + +#define BUFCFG_PINMODE_SHIFT 0 +#define BUFCFG_PINMODE_MASK GENMASK(2, 0) +#define BUFCFG_PINMODE_GPIO 0 +#define BUFCFG_PUPD_VAL_SHIFT 4 +#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) +#define BUFCFG_PUPD_VAL_2K 0 +#define BUFCFG_PUPD_VAL_20K 1 +#define BUFCFG_PUPD_VAL_50K 2 +#define BUFCFG_PUPD_VAL_910 3 +#define BUFCFG_PU_EN BIT(8) +#define BUFCFG_PD_EN BIT(9) +#define BUFCFG_Px_EN_MASK GENMASK(9, 8) +#define BUFCFG_SLEWSEL BIT(10) +#define BUFCFG_OVINEN BIT(12) +#define BUFCFG_OVINEN_EN BIT(13) +#define BUFCFG_OVINEN_MASK GENMASK(13, 12) +#define BUFCFG_OVOUTEN BIT(14) +#define BUFCFG_OVOUTEN_EN BIT(15) +#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) +#define BUFCFG_INDATAOV_VAL BIT(16) +#define BUFCFG_INDATAOV_EN BIT(17) +#define BUFCFG_INDATAOV_MASK GENMASK(17, 16) +#define BUFCFG_OUTDATAOV_VAL BIT(18) +#define BUFCFG_OUTDATAOV_EN BIT(19) +#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) +#define BUFCFG_OD_EN BIT(21) + +/** + * struct mofld_family - Intel pin family description + * @barno: MMIO BAR number where registers for this family reside + * @pin_base: Starting pin of pins in this family + * @npins: Number of pins in this family + * @protected: True if family is protected by access + * @regs: family specific common registers + */ +struct mofld_family { + unsigned int barno; + unsigned int pin_base; + size_t npins; + bool protected; + void __iomem *regs; +}; + +#define MOFLD_FAMILY(b, s, e) \ + { \ + .barno = (b), \ + .pin_base = (s), \ + .npins = (e) - (s) + 1, \ + } + +static const struct pinctrl_pin_desc mofld_pins[] = { + /* ULPI (13 pins) */ + PINCTRL_PIN(0, "GP101_ULPI_CLK"), + PINCTRL_PIN(1, "GP136_ULPI_D0"), + PINCTRL_PIN(2, "GP143_ULPI_D1"), + PINCTRL_PIN(3, "GP144_ULPI_D2"), + PINCTRL_PIN(4, "GP145_ULPI_D3"), + PINCTRL_PIN(5, "GP146_ULPI_D4"), + PINCTRL_PIN(6, "GP147_ULPI_D5"), + PINCTRL_PIN(7, "GP148_ULPI_D6"), + PINCTRL_PIN(8, "GP149_ULPI_D7"), + PINCTRL_PIN(9, "ULPI_DIR"), + PINCTRL_PIN(10, "ULPI_NXT"), + PINCTRL_PIN(11, "ULPI_REFCLK"), + PINCTRL_PIN(12, "ULPI_STP"), + /* eMMC (12 pins) */ + PINCTRL_PIN(13, "EMMC_CLK"), + PINCTRL_PIN(14, "EMMC_CMD"), + PINCTRL_PIN(15, "EMMC_D0"), + PINCTRL_PIN(16, "EMMC_D1"), + PINCTRL_PIN(17, "EMMC_D2"), + PINCTRL_PIN(18, "EMMC_D3"), + PINCTRL_PIN(19, "EMMC_D4"), + PINCTRL_PIN(20, "EMMC_D5"), + PINCTRL_PIN(21, "EMMC_D6"), + PINCTRL_PIN(22, "EMMC_D7"), + PINCTRL_PIN(23, "EMMC_RST_N"), + PINCTRL_PIN(24, "EMMC_RCLK"), + /* SDIO (20 pins) */ + PINCTRL_PIN(25, "GP77_SD_CD"), + PINCTRL_PIN(26, "GP78_SD_CLK"), + PINCTRL_PIN(27, "GP79_SD_CMD"), + PINCTRL_PIN(28, "GP80_SD_D0"), + PINCTRL_PIN(29, "GP81_SD_D1"), + PINCTRL_PIN(30, "GP82_SD_D2"), + PINCTRL_PIN(31, "GP83_SD_D3"), + PINCTRL_PIN(32, "GP84_SD_LS_CLK_FB"), + PINCTRL_PIN(33, "GP85_SD_LS_CMD_DIR"), + PINCTRL_PIN(34, "GP86_SD_LS_D_DIR"), + PINCTRL_PIN(35, "GP88_SD_LS_SEL"), + PINCTRL_PIN(36, "GP87_SD_PD"), + PINCTRL_PIN(37, "GP89_SD_WP"), + PINCTRL_PIN(38, "GP90_SDIO_CLK"), + PINCTRL_PIN(39, "GP91_SDIO_CMD"), + PINCTRL_PIN(40, "GP92_SDIO_D0"), + PINCTRL_PIN(41, "GP93_SDIO_D1"), + PINCTRL_PIN(42, "GP94_SDIO_D2"), + PINCTRL_PIN(43, "GP95_SDIO_D3"), + PINCTRL_PIN(44, "GP96_SDIO_PD"), + /* HSI (8 pins) */ + PINCTRL_PIN(45, "HSI_ACDATA"), + PINCTRL_PIN(46, "HSI_ACFLAG"), + PINCTRL_PIN(47, "HSI_ACREADY"), + PINCTRL_PIN(48, "HSI_ACWAKE"), + PINCTRL_PIN(49, "HSI_CADATA"), + PINCTRL_PIN(50, "HSI_CAFLAG"), + PINCTRL_PIN(51, "HSI_CAREADY"), + PINCTRL_PIN(52, "HSI_CAWAKE"), + /* SSP Audio (14 pins) */ + PINCTRL_PIN(53, "GP70"), + PINCTRL_PIN(54, "GP71"), + PINCTRL_PIN(55, "GP32_I2S_0_CLK"), + PINCTRL_PIN(56, "GP33_I2S_0_FS"), + PINCTRL_PIN(57, "GP34_I2S_0_RXD"), + PINCTRL_PIN(58, "GP35_I2S_0_TXD"), + PINCTRL_PIN(59, "GP36_I2S_1_CLK"), + PINCTRL_PIN(60, "GP37_I2S_1_FS"), + PINCTRL_PIN(61, "GP38_I2S_1_RXD"), + PINCTRL_PIN(62, "GP39_I2S_1_TXD"), + PINCTRL_PIN(63, "GP40_I2S_2_CLK"), + PINCTRL_PIN(64, "GP41_I2S_2_FS"), + PINCTRL_PIN(65, "GP42_I2S_2_RXD"), + PINCTRL_PIN(66, "GP43_I2S_2_TXD"), + /* GP SSP (22 pins) */ + PINCTRL_PIN(67, "GP120_SPI_0_CLK"), + PINCTRL_PIN(68, "GP121_SPI_0_SS"), + PINCTRL_PIN(69, "GP122_SPI_0_RXD"), + PINCTRL_PIN(70, "GP123_SPI_0_TXD"), + PINCTRL_PIN(71, "GP102_SPI_1_CLK"), + PINCTRL_PIN(72, "GP103_SPI_1_SS0"), + PINCTRL_PIN(73, "GP104_SPI_1_SS1"), + PINCTRL_PIN(74, "GP105_SPI_1_SS2"), + PINCTRL_PIN(75, "GP106_SPI_1_SS3"), + PINCTRL_PIN(76, "GP107_SPI_1_RXD"), + PINCTRL_PIN(77, "GP108_SPI_1_TXD"), + PINCTRL_PIN(78, "GP109_SPI_2_CLK"), + PINCTRL_PIN(79, "GP110_SPI_2_SS0"), + PINCTRL_PIN(80, "GP111_SPI_2_SS1"), + PINCTRL_PIN(81, "GP112_SPI_2_SS2"), + PINCTRL_PIN(82, "GP113_SPI_2_SS3"), + PINCTRL_PIN(83, "GP114_SPI_2_RXD"), + PINCTRL_PIN(84, "GP115_SPI_2_TXD"), + PINCTRL_PIN(85, "GP116_SPI_3_CLK"), + PINCTRL_PIN(86, "GP117_SPI_3_SS"), + PINCTRL_PIN(87, "GP118_SPI_3_RXD"), + PINCTRL_PIN(88, "GP119_SPI_3_TXD"), + /* I2C (20 pins) */ + PINCTRL_PIN(89, "I2C_0_SCL"), + PINCTRL_PIN(90, "I2C_0_SDA"), + PINCTRL_PIN(91, "GP19_I2C_1_SCL"), + PINCTRL_PIN(92, "GP20_I2C_1_SDA"), + PINCTRL_PIN(93, "GP21_I2C_2_SCL"), + PINCTRL_PIN(94, "GP22_I2C_2_SDA"), + PINCTRL_PIN(95, "GP17_I2C_3_SCL_HDMI"), + PINCTRL_PIN(96, "GP18_I2C_3_SDA_HDMI"), + PINCTRL_PIN(97, "GP23_I2C_4_SCL"), + PINCTRL_PIN(98, "GP24_I2C_4_SDA"), + PINCTRL_PIN(99, "GP25_I2C_5_SCL"), + PINCTRL_PIN(100, "GP26_I2C_5_SDA"), + PINCTRL_PIN(101, "GP27_I2C_6_SCL"), + PINCTRL_PIN(102, "GP28_I2C_6_SDA"), + PINCTRL_PIN(103, "GP29_I2C_7_SCL"), + PINCTRL_PIN(104, "GP30_I2C_7_SDA"), + PINCTRL_PIN(105, "I2C_8_SCL"), + PINCTRL_PIN(106, "I2C_8_SDA"), + PINCTRL_PIN(107, "I2C_9_SCL"), + PINCTRL_PIN(108, "I2C_9_SDA"), + /* UART (23 pins) */ + PINCTRL_PIN(109, "GP124_UART_0_CTS"), + PINCTRL_PIN(110, "GP125_UART_0_RTS"), + PINCTRL_PIN(111, "GP126_UART_0_RX"), + PINCTRL_PIN(112, "GP127_UART_0_TX"), + PINCTRL_PIN(113, "GP128_UART_1_CTS"), + PINCTRL_PIN(114, "GP129_UART_1_RTS"), + PINCTRL_PIN(115, "GP130_UART_1_RX"), + PINCTRL_PIN(116, "GP131_UART_1_TX"), + PINCTRL_PIN(117, "GP132_UART_2_CTS"), + PINCTRL_PIN(118, "GP133_UART_2_RTS"), + PINCTRL_PIN(119, "GP134_UART_2_RX"), + PINCTRL_PIN(120, "GP135_UART_2_TX"), + PINCTRL_PIN(121, "GP97"), + PINCTRL_PIN(122, "GP154"), + PINCTRL_PIN(123, "GP155"), + PINCTRL_PIN(124, "GP156"), + PINCTRL_PIN(125, "GP157"), + PINCTRL_PIN(126, "GP158"), + PINCTRL_PIN(127, "GP159"), + PINCTRL_PIN(128, "GP160"), + PINCTRL_PIN(129, "GP161"), + PINCTRL_PIN(130, "GP12_PWM0"), + PINCTRL_PIN(131, "GP13_PWM1"), + /* GPIO South (20 pins) */ + PINCTRL_PIN(132, "GP176"), + PINCTRL_PIN(133, "GP177"), + PINCTRL_PIN(134, "GP178"), + PINCTRL_PIN(135, "GP179"), + PINCTRL_PIN(136, "GP180"), + PINCTRL_PIN(137, "GP181"), + PINCTRL_PIN(138, "GP182_PWM2"), + PINCTRL_PIN(139, "GP183_PWM3"), + PINCTRL_PIN(140, "GP184"), + PINCTRL_PIN(141, "GP185"), + PINCTRL_PIN(142, "GP186"), + PINCTRL_PIN(143, "GP187"), + PINCTRL_PIN(144, "GP188"), + PINCTRL_PIN(145, "GP189"), + PINCTRL_PIN(146, "GP190"), + PINCTRL_PIN(147, "GP191"), + PINCTRL_PIN(148, "GP14"), + PINCTRL_PIN(149, "GP15"), + PINCTRL_PIN(150, "GP162"), + PINCTRL_PIN(151, "GP163"), + /* Camera Sideband (15 pins) */ + PINCTRL_PIN(152, "GP0"), + PINCTRL_PIN(153, "GP1"), + PINCTRL_PIN(154, "GP2"), + PINCTRL_PIN(155, "GP3"), + PINCTRL_PIN(156, "GP4"), + PINCTRL_PIN(157, "GP5"), + PINCTRL_PIN(158, "GP6"), + PINCTRL_PIN(159, "GP7"), + PINCTRL_PIN(160, "GP8"), + PINCTRL_PIN(161, "GP9"), + PINCTRL_PIN(162, "GP10"), + PINCTRL_PIN(163, "GP11"), + PINCTRL_PIN(164, "GP16_HDMI_HPD"), + PINCTRL_PIN(165, "GP68_DSI_A_TE"), + PINCTRL_PIN(166, "GP69_DSI_C_TE"), + /* Clock (14 pins) */ + PINCTRL_PIN(167, "GP137"), + PINCTRL_PIN(168, "GP138"), + PINCTRL_PIN(169, "GP139"), + PINCTRL_PIN(170, "GP140"), + PINCTRL_PIN(171, "GP141"), + PINCTRL_PIN(172, "GP142"), + PINCTRL_PIN(173, "GP98"), + PINCTRL_PIN(174, "OSC_CLK_CTRL0"), + PINCTRL_PIN(175, "OSC_CLK_CTRL1"), + PINCTRL_PIN(176, "OSC_CLK0"), + PINCTRL_PIN(177, "OSC_CLK1"), + PINCTRL_PIN(178, "OSC_CLK2"), + PINCTRL_PIN(179, "OSC_CLK3"), + PINCTRL_PIN(180, "OSC_CLK4"), + /* PMIC (15 pins) */ + PINCTRL_PIN(181, "PROCHOT"), + PINCTRL_PIN(182, "RESETOUT"), + PINCTRL_PIN(183, "RTC_CLK"), + PINCTRL_PIN(184, "STANDBY"), + PINCTRL_PIN(185, "SVID_ALERT"), + PINCTRL_PIN(186, "SVID_CLK"), + PINCTRL_PIN(187, "SVID_D"), + PINCTRL_PIN(188, "THERMTRIP"), + PINCTRL_PIN(189, "PREQ"), + PINCTRL_PIN(190, "ZQ_A"), + PINCTRL_PIN(191, "ZQ_B"), + PINCTRL_PIN(192, "GP64_FAST_INT0"), + PINCTRL_PIN(193, "GP65_FAST_INT1"), + PINCTRL_PIN(194, "GP66_FAST_INT2"), + PINCTRL_PIN(195, "GP67_FAST_INT3"), + /* Keyboard (20 pins) */ + PINCTRL_PIN(196, "GP44"), + PINCTRL_PIN(197, "GP45"), + PINCTRL_PIN(198, "GP46"), + PINCTRL_PIN(199, "GP47"), + PINCTRL_PIN(200, "GP48"), + PINCTRL_PIN(201, "GP49"), + PINCTRL_PIN(202, "GP50"), + PINCTRL_PIN(203, "GP51"), + PINCTRL_PIN(204, "GP52"), + PINCTRL_PIN(205, "GP53"), + PINCTRL_PIN(206, "GP54"), + PINCTRL_PIN(207, "GP55"), + PINCTRL_PIN(208, "GP56"), + PINCTRL_PIN(209, "GP57"), + PINCTRL_PIN(210, "GP58"), + PINCTRL_PIN(211, "GP59"), + PINCTRL_PIN(212, "GP60"), + PINCTRL_PIN(213, "GP61"), + PINCTRL_PIN(214, "GP62"), + PINCTRL_PIN(215, "GP63"), + /* GPIO North (13 pins) */ + PINCTRL_PIN(216, "GP164"), + PINCTRL_PIN(217, "GP165"), + PINCTRL_PIN(218, "GP166"), + PINCTRL_PIN(219, "GP167"), + PINCTRL_PIN(220, "GP168_MJTAG_TCK"), + PINCTRL_PIN(221, "GP169_MJTAG_TDI"), + PINCTRL_PIN(222, "GP170_MJTAG_TDO"), + PINCTRL_PIN(223, "GP171_MJTAG_TMS"), + PINCTRL_PIN(224, "GP172_MJTAG_TRST"), + PINCTRL_PIN(225, "GP173"), + PINCTRL_PIN(226, "GP174"), + PINCTRL_PIN(227, "GP175"), + PINCTRL_PIN(228, "GP176"), + /* PTI (22 pins) */ + PINCTRL_PIN(229, "GP72_PTI_CLK"), + PINCTRL_PIN(230, "GP73_PTI_D0"), + PINCTRL_PIN(231, "GP74_PTI_D1"), + PINCTRL_PIN(232, "GP75_PTI_D2"), + PINCTRL_PIN(233, "GP76_PTI_D3"), + PINCTRL_PIN(234, "GP164"), + PINCTRL_PIN(235, "GP165"), + PINCTRL_PIN(236, "GP166"), + PINCTRL_PIN(237, "GP167"), + PINCTRL_PIN(238, "GP168_MJTAG_TCK"), + PINCTRL_PIN(239, "GP169_MJTAG_TDI"), + PINCTRL_PIN(240, "GP170_MJTAG_TDO"), + PINCTRL_PIN(241, "GP171_MJTAG_TMS"), + PINCTRL_PIN(242, "GP172_MJTAG_TRST"), + PINCTRL_PIN(243, "GP173"), + PINCTRL_PIN(244, "GP174"), + PINCTRL_PIN(245, "GP175"), + PINCTRL_PIN(246, "JTAG_TCK"), + PINCTRL_PIN(247, "JTAG_TDI"), + PINCTRL_PIN(248, "JTAG_TDO"), + PINCTRL_PIN(249, "JTAG_TMS"), + PINCTRL_PIN(250, "JTAG_TRST"), +}; + +static const struct mofld_family mofld_families[] = { + MOFLD_FAMILY(0, 0, 12), + MOFLD_FAMILY(1, 13, 24), + MOFLD_FAMILY(2, 25, 44), + MOFLD_FAMILY(3, 45, 52), + MOFLD_FAMILY(4, 53, 66), + MOFLD_FAMILY(5, 67, 88), + MOFLD_FAMILY(6, 89, 108), + MOFLD_FAMILY(7, 109, 131), + MOFLD_FAMILY(8, 132, 151), + MOFLD_FAMILY(9, 152, 166), + MOFLD_FAMILY(10, 167, 180), + MOFLD_FAMILY(11, 181, 195), + MOFLD_FAMILY(12, 196, 215), + MOFLD_FAMILY(13, 216, 228), + MOFLD_FAMILY(14, 229, 250), +}; + +/** + * struct mofld_pinctrl - Intel Merrifield pinctrl private structure + * @dev: Pointer to the device structure + * @lock: Lock to serialize register access + * @pctldesc: Pin controller description + * @pctldev: Pointer to the pin controller device + * @families: Array of families this pinctrl handles + * @nfamilies: Number of families in the array + * @functions: Array of functions + * @nfunctions: Number of functions in the array + * @groups: Array of pin groups + * @ngroups: Number of groups in the array + * @pins: Array of pins this pinctrl controls + * @npins: Number of pins in the array + */ +struct mofld_pinctrl { + struct device *dev; + raw_spinlock_t lock; + struct pinctrl_desc pctldesc; + struct pinctrl_dev *pctldev; + + /* Pin controller configuration */ + const struct mofld_family *families; + size_t nfamilies; + const struct intel_function *functions; + size_t nfunctions; + const struct intel_pingroup *groups; + size_t ngroups; + const struct pinctrl_pin_desc *pins; + size_t npins; +}; + +#define pin_to_bufno(f, p) ((p) - (f)->pin_base) + +static const struct mofld_family *mofld_get_family(struct mofld_pinctrl *mp, unsigned int pin) +{ + const struct mofld_family *family; + unsigned int i; + + for (i = 0; i < mp->nfamilies; i++) { + family = &mp->families[i]; + if (pin >= family->pin_base && + pin < family->pin_base + family->npins) + return family; + } + + dev_warn(mp->dev, "failed to find family for pin %u\n", pin); + return NULL; +} + +static bool mofld_buf_available(struct mofld_pinctrl *mp, unsigned int pin) +{ + const struct mofld_family *family; + + family = mofld_get_family(mp, pin); + if (!family) + return false; + + return !family->protected; +} + +static void __iomem *mofld_get_bufcfg(struct mofld_pinctrl *mp, unsigned int pin) +{ + const struct mofld_family *family; + unsigned int bufno; + + family = mofld_get_family(mp, pin); + if (!family) + return NULL; + + bufno = pin_to_bufno(family, pin); + return family->regs + BUFCFG_OFFSET + bufno * 4; +} + +static int mofld_read_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 *value) +{ + void __iomem *bufcfg; + + if (!mofld_buf_available(mp, pin)) + return -EBUSY; + + bufcfg = mofld_get_bufcfg(mp, pin); + *value = readl(bufcfg); + + return 0; +} + +static void mofld_update_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 bits, u32 mask) +{ + void __iomem *bufcfg; + u32 value; + + bufcfg = mofld_get_bufcfg(mp, pin); + value = readl(bufcfg); + + value &= ~mask; + value |= bits & mask; + + writel(value, bufcfg); +} + +static int mofld_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + + return mp->ngroups; +} + +static const char *mofld_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + + return mp->groups[group].grp.name; +} + +static int mofld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, + const unsigned int **pins, unsigned int *npins) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + + *pins = mp->groups[group].grp.pins; + *npins = mp->groups[group].grp.npins; + return 0; +} + +static void mofld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int pin) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + u32 value, mode; + int ret; + + ret = mofld_read_bufcfg(mp, pin, &value); + if (ret) { + seq_puts(s, "not available"); + return; + } + + mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; + if (!mode) + seq_puts(s, "GPIO "); + else + seq_printf(s, "mode %d ", mode); + + seq_printf(s, "0x%08x", value); +} + +static const struct pinctrl_ops mofld_pinctrl_ops = { + .get_groups_count = mofld_get_groups_count, + .get_group_name = mofld_get_group_name, + .get_group_pins = mofld_get_group_pins, + .pin_dbg_show = mofld_pin_dbg_show, +}; + +static int mofld_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + + return mp->nfunctions; +} + +static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + + return mp->functions[function].name; +} + +static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function, + const char * const **groups, unsigned int * const ngroups) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + + *groups = mp->functions[function].groups; + *ngroups = mp->functions[function].ngroups; + return 0; +} + +static int mofld_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + unsigned int group) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + const struct intel_pingroup *grp = &mp->groups[group]; + u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; + u32 mask = BUFCFG_PINMODE_MASK; + unsigned long flags; + unsigned int i; + + /* + * All pins in the groups needs to be accessible and writable + * before we can enable the mux for this group. + */ + for (i = 0; i < grp->grp.npins; i++) { + if (!mofld_buf_available(mp, grp->grp.pins[i])) + return -EBUSY; + } + + /* Now enable the mux setting for each pin in the group */ + raw_spin_lock_irqsave(&mp->lock, flags); + for (i = 0; i < grp->grp.npins; i++) + mofld_update_bufcfg(mp, grp->grp.pins[i], bits, mask); + raw_spin_unlock_irqrestore(&mp->lock, flags); + + return 0; +} + +static int mofld_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; + u32 mask = BUFCFG_PINMODE_MASK; + unsigned long flags; + + if (!mofld_buf_available(mp, pin)) + return -EBUSY; + + raw_spin_lock_irqsave(&mp->lock, flags); + mofld_update_bufcfg(mp, pin, bits, mask); + raw_spin_unlock_irqrestore(&mp->lock, flags); + + return 0; +} + +static const struct pinmux_ops mofld_pinmux_ops = { + .get_functions_count = mofld_get_functions_count, + .get_function_name = mofld_get_function_name, + .get_function_groups = mofld_get_function_groups, + .set_mux = mofld_pinmux_set_mux, + .gpio_request_enable = mofld_gpio_request_enable, +}; + +static int mofld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u32 value, term; + u16 arg = 0; + int ret; + + ret = mofld_read_bufcfg(mp, pin, &value); + if (ret) + return -ENOTSUPP; + + term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (value & BUFCFG_Px_EN_MASK) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) + return -EINVAL; + + switch (term) { + case BUFCFG_PUPD_VAL_910: + arg = 910; + break; + case BUFCFG_PUPD_VAL_2K: + arg = 2000; + break; + case BUFCFG_PUPD_VAL_20K: + arg = 20000; + break; + case BUFCFG_PUPD_VAL_50K: + arg = 50000; + break; + } + + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) + return -EINVAL; + + switch (term) { + case BUFCFG_PUPD_VAL_910: + arg = 910; + break; + case BUFCFG_PUPD_VAL_2K: + arg = 2000; + break; + case BUFCFG_PUPD_VAL_20K: + arg = 20000; + break; + case BUFCFG_PUPD_VAL_50K: + arg = 50000; + break; + } + + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!(value & BUFCFG_OD_EN)) + return -EINVAL; + break; + + case PIN_CONFIG_SLEW_RATE: + if (!(value & BUFCFG_SLEWSEL)) + arg = 0; + else + arg = 1; + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int mofld_config_set_pin(struct mofld_pinctrl *mp, unsigned int pin, + unsigned long config) +{ + unsigned int param = pinconf_to_config_param(config); + unsigned int arg = pinconf_to_config_argument(config); + u32 bits = 0, mask = 0; + unsigned long flags; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + bits |= BUFCFG_PU_EN; + + switch (arg) { + case 50000: + bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; + break; + case 20000: + bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; + break; + case 2000: + bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; + break; + default: + return -EINVAL; + } + + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; + bits |= BUFCFG_PD_EN; + + switch (arg) { + case 50000: + bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; + break; + case 20000: + bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; + break; + case 2000: + bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; + break; + default: + return -EINVAL; + } + + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + mask |= BUFCFG_OD_EN; + if (arg) + bits |= BUFCFG_OD_EN; + break; + + case PIN_CONFIG_SLEW_RATE: + mask |= BUFCFG_SLEWSEL; + if (arg) + bits |= BUFCFG_SLEWSEL; + break; + } + + raw_spin_lock_irqsave(&mp->lock, flags); + mofld_update_bufcfg(mp, pin, bits, mask); + raw_spin_unlock_irqrestore(&mp->lock, flags); + + return 0; +} + +static int mofld_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int nconfigs) +{ + struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); + unsigned int i; + int ret; + + if (!mofld_buf_available(mp, pin)) + return -ENOTSUPP; + + for (i = 0; i < nconfigs; i++) { + switch (pinconf_to_config_param(configs[i])) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + case PIN_CONFIG_SLEW_RATE: + ret = mofld_config_set_pin(mp, pin, configs[i]); + if (ret) + return ret; + break; + + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static int mofld_config_group_get(struct pinctrl_dev *pctldev, unsigned int group, + unsigned long *config) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret = mofld_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + ret = mofld_config_get(pctldev, pins[0], config); + if (ret) + return ret; + + return 0; +} + +static int mofld_config_group_set(struct pinctrl_dev *pctldev, unsigned int group, + unsigned long *configs, unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int i, ret; + + ret = mofld_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = mofld_config_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops mofld_pinconf_ops = { + .is_generic = true, + .pin_config_get = mofld_config_get, + .pin_config_set = mofld_config_set, + .pin_config_group_get = mofld_config_group_get, + .pin_config_group_set = mofld_config_group_set, +}; + +static const struct pinctrl_desc mofld_pinctrl_desc = { + .pctlops = &mofld_pinctrl_ops, + .pmxops = &mofld_pinmux_ops, + .confops = &mofld_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int mofld_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mofld_family *families; + struct mofld_pinctrl *mp; + void __iomem *regs; + size_t nfamilies; + unsigned int i; + + mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL); + if (!mp) + return -ENOMEM; + + mp->dev = dev; + raw_spin_lock_init(&mp->lock); + + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + nfamilies = ARRAY_SIZE(mofld_families), + families = devm_kmemdup(dev, mofld_families, sizeof(mofld_families), GFP_KERNEL); + if (!families) + return -ENOMEM; + + /* Splice memory resource by chunk per family */ + for (i = 0; i < nfamilies; i++) { + struct mofld_family *family = &families[i]; + + family->regs = regs + family->barno * MOFLD_FAMILY_LEN; + } + + mp->families = families; + mp->nfamilies = nfamilies; + mp->pctldesc = mofld_pinctrl_desc; + mp->pctldesc.name = dev_name(dev); + mp->pctldesc.pins = mofld_pins; + mp->pctldesc.npins = ARRAY_SIZE(mofld_pins); + + mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp); + if (IS_ERR(mp->pctldev)) + return PTR_ERR(mp->pctldev); + + platform_set_drvdata(pdev, mp); + return 0; +} + +static const struct acpi_device_id mofld_acpi_table[] = { + { "INTC1003" }, + { } +}; +MODULE_DEVICE_TABLE(acpi, mofld_acpi_table); + +static struct platform_driver mofld_pinctrl_driver = { + .probe = mofld_pinctrl_probe, + .driver = { + .name = "pinctrl-moorefield", + .acpi_match_table = mofld_acpi_table, + }, +}; + +static int __init mofld_pinctrl_init(void) +{ + return platform_driver_register(&mofld_pinctrl_driver); +} +subsys_initcall(mofld_pinctrl_init); + +static void __exit mofld_pinctrl_exit(void) +{ + platform_driver_unregister(&mofld_pinctrl_driver); +} +module_exit(mofld_pinctrl_exit); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_DESCRIPTION("Intel Moorefield SoC pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:pinctrl-moorefield"); -- cgit v1.2.3 From 97775ebbe89b5a97e9465e4378f5b1c2fc7d4faa Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Mon, 31 Oct 2022 23:28:33 +0100 Subject: pinctrl: nuvoton: wpcm450: Convert irqchip to IRQCHIP_IMMUTABLE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 6c846d026d490 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning for irqchips that are not marked with IRQCHIP_IMMUTABLE. Convert the pinctrl-wpcm450 driver to an immutable irqchip. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20221031222833.201322-1-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index 8193b92da403..211ad32cc0d8 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -49,7 +49,6 @@ struct wpcm450_bank; struct wpcm450_gpio { struct gpio_chip gc; struct wpcm450_pinctrl *pctrl; - struct irq_chip irqc; const struct wpcm450_bank *bank; }; @@ -142,7 +141,8 @@ static void wpcm450_gpio_irq_ack(struct irq_data *d) static void wpcm450_gpio_irq_mask(struct irq_data *d) { - struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct wpcm450_gpio *gpio = gpiochip_get_data(gc); struct wpcm450_pinctrl *pctrl = gpio->pctrl; unsigned long flags; unsigned long even; @@ -157,11 +157,14 @@ static void wpcm450_gpio_irq_mask(struct irq_data *d) __assign_bit(bit, &even, 0); iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } static void wpcm450_gpio_irq_unmask(struct irq_data *d) { - struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct wpcm450_gpio *gpio = gpiochip_get_data(gc); struct wpcm450_pinctrl *pctrl = gpio->pctrl; unsigned long flags; unsigned long even; @@ -171,6 +174,8 @@ static void wpcm450_gpio_irq_unmask(struct irq_data *d) if (bit < 0) return; + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + raw_spin_lock_irqsave(&pctrl->lock, flags); even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); __assign_bit(bit, &even, 1); @@ -293,6 +298,8 @@ static const struct irq_chip wpcm450_gpio_irqchip = { .irq_unmask = wpcm450_gpio_irq_unmask, .irq_mask = wpcm450_gpio_irq_mask, .irq_set_type = wpcm450_gpio_set_irq_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static void wpcm450_gpio_irqhandler(struct irq_desc *desc) @@ -1068,9 +1075,8 @@ static int wpcm450_gpio_register(struct platform_device *pdev, gpio->gc.fwnode = child; gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; - gpio->irqc = wpcm450_gpio_irqchip; girq = &gpio->gc.irq; - girq->chip = &gpio->irqc; + gpio_irq_chip_set_chip(girq, &wpcm450_gpio_irqchip); girq->parent_handler = wpcm450_gpio_irqhandler; girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS, sizeof(*girq->parents), GFP_KERNEL); -- cgit v1.2.3 From 4f1d423cd2bd0d8cc20dfbb8d2e4e14b1e417790 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Nov 2022 19:59:04 +0100 Subject: pinctrl: nuvoton: wpcm450: Refactor MFSEL setting code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In preparation for the next patch, which makes the logic around setting/resetting bits in MFSEL a little more complicated, move that code to a new function Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20221105185911.1547847-2-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index 211ad32cc0d8..49b2177af17b 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -800,6 +800,14 @@ static const struct pinctrl_pin_desc wpcm450_pins[] = { WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127), }; +/* Helper function to update MFSEL field according to the selected function */ +static void wpcm450_update_mfsel(struct regmap *gcr_regmap, int reg, int bit, int fn, int fn_selected) +{ + bool value = (fn == fn_selected); + + regmap_update_bits(gcr_regmap, reg, BIT(bit), value ? BIT(bit) : 0); +} + /* Enable mode in pin group */ static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, int npins, int func) @@ -811,13 +819,11 @@ static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, cfg = &pincfg[pin[i]]; if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) { if (cfg->reg0) - regmap_update_bits(gcr_regmap, cfg->reg0, - BIT(cfg->bit0), - (cfg->fn0 == func) ? BIT(cfg->bit0) : 0); + wpcm450_update_mfsel(gcr_regmap, cfg->reg0, + cfg->bit0, cfg->fn0, func); if (cfg->reg1) - regmap_update_bits(gcr_regmap, cfg->reg1, - BIT(cfg->bit1), - (cfg->fn1 == func) ? BIT(cfg->bit1) : 0); + wpcm450_update_mfsel(gcr_regmap, cfg->reg1, + cfg->bit1, cfg->fn1, func); } } } -- cgit v1.2.3 From 6c98ac42120dcadd799f0660e7d15cd6b5d0073e Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Nov 2022 19:59:05 +0100 Subject: pinctrl: nuvoton: wpcm450: Fix handling of inverted MFSEL bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SCS3SEL and KBCCSEL use inverted logic: Whereas in other fields 0 selects the GPIO function and 1 selects the special function, in these two fields, 0 selects the special function and 1 selects the GPIO function. Adjust the code to handle this quirk. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20221105185911.1547847-3-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-wpcm450.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index 49b2177af17b..2d1c1652cfd9 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -628,6 +628,9 @@ struct wpcm450_pincfg { int fn1, reg1, bit1; }; +/* Add this value to bit0 or bit1 to indicate that the MFSEL bit is inverted */ +#define INV BIT(5) + static const struct wpcm450_pincfg pincfg[] = { /* PIN FUNCTION 1 FUNCTION 2 */ WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0), @@ -665,7 +668,7 @@ static const struct wpcm450_pincfg pincfg[] = { WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0), WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0), - WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0), + WPCM450_PINCFG(34, scs3, MFSEL1, 5 | INV, none, NONE, 0), WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0), WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0), WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */ @@ -725,8 +728,8 @@ static const struct wpcm450_pincfg pincfg[] = { WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0), WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0), WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0), - WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0), - WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(93, kbcc, MFSEL1, 17 | INV, none, NONE, 0), + WPCM450_PINCFG(94, kbcc, MFSEL1, 17 | INV, none, NONE, 0), WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0), WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0), @@ -805,6 +808,11 @@ static void wpcm450_update_mfsel(struct regmap *gcr_regmap, int reg, int bit, in { bool value = (fn == fn_selected); + if (bit & INV) { + value = !value; + bit &= ~INV; + } + regmap_update_bits(gcr_regmap, reg, BIT(bit), value ? BIT(bit) : 0); } -- cgit v1.2.3 From 3476b354c65db442580ef355885c69e60c546ef0 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Sun, 6 Nov 2022 09:01:11 +0100 Subject: pinctrl: mediatek: fix the pinconf register offset of some pins Correct the bias-pull-up, bias-pull-down and bias-disable register offset of mt7986 pin-42 to pin-49, in the original driver, the relative offset value was erroneously decremented by 1. Fixes: 360de6728064 ("pinctrl: mediatek: add support for MT7986 SoC") Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221106080114.7426-5-linux@fw-web.de Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index 95f32e62e02f..d13c59510468 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -316,10 +316,10 @@ static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), @@ -354,10 +354,10 @@ static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), @@ -392,10 +392,10 @@ static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), -- cgit v1.2.3 From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Sun, 6 Nov 2022 09:01:12 +0100 Subject: pinctrl: mediatek: extend pinctrl-moore to support new bias functions Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo and mtk_pinconf_bias_get_combo, and make the functions able to support almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. This patch enables pinctrl_moore to support these functions. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-moore.c | 49 +++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 7 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 9474ada5addb..1ec0413959e1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -8,6 +8,7 @@ * */ +#include #include #include @@ -108,7 +109,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); u32 param = pinconf_to_config_param(*config); - int val, val2, err, reg, ret = 1; + int val, val2, err, pullup, reg, ret = 1; const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; @@ -117,7 +118,13 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_disable_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE) + return -EINVAL; + } else if (hw->soc->bias_disable_get) { err = hw->soc->bias_disable_get(hw, desc, &ret); if (err) return err; @@ -126,7 +133,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, } break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) + return -EINVAL; + if (!pullup) + return -EINVAL; + } else if (hw->soc->bias_get) { err = hw->soc->bias_get(hw, desc, 1, &ret); if (err) return err; @@ -135,7 +150,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, } break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) + return -EINVAL; + if (pullup) + return -EINVAL; + } else if (hw->soc->bias_get) { err = hw->soc->bias_get(hw, desc, 0, &ret); if (err) return err; @@ -238,7 +261,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_disable_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); + if (err) + return err; + } else if (hw->soc->bias_disable_set) { err = hw->soc->bias_disable_set(hw, desc); if (err) return err; @@ -247,7 +274,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, } break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 1, arg); + if (err) + return err; + } else if (hw->soc->bias_set) { err = hw->soc->bias_set(hw, desc, 1); if (err) return err; @@ -256,7 +287,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, } break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 0, arg); + if (err) + return err; + } else if (hw->soc->bias_set) { err = hw->soc->bias_set(hw, desc, 0); if (err) return err; -- cgit v1.2.3 From 2c58d8dc9cd0692665f3512842d97ef2869cb027 Mon Sep 17 00:00:00 2001 From: Sam Shih Date: Sun, 6 Nov 2022 09:01:13 +0100 Subject: pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") add SoC specify 'pull_type' attribute for bias configuration. This patch add pull_type attribute to pinctrl-mt7986.c, and make bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index d13c59510468..db3497d6787a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), }; +static const unsigned int mt7986_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ + MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ + MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ + MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ + MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ + MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ + MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ + MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ + MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ + MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ + MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ + MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ + MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ + MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ + MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ + MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ + MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ + MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ + MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ + MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ +}; + static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), @@ -866,6 +920,7 @@ static struct mtk_pin_soc mt7986a_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1, @@ -887,6 +942,7 @@ static struct mtk_pin_soc mt7986b_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1, -- cgit v1.2.3 From 52d13b1d936ecb034b0a13b613188713efcdf6c3 Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Mon, 7 Nov 2022 02:15:10 -0500 Subject: pinctrl: freescale: Fix i.MXRT1050 pad names The pad names for the i.MXRT1050 were incorrect. Fix them. Cc: Giulio Benetti Signed-off-by: Jesse Taube Link: https://lore.kernel.org/r/20221107071511.2764628-7-Mr.Bossman075@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 546 ++++++++++++-------------- 1 file changed, 253 insertions(+), 293 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c index 11f31c90ad30..def683839ebe 100644 --- a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c @@ -13,155 +13,135 @@ #include "pinctrl-imx.h" enum imxrt1050_pads { - IMXRT1050_PAD_RESERVE0 = 0, - IMXRT1050_PAD_RESERVE1 = 1, - IMXRT1050_PAD_RESERVE2 = 2, - IMXRT1050_PAD_RESERVE3 = 3, - IMXRT1050_PAD_RESERVE4 = 4, - IMXRT1050_PAD_RESERVE5 = 5, - IMXRT1050_PAD_RESERVE6 = 6, - IMXRT1050_PAD_RESERVE7 = 7, - IMXRT1050_PAD_RESERVE8 = 8, - IMXRT1050_PAD_RESERVE9 = 9, - IMXRT1050_IOMUXC_GPIO1_IO00 = 10, - IMXRT1050_IOMUXC_GPIO1_IO01 = 11, - IMXRT1050_IOMUXC_GPIO1_IO02 = 12, - IMXRT1050_IOMUXC_GPIO1_IO03 = 13, - IMXRT1050_IOMUXC_GPIO1_IO04 = 14, - IMXRT1050_IOMUXC_GPIO1_IO05 = 15, - IMXRT1050_IOMUXC_GPIO1_IO06 = 16, - IMXRT1050_IOMUXC_GPIO1_IO07 = 17, - IMXRT1050_IOMUXC_GPIO1_IO08 = 18, - IMXRT1050_IOMUXC_GPIO1_IO09 = 19, - IMXRT1050_IOMUXC_GPIO1_IO10 = 20, - IMXRT1050_IOMUXC_GPIO1_IO11 = 21, - IMXRT1050_IOMUXC_GPIO1_IO12 = 22, - IMXRT1050_IOMUXC_GPIO1_IO13 = 23, - IMXRT1050_IOMUXC_GPIO1_IO14 = 24, - IMXRT1050_IOMUXC_GPIO1_IO15 = 25, - IMXRT1050_IOMUXC_ENET_MDC = 26, - IMXRT1050_IOMUXC_ENET_MDIO = 27, - IMXRT1050_IOMUXC_ENET_TD3 = 28, - IMXRT1050_IOMUXC_ENET_TD2 = 29, - IMXRT1050_IOMUXC_ENET_TD1 = 30, - IMXRT1050_IOMUXC_ENET_TD0 = 31, - IMXRT1050_IOMUXC_ENET_TX_CTL = 32, - IMXRT1050_IOMUXC_ENET_TXC = 33, - IMXRT1050_IOMUXC_ENET_RX_CTL = 34, - IMXRT1050_IOMUXC_ENET_RXC = 35, - IMXRT1050_IOMUXC_ENET_RD0 = 36, - IMXRT1050_IOMUXC_ENET_RD1 = 37, - IMXRT1050_IOMUXC_ENET_RD2 = 38, - IMXRT1050_IOMUXC_ENET_RD3 = 39, - IMXRT1050_IOMUXC_SD1_CLK = 40, - IMXRT1050_IOMUXC_SD1_CMD = 41, - IMXRT1050_IOMUXC_SD1_DATA0 = 42, - IMXRT1050_IOMUXC_SD1_DATA1 = 43, - IMXRT1050_IOMUXC_SD1_DATA2 = 44, - IMXRT1050_IOMUXC_SD1_DATA3 = 45, - IMXRT1050_IOMUXC_SD1_DATA4 = 46, - IMXRT1050_IOMUXC_SD1_DATA5 = 47, - IMXRT1050_IOMUXC_SD1_DATA6 = 48, - IMXRT1050_IOMUXC_SD1_DATA7 = 49, - IMXRT1050_IOMUXC_SD1_RESET_B = 50, - IMXRT1050_IOMUXC_SD1_STROBE = 51, - IMXRT1050_IOMUXC_SD2_CD_B = 52, - IMXRT1050_IOMUXC_SD2_CLK = 53, - IMXRT1050_IOMUXC_SD2_CMD = 54, - IMXRT1050_IOMUXC_SD2_DATA0 = 55, - IMXRT1050_IOMUXC_SD2_DATA1 = 56, - IMXRT1050_IOMUXC_SD2_DATA2 = 57, - IMXRT1050_IOMUXC_SD2_DATA3 = 58, - IMXRT1050_IOMUXC_SD2_RESET_B = 59, - IMXRT1050_IOMUXC_SD2_WP = 60, - IMXRT1050_IOMUXC_NAND_ALE = 61, - IMXRT1050_IOMUXC_NAND_CE0 = 62, - IMXRT1050_IOMUXC_NAND_CE1 = 63, - IMXRT1050_IOMUXC_NAND_CE2 = 64, - IMXRT1050_IOMUXC_NAND_CE3 = 65, - IMXRT1050_IOMUXC_NAND_CLE = 66, - IMXRT1050_IOMUXC_NAND_DATA00 = 67, - IMXRT1050_IOMUXC_NAND_DATA01 = 68, - IMXRT1050_IOMUXC_NAND_DATA02 = 69, - IMXRT1050_IOMUXC_NAND_DATA03 = 70, - IMXRT1050_IOMUXC_NAND_DATA04 = 71, - IMXRT1050_IOMUXC_NAND_DATA05 = 72, - IMXRT1050_IOMUXC_NAND_DATA06 = 73, - IMXRT1050_IOMUXC_NAND_DATA07 = 74, - IMXRT1050_IOMUXC_NAND_DQS = 75, - IMXRT1050_IOMUXC_NAND_RE_B = 76, - IMXRT1050_IOMUXC_NAND_READY_B = 77, - IMXRT1050_IOMUXC_NAND_WE_B = 78, - IMXRT1050_IOMUXC_NAND_WP_B = 79, - IMXRT1050_IOMUXC_SAI5_RXFS = 80, - IMXRT1050_IOMUXC_SAI5_RXC = 81, - IMXRT1050_IOMUXC_SAI5_RXD0 = 82, - IMXRT1050_IOMUXC_SAI5_RXD1 = 83, - IMXRT1050_IOMUXC_SAI5_RXD2 = 84, - IMXRT1050_IOMUXC_SAI5_RXD3 = 85, - IMXRT1050_IOMUXC_SAI5_MCLK = 86, - IMXRT1050_IOMUXC_SAI1_RXFS = 87, - IMXRT1050_IOMUXC_SAI1_RXC = 88, - IMXRT1050_IOMUXC_SAI1_RXD0 = 89, - IMXRT1050_IOMUXC_SAI1_RXD1 = 90, - IMXRT1050_IOMUXC_SAI1_RXD2 = 91, - IMXRT1050_IOMUXC_SAI1_RXD3 = 92, - IMXRT1050_IOMUXC_SAI1_RXD4 = 93, - IMXRT1050_IOMUXC_SAI1_RXD5 = 94, - IMXRT1050_IOMUXC_SAI1_RXD6 = 95, - IMXRT1050_IOMUXC_SAI1_RXD7 = 96, - IMXRT1050_IOMUXC_SAI1_TXFS = 97, - IMXRT1050_IOMUXC_SAI1_TXC = 98, - IMXRT1050_IOMUXC_SAI1_TXD0 = 99, - IMXRT1050_IOMUXC_SAI1_TXD1 = 100, - IMXRT1050_IOMUXC_SAI1_TXD2 = 101, - IMXRT1050_IOMUXC_SAI1_TXD3 = 102, - IMXRT1050_IOMUXC_SAI1_TXD4 = 103, - IMXRT1050_IOMUXC_SAI1_TXD5 = 104, - IMXRT1050_IOMUXC_SAI1_TXD6 = 105, - IMXRT1050_IOMUXC_SAI1_TXD7 = 106, - IMXRT1050_IOMUXC_SAI1_MCLK = 107, - IMXRT1050_IOMUXC_SAI2_RXFS = 108, - IMXRT1050_IOMUXC_SAI2_RXC = 109, - IMXRT1050_IOMUXC_SAI2_RXD0 = 110, - IMXRT1050_IOMUXC_SAI2_TXFS = 111, - IMXRT1050_IOMUXC_SAI2_TXC = 112, - IMXRT1050_IOMUXC_SAI2_TXD0 = 113, - IMXRT1050_IOMUXC_SAI2_MCLK = 114, - IMXRT1050_IOMUXC_SAI3_RXFS = 115, - IMXRT1050_IOMUXC_SAI3_RXC = 116, - IMXRT1050_IOMUXC_SAI3_RXD = 117, - IMXRT1050_IOMUXC_SAI3_TXFS = 118, - IMXRT1050_IOMUXC_SAI3_TXC = 119, - IMXRT1050_IOMUXC_SAI3_TXD = 120, - IMXRT1050_IOMUXC_SAI3_MCLK = 121, - IMXRT1050_IOMUXC_SPDIF_TX = 122, - IMXRT1050_IOMUXC_SPDIF_RX = 123, - IMXRT1050_IOMUXC_SPDIF_EXT_CLK = 124, - IMXRT1050_IOMUXC_ECSPI1_SCLK = 125, - IMXRT1050_IOMUXC_ECSPI1_MOSI = 126, - IMXRT1050_IOMUXC_ECSPI1_MISO = 127, - IMXRT1050_IOMUXC_ECSPI1_SS0 = 128, - IMXRT1050_IOMUXC_ECSPI2_SCLK = 129, - IMXRT1050_IOMUXC_ECSPI2_MOSI = 130, - IMXRT1050_IOMUXC_ECSPI2_MISO = 131, - IMXRT1050_IOMUXC_ECSPI2_SS0 = 132, - IMXRT1050_IOMUXC_I2C1_SCL = 133, - IMXRT1050_IOMUXC_I2C1_SDA = 134, - IMXRT1050_IOMUXC_I2C2_SCL = 135, - IMXRT1050_IOMUXC_I2C2_SDA = 136, - IMXRT1050_IOMUXC_I2C3_SCL = 137, - IMXRT1050_IOMUXC_I2C3_SDA = 138, - IMXRT1050_IOMUXC_I2C4_SCL = 139, - IMXRT1050_IOMUXC_I2C4_SDA = 140, - IMXRT1050_IOMUXC_UART1_RXD = 141, - IMXRT1050_IOMUXC_UART1_TXD = 142, - IMXRT1050_IOMUXC_UART2_RXD = 143, - IMXRT1050_IOMUXC_UART2_TXD = 144, - IMXRT1050_IOMUXC_UART3_RXD = 145, - IMXRT1050_IOMUXC_UART3_TXD = 146, - IMXRT1050_IOMUXC_UART4_RXD = 147, - IMXRT1050_IOMUXC_UART4_TXD = 148, + IMXRT1050_PAD_RESERVE0, + IMXRT1050_PAD_RESERVE1, + IMXRT1050_PAD_RESERVE2, + IMXRT1050_PAD_RESERVE3, + IMXRT1050_PAD_RESERVE4, + IMXRT1050_PAD_EMC_00, + IMXRT1050_PAD_EMC_01, + IMXRT1050_PAD_EMC_02, + IMXRT1050_PAD_EMC_03, + IMXRT1050_PAD_EMC_04, + IMXRT1050_PAD_EMC_05, + IMXRT1050_PAD_EMC_06, + IMXRT1050_PAD_EMC_07, + IMXRT1050_PAD_EMC_08, + IMXRT1050_PAD_EMC_09, + IMXRT1050_PAD_EMC_10, + IMXRT1050_PAD_EMC_11, + IMXRT1050_PAD_EMC_12, + IMXRT1050_PAD_EMC_13, + IMXRT1050_PAD_EMC_14, + IMXRT1050_PAD_EMC_15, + IMXRT1050_PAD_EMC_16, + IMXRT1050_PAD_EMC_17, + IMXRT1050_PAD_EMC_18, + IMXRT1050_PAD_EMC_19, + IMXRT1050_PAD_EMC_20, + IMXRT1050_PAD_EMC_21, + IMXRT1050_PAD_EMC_22, + IMXRT1050_PAD_EMC_23, + IMXRT1050_PAD_EMC_24, + IMXRT1050_PAD_EMC_25, + IMXRT1050_PAD_EMC_26, + IMXRT1050_PAD_EMC_27, + IMXRT1050_PAD_EMC_28, + IMXRT1050_PAD_EMC_29, + IMXRT1050_PAD_EMC_30, + IMXRT1050_PAD_EMC_31, + IMXRT1050_PAD_EMC_32, + IMXRT1050_PAD_EMC_33, + IMXRT1050_PAD_EMC_34, + IMXRT1050_PAD_EMC_35, + IMXRT1050_PAD_EMC_36, + IMXRT1050_PAD_EMC_37, + IMXRT1050_PAD_EMC_38, + IMXRT1050_PAD_EMC_39, + IMXRT1050_PAD_EMC_40, + IMXRT1050_PAD_EMC_41, + IMXRT1050_PAD_AD_B0_00, + IMXRT1050_PAD_AD_B0_01, + IMXRT1050_PAD_AD_B0_02, + IMXRT1050_PAD_AD_B0_03, + IMXRT1050_PAD_AD_B0_04, + IMXRT1050_PAD_AD_B0_05, + IMXRT1050_PAD_AD_B0_06, + IMXRT1050_PAD_AD_B0_07, + IMXRT1050_PAD_AD_B0_08, + IMXRT1050_PAD_AD_B0_09, + IMXRT1050_PAD_AD_B0_10, + IMXRT1050_PAD_AD_B0_11, + IMXRT1050_PAD_AD_B0_12, + IMXRT1050_PAD_AD_B0_13, + IMXRT1050_PAD_AD_B0_14, + IMXRT1050_PAD_AD_B0_15, + IMXRT1050_PAD_AD_B1_00, + IMXRT1050_PAD_AD_B1_01, + IMXRT1050_PAD_AD_B1_02, + IMXRT1050_PAD_AD_B1_03, + IMXRT1050_PAD_AD_B1_04, + IMXRT1050_PAD_AD_B1_05, + IMXRT1050_PAD_AD_B1_06, + IMXRT1050_PAD_AD_B1_07, + IMXRT1050_PAD_AD_B1_08, + IMXRT1050_PAD_AD_B1_09, + IMXRT1050_PAD_AD_B1_10, + IMXRT1050_PAD_AD_B1_11, + IMXRT1050_PAD_AD_B1_12, + IMXRT1050_PAD_AD_B1_13, + IMXRT1050_PAD_AD_B1_14, + IMXRT1050_PAD_AD_B1_15, + IMXRT1050_PAD_B0_00, + IMXRT1050_PAD_B0_01, + IMXRT1050_PAD_B0_02, + IMXRT1050_PAD_B0_03, + IMXRT1050_PAD_B0_04, + IMXRT1050_PAD_B0_05, + IMXRT1050_PAD_B0_06, + IMXRT1050_PAD_B0_07, + IMXRT1050_PAD_B0_08, + IMXRT1050_PAD_B0_09, + IMXRT1050_PAD_B0_10, + IMXRT1050_PAD_B0_11, + IMXRT1050_PAD_B0_12, + IMXRT1050_PAD_B0_13, + IMXRT1050_PAD_B0_14, + IMXRT1050_PAD_B0_15, + IMXRT1050_PAD_B1_00, + IMXRT1050_PAD_B1_01, + IMXRT1050_PAD_B1_02, + IMXRT1050_PAD_B1_03, + IMXRT1050_PAD_B1_04, + IMXRT1050_PAD_B1_05, + IMXRT1050_PAD_B1_06, + IMXRT1050_PAD_B1_07, + IMXRT1050_PAD_B1_08, + IMXRT1050_PAD_B1_09, + IMXRT1050_PAD_B1_10, + IMXRT1050_PAD_B1_11, + IMXRT1050_PAD_B1_12, + IMXRT1050_PAD_B1_13, + IMXRT1050_PAD_B1_14, + IMXRT1050_PAD_B1_15, + IMXRT1050_PAD_SD_B0_00, + IMXRT1050_PAD_SD_B0_01, + IMXRT1050_PAD_SD_B0_02, + IMXRT1050_PAD_SD_B0_03, + IMXRT1050_PAD_SD_B0_04, + IMXRT1050_PAD_SD_B0_05, + IMXRT1050_PAD_SD_B1_00, + IMXRT1050_PAD_SD_B1_01, + IMXRT1050_PAD_SD_B1_02, + IMXRT1050_PAD_SD_B1_03, + IMXRT1050_PAD_SD_B1_04, + IMXRT1050_PAD_SD_B1_05, + IMXRT1050_PAD_SD_B1_06, + IMXRT1050_PAD_SD_B1_07, + IMXRT1050_PAD_SD_B1_08, + IMXRT1050_PAD_SD_B1_09, + IMXRT1050_PAD_SD_B1_10, + IMXRT1050_PAD_SD_B1_11, }; /* Pad names for the pinmux subsystem */ @@ -171,150 +151,130 @@ static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = { IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2), IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3), IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE5), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE6), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE7), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE8), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE9), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO00), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO01), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO02), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO03), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO04), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO05), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO06), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO07), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO08), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO09), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO10), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO11), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO12), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO13), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO14), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO15), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDIO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TX_CTL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RX_CTL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CMD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_RESET_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_STROBE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CD_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CMD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_RESET_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_WP), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_ALE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CLE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA00), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA01), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA02), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA03), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA04), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA05), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA06), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA07), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DQS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_RE_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_READY_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WE_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WP_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_TX), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_RX), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_EXT_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MOSI), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MISO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SS0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MOSI), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MISO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SS0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_TXD), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_16), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_17), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_18), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_19), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_20), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_21), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_22), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_23), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_24), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_25), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_26), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_27), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_28), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_29), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_30), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_31), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_32), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_33), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_34), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_35), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_36), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_37), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_38), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_39), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_40), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_41), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_11), }; static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = { -- cgit v1.2.3 From 5a0047360743695ecfe4ca33300222ddd39c4612 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 4 Nov 2022 15:23:44 +0100 Subject: pinctrl: tegra: Separate Tegra194 instances Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/tegra/pinctrl-tegra.c | 33 ++-- drivers/pinctrl/tegra/pinctrl-tegra.h | 2 + drivers/pinctrl/tegra/pinctrl-tegra194.c | 286 +++++++++++++++++-------------- 3 files changed, 173 insertions(+), 148 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 834a2d50f89b..1729b7ddfa94 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -670,19 +670,6 @@ static const struct pinconf_ops tegra_pinconf_ops = { #endif }; -static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { - .name = "Tegra GPIOs", - .id = 0, - .base = 0, -}; - -static struct pinctrl_desc tegra_pinctrl_desc = { - .pctlops = &tegra_pinctrl_ops, - .pmxops = &tegra_pinmux_ops, - .confops = &tegra_pinconf_ops, - .owner = THIS_MODULE, -}; - static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) { int i = 0; @@ -833,10 +820,18 @@ int tegra_pinctrl_probe(struct platform_device *pdev, } } - tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; - tegra_pinctrl_desc.name = dev_name(&pdev->dev); - tegra_pinctrl_desc.pins = pmx->soc->pins; - tegra_pinctrl_desc.npins = pmx->soc->npins; + pmx->gpio_range.name = "Tegra GPIOs"; + pmx->gpio_range.id = 0; + pmx->gpio_range.base = 0; + pmx->gpio_range.npins = pmx->soc->ngpios; + + pmx->desc.pctlops = &tegra_pinctrl_ops; + pmx->desc.pmxops = &tegra_pinmux_ops; + pmx->desc.confops = &tegra_pinconf_ops; + pmx->desc.owner = THIS_MODULE; + pmx->desc.name = dev_name(&pdev->dev); + pmx->desc.pins = pmx->soc->pins; + pmx->desc.npins = pmx->soc->npins; for (i = 0; ; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); @@ -862,7 +857,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, return PTR_ERR(pmx->regs[i]); } - pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx); + pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx); if (IS_ERR(pmx->pctl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); return PTR_ERR(pmx->pctl); @@ -871,7 +866,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, tegra_pinctrl_clear_parked_bits(pmx); if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) - pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); + pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range); platform_set_drvdata(pdev, pmx); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index f8269858eb78..6130cba7cce5 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -15,6 +15,8 @@ struct tegra_pmx { const struct tegra_pinctrl_soc_data *soc; const char **group_pins; + struct pinctrl_gpio_range gpio_range; + struct pinctrl_desc desc; int nbanks; void __iomem **regs; u32 *backup_regs; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c index f6c5d5e6dbb6..277973c88434 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include @@ -23,7 +24,7 @@ #include "pinctrl-tegra.h" /* Define unique ID for each pins */ -enum pin_id { +enum { TEGRA_PIN_DAP6_SCLK_PA0, TEGRA_PIN_DAP6_DOUT_PA1, TEGRA_PIN_DAP6_DIN_PA2, @@ -189,6 +190,31 @@ enum pin_id { TEGRA_PIN_SPI1_MOSI_PZ5, TEGRA_PIN_SPI1_CS0_PZ6, TEGRA_PIN_SPI1_CS1_PZ7, + TEGRA_PIN_UFS0_REF_CLK_PFF0, + TEGRA_PIN_UFS0_RST_PFF1, + TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, + TEGRA_PIN_PEX_L5_RST_N_PGG1, + TEGRA_PIN_DIRECTDC_COMP, + TEGRA_PIN_SDMMC4_CLK, + TEGRA_PIN_SDMMC4_CMD, + TEGRA_PIN_SDMMC4_DQS, + TEGRA_PIN_SDMMC4_DAT7, + TEGRA_PIN_SDMMC4_DAT6, + TEGRA_PIN_SDMMC4_DAT5, + TEGRA_PIN_SDMMC4_DAT4, + TEGRA_PIN_SDMMC4_DAT3, + TEGRA_PIN_SDMMC4_DAT2, + TEGRA_PIN_SDMMC4_DAT1, + TEGRA_PIN_SDMMC4_DAT0, + TEGRA_PIN_SDMMC1_COMP, + TEGRA_PIN_SDMMC1_HV_TRIM, + TEGRA_PIN_SDMMC3_COMP, + TEGRA_PIN_SDMMC3_HV_TRIM, + TEGRA_PIN_EQOS_COMP, + TEGRA_PIN_QSPI_COMP, +}; + +enum { TEGRA_PIN_CAN1_DOUT_PAA0, TEGRA_PIN_CAN1_DIN_PAA1, TEGRA_PIN_CAN0_DOUT_PAA2, @@ -219,28 +245,6 @@ enum pin_id { TEGRA_PIN_POWER_ON_PEE4, TEGRA_PIN_PWR_I2C_SCL_PEE5, TEGRA_PIN_PWR_I2C_SDA_PEE6, - TEGRA_PIN_UFS0_REF_CLK_PFF0, - TEGRA_PIN_UFS0_RST_PFF1, - TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, - TEGRA_PIN_PEX_L5_RST_N_PGG1, - TEGRA_PIN_DIRECTDC_COMP, - TEGRA_PIN_SDMMC4_CLK, - TEGRA_PIN_SDMMC4_CMD, - TEGRA_PIN_SDMMC4_DQS, - TEGRA_PIN_SDMMC4_DAT7, - TEGRA_PIN_SDMMC4_DAT6, - TEGRA_PIN_SDMMC4_DAT5, - TEGRA_PIN_SDMMC4_DAT4, - TEGRA_PIN_SDMMC4_DAT3, - TEGRA_PIN_SDMMC4_DAT2, - TEGRA_PIN_SDMMC4_DAT1, - TEGRA_PIN_SDMMC4_DAT0, - TEGRA_PIN_SDMMC1_COMP, - TEGRA_PIN_SDMMC1_HV_TRIM, - TEGRA_PIN_SDMMC3_COMP, - TEGRA_PIN_SDMMC3_HV_TRIM, - TEGRA_PIN_EQOS_COMP, - TEGRA_PIN_QSPI_COMP, TEGRA_PIN_SYS_RESET_N, TEGRA_PIN_SHUTDOWN_N, TEGRA_PIN_PMU_INT_N, @@ -415,36 +419,6 @@ static const struct pinctrl_pin_desc tegra194_pins[] = { PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"), PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"), PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"), - PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"), - PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"), - PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"), - PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"), - PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"), - PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"), - PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"), - PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"), - PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"), - PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"), - PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"), - PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"), - PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"), - PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"), - PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"), - PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"), - PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"), - PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"), - PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"), - PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"), - PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"), - PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"), - PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"), - PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"), - PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"), - PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"), - PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"), - PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"), - PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"), - PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"), PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PFF0, "UFS0_REF_CLK_PFF0"), PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PFF1, "UFS0_RST_PFF1"), PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"), @@ -467,11 +441,6 @@ static const struct pinctrl_pin_desc tegra194_pins[] = { PINCTRL_PIN(TEGRA_PIN_SDMMC3_HV_TRIM, "SDMMC3_HV_TRIM"), PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"), PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"), - PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"), - PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"), - PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"), - PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"), - PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), }; static const unsigned int dap6_sclk_pa0_pins[] = { @@ -1379,29 +1348,7 @@ static struct tegra_function tegra194_functions[] = { .drvtype_bit = 13, \ .lpdr_bit = e_lpdr, \ -#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 1) +/* main drive pin groups */ #define drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0) #define drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0) #define drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0) @@ -1509,17 +1456,6 @@ static struct tegra_function tegra194_functions[] = { #define drive_sdmmc3_dat0_po2 DRV_PINGROUP_ENTRY_Y(0xa01c, -1, -1, -1, -1, 28, 2, 30, 2, 0) #define drive_sdmmc3_cmd_po1 DRV_PINGROUP_ENTRY_Y(0xa02c, -1, -1, -1, -1, 28, 2, 30, 2, 0) #define drive_sdmmc3_clk_po0 DRV_PINGROUP_ENTRY_Y(0xa034, -1, -1, -1, -1, 28, 2, 30, 2, 0) -#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1) #define drive_gpu_pwr_req_px0 DRV_PINGROUP_ENTRY_Y(0xD004, 12, 5, 20, 5, -1, -1, -1, -1, 0) #define drive_spi3_miso_py1 DRV_PINGROUP_ENTRY_Y(0xD00c, 12, 5, 20, 5, -1, -1, -1, -1, 0) #define drive_spi1_cs0_pz6 DRV_PINGROUP_ENTRY_Y(0xD014, 12, 5, 20, 5, -1, -1, -1, -1, 0) @@ -1600,6 +1536,42 @@ static struct tegra_function tegra194_functions[] = { #define drive_directdc1_in_pv1 DRV_PINGROUP_ENTRY_N(no_entry) #define drive_directdc1_clk_pv0 DRV_PINGROUP_ENTRY_N(no_entry) +/* AON drive pin groups */ +#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 0) + #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \ gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in, io_rail) \ { \ @@ -1622,30 +1594,6 @@ static struct tegra_function tegra194_functions[] = { } static const struct tegra_pingroup tegra194_groups[] = { - - PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), PINGROUP(soc_gpio33_pt0, RSVD0, SPDIF, RSVD2, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"), PINGROUP(soc_gpio32_ps7, RSVD0, SPDIF, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"), PINGROUP(soc_gpio31_ps6, RSVD0, SDMMC1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"), @@ -1805,17 +1753,6 @@ static const struct tegra_pingroup tegra194_groups[] = { PINGROUP(sdmmc4_dat2, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"), PINGROUP(sdmmc4_dat1, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"), PINGROUP(sdmmc4_dat0, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"), - PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 1, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 1, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), PINGROUP(gpu_pwr_req_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0xD000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"), PINGROUP(spi3_miso_py1, SPI3, RSVD1, RSVD2, RSVD3, 0xD008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"), PINGROUP(spi1_cs0_pz6, SPI1, RSVD1, RSVD2, RSVD3, 0xD010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"), @@ -1857,13 +1794,104 @@ static const struct tegra_pinctrl_soc_data tegra194_pinctrl = { .sfsel_in_mux = true, }; +static const struct pinctrl_pin_desc tegra194_aon_pins[] = { + PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"), + PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"), + PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"), + PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"), + PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"), + PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"), + PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"), + PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"), + PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"), + PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"), + PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"), + PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"), + PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"), + PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"), + PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"), + PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"), + PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"), + PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"), + PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"), + PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"), + PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"), + PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"), + PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"), + PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"), + PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"), + PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"), + PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"), + PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"), + PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), +}; + +static const struct tegra_pingroup tegra194_aon_groups[] = { + PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), +}; + +static const struct tegra_pinctrl_soc_data tegra194_pinctrl_aon = { + .pins = tegra194_aon_pins, + .npins = ARRAY_SIZE(tegra194_aon_pins), + .functions = tegra194_functions, + .nfunctions = ARRAY_SIZE(tegra194_functions), + .groups = tegra194_aon_groups, + .ngroups = ARRAY_SIZE(tegra194_aon_groups), + .hsm_in_mux = true, + .schmitt_in_mux = true, + .drvtype_in_mux = true, + .sfsel_in_mux = true, +}; + static int tegra194_pinctrl_probe(struct platform_device *pdev) { - return tegra_pinctrl_probe(pdev, &tegra194_pinctrl); + const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev); + + return tegra_pinctrl_probe(pdev, soc); } static const struct of_device_id tegra194_pinctrl_of_match[] = { - { .compatible = "nvidia,tegra194-pinmux", }, + { .compatible = "nvidia,tegra194-pinmux", .data = &tegra194_pinctrl }, + { .compatible = "nvidia,tegra194-pinmux-aon", .data = &tegra194_pinctrl_aon }, { }, }; -- cgit v1.2.3 From 06de519345f4af5b7ee48aaa30228fe5ac5de233 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 11 Nov 2022 14:00:48 +0200 Subject: pinctrl: Move for_each_maps() to namespace and hide iterator inside First of all, while for_each_maps() is private to pin control subsystem it's still better to have it put into a namespace. Besides that, users are not relying on iterator variable, so hide it inside for-loop. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20221111120048.42968-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/core.c | 6 ++---- drivers/pinctrl/core.h | 10 +++++----- 2 files changed, 7 insertions(+), 9 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 655f9502e73f..41fd84738707 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1029,7 +1029,6 @@ static struct pinctrl *create_pinctrl(struct device *dev, struct pinctrl *p; const char *devname; struct pinctrl_maps *maps_node; - int i; const struct pinctrl_map *map; int ret; @@ -1055,7 +1054,7 @@ static struct pinctrl *create_pinctrl(struct device *dev, mutex_lock(&pinctrl_maps_mutex); /* Iterate over the pin control maps to locate the right ones */ - for_each_maps(maps_node, i, map) { + for_each_pin_map(maps_node, map) { /* Map must be for this device */ if (strcmp(map->dev_name, devname)) continue; @@ -1806,13 +1805,12 @@ static inline const char *map_type(enum pinctrl_map_type type) static int pinctrl_maps_show(struct seq_file *s, void *what) { struct pinctrl_maps *maps_node; - int i; const struct pinctrl_map *map; seq_puts(s, "Pinctrl maps:\n"); mutex_lock(&pinctrl_maps_mutex); - for_each_maps(maps_node, i, map) { + for_each_pin_map(maps_node, map) { seq_printf(s, "device %s\nstate %s\ntype %s (%d)\n", map->dev_name, map->name, map_type(map->type), map->type); diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 4d0bdb9fb99b..530370443c19 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -252,8 +252,8 @@ extern int pinctrl_force_default(struct pinctrl_dev *pctldev); extern struct mutex pinctrl_maps_mutex; extern struct list_head pinctrl_maps; -#define for_each_maps(_maps_node_, _i_, _map_) \ - list_for_each_entry(_maps_node_, &pinctrl_maps, node) \ - for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \ - _i_ < _maps_node_->num_maps; \ - _i_++, _map_ = &_maps_node_->maps[_i_]) +#define for_each_pin_map(_maps_node_, _map_) \ + list_for_each_entry(_maps_node_, &pinctrl_maps, node) \ + for (unsigned int __i = 0; \ + __i < _maps_node_->num_maps && (_map_ = &_maps_node_->maps[__i]); \ + __i++) -- cgit v1.2.3 From d871ea85917599ce4aa507f8b5521e17656a09dc Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 8 Nov 2022 18:32:23 +0000 Subject: pinctrl: renesas: rzv2m: remove unnecessary check from rzv2m_dt_node_to_map() This patch removes the unnecessary check from rzv2m_dt_node_to_map() as the ret value is already negative. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20221108183223.3902097-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzv2m.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index e8c18198bebd..62e911b7d007 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -397,8 +397,7 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev, ret = -EINVAL; done: - if (ret < 0) - rzv2m_dt_free_map(pctldev, *map, *num_maps); + rzv2m_dt_free_map(pctldev, *map, *num_maps); return ret; } -- cgit v1.2.3 From 41a87e789c7c2cdeb302331043f866c0138f0413 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 8 Nov 2022 19:13:09 +0000 Subject: pinctrl: renesas: rzg2l: remove unnecessary check from rzg2l_dt_node_to_map() This patch removes the unnecessary check from rzg2l_dt_node_to_map() as the ret value is already negative. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20221108191309.3908415-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a43824fd9505..4e79b2961232 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -435,8 +435,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, ret = -EINVAL; done: - if (ret < 0) - rzg2l_dt_free_map(pctldev, *map, *num_maps); + rzg2l_dt_free_map(pctldev, *map, *num_maps); return ret; } -- cgit v1.2.3 From f73f88acbc18a679def4c16eb8648cc279995075 Mon Sep 17 00:00:00 2001 From: zhanghongchen Date: Mon, 14 Nov 2022 10:49:41 +0800 Subject: pinctrl: pinctrl-loongson2: add pinctrl driver support The Loongson-2 SoC has a few pins that can be used as GPIOs or take multiple other functions. Add a driver for the pinmuxing. There is currently no support for GPIO pin pull-up and pull-down. Signed-off-by: zhanghongchen Co-developed-by: Yinbo Zhu Signed-off-by: Yinbo Zhu Link: https://lore.kernel.org/r/20221114024942.8111-1-zhuyinbo@loongson.cn Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 11 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-loongson2.c | 311 ++++++++++++++++++++++++++++++++++++ 3 files changed, 323 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-loongson2.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f71fefff400f..35f167f70829 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -258,6 +258,17 @@ config PINCTRL_FALCON depends on SOC_FALCON depends on PINCTRL_LANTIQ +config PINCTRL_LOONGSON2 + tristate "Pinctrl driver for the Loongson-2 SoC" + depends on LOONGARCH || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + help + This selects pin control driver for the Loongson-2 SoC. It + provides pin config functions multiplexing. GPIO pin pull-up, + pull-down functions are not supported. Say yes to enable + pinctrl for Loongson-2 SoC. + config PINCTRL_XWAY bool depends on SOC_TYPE_XWAY diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 89bfa01b5231..d5939840bb2a 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o obj-$(CONFIG_PINCTRL_KEEMBAY) += pinctrl-keembay.o obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o +obj-$(CONFIG_PINCTRL_LOONGSON2) += pinctrl-loongson2.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o diff --git a/drivers/pinctrl/pinctrl-loongson2.c b/drivers/pinctrl/pinctrl-loongson2.c new file mode 100644 index 000000000000..1e9ec87e6930 --- /dev/null +++ b/drivers/pinctrl/pinctrl-loongson2.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: zhanghongchen + * Yinbo Zhu + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" + +#define PMX_GROUP(name, offset, bitv) \ + { \ + .grp = PINCTRL_PINGROUP((#name), (name ## _pins), \ + ARRAY_SIZE((name ## _pins))), \ + .reg = offset, \ + .bit = bitv, \ + } + +#define SPECIFIC_GROUP(group) \ + static const char * const group##_groups[] = { \ + #group \ + } + +#define FUNCTION(fn) \ + { \ + .name = #fn, \ + .groups = fn ## _groups, \ + .num_groups = ARRAY_SIZE(fn ## _groups), \ + } + +struct loongson2_pinctrl { + struct device *dev; + struct pinctrl_dev *pcdev; + struct pinctrl_desc desc; + struct device_node *of_node; + spinlock_t lock; + void * __iomem reg_base; +}; + +struct loongson2_pmx_group { + struct pingroup grp; + unsigned int reg; + unsigned int bit; +}; + +struct loongson2_pmx_func { + const char *name; + const char * const *groups; + unsigned int num_groups; +}; + +#define LOONGSON2_PIN(x) PINCTRL_PIN(x, "gpio"#x) +static const struct pinctrl_pin_desc loongson2_pctrl_pins[] = { + LOONGSON2_PIN(0), LOONGSON2_PIN(1), LOONGSON2_PIN(2), LOONGSON2_PIN(3), + LOONGSON2_PIN(4), LOONGSON2_PIN(5), LOONGSON2_PIN(6), LOONGSON2_PIN(7), + LOONGSON2_PIN(8), LOONGSON2_PIN(9), LOONGSON2_PIN(10), LOONGSON2_PIN(11), + LOONGSON2_PIN(12), LOONGSON2_PIN(13), LOONGSON2_PIN(14), + LOONGSON2_PIN(16), LOONGSON2_PIN(17), LOONGSON2_PIN(18), LOONGSON2_PIN(19), + LOONGSON2_PIN(20), LOONGSON2_PIN(21), LOONGSON2_PIN(22), LOONGSON2_PIN(23), + LOONGSON2_PIN(24), LOONGSON2_PIN(25), LOONGSON2_PIN(26), LOONGSON2_PIN(27), + LOONGSON2_PIN(28), LOONGSON2_PIN(29), LOONGSON2_PIN(30), + LOONGSON2_PIN(32), LOONGSON2_PIN(33), LOONGSON2_PIN(34), LOONGSON2_PIN(35), + LOONGSON2_PIN(36), LOONGSON2_PIN(37), LOONGSON2_PIN(38), LOONGSON2_PIN(39), + LOONGSON2_PIN(40), LOONGSON2_PIN(41), + LOONGSON2_PIN(44), LOONGSON2_PIN(45), LOONGSON2_PIN(46), LOONGSON2_PIN(47), + LOONGSON2_PIN(48), LOONGSON2_PIN(49), LOONGSON2_PIN(50), LOONGSON2_PIN(51), + LOONGSON2_PIN(52), LOONGSON2_PIN(53), LOONGSON2_PIN(54), LOONGSON2_PIN(55), + LOONGSON2_PIN(56), LOONGSON2_PIN(57), LOONGSON2_PIN(58), LOONGSON2_PIN(59), + LOONGSON2_PIN(60), LOONGSON2_PIN(61), LOONGSON2_PIN(62), LOONGSON2_PIN(63), +}; + +static const unsigned int gpio_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 46, 55, + 56, 57, 58, 59, 60, 61, 62, 63}; +static const unsigned int sdio_pins[] = {36, 37, 38, 39, 40, 41}; +static const unsigned int can1_pins[] = {34, 35}; +static const unsigned int can0_pins[] = {32, 33}; +static const unsigned int pwm3_pins[] = {23}; +static const unsigned int pwm2_pins[] = {22}; +static const unsigned int pwm1_pins[] = {21}; +static const unsigned int pwm0_pins[] = {20}; +static const unsigned int i2c1_pins[] = {18, 19}; +static const unsigned int i2c0_pins[] = {16, 17}; +static const unsigned int nand_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, + 52, 53, 54, 55, 56, 57, 58, 59, 60, + 61, 62, 63}; +static const unsigned int sata_led_pins[] = {14}; +static const unsigned int i2s_pins[] = {24, 25, 26, 27, 28}; +static const unsigned int hda_pins[] = {24, 25, 26, 27, 28, 29, 30}; + +static struct loongson2_pmx_group loongson2_pmx_groups[] = { + PMX_GROUP(gpio, 0x0, 64), + PMX_GROUP(sdio, 0x0, 20), + PMX_GROUP(can1, 0x0, 17), + PMX_GROUP(can0, 0x0, 16), + PMX_GROUP(pwm3, 0x0, 15), + PMX_GROUP(pwm2, 0x0, 14), + PMX_GROUP(pwm1, 0x0, 13), + PMX_GROUP(pwm0, 0x0, 12), + PMX_GROUP(i2c1, 0x0, 11), + PMX_GROUP(i2c0, 0x0, 10), + PMX_GROUP(nand, 0x0, 9), + PMX_GROUP(sata_led, 0x0, 8), + PMX_GROUP(i2s, 0x0, 6), + PMX_GROUP(hda, 0x0, 4), +}; + +SPECIFIC_GROUP(sdio); +SPECIFIC_GROUP(can1); +SPECIFIC_GROUP(can0); +SPECIFIC_GROUP(pwm3); +SPECIFIC_GROUP(pwm2); +SPECIFIC_GROUP(pwm1); +SPECIFIC_GROUP(pwm0); +SPECIFIC_GROUP(i2c1); +SPECIFIC_GROUP(i2c0); +SPECIFIC_GROUP(nand); +SPECIFIC_GROUP(sata_led); +SPECIFIC_GROUP(i2s); +SPECIFIC_GROUP(hda); + +static const char * const gpio_groups[] = { + "sdio", + "can1", "can0", + "pwm3", "pwm2", "pwm1", "pwm0", + "i2c1", "i2c0", + "nand", + "sata_led", + "i2s", + "hda", +}; + +static const struct loongson2_pmx_func loongson2_pmx_functions[] = { + FUNCTION(gpio), + FUNCTION(sdio), + FUNCTION(can1), + FUNCTION(can0), + FUNCTION(pwm3), + FUNCTION(pwm2), + FUNCTION(pwm1), + FUNCTION(pwm0), + FUNCTION(i2c1), + FUNCTION(i2c0), + FUNCTION(nand), + FUNCTION(sata_led), + FUNCTION(i2s), + FUNCTION(hda), +}; + +static int loongson2_get_groups_count(struct pinctrl_dev *pcdev) +{ + return ARRAY_SIZE(loongson2_pmx_groups); +} + +static const char *loongson2_get_group_name(struct pinctrl_dev *pcdev, + unsigned int selector) +{ + return loongson2_pmx_groups[selector].grp.name; +} + +static int loongson2_get_group_pins(struct pinctrl_dev *pcdev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + *pins = loongson2_pmx_groups[selector].grp.pins; + *num_pins = loongson2_pmx_groups[selector].grp.npins; + + return 0; +} + +static void loongson2_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, + unsigned int offset) +{ + seq_printf(s, " %s", dev_name(pcdev->dev)); +} + +static const struct pinctrl_ops loongson2_pctrl_ops = { + .get_groups_count = loongson2_get_groups_count, + .get_group_name = loongson2_get_group_name, + .get_group_pins = loongson2_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, + .pin_dbg_show = loongson2_pin_dbg_show, +}; + +static int loongson2_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned int func_num, + unsigned int group_num) +{ + struct loongson2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pcdev); + void * __iomem reg = pctrl->reg_base + + loongson2_pmx_groups[group_num].reg; + unsigned int mux_bit = loongson2_pmx_groups[group_num].bit; + unsigned int val; + unsigned long flags; + + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(reg); + if (func_num == 0) + val &= ~BIT(mux_bit); + else + val |= BIT(mux_bit); + writel(val, reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int loongson2_pmx_get_funcs_count(struct pinctrl_dev *pcdev) +{ + return ARRAY_SIZE(loongson2_pmx_functions); +} + +static const char *loongson2_pmx_get_func_name(struct pinctrl_dev *pcdev, + unsigned int selector) +{ + return loongson2_pmx_functions[selector].name; +} + +static int loongson2_pmx_get_groups(struct pinctrl_dev *pcdev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = loongson2_pmx_functions[selector].groups; + *num_groups = loongson2_pmx_functions[selector].num_groups; + + return 0; +} + +static const struct pinmux_ops loongson2_pmx_ops = { + .set_mux = loongson2_pmx_set_mux, + .get_functions_count = loongson2_pmx_get_funcs_count, + .get_function_name = loongson2_pmx_get_func_name, + .get_function_groups = loongson2_pmx_get_groups, +}; + +static int loongson2_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct loongson2_pinctrl *pctrl; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->reg_base)) + return PTR_ERR(pctrl->reg_base); + + spin_lock_init(&pctrl->lock); + + pctrl->dev = dev; + pctrl->desc.name = "pinctrl-loongson2"; + pctrl->desc.owner = THIS_MODULE; + pctrl->desc.pctlops = &loongson2_pctrl_ops; + pctrl->desc.pmxops = &loongson2_pmx_ops; + pctrl->desc.pins = loongson2_pctrl_pins; + pctrl->desc.npins = ARRAY_SIZE(loongson2_pctrl_pins); + + pctrl->pcdev = devm_pinctrl_register(pctrl->dev, &pctrl->desc, pctrl); + if (IS_ERR(pctrl->pcdev)) + return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->pcdev), + "can't register pinctrl device"); + + return 0; +} + +static const struct of_device_id loongson2_pinctrl_dt_match[] = { + { + .compatible = "loongson,ls2k-pinctrl", + }, + { } +}; + +static struct platform_driver loongson2_pinctrl_driver = { + .probe = loongson2_pinctrl_probe, + .driver = { + .name = "loongson2-pinctrl", + .of_match_table = loongson2_pinctrl_dt_match, + }, +}; + +static int __init loongson2_pinctrl_init(void) +{ + return platform_driver_register(&loongson2_pinctrl_driver); +} +arch_initcall(loongson2_pinctrl_init); + +static void __exit loongson2_pinctrl_exit(void) +{ + platform_driver_unregister(&loongson2_pinctrl_driver); +} +module_exit(loongson2_pinctrl_exit); + +MODULE_DESCRIPTION("Loongson2 Pinctrl driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 80d34260f36c6c55f03c3c33be4a11ec06202e98 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 Nov 2022 14:33:04 +0100 Subject: pinctrl: renesas: gpio: Use dynamic GPIO base if no function GPIOs Since commit 502df79b860563d7 ("gpiolib: Warn on drivers still using static gpiobase allocation") in gpio/for-next, one or more warnings are printed during boot on systems where the pin controller also provides GPIO functionality: gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation. Fix this for ARM-based SH/R-Mobile SoCs by: 1. Taking into account a non-zero GPIO base in the various GPIO chip callbacks, 2. Switching to dynamic allocation of the GPIO base when support for legacy function GPIOs is not enabled. On SuperH SoCs using legacy function GPIOs, the GPIO bases of the GPIO controller and the GPIO function controller must not be changed, as all board files rely on the fixed GPIO_* and GPIO_FN_* definitions provided by the various header files. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/df2cf30ac4c3cbee726799f32b727c1ebe62819c.1668000684.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/gpio.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/renesas/gpio.c b/drivers/pinctrl/renesas/gpio.c index ea3d38b4af8d..5758daf94fe2 100644 --- a/drivers/pinctrl/renesas/gpio.c +++ b/drivers/pinctrl/renesas/gpio.c @@ -135,12 +135,12 @@ static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) if (idx < 0 || pfc->info->pins[idx].enum_id == 0) return -EINVAL; - return pinctrl_gpio_request(offset); + return pinctrl_gpio_request(gc->base + offset); } static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) { - return pinctrl_gpio_free(offset); + return pinctrl_gpio_free(gc->base + offset); } static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, @@ -164,7 +164,7 @@ static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) { - return pinctrl_gpio_direction_input(offset); + return pinctrl_gpio_direction_input(gc->base + offset); } static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, @@ -172,7 +172,7 @@ static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, { gpio_pin_set_value(gpiochip_get_data(gc), offset, value); - return pinctrl_gpio_direction_output(offset); + return pinctrl_gpio_direction_output(gc->base + offset); } static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) @@ -238,7 +238,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) gc->label = pfc->info->name; gc->parent = pfc->dev; gc->owner = THIS_MODULE; - gc->base = 0; + gc->base = IS_ENABLED(CONFIG_PINCTRL_SH_FUNC_GPIO) ? 0 : -1; gc->ngpio = pfc->nr_gpio_pins; return 0; -- cgit v1.2.3 From c0f358fde37a6af517850c1f90e7d4241f472da9 Mon Sep 17 00:00:00 2001 From: Ren Zhijie Date: Mon, 21 Nov 2022 13:26:08 +0000 Subject: pinctrl: pinctrl-loongson2: fix Kconfig dependency If CONFIG_PINCTRL_LOONGSON2=y and CONFIG_OF is not set, gcc complained about undefined reference: drivers/pinctrl/pinctrl-loongson2.o: In function `pinconf_generic_dt_node_to_map_all': pinctrl-loongson2.c:(.text+0x1c4): undefined reference to `pinconf_generic_dt_node_to_map' To fix this error, add depends on OF to config PINCTRL_LOONGSON2. Fixes: f73f88acbc18 ("pinctrl: pinctrl-loongson2: add pinctrl driver support") Signed-off-by: Ren Zhijie Link: https://lore.kernel.org/r/20221121132608.230645-1-renzhijie2@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 35f167f70829..7d5f5458c72e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -260,7 +260,7 @@ config PINCTRL_FALCON config PINCTRL_LOONGSON2 tristate "Pinctrl driver for the Loongson-2 SoC" - depends on LOONGARCH || COMPILE_TEST + depends on OF && (LOONGARCH || COMPILE_TEST) select PINMUX select GENERIC_PINCONF help -- cgit v1.2.3 From ac8a616c32e12f01878d54f2e7077720dc3dc305 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Nov 2022 16:50:58 +0100 Subject: pinctrl: starfive: Use existing variable gpio Use the existing variable "gpio", instead of obtaining the hwirq number again. Signed-off-by: Geert Uytterhoeven Reviewed-by: Emil Renner Berthing Link: https://lore.kernel.org/r/3b6b8597792a393d0f21b8489dd933663dfd2b90.1669045778.git.geert+renesas@glider.be Signed-off-by: Linus Walleij --- drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c index a90b770821d6..530fe340a9a1 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c @@ -1082,7 +1082,7 @@ static void starfive_irq_mask(struct irq_data *d) writel_relaxed(value, ie); raw_spin_unlock_irqrestore(&sfp->lock, flags); - gpiochip_disable_irq(&sfp->gc, d->hwirq); + gpiochip_disable_irq(&sfp->gc, gpio); } static void starfive_irq_mask_ack(struct irq_data *d) @@ -1111,7 +1111,7 @@ static void starfive_irq_unmask(struct irq_data *d) unsigned long flags; u32 value; - gpiochip_enable_irq(&sfp->gc, d->hwirq); + gpiochip_enable_irq(&sfp->gc, gpio); raw_spin_lock_irqsave(&sfp->lock, flags); value = readl_relaxed(ie) | mask; -- cgit v1.2.3 From a8acc11643082a706de86a19f1f824712d971984 Mon Sep 17 00:00:00 2001 From: ZhangPeng Date: Tue, 22 Nov 2022 07:58:53 +0000 Subject: pinctrl: k210: call of_node_put() Since for_each_available_child_of_node() will increase the refcount of node, we need to call of_node_put() manually when breaking out of the iteration. Fixes: d4c34d09ab03 ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver") Signed-off-by: ZhangPeng Reviewed-by: Damien Le Moal Link: https://lore.kernel.org/r/20221122075853.2496680-1-zhangpeng362@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-k210.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index 288e44457fec..97920fb517bc 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -864,8 +864,10 @@ static int k210_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, for_each_available_child_of_node(np_config, np) { ret = k210_pinctrl_dt_subnode_to_map(pctldev, np, map, &reserved_maps, num_maps); - if (ret < 0) + if (ret < 0) { + of_node_put(np); goto err; + } } return 0; -- cgit v1.2.3 From eb78d3604d6bcbe9743e036114c33a5a17090a0a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 17 Nov 2022 13:08:06 +0200 Subject: pinctrl: intel: Enumerate PWM device when community has a capability MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some of the Communities may have PWM capability. In such cases, enumerate the PWM device via respective driver. A user is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko Acked-by: Thierry Reding Reviewed-by: Mika Westerberg Acked-by: Linus Walleij Acked-by: Uwe Kleine-König --- drivers/pinctrl/intel/pinctrl-intel.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 52ecd66ce357..d74c8b650aa7 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -21,6 +21,8 @@ #include #include +#include + #include "../core.h" #include "pinctrl-intel.h" @@ -46,6 +48,8 @@ #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) #define PADOWN_GPP(p) ((p) / 8) +#define PWMC 0x204 + /* Offset from pad_regs */ #define PADCFG0 0x000 #define PADCFG0_RXEVCFG_SHIFT 25 @@ -1499,6 +1503,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) return 0; } +static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, + struct intel_community *community) +{ + static const struct pwm_lpss_boardinfo info = { + .clk_rate = 19200000, + .npwm = 1, + .base_unit_bits = 22, + .bypass = true, + }; + struct pwm_lpss_chip *pwm; + + if (!(community->features & PINCTRL_FEATURE_PWM)) + return 0; + + if (!IS_REACHABLE(CONFIG_PWM_LPSS)) + return 0; + + pwm = devm_pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); + return PTR_ERR_OR_ZERO(pwm); +} + static int intel_pinctrl_probe(struct platform_device *pdev, const struct intel_pinctrl_soc_data *soc_data) { @@ -1584,6 +1609,10 @@ static int intel_pinctrl_probe(struct platform_device *pdev, ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); if (ret) return ret; + + ret = intel_pinctrl_probe_pwm(pctrl, community); + if (ret) + return ret; } irq = platform_get_irq(pdev, 0); -- cgit v1.2.3 From 5ead93289815a075d43c415e35c8beafafb801c9 Mon Sep 17 00:00:00 2001 From: ZhangPeng Date: Fri, 25 Nov 2022 07:01:56 +0000 Subject: pinctrl: pinconf-generic: add missing of_node_put() of_node_put() needs to be called when jumping out of the loop, since for_each_available_child_of_node() will increase the refcount of node. Fixes: c7289500e29d ("pinctrl: pinconf-generic: scan also referenced phandle node") Signed-off-by: ZhangPeng Link: https://lore.kernel.org/r/20221125070156.3535855-1-zhangpeng362@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinconf-generic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 415d1df8f46a..365c4b0ca465 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -395,8 +395,10 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, for_each_available_child_of_node(np_config, np) { ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, &reserved_maps, num_maps, type); - if (ret < 0) + if (ret < 0) { + of_node_put(np); goto exit; + } } return 0; -- cgit v1.2.3 From 7ebfe10ec36b80637fe746dc2371ff1d9ce71efa Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 25 Nov 2022 11:34:35 +0100 Subject: pinctrl: loongson2: Fix some const correctness The kernel robot using sparse is complaining like this: drivers/pinctrl/pinctrl-loongson2.c:212:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void *[noderef] __iomem reg @@ (...) I think the problem is simply that the register base is defined as void * __iomem instead of void __iomem * and this is because of the way const correctness works with pointer infix order. Fix it up. I think. Reported-by: kernel test robot Cc: zhanghongchen Cc: Yinbo Zhu Fixes: f73f88acbc18 ("pinctrl: pinctrl-loongson2: add pinctrl driver support") Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-loongson2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-loongson2.c b/drivers/pinctrl/pinctrl-loongson2.c index 1e9ec87e6930..a72ffeca26fb 100644 --- a/drivers/pinctrl/pinctrl-loongson2.c +++ b/drivers/pinctrl/pinctrl-loongson2.c @@ -45,7 +45,7 @@ struct loongson2_pinctrl { struct pinctrl_desc desc; struct device_node *of_node; spinlock_t lock; - void * __iomem reg_base; + void __iomem *reg_base; }; struct loongson2_pmx_group { @@ -202,7 +202,7 @@ static int loongson2_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned int func_nu unsigned int group_num) { struct loongson2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pcdev); - void * __iomem reg = pctrl->reg_base + + void __iomem *reg = pctrl->reg_base + loongson2_pmx_groups[group_num].reg; unsigned int mux_bit = loongson2_pmx_groups[group_num].bit; unsigned int val; -- cgit v1.2.3 From 6349c162b7dc69da82d508bccf68ef017893573e Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Sat, 26 Nov 2022 13:16:36 -0600 Subject: pinctrl: sunxi: d1: Add CAN bus pinmuxes The D1 pin controller contains muxes for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the pin controller is the same across all SoC variants. Signed-off-by: Fabien Poussin Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20221126191636.6673-1-samuel@sholland.org Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c index 40858b881298..9cc94be1046d 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c @@ -47,6 +47,7 @@ static const struct sunxi_desc_pin d1_pins[] = { SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN2 */ SUNXI_FUNCTION(0x6, "lcd0"), /* D18 */ SUNXI_FUNCTION(0x7, "uart4"), /* TX */ + SUNXI_FUNCTION(0x8, "can0"), /* TX */ SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 2)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -57,6 +58,7 @@ static const struct sunxi_desc_pin d1_pins[] = { SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN0 */ SUNXI_FUNCTION(0x6, "lcd0"), /* D19 */ SUNXI_FUNCTION(0x7, "uart4"), /* RX */ + SUNXI_FUNCTION(0x8, "can0"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 3)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -67,6 +69,7 @@ static const struct sunxi_desc_pin d1_pins[] = { SUNXI_FUNCTION(0x5, "i2s2_din"), /* DIN1 */ SUNXI_FUNCTION(0x6, "lcd0"), /* D20 */ SUNXI_FUNCTION(0x7, "uart5"), /* TX */ + SUNXI_FUNCTION(0x8, "can1"), /* TX */ SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 4)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -77,6 +80,7 @@ static const struct sunxi_desc_pin d1_pins[] = { SUNXI_FUNCTION(0x5, "pwm0"), SUNXI_FUNCTION(0x6, "lcd0"), /* D21 */ SUNXI_FUNCTION(0x7, "uart5"), /* RX */ + SUNXI_FUNCTION(0x8, "can1"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 5)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), SUNXI_FUNCTION(0x0, "gpio_in"), -- cgit v1.2.3 From cf2fc8f8b2cbe7ca091fa6a1d6b3b6ec644d7651 Mon Sep 17 00:00:00 2001 From: ye xingchen Date: Tue, 22 Nov 2022 16:31:57 +0800 Subject: pinctrl: qcom: remove duplicate included header files linux/seq_file.h is included more than once. Signed-off-by: ye xingchen Link: https://lore.kernel.org/r/202211221631577017318@zte.com.cn Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 1 - drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 1 - drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c | 1 - 3 files changed, 3 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 8f7d58a4efe0..6e8ac3ece94d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -601,7 +601,6 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) } #ifdef CONFIG_DEBUG_FS -#include static void msm_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index b1748791a01e..99314925bb13 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -536,7 +536,6 @@ static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, #ifdef CONFIG_DEBUG_FS -#include static void pm8xxx_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 30a934245c1b..a46650db678a 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -536,7 +536,6 @@ static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip, #ifdef CONFIG_DEBUG_FS -#include static void pm8xxx_mpp_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev, -- cgit v1.2.3 From 78ee2e071d1ba28ad945de86f828366583376485 Mon Sep 17 00:00:00 2001 From: Bernhard Rosenkränzer Date: Tue, 29 Nov 2022 03:33:55 +0100 Subject: pinctrl: mediatek: common: Remove check for pins-are-numbered MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the check for the unnecessary pins-are-numbered Devicetree property. Signed-off-by: Bernhard Rosenkränzer Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Acked-by: Krzysztof Kozlowski Acked-by: Kevin Hilman Link: https://lore.kernel.org/r/20221129023401.278780-2-bero@baylibre.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 076ae0b38e3d..553d16703475 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -1057,7 +1057,6 @@ int mtk_pctrl_init(struct platform_device *pdev, struct pinctrl_pin_desc *pins; struct mtk_pinctrl *pctl; struct device_node *np = pdev->dev.of_node, *node; - struct property *prop; int ret, i; pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); @@ -1066,11 +1065,6 @@ int mtk_pctrl_init(struct platform_device *pdev, platform_set_drvdata(pdev, pctl); - prop = of_find_property(np, "pins-are-numbered", NULL); - if (!prop) - return dev_err_probe(dev, -EINVAL, - "only support pins-are-numbered format\n"); - node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); if (node) { pctl->regmap1 = syscon_node_to_regmap(node); -- cgit v1.2.3 From b2de4316ec677e8dd09003682a1c843290b916f2 Mon Sep 17 00:00:00 2001 From: Bernhard Rosenkränzer Date: Tue, 29 Nov 2022 03:33:56 +0100 Subject: pinctrl: stm32: Remove check for pins-are-numbered MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the check for the unnecessary pins-are-numbered DeviceTree property Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Matthias Brugger Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221129023401.278780-3-bero@baylibre.com Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index cc9472b28404..1cddca506ad7 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -1499,11 +1499,6 @@ int stm32_pctl_probe(struct platform_device *pdev) if (!match_data) return -EINVAL; - if (!device_property_present(dev, "pins-are-numbered")) { - dev_err(dev, "only support pins-are-numbered format\n"); - return -EINVAL; - } - pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); if (!pctl) return -ENOMEM; -- cgit v1.2.3 From 83e1bcaf8cef26edaaf2a6098ef760f563683483 Mon Sep 17 00:00:00 2001 From: Gaosheng Cui Date: Tue, 29 Nov 2022 20:01:26 +0800 Subject: pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The thunderbay_add_functions() will free memory of thunderbay_funcs when everything is ok, but thunderbay_funcs will not be freed when thunderbay_add_functions() fails, then there will be a memory leak, so we need to add kfree() when thunderbay_add_functions() fails to fix it. In addition, doing some cleaner works, moving kfree(funcs) from thunderbay_add_functions() to thunderbay_build_functions(). Fixes: 12422af8194d ("pinctrl: Add Intel Thunder Bay pinctrl driver") Signed-off-by: Gaosheng Cui Reviewed-by: Rafał Miłecki Link: https://lore.kernel.org/r/20221129120126.1567338-1-cuigaosheng1@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-thunderbay.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/pinctrl-thunderbay.c b/drivers/pinctrl/pinctrl-thunderbay.c index 9328b17485cf..590bbbf619af 100644 --- a/drivers/pinctrl/pinctrl-thunderbay.c +++ b/drivers/pinctrl/pinctrl-thunderbay.c @@ -808,7 +808,7 @@ static int thunderbay_add_functions(struct thunderbay_pinctrl *tpc, struct funct funcs[i].num_group_names, funcs[i].data); } - kfree(funcs); + return 0; } @@ -817,6 +817,7 @@ static int thunderbay_build_functions(struct thunderbay_pinctrl *tpc) struct function_desc *thunderbay_funcs; void *ptr; int pin; + int ret; /* * Allocate maximum possible number of functions. Assume every pin @@ -860,7 +861,10 @@ static int thunderbay_build_functions(struct thunderbay_pinctrl *tpc) return -ENOMEM; thunderbay_funcs = ptr; - return thunderbay_add_functions(tpc, thunderbay_funcs); + ret = thunderbay_add_functions(tpc, thunderbay_funcs); + + kfree(thunderbay_funcs); + return ret; } static int thunderbay_pinconf_set_tristate(struct thunderbay_pinctrl *tpc, -- cgit v1.2.3