From 1aa2d8d4055267462f8943e2a1e6eb2e7034eb25 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 28 Jan 2013 14:23:45 +0100 Subject: pinctrl/abx500: add AB8505 sub-driver Add AB8505 sub driver to the ABx5x family. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: Olof Johansson Signed-off-by: Patrice Chotard Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ab8505.c | 380 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 380 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-ab8505.c (limited to 'drivers/pinctrl/pinctrl-ab8505.c') diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/pinctrl-ab8505.c new file mode 100644 index 000000000000..40dc3e107daf --- /dev/null +++ b/drivers/pinctrl/pinctrl-ab8505.c @@ -0,0 +1,380 @@ +/* + * Copyright (C) ST-Ericsson SA 2012 + * + * Author: Patrice Chotard for ST-Ericsson. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include "pinctrl-abx500.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define ABX500_GPIO(offset) (offset) + +#define AB8505_PIN_N4 ABX500_GPIO(1) +#define AB8505_PIN_R5 ABX500_GPIO(2) +#define AB8505_PIN_P5 ABX500_GPIO(3) +/* hole */ +#define AB8505_PIN_B16 ABX500_GPIO(10) +#define AB8505_PIN_B17 ABX500_GPIO(11) +/* hole */ +#define AB8505_PIN_D17 ABX500_GPIO(13) +#define AB8505_PIN_C16 ABX500_GPIO(14) +/* hole */ +#define AB8505_PIN_P2 ABX500_GPIO(17) +#define AB8505_PIN_N3 ABX500_GPIO(18) +#define AB8505_PIN_T1 ABX500_GPIO(19) +#define AB8505_PIN_P3 ABX500_GPIO(20) +/* hole */ +#define AB8505_PIN_H14 ABX500_GPIO(34) +/* hole */ +#define AB8505_PIN_J15 ABX500_GPIO(40) +#define AB8505_PIN_J14 ABX500_GPIO(41) +/* hole */ +#define AB8505_PIN_L4 ABX500_GPIO(50) +/* hole */ +#define AB8505_PIN_D16 ABX500_GPIO(52) +#define AB8505_PIN_D15 ABX500_GPIO(53) + +/* indicates the higher GPIO number */ +#define AB8505_GPIO_MAX_NUMBER 53 + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc ab8505_pins[] = { + PINCTRL_PIN(AB8505_PIN_N4, "GPIO1_N4"), + PINCTRL_PIN(AB8505_PIN_R5, "GPIO2_R5"), + PINCTRL_PIN(AB8505_PIN_P5, "GPIO3_P5"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_B16, "GPIO10_B16"), + PINCTRL_PIN(AB8505_PIN_B17, "GPIO11_B17"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_D17, "GPIO13_D17"), + PINCTRL_PIN(AB8505_PIN_C16, "GPIO14_C16"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_P2, "GPIO17_P2"), + PINCTRL_PIN(AB8505_PIN_N3, "GPIO18_N3"), + PINCTRL_PIN(AB8505_PIN_T1, "GPIO19_T1"), + PINCTRL_PIN(AB8505_PIN_P3, "GPIO20_P3"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_H14, "GPIO34_H14"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_J15, "GPIO40_J15"), + PINCTRL_PIN(AB8505_PIN_J14, "GPIO41_J14"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_L4, "GPIO50_L4"), +/* hole */ + PINCTRL_PIN(AB8505_PIN_D16, "GPIO52_D16"), + PINCTRL_PIN(AB8505_PIN_D15, "GPIO53_D15"), +}; + +/* + * Maps local GPIO offsets to local pin numbers + */ +static const struct abx500_pinrange ab8505_pinranges[] = { + ABX500_PINRANGE(1, 3, ABX500_ALT_A), + ABX500_PINRANGE(10, 2, ABX500_DEFAULT), + ABX500_PINRANGE(13, 1, ABX500_DEFAULT), + ABX500_PINRANGE(14, 1, ABX500_ALT_A), + ABX500_PINRANGE(17, 4, ABX500_ALT_A), + ABX500_PINRANGE(34, 1, ABX500_ALT_A), + ABX500_PINRANGE(40, 2, ABX500_ALT_A), + ABX500_PINRANGE(50, 1, ABX500_DEFAULT), + ABX500_PINRANGE(52, 2, ABX500_ALT_A), +}; + +/* + * Read the pin group names like this: + * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function + * + * The groups are arranged as sets per altfunction column, so we can + * mux in one group at a time by selecting the same altfunction for them + * all. When functions require pins on different altfunctions, you need + * to combine several groups. + */ + +/* default column */ +static const unsigned sysclkreq2_d_1_pins[] = { AB8505_PIN_N4 }; +static const unsigned sysclkreq3_d_1_pins[] = { AB8505_PIN_R5 }; +static const unsigned sysclkreq4_d_1_pins[] = { AB8505_PIN_P5 }; +static const unsigned gpio10_d_1_pins[] = { AB8505_PIN_B16 }; +static const unsigned gpio11_d_1_pins[] = { AB8505_PIN_B17 }; +static const unsigned gpio13_d_1_pins[] = { AB8505_PIN_D17 }; +static const unsigned pwmout1_d_1_pins[] = { AB8505_PIN_C16 }; +/* audio data interface 2*/ +static const unsigned adi2_d_1_pins[] = { AB8505_PIN_P2, AB8505_PIN_N3, + AB8505_PIN_T1, AB8505_PIN_P3 }; +static const unsigned extcpena_d_1_pins[] = { AB8505_PIN_H14 }; +/* modem SDA/SCL */ +static const unsigned modsclsda_d_1_pins[] = { AB8505_PIN_J15, AB8505_PIN_J14 }; +static const unsigned gpio50_d_1_pins[] = { AB8505_PIN_L4 }; +static const unsigned resethw_d_1_pins[] = { AB8505_PIN_D16 }; +static const unsigned service_d_1_pins[] = { AB8505_PIN_D15 }; + +/* Altfunction A column */ +static const unsigned gpio1_a_1_pins[] = { AB8505_PIN_N4 }; +static const unsigned gpio2_a_1_pins[] = { AB8505_PIN_R5 }; +static const unsigned gpio3_a_1_pins[] = { AB8505_PIN_P5 }; +static const unsigned hiqclkena_a_1_pins[] = { AB8505_PIN_B16 }; +static const unsigned pdmclk_a_1_pins[] = { AB8505_PIN_B17 }; +static const unsigned uarttxdata_a_1_pins[] = { AB8505_PIN_D17 }; +static const unsigned gpio14_a_1_pins[] = { AB8505_PIN_C16 }; +static const unsigned gpio17_a_1_pins[] = { AB8505_PIN_P2 }; +static const unsigned gpio18_a_1_pins[] = { AB8505_PIN_N3 }; +static const unsigned gpio19_a_1_pins[] = { AB8505_PIN_T1 }; +static const unsigned gpio20_a_1_pins[] = { AB8505_PIN_P3 }; +static const unsigned gpio34_a_1_pins[] = { AB8505_PIN_H14 }; +static const unsigned gpio40_a_1_pins[] = { AB8505_PIN_J15 }; +static const unsigned gpio41_a_1_pins[] = { AB8505_PIN_J14 }; +static const unsigned uartrxdata_a_1_pins[] = { AB8505_PIN_J14 }; +static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 }; +static const unsigned gpio52_a_1_pins[] = { AB8505_PIN_D16 }; +static const unsigned gpio53_a_1_pins[] = { AB8505_PIN_D15 }; + +/* Altfunction B colum */ +static const unsigned pdmdata_b_1_pins[] = { AB8505_PIN_B16 }; +static const unsigned extvibrapwm1_b_1_pins[] = { AB8505_PIN_D17 }; +static const unsigned extvibrapwm2_b_1_pins[] = { AB8505_PIN_L4 }; + +/* Altfunction C column */ +static const unsigned usbvdat_c_1_pins[] = { AB8505_PIN_D17 }; + +#define AB8505_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct abx500_pingroup ab8505_groups[] = { + AB8505_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(adi2_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(resethw_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(service_d_1, ABX500_DEFAULT), + AB8505_PIN_GROUP(gpio1_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio2_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio3_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(uarttxdata_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio14_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio17_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio18_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio19_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio20_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio34_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(uartrxdata_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B), + AB8505_PIN_GROUP(extvibrapwm1_b_1, ABX500_ALT_B), + AB8505_PIN_GROUP(extvibrapwm2_b_1, ABX500_ALT_B), + AB8505_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C), +}; + +/* We use this macro to define the groups applicable to a function */ +#define AB8505_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +AB8505_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1", + "sysclkreq4_d_1"); +AB8505_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", + "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1", + "gpio17_a_1", "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", + "gpio34_a_1", "gpio40_a_1", "gpio41_a_1", "gpio50_d_1", + "gpio52_a_1", "gpio53_a_1"); +AB8505_FUNC_GROUPS(pwmout, "pwmout1_d_1"); +AB8505_FUNC_GROUPS(adi2, "adi2_d_1"); +AB8505_FUNC_GROUPS(extcpena, "extcpena_d_1"); +AB8505_FUNC_GROUPS(modsclsda, "modsclsda_d_1"); +AB8505_FUNC_GROUPS(resethw, "resethw_d_1"); +AB8505_FUNC_GROUPS(service, "service_d_1"); +AB8505_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1"); +AB8505_FUNC_GROUPS(pdm, "pdmclk_a_1", "pdmdata_b_1"); +AB8505_FUNC_GROUPS(uartdata, "uarttxdata_a_1", "uartrxdata_a_1"); +AB8505_FUNC_GROUPS(extvibra, "extvibrapwm1_b_1", "extvibrapwm2_b_1"); +AB8505_FUNC_GROUPS(usbvdat, "usbvdat_c_1"); + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct abx500_function ab8505_functions[] = { + FUNCTION(sysclkreq), + FUNCTION(gpio), + FUNCTION(pwmout), + FUNCTION(adi2), + FUNCTION(extcpena), + FUNCTION(modsclsda), + FUNCTION(resethw), + FUNCTION(service), + FUNCTION(hiqclkena), + FUNCTION(pdm), + FUNCTION(uartdata), + FUNCTION(extvibra), + FUNCTION(extvibra), + FUNCTION(usbvdat), +}; + +/* + * this table translates what's is in the AB8505 specification regarding the + * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C). + * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1, + * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val), + * + * example : + * + * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), + * means that pin AB8505_PIN_D18 (pin 13) supports 4 mux (default/ALT_A, + * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to + * select the mux. ALTA, ALTB and ALTC val indicates values to write in + * ALTERNATFUNC register. We need to specifies these values as SOC + * designers didn't apply the same logic on how to select mux in the + * ABx500 family. + * + * As this pins supports at least ALT_B mux, default mux is + * selected by writing 1 in GPIOSEL bit : + * + * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3 + * default | 1 | 0 | 0 + * alt_A | 0 | 0 | 1 + * alt_B | 0 | 0 | 0 + * alt_C | 0 | 1 | 0 + * + * ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED), + * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL + * register is used to select the mux. As this pins doesn't support at + * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit : + * + * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1= + * default | 0 | 0 | 0 + * alt_A | 1 | 0 | 0 + */ + +struct alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1] = { + ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */ + ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/ + ALTERNATE_FUNCTIONS(4, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO4, bit 3 reserved */ + ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5, bit 4 reserved */ + ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6, bit 5 reserved */ + ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7, bit 6 reserved */ + ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8, bit 7 reserved */ + + ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */ + ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */ + ALTERNATE_FUNCTIONS(11, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */ + ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */ + ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */ + ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */ + ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */ + ALTERNATE_FUNCTIONS(16, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 7 reserved */ + /* + * pins 17 to 20 are special case, only bit 0 is used to select + * alternate function for these 4 pins. + * bits 1 to 3 are reserved + */ + ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21, bit 4 reserved */ + ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22, bit 5 reserved */ + ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23, bit 6 reserved */ + ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24, bit 7 reserved */ + + ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25, bit 0 reserved */ + ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26, bit 1 reserved */ + ALTERNATE_FUNCTIONS(27, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO27, bit 2 reserved */ + ALTERNATE_FUNCTIONS(28, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO28, bit 3 reserved */ + ALTERNATE_FUNCTIONS(29, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO29, bit 4 reserved */ + ALTERNATE_FUNCTIONS(30, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO30, bit 5 reserved */ + ALTERNATE_FUNCTIONS(31, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO31, bit 6 reserved */ + ALTERNATE_FUNCTIONS(32, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO32, bit 7 reserved */ + + ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33, bit 0 reserved */ + ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35, bit 2 reserved */ + ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36, bit 2 reserved */ + ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37, bit 2 reserved */ + ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38, bit 2 reserved */ + ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39, bit 2 reserved */ + ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7*/ + + ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */ + ALTERNATE_FUNCTIONS(42, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO42, bit 1 reserved */ + ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43, bit 2 reserved */ + ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44, bit 3 reserved */ + ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45, bit 4 reserved */ + ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46, bit 5 reserved */ + ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47, bit 6 reserved */ + ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48, bit 7 reserved */ + + ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */ + ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA controlled by bit 1 */ + ALTERNATE_FUNCTIONS(51, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */ + ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */ + ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */ +}; + +/* + * For AB8505 Only some GPIOs are interrupt capable, and they are + * organized in discontiguous clusters: + * + * GPIO10 to GPIO11 + * GPIO13 + * GPIO40 and GPIO41 + * GPIO50 + * GPIO52 to GPIO53 + */ +struct abx500_gpio_irq_cluster ab8505_gpio_irq_cluster[] = { + GPIO_IRQ_CLUSTER(9, 10, 0), /* GPIO numbers start from 1 */ + GPIO_IRQ_CLUSTER(12, 12, 0), + GPIO_IRQ_CLUSTER(39, 40, 0), + GPIO_IRQ_CLUSTER(49, 49, 0), + GPIO_IRQ_CLUSTER(51, 52, 0), +}; + +static struct abx500_pinctrl_soc_data ab8505_soc = { + .gpio_ranges = ab8505_pinranges, + .gpio_num_ranges = ARRAY_SIZE(ab8505_pinranges), + .pins = ab8505_pins, + .npins = ARRAY_SIZE(ab8505_pins), + .functions = ab8505_functions, + .nfunctions = ARRAY_SIZE(ab8505_functions), + .groups = ab8505_groups, + .ngroups = ARRAY_SIZE(ab8505_groups), + .alternate_functions = ab8505_alternate_functions, + .gpio_irq_cluster = ab8505_gpio_irq_cluster, + .ngpio_irq_cluster = ARRAY_SIZE(ab8505_gpio_irq_cluster), + .irq_gpio_rising_offset = AB8500_INT_GPIO6R, + .irq_gpio_falling_offset = AB8500_INT_GPIO6F, + .irq_gpio_factor = 1, +}; + +void +abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc) +{ + *soc = &ab8505_soc; +} -- cgit v1.2.3 From b9fab6e45d2d41de5495f7d40808e9e131652f92 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 31 Jan 2013 09:45:17 +0000 Subject: pinctrl/abx500: align GPIO cluster boundaries Not quite sure how this ever worked. In ab8500_gpio_to_irq() the GPIO for conversion is passed through as the second argument. If GPIO13, which is a valid GPIO for IRQ functionality, was received; it would be rejected by the following guard: GPIO_IRQ_CLUSTER(5, 12, 0); /* GPIO numbers start from 1 */ if (offset >= cluster->start && offset <= cluster->end) /* Valid GPIO for IRQ use */ Signed-off-by: Lee Jones [Augmented to account for off-by-one problem] Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ab8500.c | 6 +++--- drivers/pinctrl/pinctrl-ab8505.c | 10 +++++----- drivers/pinctrl/pinctrl-ab8540.c | 4 ++-- drivers/pinctrl/pinctrl-ab9540.c | 8 ++++---- drivers/pinctrl/pinctrl-abx500.c | 6 ++++-- 5 files changed, 18 insertions(+), 16 deletions(-) (limited to 'drivers/pinctrl/pinctrl-ab8505.c') diff --git a/drivers/pinctrl/pinctrl-ab8500.c b/drivers/pinctrl/pinctrl-ab8500.c index 2cd424e630e4..67dc9428bab2 100644 --- a/drivers/pinctrl/pinctrl-ab8500.c +++ b/drivers/pinctrl/pinctrl-ab8500.c @@ -456,9 +456,9 @@ struct alternate_functions ab8500_alternate_functions[AB8500_GPIO_MAX_NUMBER + 1 * GPIO36 to GPIO41 */ struct abx500_gpio_irq_cluster ab8500_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(5, 12, 0), /* GPIO numbers start from 1 */ - GPIO_IRQ_CLUSTER(23, 24, 0), - GPIO_IRQ_CLUSTER(35, 40, 0), + GPIO_IRQ_CLUSTER(6, 13, 0), + GPIO_IRQ_CLUSTER(24, 25, 0), + GPIO_IRQ_CLUSTER(36, 41, 0), }; static struct abx500_pinctrl_soc_data ab8500_soc = { diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/pinctrl-ab8505.c index 40dc3e107daf..825710afb2e1 100644 --- a/drivers/pinctrl/pinctrl-ab8505.c +++ b/drivers/pinctrl/pinctrl-ab8505.c @@ -349,11 +349,11 @@ struct alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1 * GPIO52 to GPIO53 */ struct abx500_gpio_irq_cluster ab8505_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(9, 10, 0), /* GPIO numbers start from 1 */ - GPIO_IRQ_CLUSTER(12, 12, 0), - GPIO_IRQ_CLUSTER(39, 40, 0), - GPIO_IRQ_CLUSTER(49, 49, 0), - GPIO_IRQ_CLUSTER(51, 52, 0), + GPIO_IRQ_CLUSTER(10, 11, 0), + GPIO_IRQ_CLUSTER(13, 13, 0), + GPIO_IRQ_CLUSTER(40, 41, 0), + GPIO_IRQ_CLUSTER(50, 50, 0), + GPIO_IRQ_CLUSTER(52, 53, 0), }; static struct abx500_pinctrl_soc_data ab8505_soc = { diff --git a/drivers/pinctrl/pinctrl-ab8540.c b/drivers/pinctrl/pinctrl-ab8540.c index e75310de7067..0fcd9431607c 100644 --- a/drivers/pinctrl/pinctrl-ab8540.c +++ b/drivers/pinctrl/pinctrl-ab8540.c @@ -377,8 +377,8 @@ static struct pullud ab8540_pullud = { * GPIO51 to GPIO54 */ struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(42, 43, 2), /* GPIO numbers start from 1 */ - GPIO_IRQ_CLUSTER(50, 53, 0), + GPIO_IRQ_CLUSTER(43, 44, 2), + GPIO_IRQ_CLUSTER(51, 54, 0), }; static struct abx500_pinctrl_soc_data ab8540_soc = { diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/pinctrl-ab9540.c index 31fec3e5dd52..28dfb2ee5531 100644 --- a/drivers/pinctrl/pinctrl-ab9540.c +++ b/drivers/pinctrl/pinctrl-ab9540.c @@ -455,10 +455,10 @@ struct alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] }; struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(9, 12, 0), /* GPIO numbers start from 1 */ - GPIO_IRQ_CLUSTER(23, 24, 0), - GPIO_IRQ_CLUSTER(39, 40, 0), - GPIO_IRQ_CLUSTER(49, 53, 0), + GPIO_IRQ_CLUSTER(10, 13, 0), + GPIO_IRQ_CLUSTER(24, 25, 0), + GPIO_IRQ_CLUSTER(40, 41, 0), + GPIO_IRQ_CLUSTER(50, 54, 0), }; static struct abx500_pinctrl_soc_data ab9540_soc = { diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index 9bdfcb97ef57..a9e720ffabfb 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -272,6 +272,8 @@ static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); + /* The AB8500 GPIO numbers are off by one */ + int gpio = offset + 1; int base = pct->irq_base; int i; @@ -279,8 +281,8 @@ static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) struct abx500_gpio_irq_cluster *cluster = &pct->irq_cluster[i]; - if (offset >= cluster->start && offset <= cluster->end) - return base + offset - cluster->start; + if (gpio >= cluster->start && gpio <= cluster->end) + return base + gpio - cluster->start; /* Advance by the number of gpios in this cluster */ base += cluster->end + cluster->offset - cluster->start + 1; -- cgit v1.2.3 From a6a16d274e734afa769a9651dfaf8315d404c116 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 31 Jan 2013 09:57:52 +0000 Subject: pinctrl/abx500: replace IRQ offsets with table read-in values The ABx500 GPIO controller used to provide a set of virtual contiguous IRQs for use by sub-devices, but they have been removed after a request from Mainline Maintainers. Now the AB8500 core driver deals with almost all IRQ related issues instead. The ABx500 GPIO driver is now only used to convert between GPIO and IRQ numbers which is actually quite difficult, as the ABx500 GPIO's associated IRQs are clustered together throughout the interrupt number space at irregular intervals. To solve this quandary, we have placed the read-in values into the existing cluster information table to use during conversion. Signed-off-by: Lee Jones [Moved irq_base removal into this patch] Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ab8500.c | 6 +++--- drivers/pinctrl/pinctrl-ab8505.c | 10 +++++----- drivers/pinctrl/pinctrl-ab8540.c | 5 +++-- drivers/pinctrl/pinctrl-ab9540.c | 8 ++++---- drivers/pinctrl/pinctrl-abx500.c | 18 +++++++++++------- drivers/pinctrl/pinctrl-abx500.h | 10 ++++++---- 6 files changed, 32 insertions(+), 25 deletions(-) (limited to 'drivers/pinctrl/pinctrl-ab8505.c') diff --git a/drivers/pinctrl/pinctrl-ab8500.c b/drivers/pinctrl/pinctrl-ab8500.c index 67dc9428bab2..42675ee3de1d 100644 --- a/drivers/pinctrl/pinctrl-ab8500.c +++ b/drivers/pinctrl/pinctrl-ab8500.c @@ -456,9 +456,9 @@ struct alternate_functions ab8500_alternate_functions[AB8500_GPIO_MAX_NUMBER + 1 * GPIO36 to GPIO41 */ struct abx500_gpio_irq_cluster ab8500_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(6, 13, 0), - GPIO_IRQ_CLUSTER(24, 25, 0), - GPIO_IRQ_CLUSTER(36, 41, 0), + GPIO_IRQ_CLUSTER(6, 13, 34), + GPIO_IRQ_CLUSTER(24, 25, 24), + GPIO_IRQ_CLUSTER(36, 41, 14), }; static struct abx500_pinctrl_soc_data ab8500_soc = { diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/pinctrl-ab8505.c index 825710afb2e1..f8075c6c24f7 100644 --- a/drivers/pinctrl/pinctrl-ab8505.c +++ b/drivers/pinctrl/pinctrl-ab8505.c @@ -349,11 +349,11 @@ struct alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1 * GPIO52 to GPIO53 */ struct abx500_gpio_irq_cluster ab8505_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(10, 11, 0), - GPIO_IRQ_CLUSTER(13, 13, 0), - GPIO_IRQ_CLUSTER(40, 41, 0), - GPIO_IRQ_CLUSTER(50, 50, 0), - GPIO_IRQ_CLUSTER(52, 53, 0), + GPIO_IRQ_CLUSTER(10, 11, 34), + GPIO_IRQ_CLUSTER(13, 13, 34), + GPIO_IRQ_CLUSTER(40, 41, 14), + GPIO_IRQ_CLUSTER(50, 50, 63), + GPIO_IRQ_CLUSTER(52, 53, 63), }; static struct abx500_pinctrl_soc_data ab8505_soc = { diff --git a/drivers/pinctrl/pinctrl-ab8540.c b/drivers/pinctrl/pinctrl-ab8540.c index 0fcd9431607c..ac2e1352a5a2 100644 --- a/drivers/pinctrl/pinctrl-ab8540.c +++ b/drivers/pinctrl/pinctrl-ab8540.c @@ -377,8 +377,9 @@ static struct pullud ab8540_pullud = { * GPIO51 to GPIO54 */ struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(43, 44, 2), - GPIO_IRQ_CLUSTER(51, 54, 0), + GPIO_IRQ_CLUSTER(43, 43, 126), + GPIO_IRQ_CLUSTER(44, 44, 127), + GPIO_IRQ_CLUSTER(51, 54, 63), }; static struct abx500_pinctrl_soc_data ab8540_soc = { diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/pinctrl-ab9540.c index 28dfb2ee5531..a169e5bea172 100644 --- a/drivers/pinctrl/pinctrl-ab9540.c +++ b/drivers/pinctrl/pinctrl-ab9540.c @@ -455,10 +455,10 @@ struct alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] }; struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(10, 13, 0), - GPIO_IRQ_CLUSTER(24, 25, 0), - GPIO_IRQ_CLUSTER(40, 41, 0), - GPIO_IRQ_CLUSTER(50, 54, 0), + GPIO_IRQ_CLUSTER(10, 13, 34), + GPIO_IRQ_CLUSTER(24, 25, 24), + GPIO_IRQ_CLUSTER(40, 41, 14), + GPIO_IRQ_CLUSTER(50, 54, 63), }; static struct abx500_pinctrl_soc_data ab9540_soc = { diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index b8f6c7597d53..720e77998e64 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -100,7 +100,6 @@ struct abx500_pinctrl { struct gpio_chip chip; struct ab8500 *parent; struct mutex lock; - u32 irq_base; struct abx500_gpio_irq_cluster *irq_cluster; int irq_cluster_size; }; @@ -262,18 +261,24 @@ static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); /* The AB8500 GPIO numbers are off by one */ int gpio = offset + 1; - int base = pct->irq_base; + int hwirq; int i; for (i = 0; i < pct->irq_cluster_size; i++) { struct abx500_gpio_irq_cluster *cluster = &pct->irq_cluster[i]; - if (gpio >= cluster->start && gpio <= cluster->end) - return base + gpio - cluster->start; + if (gpio >= cluster->start && gpio <= cluster->end) { + /* + * The ABx500 GPIO's associated IRQs are clustered together + * throughout the interrupt numbers at irregular intervals. + * To solve this quandry, we have placed the read-in values + * into the cluster information table. + */ + hwirq = gpio + cluster->to_irq; - /* Advance by the number of gpios in this cluster */ - base += cluster->end + cluster->offset - cluster->start + 1; + return irq_create_mapping(pct->parent->domain, hwirq); + } } return -EINVAL; @@ -876,7 +881,6 @@ static int abx500_gpio_probe(struct platform_device *pdev) pct->chip = abx500gpio_chip; pct->chip.dev = &pdev->dev; pct->chip.base = pdata->gpio_base; - pct->irq_base = pdata->irq_base; pct->chip.base = (np) ? -1 : pdata->gpio_base; /* initialize the lock */ diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/pinctrl-abx500.h index df8e0ff0c5d5..eeca8f973999 100644 --- a/drivers/pinctrl/pinctrl-abx500.h +++ b/drivers/pinctrl/pinctrl-abx500.h @@ -98,7 +98,7 @@ struct pullud { { \ .start = a, \ .end = b, \ - .offset = c, \ + .to_irq = c, \ } /** @@ -106,14 +106,16 @@ struct pullud { * capable * @start: The pin number of the first pin interrupt capable * @end: The pin number of the last pin interrupt capable - * @offset: offset used to compute specific setting strategy of - * the interrupt line + * @to_irq: The ABx500 GPIO's associated IRQs are clustered + * together throughout the interrupt numbers at irregular + * intervals. To solve this quandary, we will place the + * read-in values into the cluster information table */ struct abx500_gpio_irq_cluster { int start; int end; - int offset; + int to_irq; }; /** -- cgit v1.2.3 From 43a255dba132c1783f4ca16b528d55e55b4b4d83 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 4 Feb 2013 15:21:41 +0100 Subject: pinctrl/abx500: use direct IRQ defines Make it harder to do mistakes by introducing the actual defined ABx500 IRQ number into the IRQ cluster definitions. Deduct cluster offset from the GPIO offset to make each cluster coherent. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ab8500.c | 6 +++--- drivers/pinctrl/pinctrl-ab8505.c | 10 +++++----- drivers/pinctrl/pinctrl-ab8540.c | 6 +++--- drivers/pinctrl/pinctrl-ab9540.c | 8 ++++---- drivers/pinctrl/pinctrl-abx500.c | 3 +-- 5 files changed, 16 insertions(+), 17 deletions(-) (limited to 'drivers/pinctrl/pinctrl-ab8505.c') diff --git a/drivers/pinctrl/pinctrl-ab8500.c b/drivers/pinctrl/pinctrl-ab8500.c index 42675ee3de1d..3b471d87c211 100644 --- a/drivers/pinctrl/pinctrl-ab8500.c +++ b/drivers/pinctrl/pinctrl-ab8500.c @@ -456,9 +456,9 @@ struct alternate_functions ab8500_alternate_functions[AB8500_GPIO_MAX_NUMBER + 1 * GPIO36 to GPIO41 */ struct abx500_gpio_irq_cluster ab8500_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(6, 13, 34), - GPIO_IRQ_CLUSTER(24, 25, 24), - GPIO_IRQ_CLUSTER(36, 41, 14), + GPIO_IRQ_CLUSTER(6, 13, AB8500_INT_GPIO6R), + GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R), + GPIO_IRQ_CLUSTER(36, 41, AB8500_INT_GPIO36R), }; static struct abx500_pinctrl_soc_data ab8500_soc = { diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/pinctrl-ab8505.c index f8075c6c24f7..3a4238e879e3 100644 --- a/drivers/pinctrl/pinctrl-ab8505.c +++ b/drivers/pinctrl/pinctrl-ab8505.c @@ -349,11 +349,11 @@ struct alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1 * GPIO52 to GPIO53 */ struct abx500_gpio_irq_cluster ab8505_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(10, 11, 34), - GPIO_IRQ_CLUSTER(13, 13, 34), - GPIO_IRQ_CLUSTER(40, 41, 14), - GPIO_IRQ_CLUSTER(50, 50, 63), - GPIO_IRQ_CLUSTER(52, 53, 63), + GPIO_IRQ_CLUSTER(10, 11, AB8500_INT_GPIO10R), + GPIO_IRQ_CLUSTER(13, 13, AB8500_INT_GPIO13R), + GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R), + GPIO_IRQ_CLUSTER(50, 50, AB9540_INT_GPIO50R), + GPIO_IRQ_CLUSTER(52, 53, AB9540_INT_GPIO52R), }; static struct abx500_pinctrl_soc_data ab8505_soc = { diff --git a/drivers/pinctrl/pinctrl-ab8540.c b/drivers/pinctrl/pinctrl-ab8540.c index ac2e1352a5a2..8ee1e8d95f65 100644 --- a/drivers/pinctrl/pinctrl-ab8540.c +++ b/drivers/pinctrl/pinctrl-ab8540.c @@ -377,9 +377,9 @@ static struct pullud ab8540_pullud = { * GPIO51 to GPIO54 */ struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(43, 43, 126), - GPIO_IRQ_CLUSTER(44, 44, 127), - GPIO_IRQ_CLUSTER(51, 54, 63), + GPIO_IRQ_CLUSTER(43, 43, AB8540_INT_GPIO43F), + GPIO_IRQ_CLUSTER(44, 44, AB8540_INT_GPIO44F), + GPIO_IRQ_CLUSTER(51, 54, AB9540_INT_GPIO51R), }; static struct abx500_pinctrl_soc_data ab8540_soc = { diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/pinctrl-ab9540.c index a169e5bea172..7610bd012b98 100644 --- a/drivers/pinctrl/pinctrl-ab9540.c +++ b/drivers/pinctrl/pinctrl-ab9540.c @@ -455,10 +455,10 @@ struct alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] }; struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = { - GPIO_IRQ_CLUSTER(10, 13, 34), - GPIO_IRQ_CLUSTER(24, 25, 24), - GPIO_IRQ_CLUSTER(40, 41, 14), - GPIO_IRQ_CLUSTER(50, 54, 63), + GPIO_IRQ_CLUSTER(10, 13, AB8500_INT_GPIO10R), + GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R), + GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R), + GPIO_IRQ_CLUSTER(50, 54, AB9540_INT_GPIO50R), }; static struct abx500_pinctrl_soc_data ab9540_soc = { diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c index 720e77998e64..caecdd373061 100644 --- a/drivers/pinctrl/pinctrl-abx500.c +++ b/drivers/pinctrl/pinctrl-abx500.c @@ -275,8 +275,7 @@ static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) * To solve this quandry, we have placed the read-in values * into the cluster information table. */ - hwirq = gpio + cluster->to_irq; - + hwirq = gpio - cluster->start + cluster->to_irq; return irq_create_mapping(pct->parent->domain, hwirq); } } -- cgit v1.2.3